-- Operations synthesis.
-- Copyright (C) 2019 Tristan Gingold
--
-- This file is part of GHDL.
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
-- MA 02110-1301, USA.
with Types; use Types;
with Types_Utils; use Types_Utils;
with Mutils;
with Vhdl.Ieee.Std_Logic_1164; use Vhdl.Ieee.Std_Logic_1164;
with Vhdl.Errors; use Vhdl.Errors;
with Vhdl.Utils; use Vhdl.Utils;
with Areapools;
with Netlists; use Netlists;
with Netlists.Gates; use Netlists.Gates;
with Netlists.Builders; use Netlists.Builders;
with Netlists.Folds; use Netlists.Folds;
with Netlists.Utils;
with Synth.Errors; use Synth.Errors;
with Synth.Stmts; use Synth.Stmts;
with Synth.Expr; use Synth.Expr;
with Synth.Source;
with Synth.Static_Oper; use Synth.Static_Oper;
package body Synth.Oper is
procedure Set_Location (N : Net; Loc : Node)
renames Synth.Source.Set_Location;
function Synth_Uresize
(Ctxt : Context_Acc; N : Net; W : Width; Loc : Node) return Net is
begin
return Build2_Uresize (Ctxt, N, W, Get_Location (Loc));
end Synth_Uresize;
function Synth_Uresize
(Ctxt : Context_Acc; Val : Valtyp; W : Width; Loc : Node) return Net
is
Res : Net;
begin
if Is_Static (Val.Val) and then Val.Typ.Kind = Type_Discrete then
if Val.Typ.Drange.Is_Signed and then Read_Discrete (Val) < 0 then
-- TODO.
raise Internal_Error;
else
Res := Build2_Const_Uns
(Ctxt, To_Uns64 (Read_Discrete (Val)), W);
end if;
Set_Location (Res, Loc);
return Res;
end if;
return Synth_Uresize (Ctxt, Get_Net (Ctxt, Val), W, Loc);
end Synth_Uresize;
function Synth_Sresize
(Ctxt : Context_Acc; Val : Valtyp; W : Width; Loc : Node) return Net
is
Res : Net;
begin
if Is_Static (Val.Val) and then Val.Typ.Kind = Type_Discrete then
if Val.Typ.Drange.Is_Signed then
Res := Build2_Const_Int (Ctxt, Read_Discrete (Val), W);
else
-- TODO.
raise Internal_Error;
end if;
Set_Location (Res, Loc);
return Res;
end if;
return Build2_Sresize (Ctxt, Get_Net (Ctxt, Val), W,
Get_Location (Loc));
end Synth_Sresize;
function Synth_Bit_Eq_Const
(Ctxt : Context_Acc; Cst : Valtyp; Expr : Valtyp; Loc : Node)
return Valtyp
is
Val : Uns32;
Zx : Uns32;
N : Net;
begin
if Is_Static (Expr.Val) then
return Create_Value_Discrete
(Boolean'Pos (Read_Discrete (Cst) = Read_Discrete (Expr)),
Boolean_Type);
end if;
To_Logic (Read_Discrete (Cst), Cst.Typ, Val, Zx);
if Zx /= 0 then
-- Equal unknown -> return X
N := Build_Const_UL32 (Ctxt, 0, 1, 1);
Set_Location (N, Loc);
return Create_Value_Net (N, Boolean_Type);
elsif Val = 1 then
-- The result type is a boolean; convert if needed.
if Expr.Typ.Kind = Type_Logic then
return Create_Value_Net (Get_Net (Ctxt, Expr), Boolean_Type);
else
pragma Assert (Expr.Typ.Kind = Type_Bit);
return Expr;
end if;
else
pragma Assert (Val = 0);
N := Build_Monadic (Ctxt, Id_Not, Get_Net (Ctxt, Expr));
Set_Location (N, Loc);
return Create_Value_Net (N, Boolean_Type);
end if;
end Synth_Bit_Eq_Const;
-- Create the result range of an operator. According to the ieee standard,
-- the range is LEN-1 downto 0.
function Create_Res_Bound (Prev : Valtyp) return Type_Acc
is
Res : Type_Acc;
begin
Res := Prev.Typ;
case Res.Kind is
when Type_Vector =>
if Res.Vbound.Dir = Dir_Downto
and then Res.Vbound.Right = 0
then
-- Normalized range
return Res;
end if;
return Create_Vec_Type_By_Length (Res.W, Res.Vec_El);
when Type_Slice =>
return Create_Vec_Type_By_Length (Res.W, Res.Slice_El);
when Type_Unbounded_Vector =>
raise Internal_Error;
when others =>
raise Internal_Error;
end case;
end Create_Res_Bound;
function Create_Bounds_From_Length
(Syn_Inst : Synth_Instance_Acc; Atype : Iir; Len : Iir_Index32)
return Bound_Type
is
Res : Bound_Type;
Index_Bounds : Discrete_Range_Type;
begin
Synth_Discrete_Range (Syn_Inst, Atype, Index_Bounds);
Res := (Left => Int32 (Index_Bounds.Left),
Right => 0,
Dir => Index_Bounds.Dir,
Len => Uns32 (Len));
if Len = 0 then
-- Special case.
Res.Right := Res.Left;
case Index_Bounds.Dir is
when Dir_To =>
Res.Left := Res.Right + 1;
when Dir_Downto =>
Res.Left := Res.Right - 1;
end case;
else
case Index_Bounds.Dir is
when Dir_To =>
Res.Right := Res.Left + Int32 (Len - 1);
when Dir_Downto =>
Res.Right := Res.Left - Int32 (Len - 1);
end case;
end if;
return Res;
end Create_Bounds_From_Length;
-- Do a match comparison between CST and OPER.
-- Return No_Net if CST has incorrect value.
function Synth_Match (Ctxt : Context_Acc;
Cst : Valtyp;
Oper : Valtyp;
Expr : Node;
Op : Compare_Module_Id := Id_Eq) return Net
is
Wd : constant Width := Cst.Typ.W;
pragma Assert (Wd > 0);
Nwords : constant Natural := Natural ((Wd + 31) / 32);
Mask : Uns32_Arr_Acc;
Vals : Uns32_Arr_Acc;
Boff : Natural;
Woff : Natural;
B : Uns32;
M : Uns32;
Nv : Net;
Nm : Net;
Res : Net;
begin
-- Flatten 0/1 DC.
Mask := new Uns32_Arr'(0 .. Nwords - 1 => 0);
Vals := new Uns32_Arr'(0 .. Nwords - 1 => 0);
Boff := 0;
Woff := 0;
for I in reverse 1 .. Vec_Length (Cst.Typ) loop
case Read_U8 (Cst.Val.Mem + Size_Type (I - 1)) is
when Std_Logic_0_Pos
| Std_Logic_L_Pos =>
B := 0;
M := 1;
when Std_Logic_1_Pos
| Std_Logic_H_Pos =>
B := 1;
M := 1;
when Std_Logic_U_Pos
| Std_Logic_X_Pos
| Std_Logic_Z_Pos
| Std_Logic_W_Pos =>
-- Never match
-- FIXME: warning ?
Unchecked_Deallocate (Mask);
Unchecked_Deallocate (Vals);
return No_Net;
when Std_Logic_D_Pos =>
B := 0;
M := 0;
when others =>
raise Internal_Error;
end case;
Mask (Woff) := Mask (Woff) or Shift_Left (M, Boff);
Vals (Woff) := Vals (Woff) or Shift_Left (B, Boff);
Boff := Boff + 1;
if Boff = 32 then
Boff := 0;
Woff := Woff + 1;
end if;
end loop;
-- Generate and + eq
Nv := Build2_Const_Vec (Ctxt, Wd, Vals.all);
Set_Location (Nv, Expr);
Unchecked_Deallocate (Vals);
Nm := Build2_Const_Vec (Ctxt, Wd, Mask.all);
Set_Location (Nm, Expr);
Unchecked_Deallocate (Mask);
Res := Build_Dyadic (Ctxt, Id_And, Get_Net (Ctxt, Oper), Nm);
Set_Location (Res, Expr);
Res := Build_Compare (Ctxt, Op, Res, Nv);
Set_Location (Res, Expr);
return Res;
end Synth_Match;
-- Note: LEFT or RIGHT can be a single bit.
function Synth_Dyadic_Uns_Uns (Ctxt : Context_Acc;
Id : Dyadic_Module_Id;
Left, Right : Valtyp;
Expr : Node) return Valtyp
is
W : constant Width := Width'Max (Left.Typ.W, Right.Typ.W);
El_Typ : Type_Acc;
Rtype : Type_Acc;
L1, R1 : Net;
N : Net;
begin
if Left.Typ.Kind = Type_Vector then
El_Typ := Left.Typ.Vec_El;
elsif Right.Typ.Kind = Type_Vector then
El_Typ := Right.Typ.Vec_El;
else
raise Internal_Error;
end if;
Rtype := Create_Vec_Type_By_Length (W, El_Typ);
L1 := Synth_Uresize (Ctxt, Left, W, Expr);
R1 := Synth_Uresize (Ctxt, Right, W, Expr);
N := Build_Dyadic (Ctxt, Id, L1, R1);
Set_Location (N, Expr);
return Create_Value_Net (N, Rtype);
end Synth_Dyadic_Uns_Uns;
function Synth_Dyadic_Uns_Nat (Ctxt : Context_Acc;
Id : Dyadic_Module_Id;
Left, Right : Valtyp;
Expr : Node) return Valtyp
is
L : constant Net := Get_Net (Ctxt, Left);
R1 : Net;
N : Net;
begin
R1 := Synth_Uresize (Ctxt, Right, Left.Typ.W, Expr);
N := Build_Dyadic (Ctxt, Id, L, R1);
Set_Location (N, Expr);
return Create_Value_Net (N, Create_Res_Bound (Left));
end Synth_Dyadic_Uns_Nat;
function Synth_Dyadic_Nat_Uns (Ctxt : Context_Acc;
Id : Dyadic_Module_Id;
Left, Right : Valtyp;
Expr : Node) return Valtyp
is
R : constant Net := Get_Net (Ctxt, Right);
L1 : Net;
N : Net;
begin
L1 := Synth_Uresize (Ctxt, Left, Right.Typ.W, Expr);
N := Build_Dyadic (Ctxt, Id, L1, R);
Set_Location (N, Expr);
return Create_Value_Net (N, Create_Res_Bound (Right));
end Synth_Dyadic_Nat_Uns;
-- Note: LEFT or RIGHT can be a single bit.
function Synth_Dyadic_Sgn_Sgn (Ctxt : Context_Acc;
Id : Dyadic_Module_Id;
Left, Right : Valtyp;
Expr : Node) return Valtyp
is
W : constant Width := Width'Max (Left.Typ.W, Right.Typ.W);
El_Typ : Type_Acc;
Rtype : Type_Acc;
L1, R1 : Net;
N : Net;
begin
if Left.Typ.Kind = Type_Vector then
El_Typ := Left.Typ.Vec_El;
elsif Right.Typ.Kind = Type_Vector then
El_Typ := Right.Typ.Vec_El;
else
raise Internal_Error;
end if;
Rtype := Create_Vec_Type_By_Length (W, El_Typ);
L1 := Synth_Sresize (Ctxt, Left, W, Expr);
R1 := Synth_Sresize (Ctxt, Right, W, Expr);
N := Build_Dyadic (Ctxt, Id, L1, R1);
Set_Location (N, Expr);
return Create_Value_Net (N, Rtype);
end Synth_Dyadic_Sgn_Sgn;
function Synth_Dyadic_Sgn_Int (Ctxt : Context_Acc;
Id : Dyadic_Module_Id;
Left, Right : Valtyp;
Expr : Node) return Valtyp
is
L : constant Net := Get_Net (Ctxt, Left);
R1 : Net;
N : Net;
begin
R1 := Synth_Sresize (Ctxt, Right, Left.Typ.W, Expr);
N := Build_Dyadic (Ctxt, Id, L, R1);
Set_Location (N, Expr);
return Create_Value_Net (N, Create_Res_Bound (Left));
end Synth_Dyadic_Sgn_Int;
function Synth_Dyadic_Int_Sgn (Ctxt : Context_Acc;
Id : Dyadic_Module_Id;
Left, Right : Valtyp;
Expr : Node) return Valtyp
is
R : constant Net := Get_Net (Ctxt, Right);
L1 : Net;
N : Net;
begin
L1 := Synth_Sresize (Ctxt, Left, Right.Typ.W, Expr);
N := Build_Dyadic (Ctxt, Id, R, L1);
Set_Location (N, Expr);
return Create_Value_Net (N, Create_Res_Bound (Right));
end Synth_Dyadic_Int_Sgn;
function Synth_Dyadic_Operation (Syn_Inst : Synth_Instance_Acc;
Imp : Node;
Left_Expr : Node;
Right_Expr : Node;
Expr : Node) return Valtyp
is
Ctxt : constant Context_Acc := Get_Build (Syn_Inst);
Def : constant Iir_Predefined_Functions :=
Get_Implicit_Definition (Imp);
Inter_Chain : constant Node :=
Get_Interface_Declaration_Chain (Imp);
Expr_Type : constant Node := Get_Type (Expr);
Left_Type : constant Node := Get_Type (Inter_Chain);
Right_Type : constant Node := Get_Type (Get_Chain (Inter_Chain));
Left_Typ : constant Type_Acc :=
Get_Subtype_Object (Syn_Inst, Left_Type);
Right_Typ : constant Type_Acc :=
Get_Subtype_Object (Syn_Inst, Right_Type);
Expr_Typ : constant Type_Acc := Get_Subtype_Object (Syn_Inst, Expr_Type);
Srec : Memtyp;
Left : Valtyp;
Right : Valtyp;
function Synth_Bit_Dyadic (Id : Dyadic_Module_Id) return Valtyp
is
N : Net;
begin
N := Build_Dyadic
(Ctxt, Id, Get_Net (Ctxt, Left), Get_Net (Ctxt, Right));
Set_Location (N, Expr);
return Create_Value_Net (N, Left.Typ);
end Synth_Bit_Dyadic;
function Synth_Compare (Id : Compare_Module_Id; Res_Type : Type_Acc)
return Valtyp
is
N : Net;
begin
pragma Assert (Left_Type = Right_Type);
pragma Assert (Res_Type = Expr_Typ);
N := Build2_Compare
(Ctxt, Id, Get_Net (Ctxt, Left), Get_Net (Ctxt, Right));
Set_Location (N, Expr);
return Create_Value_Net (N, Res_Type);
end Synth_Compare;
function Synth_Minmax (Id : Compare_Module_Id) return Valtyp
is
L : constant Net := Get_Net (Ctxt, Left);
R : constant Net := Get_Net (Ctxt, Right);
Sel, N : Net;
begin
pragma Assert (Left_Type = Right_Type);
Sel := Build2_Compare (Ctxt, Id, L, R);
Set_Location (Sel, Expr);
N := Build_Mux2 (Ctxt, Sel, R, L);
Set_Location (N, Expr);
return Create_Value_Net (N, Expr_Typ);
end Synth_Minmax;
function Synth_Compare_Array (Id : Compare_Module_Id;
Res_Type : Type_Acc) return Valtyp
is
N : Net;
begin
if Left.Typ.Kind = Type_Vector then
Warning_Msg_Synth
(+Expr, "comparing non-numeric vector is unexpected");
if Left.Typ.W = Right.Typ.W then
N := Build2_Compare
(Ctxt, Id, Get_Net (Ctxt, Left), Get_Net (Ctxt, Right));
Set_Location (N, Expr);
return Create_Value_Net (N, Res_Type);
elsif Left.Typ.W < Right.Typ.W then
-- TODO: truncate right, compare using id_eq.
raise Internal_Error;
else
-- TODO: truncate left, compare using id.
raise Internal_Error;
end if;
else
raise Internal_Error;
end if;
end Synth_Compare_Array;
function Synth_Compare_Uns_Nat
(Id : Compare_Module_Id; Res_Type : Type_Acc) return Valtyp
is
N : Net;
begin
N := Synth_Uresize (Ctxt, Right, Left.Typ.W, Expr);
N := Build2_Compare (Ctxt, Id, Get_Net (Ctxt, Left), N);
Set_Location (N, Expr);
return Create_Value_Net (N, Res_Type);
end Synth_Compare_Uns_Nat;
function Synth_Compare_Nat_Uns
(Id : Compare_Module_Id; Res_Type : Type_Acc) return Valtyp
is
N : Net;
begin
N := Synth_Uresize (Ctxt, Left, Right.Typ.W, Expr);
N := Build2_Compare (Ctxt, Id, Get_Net (Ctxt, Right), N);
Set_Location (N, Expr);
return Create_Value_Net (N, Res_Type);
end Synth_Compare_Nat_Uns;
function Synth_Compare_Sgn_Int
(Id : Compare_Module_Id; Res_Typ : Type_Acc) return Valtyp
is
N : Net;
begin
N := Synth_Sresize (Ctxt, Right, Left.Typ.W, Expr);
N := Build2_Compare (Ctxt, Id, Get_Net (Ctxt, Left), N);
Set_Location (Npre { line-height: 125%; margin: 0; }
td.linenos pre { color: #000000; background-color: #f0f0f0; padding: 0 5px 0 5px; }
span.linenos { color: #000000; background-color: #f0f0f0; padding: 0 5px 0 5px; }
td.linenos pre.special { color: #000000; background-color: #ffffc0; padding: 0 5px 0 5px; }
span.linenos.special { color: #000000; background-color: #ffffc0; padding: 0 5px 0 5px; }
.highlight .hll { background-color: #ffffcc }
.highlight { background: #ffffff; }
.highlight .c { color: #888888 } /* Comment */
.highlight .err { color: #a61717; background-color: #e3d2d2 } /* Error */
.highlight .k { color: #008800; font-weight: bold } /* Keyword */
.highlight .ch { color: #888888 } /* Comment.Hashbang */
.highlight .cm { color: #888888 } /* Comment.Multiline */
.highlight .cp { color: #cc0000; font-weight: bold } /* Comment.Preproc */
.highlight .cpf { color: #888888 } /* Comment.PreprocFile */
.highlight .c1 { color: #888888 } /* Comment.Single */
.highlight .cs { color: #cc0000; font-weight: bold; background-color: #fff0f0 } /* Comment.Special */
.highlight .gd { color: #000000; background-color: #ffdddd } /* Generic.Deleted */
.highlight .ge { font-style: italic } /* Generic.Emph */
.highlight .gr { color: #aa0000 } /* Generic.Error */
.highlight .gh { color: #333333 } /* Generic.Heading */
.highlight .gi { color: #000000; background-color: #ddffdd } /* Generic.Inserted */
.highlight .go { color: #888888 } /* Generic.Output */
.highlight .gp { color: #555555 } /* Generic.Prompt */
.highlight .gs { font-weight: bold } /* Generic.Strong */
.highlight .gu { color: #666666 } /* Generic.Subheading */
.highlight .gt { color: #aa0000 } /* Generic.Traceback */
.highlight .kc { color: #008800; font-weight: bold } /* Keyword.Constant */
.highlight .kd { color: #008800; font-weight: bold } /* Keyword.Declaration */
.highlight .kn { color: #008800; font-weight: bold } /* Keyword.Namespace */
.highlight .kp { color: #008800 } /* Keyword.Pseudo */
.highlight .kr { color: #008800; font-weight: bold } /* Keyword.Reserved */
.highlight .kt { color: #888888; font-weight: bold } /* Keyword.Type */
.highlight .m { color: #0000DD; font-weight: bold } /* Literal.Number */
.highlight .s { color: #dd2200; background-color: #fff0f0 } /* Literal.String */
.highlight .na { color: #336699 } /* Name.Attribute */
.highlight .nb { color: #003388 } /* Name.Builtin */
.highlight .nc { color: #bb0066; font-weight: bold } /* Name.Class */
.highlight .no { color: #003366; font-weight: bold } /* Name.Constant */
.highlight .nd { color: #555555 } /* Name.Decorator */
.highlight .ne { color: #bb0066; font-weight: bold } /* Name.Exception */
.highlight .nf { color: #0066bb; font-weight: bold } /* Name.Function */
.highlight .nl { color: #336699; font-style: italic } /* Name.Label */
.highlight .nn { color: #bb0066; font-weight: bold } /* Name.Namespace */
.highlight .py { color: #336699; font-weight: bold } /* Name.Property */
.highlight .nt { color: #bb0066; font-weight: bold } /* Name.Tag */
.highlight .nv { color: #336699 } /* Name.Variable */
.highlight .ow { color: #008800 } /* Operator.Word */
.highlight .w { color: #bbbbbb } /* Text.Whitespace */
.highlight .mb { color: #0000DD; font-weight: bold } /* Literal.Number.Bin */
.highlight .mf { color: #0000DD; font-weight: bold } /* Literal.Number.Float */
.highlight .mh { color: #0000DD; font-weight: bold } /* Literal.Number.Hex */
.highlight .mi { color: #0000DD; font-weight: bold } /* Literal.Number.Integer */
.highlight .mo { color: #0000DD; font-weight: bold } /* Literal.Number.Oct */
.highlight .sa { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Affix */
.highlight .sb { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Backtick */
.highlight .sc { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Char */
.highlight .dl { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Delimiter */
.highlight .sd { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Doc */
.highlight .s2 { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Double */
.highlight .se { color: #0044dd; background-color: #fff0f0 } /* Literal.String.Escape */
.highlight .sh { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Heredoc */
.highlight .si { color: #3333bb; background-color: #fff0f0 } /* Literal.String.Interpol */
.highlight .sx { color: #22bb22; background-color: #f0fff0 } /* Literal.String.Other */
.highlight .sr { color: #008800; background-color: #fff0ff } /* Literal.String.Regex */
.highlight .s1 { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Single */
.highlight .ss { color: #aa6600; background-color: #fff0f0 } /* Literal.String.Symbol */
.highlight .bp { color: #003388 } /* Name.Builtin.Pseudo */
.highlight .fm { color: #0066bb; font-weight: bold } /* Name.Function.Magic */
.highlight .vc { color: #336699 } /* Name.Variable.Class */
.highlight .vg { color: #dd7700 } /* Name.Variable.Global */
.highlight .vi { color: #3333bb } /* Name.Variable.Instance */
.highlight .vm { color: #336699 } /* Name.Variable.Magic */
.highlight .il { color: #0000DD; font-weight: bold } /* Literal.Number.Integer.Long */% Generated using the yosys 'help -write-tex-command-reference-manual' command.
\section{abc -- use ABC for technology mapping}
\label{cmd:abc}
\begin{lstlisting}[numbers=left,frame=single]
abc [options] [selection]
This pass uses the ABC tool [1] for technology mapping of yosys's internal gate
library to a target architecture.
-exe <command>
use the specified command name instead of "yosys-abc" to execute ABC.
This can e.g. be used to call a specific version of ABC or a wrapper.
-script <file>
use the specified ABC script file instead of the default script.
if <file> starts with a plus sign (+), then the rest of the filename
string is interpreted as the command string to be passed to ABC. The
leading plus sign is removed and all commas (,) in the string are
replaced with blanks before the string is passed to ABC.
if no -script parameter is given, the following scripts are used:
for -liberty without -constr:
strash; scorr; ifraig; retime {D}; strash; dch -f; map {D}
for -liberty with -constr:
strash; scorr; ifraig; retime {D}; strash; dch -f; map {D};
buffer; upsize {D}; dnsize {D}; stime -p
for -lut:
strash; scorr; ifraig; retime; strash; dch -f; if
otherwise:
strash; scorr; ifraig; retime; strash; dch -f; map
-fast
use different default scripts that are slightly faster (at the cost
of output quality):
for -liberty without -constr:
retime {D}; map {D}
for -liberty with -constr:
retime {D}; map {D}; buffer; upsize {D}; dnsize {D}; stime -p
for -lut:
retime; if
otherwise:
retime; map
-liberty <file>
generate netlists for the specified cell library (using the liberty
file format).
-constr <file>
pass this file with timing constraints to ABC. use with -liberty.
a constr file contains two lines:
set_driving_cell <cell_name>
set_load <floating_point_number>
the set_driving_cell statement defines which cell type is assumed to
drive the primary inputs and the set_load statement sets the load in
femtofarads for each primary output.
-D <picoseconds>
set delay target. the string {D} in the default scripts above is
replaced by this option when used, and an empty string otherwise.
-lut <width>
generate netlist using luts of (max) the specified width.
-lut <w1>:<w2>
generate netlist using luts of (max) the specified width <w2>. All
luts with width <= <w1> have constant cost. for luts larger than <w1>
the area cost doubles with each additional input bit. the delay cost
is still constant for all lut widths.
-luts <cost1>,<cost2>,<cost3>,<sizeN>:<cost4-N>,..
generate netlist using luts. Use the specified costs for luts with 1,
2, 3, .. inputs.
-g type1,type2,...
Map the the specified list of gate types. Supported gates types are:
AND, NAND, OR, NOR, XOR, XNOR, MUX, AOI3, OAI3, AOI4, OAI4.
(The NOT gate is always added to this list automatically.)
-dff
also pass $_DFF_?_ and $_DFFE_??_ cells through ABC. modules with many
clock domains are automatically partitioned in clock domains and each
domain is passed through ABC independently.
-clk [!]<clock-signal-name>[,[!]<enable-signal-name>]
use only the specified clock domain. this is like -dff, but only FF
cells that belong to the specified clock domain ar L1, R1 : Net;
N : Net;
begin
L1 := Synth_Sresize (Ctxt, Left, W, Expr);
R1 := Synth_Sresize (Ctxt, Right, W, Expr);
N := Build2_Compare (Ctxt, Id, L1, R1);
Set_Location (N, Expr);
return Create_Value_Net (N, Res_Typ);
end Synth_Compare_Sgn_Sgn;
type Oper_Kind is (Oper_Left, Oper_Right);
function Synth_Udivmod (Id : Dyadic_Module_Id; Vec : Oper_Kind)
return Valtyp
is
W : constant Width := Width'Max (Left.Typ.W, Right.Typ.W);
L1, R1 : Net;
Res_Typ : Type_Acc;
N : Net;
begin
L1 := Synth_Uresize (Ctxt, Left, W, Expr);
R1 := Synth_Uresize (Ctxt, Right, W, Expr);
case Vec is
when Oper_Left =>
Res_Typ := Left.Typ;
when Oper_Right =>
Res_Typ := Right.Typ;
end case;
Res_Typ := Create_Vec_Type_By_Length (Res_Typ.W, Res_Typ.Vec_El);
N := Build_Dyadic (Ctxt, Id, L1, R1);
Set_Location (N, Expr);
N := Build2_Uresize (Ctxt, N, Res_Typ.W, Get_Location (Expr));
return Create_Value_Net (N, Res_Typ);
end Synth_Udivmod;
function Synth_Sdivmod (Id : Dyadic_Module_Id; Vec : Oper_Kind)
return Valtyp
is
W : constant Width := Width'Max (Left.Typ.W, Right.Typ.W);
L1, R1 : Net;
Res_Typ : Type_Acc;
N : Net;
begin
L1 := Synth_Sresize (Ctxt, Left, W, Expr);
R1 := Synth_Sresize (Ctxt, Right, W, Expr);
case Vec is
when Oper_Left =>
Res_Typ := Left.Typ;
when Oper_Right =>
Res_Typ := Right.Typ;
end case;
Res_Typ := Create_Vec_Type_By_Length (Res_Typ.W, Res_Typ.Vec_El);
N := Build_Dyadic (Ctxt, Id, L1, R1);
Set_Location (N, Expr);
N := Build2_Sresize (Ctxt, N, Res_Typ.W, Get_Location (Expr));
return Create_Value_Net (N, Res_Typ);
end Synth_Sdivmod;
function Synth_Shift (Sh_Pos : Module_Id; Sh_Neg : Module_Id)
return Valtyp
is
L1, R1 : Net;
N, Nn, Nr1, Cond : Net;
begin
L1 := Get_Net (Ctxt, Left);
R1 := Get_Net (Ctxt, Right);
-- Handle the case when the RHS is positive.
N := Build_Shift_Rotate (Ctxt, Sh_Pos, L1, R1);
Set_Location (N, Expr);
if not Is_Positive (Right) then
-- If we cannot trivially prove that the RHS is positive, also
-- handle the case when it could be negative.
-- At worst, the optimizer will remove that part.
Nr1 := Build_Monadic (Ctxt, Id_Neg, R1);
Set_Location (Nr1, Expr);
Nn := Build_Shift_Rotate (Ctxt, Sh_Neg, L1, Nr1);
Set_Location (Nn, Expr);
-- Extract the sign bit.
Cond := Build_Extract (Ctxt, R1, Get_Width (R1) - 1, 1);
Set_Location (Cond, Expr);
N := Build_Mux2 (Ctxt, Cond, N, Nn);
Set_Location (N, Expr);
end if;
return Create_Value_Net (N, Create_Res_Bound (Left));
end Synth_Shift;
function Synth_Rotation (Id : Module_Id) return Valtyp
is
Amt : Int64;
Ww : Width;
L1, R1 : Net;
N : Net;
begin
if Is_Static_Val (Right.Val) then
Amt := Get_Static_Discrete (Right);
if Amt < 0 then
raise Internal_Error;
end if;
Amt := Amt mod Int64 (Left.Typ.W);
R1 := Build_Const_UB32 (Ctxt, Uns32 (Amt), Right.Typ.W);
Set_Location (R1, Right_Expr);
elsif not Is_Positive (Right) then
Error_Msg_Synth (+Expr, "rotation quantity must be unsigned");
return Left;
else
R1 := Get_Net (Ctxt, Right);
Ww := Netlists.Utils.Clog2 (Left.Typ.W);
if Right.Typ.W >= Ww then
if Mutils.Is_Power2 (Uns64 (Left.Typ.W)) then
R1 := Build2_Trunc (Ctxt, Id_Utrunc, R1, Ww, +Expr);
else
Error_Msg_Synth
(+Expr, "vector length of rotation must be a power of 2");
return Left;
end if;
end if;
end if;
L1 := Get_Net (Ctxt, Left);
N := Build_Shift_Rotate (Ctxt, Id, L1, R1);
Set_Location (N, Expr);
return Create_Value_Net (N, Create_Res_Bound (Left));
end Synth_Rotation;
begin
Left := Synth_Expression_With_Type (Syn_Inst, Left_Expr, Left_Typ);
if Left = No_Valtyp then
return No_Valtyp;
end if;
Left := Synth_Subtype_Conversion (Ctxt, Left, Left_Typ, False, Expr);
Right := Synth_Expression_With_Type (Syn_Inst, Right_Expr, Right_Typ);
if Right = No_Valtyp then
return No_Valtyp;
end if;
Right := Synth_Subtype_Conversion (Ctxt, Right, Right_Typ, False, Expr);
if Is_Static_Val (Left.Val) and Is_Static_Val (Right.Val) then
Srec := Synth_Static_Dyadic_Predefined
(Syn_Inst, Imp,
Get_Value_Memtyp (Left), Get_Value_Memtyp (Right), Expr);
if Srec = Null_Memtyp then
return No_Valtyp;
end if;
return Create_Value_Memtyp (Srec);
end if;
Strip_Const (Left);
Strip_Const (Right);
case Def is
when Iir_Predefined_Error =>
return No_Valtyp;
when Iir_Predefined_Bit_And
| Iir_Predefined_Boolean_And
| Iir_Predefined_Ieee_1164_Scalar_And =>
return Synth_Bit_Dyadic (Id_And);
when Iir_Predefined_Bit_Xor
| Iir_Predefined_Boolean_Xor
| Iir_Predefined_Ieee_1164_Scalar_Xor =>
return Synth_Bit_Dyadic (Id_Xor);
when Iir_Predefined_Bit_Or
| Iir_Predefined_Boolean_Or
| Iir_Predefined_Ieee_1164_Scalar_Or =>
return Synth_Bit_Dyadic (Id_Or);
when Iir_Predefined_Bit_Nor
| Iir_Predefined_Ieee_1164_Scalar_Nor =>
return Synth_Bit_Dyadic (Id_Nor);
when Iir_Predefined_Bit_Nand
| Iir_Predefined_Boolean_Nand
| Iir_Predefined_Ieee_1164_Scalar_Nand =>
return Synth_Bit_Dyadic (Id_Nand);
when Iir_Predefined_Bit_Xnor
| Iir_Predefined_Boolean_Xnor
| Iir_Predefined_Ieee_1164_Scalar_Xnor =>
return Synth_Bit_Dyadic (Id_Xnor);
when Iir_Predefined_Ieee_1164_Vector_And
| Iir_Predefined_Ieee_Numeric_Std_And_Uns_Uns
| Iir_Predefined_Ieee_Numeric_Std_And_Sgn_Sgn =>
return Synth_Vec_Dyadic (Id_And);
when Iir_Predefined_Ieee_1164_Vector_Or
| Iir_Predefined_Ieee_Numeric_Std_Or_Uns_Uns
| Iir_Predefined_Ieee_Numeric_Std_Or_Sgn_Sgn =>
return Synth_Vec_Dyadic (Id_Or);
when Iir_Predefined_Ieee_1164_Vector_Nand
| Iir_Predefined_Ieee_Numeric_Std_Nand_Uns_Uns
| Iir_Predefined_Ieee_Numeric_Std_Nand_Sgn_Sgn =>
return Synth_Vec_Dyadic (Id_Nand);
when Iir_Predefined_Ieee_1164_Vector_Nor
| Iir_Predefined_Ieee_Numeric_Std_Nor_Uns_Uns
| Iir_Predefined_Ieee_Numeric_Std_Nor_Sgn_Sgn =>
return Synth_Vec_Dyadic (Id_Nor);
when Iir_Predefined_TF_Array_Xor
| Iir_Predefined_Ieee_1164_Vector_Xor
| Iir_Predefined_Ieee_Numeric_Std_Xor_Uns_Uns
| Iir_Predefined_Ieee_Numeric_Std_Xor_Sgn_Sgn =>
return Synth_Vec_Dyadic (Id_Xor);
when Iir_Predefined_Ieee_1164_Vector_Xnor
| Iir_Predefined_Ieee_Numeric_Std_Xnor_Uns_Uns
| Iir_Predefined_Ieee_Numeric_Std_Xnor_Sgn_Sgn =>
return Synth_Vec_Dyadic (Id_Xnor);
when Iir_Predefined_Enum_Equality =>
if Left_Typ = Bit_Type
or else Left_Typ = Logic_Type
then
if Is_Static (Left.Val) then
return Synth_Bit_Eq_Const (Ctxt, Left, Right, Expr);
elsif Is_Static (Right.Val) then
return Synth_Bit_Eq_Const (Ctxt, Right, Left, Expr);
end if;
end if;
return Synth_Compare (Id_Eq, Boolean_Type);
when Iir_Predefined_Enum_Inequality =>
-- TODO: Optimize ?
return Synth_Compare (Id_Ne, Boolean_Type);
when Iir_Predefined_Enum_Less_Equal =>
return Synth_Compare (Id_Ult, Boolean_Type);
when Iir_Predefined_Std_Ulogic_Match_Equality =>
return Synth_Compare (Id_Eq, Logic_Type);
when Iir_Predefined_Std_Ulogic_Match_Inequality =>
return Synth_Compare (Id_Ne, Logic_Type);
when Iir_Predefined_Std_Ulogic_Match_Less =>
return Synth_Compare (Id_Ult, Logic_Type);
when Iir_Predefined_Std_Ulogic_Match_Less_Equal =>
return Synth_Compare (Id_Ule, Logic_Type);
when Iir_Predefined_Std_Ulogic_Match_Greater =>
return Synth_Compare (Id_Ugt, Logic_Type);
when Iir_Predefined_Std_Ulogic_Match_Greater_Equal =>
return Synth_Compare (Id_Uge, Logic_Type);
when Iir_Predefined_Array_Equality
| Iir_Predefined_Record_Equality =>
if not Is_Matching_Bounds (Left.Typ, Right.Typ) then
Warning_Msg_Synth
(+Expr,
"length of '=' operands doesn't match, result is false");
return Create_Value_Discrete (0, Boolean_Type);
end if;
return Synth_Compare (Id_Eq, Boolean_Type);
when Iir_Predefined_Std_Ulogic_Array_Match_Equality =>
declare
Cst, Oper : Valtyp;
Res : Net;
begin
if Left.Typ.W /= Right.Typ.W then
Error_Msg_Synth
(+Expr, "operands of ?= don't have the same size");
return Create_Value_Discrete (0, Bit_Type);
end if;
if Is_Static (Left.Val) then
Cst := Left;
Oper := Right;
elsif Is_Static (Right.Val) then
Cst := Right;
Oper := Left;
else
Warning_Msg_Synth
(+Expr, "no operand of ?= is constant, handled like =");
return Synth_Compare (Id_Eq, Logic_Type);
end if;
Res := Synth_Match (Ctxt, Cst, Oper, Expr);
if Res = No_Net then
return Create_Value_Discrete (Std_Logic_X_Pos, Expr_Typ);
else
return Create_Value_Net (Res, Logic_Type);
end if;
end;
when Iir_Predefined_Std_Ulogic_Array_Match_Inequality =>
declare
Cst, Oper : Valtyp;
Res : Net;
begin
if Left.Typ.W /= Right.Typ.W then
Error_Msg_Synth
(+Expr, "operands of ?/= don't have the same size");
return Create_Value_Discrete (1, Bit_Type);
end if;
if Is_Static (Left.Val) then
Cst := Left;
Oper := Right;
elsif Is_Static (Right.Val) then
Cst := Right;
Oper := Left;
else
Warning_Msg_Synth
(+Expr, "no operand of ?/= is constant, handled like /=");
return Synth_Compare (Id_Ne, Logic_Type);
end if;
Res := Synth_Match (Ctxt, Cst, Oper, Expr, Id_Ne);
if Res = No_Net then
return Create_Value_Discrete (Std_Logic_X_Pos, Expr_Typ);
else
return Create_Value_Net (Res, Logic_Type);
end if;
end;
when Iir_Predefined_Array_Inequality
| Iir_Predefined_Record_Inequality =>
if not Is_Matching_Bounds (Left.Typ, Right.Typ) then
Warning_Msg_Synth
(+Expr,
"length of '/=' operands doesn't match, result is true");
return Create_Value_Discrete (1, Boolean_Type);
end if;
return Synth_Compare (Id_Ne, Boolean_Type);
when Iir_Predefined_Array_Greater =>
return Synth_Compare_Array (Id_Ugt, Boolean_Type);
when Iir_Predefined_Array_Greater_Equal =>
return Synth_Compare_Array (Id_Uge, Boolean_Type);
when Iir_Predefined_Array_Less =>
return Synth_Compare_Array (Id_Ult, Boolean_Type);
when Iir_Predefined_Ieee_Numeric_Std_Add_Uns_Nat
| Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Int =>
-- "+" (Unsigned, Natural)
return Synth_Dyadic_Uns_Nat (Ctxt, Id_Add, Left, Right, Expr);
when Iir_Predefined_Ieee_Numeric_Std_Add_Nat_Uns =>
-- "+" (Natural, Unsigned)
return Synth_Dyadic_Nat_Uns (Ctxt, Id_Add, Left, Right, Expr);
when Iir_Predefined_Ieee_Numeric_Std_Add_Uns_Uns
| Iir_Predefined_Ieee_Numeric_Std_Add_Uns_Log
| Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Log
| Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Slv
| Iir_Predefined_Ieee_Std_Logic_Arith_Add_Uns_Uns_Uns
| Iir_Predefined_Ieee_Std_Logic_Arith_Add_Uns_Uns_Slv
| Iir_Predefined_Ieee_Std_Logic_Arith_Add_Uns_Log_Slv
| Iir_Predefined_Ieee_Std_Logic_Arith_Add_Uns_Log_Uns =>
-- "+" (Unsigned, Unsigned)
return Synth_Dyadic_Uns_Uns (Ctxt, Id_Add, Left, Right, Expr);
when Iir_Predefined_Ieee_Numeric_Std_Add_Sgn_Int
| Iir_Predefined_Ieee_Std_Logic_Signed_Add_Slv_Int =>
-- "+" (Signed, Integer)
return Synth_Dyadic_Sgn_Int (Ctxt, Id_Add, Left, Right, Expr);
when Iir_Predefined_Ieee_Numeric_Std_Add_Int_Sgn
| Iir_Predefined_Ieee_Std_Logic_Arith_Add_Int_Sgn_Sgn
| Iir_Predefined_Ieee_Std_Logic_Arith_Add_Int_Sgn_Slv =>
-- "+" (Integer, Signed)
return Synth_Dyadic_Int_Sgn (Ctxt, Id_Add, Left, Right, Expr);
when Iir_Predefined_Ieee_Numeric_Std_Add_Sgn_Sgn
| Iir_Predefined_Ieee_Numeric_Std_Add_Sgn_Log
| Iir_Predefined_Ieee_Numeric_Std_Add_Log_Sgn
| Iir_Predefined_Ieee_Std_Logic_Arith_Add_Sgn_Sgn_Sgn
| Iir_Predefined_Ieee_Std_Logic_Arith_Add_Sgn_Log_Sgn
| Iir_Predefined_Ieee_Std_Logic_Arith_Add_Log_Sgn_Sgn
| Iir_Predefined_Ieee_Std_Logic_Arith_Add_Sgn_Sgn_Slv
| Iir_Predefined_Ieee_Std_Logic_Signed_Add_Slv_Slv =>
-- "+" (Signed, Signed)
return Synth_Dyadic_Sgn_Sgn (Ctxt, Id_Add, Left, Right, Expr);
when Iir_Predefined_Ieee_Numeric_Std_Sub_Uns_Nat
| Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Slv_Int =>
-- "-" (Unsigned, Natural)
return Synth_Dyadic_Uns_Nat (Ctxt, Id_Sub, Left, Right, Expr);
when Iir_Predefined_Ieee_Numeric_Std_Sub_Uns_Uns
| Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Slv_Slv
| Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Log_Slv
| Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Slv_Log
| Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Uns_Uns_Uns
| Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Uns_Uns_Slv
| Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Uns_Log_Uns =>
-- "-" (Unsigned, Unsigned)
return Synth_Dyadic_Uns_Uns (Ctxt, Id_Sub, Left, Right, Expr);
when Iir_Predefined_Ieee_Numeric_Std_Sub_Nat_Uns =>
-- "-" (Natural, Unsigned)
return Synth_Dyadic_Nat_Uns (Ctxt, Id_Sub, Left, Right, Expr);
when Iir_Predefined_Ieee_Numeric_Std_Sub_Sgn_Int
| Iir_Predefined_Ieee_Std_Logic_Signed_Sub_Slv_Int =>
-- "-" (Signed, Integer)
return Synth_Dyadic_Sgn_Int (Ctxt, Id_Sub, Left, Right, Expr);
when Iir_Predefined_Ieee_Numeric_Std_Sub_Int_Sgn =>
-- "-" (Integer, Signed)
return Synth_Dyadic_Int_Sgn (Ctxt, Id_Sub, Left, Right, Expr);
when Iir_Predefined_Ieee_Numeric_Std_Sub_Sgn_Sgn
| Iir_Predefined_Ieee_Numeric_Std_Sub_Sgn_Log
| Iir_Predefined_Ieee_Numeric_Std_Sub_Log_Sgn
| Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Sgn_Sgn_Sgn
| Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Sgn_Log_Sgn
| Iir_Predefined_Ieee_Std_Logic_Signed_Sub_Slv_Slv =>
-- "-" (Signed, Signed)
return Synth_Dyadic_Sgn_Sgn (Ctxt, Id_Sub, Left, Right, Expr);
when Iir_Predefined_Ieee_Numeric_Std_Mul_Sgn_Sgn
| Iir_Predefined_Ieee_Std_Logic_Arith_Mul_Sgn_Sgn_Sgn
| Iir_Predefined_Ieee_Std_Logic_Arith_Mul_Sgn_Sgn_Slv
| Iir_Predefined_Ieee_Std_Logic_Signed_Mul_Slv_Slv =>
-- "*" (Signed, Signed)
declare
W : constant Width := Left.Typ.W + Right.Typ.W;
L, R : Net;
N : Net;
begin
L := Synth_Sresize (Ctxt, Left, W, Left_Expr);
R := Synth_Sresize (Ctxt, Right, W, Right_Expr);
N := Build_Dyadic (Ctxt, Id_Smul, L, R);
Set_Location (N, Expr);
return Create_Value_Net
(N, Create_Vec_Type_By_Length (W, Left.Typ.Vec_El));
end;
when Iir_Predefined_Ieee_Numeric_Std_Mul_Sgn_Int =>
declare
Lw : constant Width := Left.Typ.W;
W : constant Width := 2 * Lw;
Rtype : Type_Acc;
L, R : Net;
N : Net;
begin
L := Synth_Sresize (Ctxt, Left, W, Left_Expr);
R := Synth_Sresize (Ctxt, Right, W, Right_Expr);
Rtype := Create_Vec_Type_By_Length (W, Left.Typ.Vec_El);
N := Build_Dyadic (Ctxt, Id_Smul, L, R);
Set_Location (N, Expr);
return Create_Value_Net (N, Rtype);
end;
when Iir_Predefined_Ieee_Numeric_Std_Mul_Int_Sgn =>
declare
Rw : constant Width := Right.Typ.W;
W : constant Width := 2 * Rw;
Rtype : Type_Acc;
L, R : Net;
N : Net;
begin
L := Synth_Sresize (Ctxt, Left, W, Left_Expr);
R := Synth_Sresize (Ctxt, Right, W, Right_Expr);
Rtype := Create_Vec_Type_By_Length (W, Right.Typ.Vec_El);
N := Build_Dyadic (Ctxt, Id_Smul, L, R);
Set_Location (N, Expr);
return Create_Value_Net (N, Rtype);
end;
when Iir_Predefined_Ieee_Numeric_Std_Mul_Uns_Uns
| Iir_Predefined_Ieee_Std_Logic_Arith_Mul_Uns_Uns_Uns
| Iir_Predefined_Ieee_Std_Logic_Arith_Mul_Uns_Uns_Slv
| Iir_Predefined_Ieee_Std_Logic_Unsigned_Mul_Slv_Slv =>
-- "*" (unsigned, unsigned)
declare
W : constant Width := Left.Typ.W + Right.Typ.W;
Rtype : Type_Acc;
L, R : Net;
N : Net;
begin
L := Synth_Uresize (Ctxt, Left, W, Left_Expr);
R := Synth_Uresize (Ctxt, Right, W, Right_Expr);
Rtype := Create_Vec_Type_By_Length (W, Left.Typ.Vec_El);
N := Build_Dyadic (Ctxt, Id_Umul, L, R);
Set_Location (N, Expr);
return Create_Value_Net (N, Rtype);
end;
when Iir_Predefined_Ieee_Numeric_Std_Mul_Uns_Nat =>
declare
Lw : constant Width := Left.Typ.W;
W : constant Width := 2 * Lw;
L1, R1 : Net;
Rtype : Type_Acc;
N : Net;
begin
L1 := Synth_Uresize (Ctxt, Left, W, Expr);
R1 := Synth_Uresize (Ctxt, Right, W, Expr);
Rtype := Create_Vec_Type_By_Length (W, Left.Typ.Vec_El);
N := Build_Dyadic (Ctxt, Id_Umul, L1, R1);
Set_Location (N, Expr);
return Create_Value_Net (N, Rtype);
end;
when Iir_Predefined_Ieee_Numeric_Std_Mul_Nat_Uns =>
declare
Rw : constant Width := Right.Typ.W;
W : constant Width := 2 * Rw;
L1, R1 : Net;
Rtype : Type_Acc;
N : Net;
begin
L1 := Synth_Uresize (Ctxt, Left, W, Expr);
R1 := Synth_Uresize (Ctxt, Right, W, Expr);
Rtype := Create_Vec_Type_By_Length (W, Right.Typ.Vec_El);
N := Build_Dyadic (Ctxt, Id_Umul, L1, R1);
Set_Location (N, Expr);
return Create_Value_Net (N, Rtype);
end;
when Iir_Predefined_Ieee_Std_Logic_Arith_Mul_Uns_Sgn_Sgn =>
-- "*" (unsigned, signed)
declare
W : constant Width := Left.Typ.W + 1 + Right.Typ.W;
Rtype : Type_Acc;
L, R : Net;
N : Net;
begin
L := Synth_Uresize (Ctxt, Left, W, Left_Expr);
R := Synth_Sresize (Ctxt, Right, W, Right_Expr);
Rtype := Create_Vec_Type_By_Length (W, Left.Typ.Vec_El);
N := Build_Dyadic (Ctxt, Id_Smul, L, R);
Set_Location (N, Expr);
return Create_Value_Net (N, Rtype);
end;
when Iir_Predefined_Ieee_Numeric_Std_Div_Uns_Uns
| Iir_Predefined_Ieee_Numeric_Std_Div_Uns_Nat =>
return Synth_Udivmod (Id_Udiv, Oper_Left);
when Iir_Predefined_Ieee_Numeric_Std_Div_Nat_Uns =>
return Synth_Udivmod (Id_Udiv, Oper_Right);
when Iir_Predefined_Ieee_Numeric_Std_Div_Sgn_Int
| Iir_Predefined_Ieee_Numeric_Std_Div_Sgn_Sgn =>
return Synth_Sdivmod (Id_Sdiv, Oper_Left);
when Iir_Predefined_Ieee_Numeric_Std_Div_Int_Sgn =>
return Synth_Sdivmod (Id_Sdiv, Oper_Right);
when Iir_Predefined_Ieee_Numeric_Std_Rem_Uns_Nat =>
return Synth_Udivmod (Id_Umod, Oper_Left);
when Iir_Predefined_Ieee_Numeric_Std_Rem_Uns_Uns
| Iir_Predefined_Ieee_Numeric_Std_Rem_Nat_Uns =>
return Synth_Udivmod (Id_Umod, Oper_Right);
when Iir_Predefined_Ieee_Numeric_Std_Rem_Sgn_Int =>
return Synth_Sdivmod (Id_Srem, Oper_Left);
when Iir_Predefined_Ieee_Numeric_Std_Rem_Sgn_Sgn
| Iir_Predefined_Ieee_Numeric_Std_Rem_Int_Sgn =>
return Synth_Sdivmod (Id_Srem, Oper_Right);
when Iir_Predefined_Ieee_Numeric_Std_Mod_Uns_Nat =>
return Synth_Udivmod (Id_Umod, Oper_Left);
when Iir_Predefined_Ieee_Numeric_Std_Mod_Uns_Uns
| Iir_Predefined_Ieee_Numeric_Std_Mod_Nat_Uns =>
return Synth_Udivmod (Id_Umod, Oper_Right);
when Iir_Predefined_Ieee_Numeric_Std_Mod_Sgn_Int =>
return Synth_Sdivmod (Id_Smod, Oper_Left);
when Iir_Predefined_Ieee_Numeric_Std_Mod_Sgn_Sgn
| Iir_Predefined_Ieee_Numeric_Std_Mod_Int_Sgn =>
return Synth_Sdivmod (Id_Smod, Oper_Right);
when Iir_Predefined_Ieee_Numeric_Std_Eq_Uns_Uns
| Iir_Predefined_Ieee_Std_Logic_Unsigned_Eq_Slv_Slv
| Iir_Predefined_Ieee_Numeric_Std_Match_Eq_Uns_Uns =>
-- "=" (Unsigned, Unsigned) [resize]
return Synth_Compare_Uns_Uns (Id_Eq, Expr_Typ);
when Iir_Predefined_Ieee_Numeric_Std_Eq_Uns_Nat
| Iir_Predefined_Ieee_Numeric_Std_Match_Eq_Uns_Nat
| Iir_Predefined_Ieee_Std_Logic_Unsigned_Eq_Slv_Int =>
-- "=" (Unsigned, Natural)
return Synth_Compare_Uns_Nat (Id_Eq, Expr_Typ);
when Iir_Predefined_Ieee_Numeric_Std_Eq_Nat_Uns
| Iir_Predefined_Ieee_Numeric_Std_Match_Eq_Nat_Uns =>
-- "=" (Natural, Unsigned) [resize]
return Synth_Compare_Nat_Uns (Id_Eq, Expr_Typ);
when Iir_Predefined_Ieee_Numeric_Std_Eq_Sgn_Int
| Iir_Predefined_Ieee_Numeric_Std_Match_Eq_Sgn_Int =>
-- "=" (Signed, Integer)
return Synth_Compare_Sgn_Int (Id_Eq, Expr_Typ);
when Iir_Predefined_Ieee_Numeric_Std_Eq_Sgn_Sgn
| Iir_Predefined_Ieee_Numeric_Std_Match_Eq_Sgn_Sgn =>
-- "=" (Signed, Signed) [resize]
return Synth_Compare_Sgn_Sgn (Id_Eq, Expr_Typ);
when Iir_Predefined_Ieee_Numeric_Std_Eq_Int_Sgn
| Iir_Predefined_Ieee_Numeric_Std_Match_Eq_Int_Sgn =>
-- "=" (Integer, Signed)
return Synth_Compare_Int_Sgn (Id_Eq, Expr_Typ);
when Iir_Predefined_Ieee_Numeric_Std_Ne_Uns_Uns
| Iir_Predefined_Ieee_Std_Logic_Unsigned_Ne_Slv_Slv
| Iir_Predefined_Ieee_Numeric_Std_Match_Ne_Uns_Uns =>
-- "/=" (Unsigned, Unsigned) [resize]
return Synth_Compare_Uns_Uns (Id_Ne, Expr_Typ);
when Iir_Predefined_Ieee_Numeric_Std_Ne_Uns_Nat
| Iir_Predefined_Ieee_Numeric_Std_Match_Ne_Uns_Nat =>
-- "/=" (Unsigned, Natural)
return Synth_Compare_Uns_Nat (Id_Ne, Expr_Typ);
when Iir_Predefined_Ieee_Numeric_Std_Ne_Nat_Uns
| Iir_Predefined_Ieee_Numeric_Std_Match_Ne_Nat_Uns =>
-- "/=" (Natural, Unsigned) [resize]
return Synth_Compare_Nat_Uns (Id_Ne, Expr_Typ);
when Iir_Predefined_Ieee_Numeric_Std_Ne_Sgn_Sgn
| Iir_Predefined_Ieee_Numeric_Std_Match_Ne_Sgn_Sgn =>
-- "/=" (Signed, Signed) [resize]
return Synth_Compare_Sgn_Sgn (Id_Ne, Expr_Typ);
when Iir_Predefined_Ieee_Numeric_Std_Ne_Sgn_Int
| Iir_Predefined_Ieee_Numeric_Std_Match_Ne_Sgn_Int =>
-- "/=" (Signed, Integer)
return Synth_Compare_Sgn_Int (Id_Ne, Expr_Typ);
when Iir_Predefined_Ieee_Numeric_Std_Ne_Int_Sgn
| Iir_Predefined_Ieee_Numeric_Std_Match_Ne_Int_Sgn =>
-- "/=" (Integer, Signed)
return Synth_Compare_Int_Sgn (Id_Ne, Expr_Typ);
when Iir_Predefined_Ieee_Numeric_Std_Lt_Uns_Nat
| Iir_Predefined_Ieee_Numeric_Std_Match_Lt_Uns_Nat =>
-- "<" (Unsigned, Natural)
if Is_Static (Right.Val) and then Read_Discrete (Right) = 0 then
-- Always false.
return Create_Value_Discrete (0, Expr_Typ);
end if;
return Synth_Compare_Uns_Nat (Id_Ult, Expr_Typ);
when Iir_Predefined_Ieee_Numeric_Std_Lt_Uns_Uns
| Iir_Predefined_Ieee_Numeric_Std_Match_Lt_Uns_Uns
| Iir_Predefined_Ieee_Std_Logic_Unsigned_Lt_Slv_Slv
| Iir_Predefined_Ieee_Std_Logic_Arith_Lt_Uns_Uns =>
-- "<" (Unsigned, Unsigned) [resize]
return Synth_Compare_Uns_Uns (Id_Ult, Expr_Typ);
when Iir_Predefined_Ieee_Numeric_Std_Lt_Nat_Uns
| Iir_Predefined_Ieee_Numeric_Std_Match_Lt_Nat_Uns =>
-- "<" (Natural, Unsigned) [resize]
return Synth_Compare_Nat_Uns (Id_Ult, Expr_Typ);
when Iir_Predefined_Ieee_Numeric_Std_Lt_Sgn_Sgn
| Iir_Predefined_Ieee_Numeric_Std_Match_Lt_Sgn_Sgn =>
-- "<" (Signed, Signed) [resize]
return Synth_Compare_Sgn_Sgn (Id_Slt, Expr_Typ);
when Iir_Predefined_Ieee_Numeric_Std_Lt_Sgn_Int
| Iir_Predefined_Ieee_Numeric_Std_Match_Lt_Sgn_Int =>
-- "<" (Signed, Integer)
return Synth_Compare_Sgn_Int (Id_Slt, Expr_Typ);
when Iir_Predefined_Ieee_Numeric_Std_Lt_Int_Sgn
| Iir_Predefined_Ieee_Numeric_Std_Match_Lt_Int_Sgn =>
-- "<" (Integer, Signed)
return Synth_Compare_Int_Sgn (Id_Slt, Expr_Typ);
when Iir_Predefined_Ieee_Numeric_Std_Le_Uns_Uns
| Iir_Predefined_Ieee_Std_Logic_Unsigned_Le_Slv_Slv
| Iir_Predefined_Ieee_Numeric_Std_Match_Le_Uns_Uns =>
-- "<=" (Unsigned, Unsigned) [resize]
return Synth_Compare_Uns_Uns (Id_Ule, Expr_Typ);
when Iir_Predefined_Ieee_Numeric_Std_Le_Uns_Nat
| Iir_Predefined_Ieee_Numeric_Std_Match_Le_Uns_Nat
| Iir_Predefined_Ieee_Std_Logic_Unsigned_Le_Slv_Int =>
-- "<=" (Unsigned, Natural)
return Synth_Compare_Uns_Nat (Id_Ule, Expr_Typ);
when Iir_Predefined_Ieee_Numeric_Std_Le_Nat_Uns
| Iir_Predefined_Ieee_Numeric_Std_Match_Le_Nat_Uns =>
-- "<=" (Natural, Unsigned) [resize]
return Synth_Compare_Nat_Uns (Id_Ule, Expr_Typ);
when Iir_Predefined_Ieee_Numeric_Std_Le_Sgn_Sgn
| Iir_Predefined_Ieee_Numeric_Std_Match_Le_Sgn_Sgn =>
-- "<=" (Signed, Signed)
return Synth_Compare_Sgn_Sgn (Id_Sle, Expr_Typ);
pan class="o">[-fine] [-full]
opt_share [-share_all]
opt_rmdff
opt_clean [-purge]
opt_const [-mux_undef] [-mux_bool] [-undriven] [-clkinv] [-fine] [-full] [-keepdc]
while <changed design>
When called with -fast the following script is used instead:
do
opt_const [-mux_undef] [-mux_bool] [-undriven] [-clkinv] [-fine] [-full] [-keepdc]
opt_share [-share_all]
opt_rmdff
opt_clean [-purge]
while <changed design in opt_rmdff>
Note: Options in square brackets (such as [-keepdc]) are passed through to
the opt_* commands when given to 'opt'.
\end{lstlisting}
\section{opt\_clean -- remove unused cells and wires}
\label{cmd:opt_clean}
\begin{lstlisting}[numbers=left,frame=single]
opt_clean [options] [selection]
This pass identifies wires and cells that are unused and removes them. Other
passes often remove cells but leave the wires in the design or reconnect the
wires but leave the old cells in the design. This pass can be used to clean up
after the passes that do the actual work.
This pass only operates on completely selected modules without processes.
-purge
also remove internal nets if they have a public name
\end{lstlisting}
\section{opt\_const -- perform const folding}
\label{cmd:opt_const}
\begin{lstlisting}[numbers=left,frame=single]
opt_const [options] [selection]
This pass performs const folding on internal cell types with constant inputs.
-mux_undef
remove 'undef' inputs from $mux, $pmux and $_MUX_ cells
-mux_bool
replace $mux cells with inverters or buffers when possible
-undriven
replace undriven nets with undef (x) constants
-clkinv
optimize clock inverters by changing FF types
-fine
perform fine-grain optimizations
-full
alias for -mux_undef -mux_bool -undriven -fine
-keepdc
some optimizations change the behavior of the circuit with respect to
don't-care bits. for example in 'a+0' a single x-bit in 'a' will cause
all result bits to be set to x. this behavior changes when 'a+0' is
replaced by 'a'. the -keepdc option disables all such optimizations.
\end{lstlisting}
\section{opt\_muxtree -- eliminate dead trees in multiplexer trees}
\label{cmd:opt_muxtree}
\begin{lstlisting}[numbers=left,frame=single]
opt_muxtree [selection]
This pass analyzes the control signals for the multiplexer trees in the design
and identifies inputs that can never be active. It then removes this dead
branches from the multiplexer trees.
This pass only operates on completely selected modules without processes.
\end{lstlisting}
\section{opt\_reduce -- simplify large MUXes and AND/OR gates}
\label{cmd:opt_reduce}
\begin{lstlisting}[numbers=left,frame=single]
opt_reduce [options] [selection]
This pass performs two interlinked optimizations:
1. it consolidates trees of large AND gates or OR gates and eliminates
duplicated inputs.
2. it identifies duplicated inputs to MUXes and replaces them with a single
input with the original control signals OR'ed together.
-fine
perform fine-grain optimizations
-full
alias for -fine
\end{lstlisting}
\section{opt\_rmdff -- remove DFFs with constant inputs}
\label{cmd:opt_rmdff}
\begin{lstlisting}[numbers=left,frame=single]
opt_rmdff [selection]
This pass identifies flip-flops with constant inputs and replaces them with
a constant driver.
\end{lstlisting}
\section{opt\_share -- consolidate identical cells}
\label{cmd:opt_share}
\begin{lstlisting}[numbers=left,frame=single]
opt_share [options] [selection]
This pass identifies cells with identical type and input signals. Such cells
are then merged to one cell.
-nomux
Do not merge MUX cells.
-share_all
Operate on all cell types, not just built-in types.
\end{lstlisting}
\section{plugin -- load and list loaded plugins}
\label{cmd:plugin}
\begin{lstlisting}[numbers=left,frame=single]
plugin [options]
Load and list loaded plugins.
-i <plugin_filename>
Load (install) the specified plugin.
-a <alias_name>
Register the specified alias name for the loaded plugin
-l
List loaded plugins
\end{lstlisting}
\section{pmuxtree -- transform \$pmux cells to trees of \$mux cells}
\label{cmd:pmuxtree}
\begin{lstlisting}[numbers=left,frame=single]
pmuxtree [options] [selection]
This pass transforms $pmux cells to a trees of $mux cells.
\end{lstlisting}
\section{prep -- generic synthesis script}
\label{cmd:prep}
\begin{lstlisting}[numbers=left,frame=single]
prep [options]
This command runs a conservative RTL synthesis. A typical application for this
is the preparation stage of a verification flow. This command does not operate
on partly selected designs.
-top <module>
use the specified module as top module (default='top')
-nordff
passed to 'memory_dff'. prohibits merging of FFs into memory read ports
-run <from_label>[:<to_label>]
only run the commands between the labels (see below). an empty
from label is synonymous to 'begin', and empty to label is
synonymous to the end of the command list.
The following commands are executed by this synthesis command:
begin:
hierarchy -check [-top <top>]
prep:
proc
opt_const
opt_clean
check
opt -keepdc
wreduce
memory_dff [-nordff]
opt_clean
memory_collect
opt -keepdc -fast
check:
stat
check
\end{lstlisting}
\section{proc -- translate processes to netlists}
\label{cmd:proc}
\begin{lstlisting}[numbers=left,frame=single]
proc [options] [selection]
This pass calls all the other proc_* passes in the most common order.
proc_clean
proc_rmdead
proc_init
proc_arst
proc_mux
proc_dlatch
proc_dff
proc_clean
This replaces the processes in the design with multiplexers,
flip-flops and latches.
The following options are supported:
-global_arst [!]<netname>
This option is passed through to proc_arst.
\end{lstlisting}
\section{proc\_arst -- detect asynchronous resets}
\label{cmd:proc_arst}
\begin{lstlisting}[numbers=left,frame=single]
proc_arst [-global_arst [!]<netname>] [selection]
This pass identifies asynchronous resets in the processes and converts them
to a different internal representation that is suitable for generating
flip-flop cells with asynchronous resets.
-global_arst [!]<netname>
In modules that have a net with the given name, use this net as async
reset for registers that have been assign initial values in their
declaration ('reg foobar = constant_value;'). Use the '!' modifier for
active low reset signals. Note: the frontend stores the default value
in the 'init' attribute on the net.
\end{lstlisting}
\section{proc\_clean -- remove empty parts of processes}
\label{cmd:proc_clean}
\begin{lstlisting}[numbers=left,frame=single]
proc_clean [selection]
This pass removes empty parts of processes and ultimately removes a process
if it contains only empty structures.
\end{lstlisting}
\section{proc\_dff -- extract flip-flops from processes}
\label{cmd:proc_dff}
\begin{lstlisting}[numbers=left,frame=single]
proc_dff [selection]
This pass identifies flip-flops in the processes and converts them to
d-type flip-flop cells.
\end{lstlisting}
\section{proc\_dlatch -- extract latches from processes}
\label{cmd:proc_dlatch}
\begin{lstlisting}[numbers=left,frame=single]
proc_dlatch [selection]
This pass identifies latches in the processes and converts them to
d-type latches.
\end{lstlisting}
\section{proc\_init -- convert initial block to init attributes}
\label{cmd:proc_init}
\begin{lstlisting}[numbers=left,frame=single]
proc_init [selection]
This pass extracts the 'init' actions from processes (generated from Verilog
'initial' blocks) and sets the initial value to the 'init' attribute on the
respective wire.
\end{lstlisting}
\section{proc\_mux -- convert decision trees to multiplexers}
\label{cmd:proc_mux}
\begin{lstlisting}[numbers=left,frame=single]
proc_mux [selection]
This pass converts the decision trees in processes (originating from if-else
and case statements) to trees of multiplexer cells.
\end{lstlisting}
\section{proc\_rmdead -- eliminate dead trees in decision trees}
\label{cmd:proc_rmdead}
\begin{lstlisting}[numbers=left,frame=single]
proc_rmdead [selection]
This pass identifies unreachable branches in decision trees and removes them.
\end{lstlisting}
\section{qwp -- quadratic wirelength placer}
\label{cmd:qwp}
\begin{lstlisting}[numbers=left,frame=single]
qwp [options] [selection]
This command runs quadratic wirelength placement on the selected modules and
annotates the cells in the design with 'qwp_position' attributes.
-ltr
Add left-to-right constraints: constrain all inputs on the left border
outputs to the right border.
-alpha
Add constraints for inputs/outputs to be placed in alphanumerical
order along the y-axis (top-to-bottom).
-grid N
Number of grid divisions in x- and y-direction. (default=16)
-dump <html_file_name>
Dump a protocol of the placement algorithm to the html file.
Note: This implementation of a quadratic wirelength placer uses exact
dense matrix operations. It is only a toy-placer for small circuits.
\end{lstlisting}
\section{read\_blif -- read BLIF file}
\label{cmd:read_blif}
\begin{lstlisting}[numbers=left,frame=single]
read_blif [filename]
Load modules from a BLIF file into the current design.
\end{lstlisting}
\section{read\_ilang -- read modules from ilang file}
\label{cmd:read_ilang}
\begin{lstlisting}[numbers=left,frame=single]
read_ilang [filename]
Load modules from an ilang file to the current design. (ilang is a text
representation of a design in yosys's internal format.)
\end{lstlisting}
\section{read\_liberty -- read cells from liberty file}
\label{cmd:read_liberty}
\begin{lstlisting}[numbers=left,frame=single]
read_liberty [filename]
Read cells from liberty file as modules into current design.
-lib
only create empty blackbox modules
-ignore_redef
ignore re-definitions of modules. (the default behavior is to
create an error message.)
-ignore_miss_func
ignore cells with missing function specification of outputs
-ignore_miss_dir
ignore cells with a missing or invalid direction
specification on a pin
-setattr <attribute_name>
set the specified attribute (to the value 1) on all loaded modules
\end{lstlisting}
\section{read\_verilog -- read modules from Verilog file}
\label{cmd:read_verilog}
\begin{lstlisting}[numbers=left,frame=single]
read_verilog [options] [filename]
Load modules from a Verilog file to the current design. A large subset of
Verilog-2005 is supported.
-sv
enable support for SystemVerilog features. (only a small subset
of SystemVerilog is supported)
-formal
enable support for assert() and assume() from SystemVerilog
replace the implicit -D SYNTHESIS with -D FORMAL
-dump_ast1
dump abstract syntax tree (before simplification)
-dump_ast2
dump abstract syntax tree (after simplification)
-dump_vlog
dump ast as Verilog code (after simplification)
-yydebug
enable parser debug output
-nolatches
usually latches are synthesized into logic loops
this option prohibits this and sets the output to 'x'
in what would be the latches hold condition
this behavior can also be achieved by setting the
'nolatches' attribute on the respective module or
always block.
-nomem2reg
under certain conditions memories are converted to registers
early during simplification to ensure correct handling of
complex corner cases. this option disables this behavior.
this can also be achieved by setting the 'nomem2reg'
attribute on the respective module or register.
This is potentially dangerous. Usually the front-end has good
reasons for converting an array to a list of registers.
Prohibiting this step will likely result in incorrect synthesis
results.
-mem2reg
always convert memories to registers. this can also be
achieved by setting the 'mem2reg' attribute on the respective
module or register.
-nomeminit
do not infer $meminit cells and instead convert initialized
memories to registers directly in the front-end.
-ppdump
dump Verilog code after pre-processor
-nopp
do not run the pre-processor
-nodpi
disable DPI-C support
-lib
only create empty blackbox modules. This implies -DBLACKBOX.
-noopt
don't perform basic optimizations (such as const folding) in the
high-level front-end.
-icells
interpret cell types starting with '$' as internal cell types
-ignore_redef
ignore re-definitions of modules. (the default behavior is to
create an error message.)
-defer
only read the abstract syntax tree and defer actual compilation
to a later 'hierarchy' command. Useful in cases where the default
parameters of modules yield invalid or not synthesizable code.
-noautowire
make the default of `default_nettype be "none" instead of "wire".
-setattr <attribute_name>
set the specified attribute (to the value 1) on all loaded modules
-Dname[=definition]
define the preprocessor symbol 'name' and set its optional value
'definition'
-Idir
add 'dir' to the directories which are used when searching include
files
The command 'verilog_defaults' can be used to register default options for
subsequent calls to 'read_verilog'.
Note that the Verilog frontend does a pretty good job of processing valid
verilog input, but has not very good error reporting. It generally is
recommended to use a simulator (for example Icarus Verilog) for checking
the syntax of the code, rather than to rely on read_verilog for that.
\end{lstlisting}
\section{rename -- rename object in the design}
\label{cmd:rename}
\begin{lstlisting}[numbers=left,frame=single]
rename old_name new_name
Rename the specified object. Note that selection patterns are not supported
by this command.
rename -enumerate [-pattern <pattern>] [selection]
Assign short auto-generated names to all selected wires and cells with private
names. The -pattern option can be used to set the pattern for the new names.
The character % in the pattern is replaced with a integer number. The default
pattern is '_%_'.
rename -hide [selection]
Assign private names (the ones with $-prefix) to all selected wires and cells
with public names. This ignores all selected ports.
rename -top new_name
Rename top module.
\end{lstlisting}
\section{sat -- solve a SAT problem in the circuit}
\label{cmd:sat}
\begin{lstlisting}[numbers=left,frame=single]
sat [options] [selection]
This command solves a SAT problem defined over the currently selected circuit
and additional constraints passed as parameters.
-all
show all solutions to the problem (this can grow exponentially, use
-max <N> instead to get <N> solutions)
-max <N>
like -all, but limit number of solutions to <N>
-enable_undef
enable modeling of undef value (aka 'x-bits')
this option is implied by -set-def, -set-undef et. cetera
-max_undef
maximize the number of undef bits in solutions, giving a better
picture of which input bits are actually vital to the solution.
-set <signal> <value>
set the specified signal to the specified value.
-set-def <signal>
add a constraint that all bits of the given signal must be defined
-set-any-undef <signal>
add a constraint that at least one bit of the given signal is undefined
-set-all-undef <signal>
add a constraint that all bits of the given signal are undefined
-set-def-inputs
add -set-def constraints for all module inputs
-show <signal>
show the model for the specified signal. if no -show option is
passed then a set of signals to be shown is automatically selected.
-show-inputs, -show-outputs, -show-ports
add all module (input/output) ports to the list of shown signals
-show-regs, -show-public, -show-all
show all registers, show signals with 'public' names, show all signals
-ignore_div_by_zero
ignore all solutions that involve a division by zero
-ignore_unknown_cells
ignore all cells that can not be matched to a SAT model
The following options can be used to set up a sequential problem:
-seq <N>
set up a sequential problem with <N> time steps. The steps will
be numbered from 1 to N.
note: for large <N> it can be significantly faster to use
-tempinduct-baseonly -maxsteps <N> instead of -seq <N>.
-set-at <N> <signal> <value>
-unset-at <N> <signal>
set or unset the specified signal to the specified value in the
given timestep. this has priority over a -set for the same signal.
-set-assumes
set all assumptions provided via $assume cells
-set-def-at <N> <signal>
-set-any-undef-at <N> <signal>
-set-all-undef-at <N> <signal>
add undef constraints in the given timestep.
-set-init <signal> <value>
set the initial value for the register driving the signal to the value
-set-init-undef
set all initial states (not set using -set-init) to undef
-set-init-def
do not force a value for the initial state but do not allow undef
-set-init-zero
set all initial states (not set using -set-init) to zero
-dump_vcd <vcd-file-name>
dump SAT model (counter example in proof) to VCD file
-dump_json <json-file-name>
dump SAT model (counter example in proof) to a WaveJSON file.
-dump_cnf <cnf-file-name>
dump CNF of SAT problem (in DIMACS format). in temporal induction
proofs this is the CNF of the first induction step.
The following additional options can be used to set up a proof. If also -seq
is passed, a temporal induction proof is performed.
-tempinduct
Perform a temporal induction proof. In a temporal induction proof it is
proven that the condition holds forever after the number of time steps
specified using -seq.
-tempinduct-def
Perform a temporal induction proof. Assume an initial state with all
registers set to defined values for the induction step.
-tempinduct-baseonly
Run only the basecase half of temporal induction (requires -maxsteps)
-tempinduct-inductonly
Run only the induction half of temporal induction
-tempinduct-skip <N>
Skip the first <N> steps of the induction proof.
note: this will assume that the base case holds for <N> steps.
this must be proven independently with "-tempinduct-baseonly
-maxsteps <N>". Use -initsteps if you just want to set a
minimal induction length.
-prove <signal> <value>
Attempt to proof that <signal> is always <value>.
-prove-x <signal> <value>
Like -prove, but an undef (x) bit in the lhs matches any value on
the right hand side. Useful for equivalence checking.
-prove-asserts
Prove that all asserts in the design hold.
-prove-skip <N>
Do not enforce the prove-condition for the first <N> time steps.
-maxsteps <N>
Set a maximum length for the induction.
-initsteps <N>
Set initial length for the induction.
This will speed up the search of the right induction length
for deep induction proofs.
-stepsize <N>
Increase the size of the induction proof in steps of <N>.
This will speed up the search of the right induction length
for deep induction proofs.
-timeout <N>
Maximum number of seconds a single SAT instance may take.
-verify
Return an error and stop the synthesis script if the proof fails.
-verify-no-timeout
Like -verify but do not return an error for timeouts.
-falsify
Return an error and stop the synthesis script if the proof succeeds.
-falsify-no-timeout
Like -falsify but do not return an error for timeouts.
\end{lstlisting}
\section{scatter -- add additional intermediate nets}
\label{cmd:scatter}
\begin{lstlisting}[numbers=left,frame=single]
scatter [selection]
This command adds additional intermediate nets on all cell ports. This is used
for testing the correct use of the SigMap helper in passes. If you don't know
what this means: don't worry -- you only need this pass when testing your own
extensions to Yosys.
Use the opt_clean command to get rid of the additional nets.
\end{lstlisting}
\section{scc -- detect strongly connected components (logic loops)}
\label{cmd:scc}
\begin{lstlisting}[numbers=left,frame=single]
scc [options] [selection]
This command identifies strongly connected components (aka logic loops) in the
design.
-expect <num>
expect to find exactly <num> SSCs. A different number of SSCs will
produce an error.
-max_depth <num>
limit to loops not longer than the specified number of cells. This
can e.g. be useful in identifying small local loops in a module that
implements one large SCC.
-nofeedback
do not count cells that have their output fed back into one of their
inputs as single-cell scc.
-all_cell_types
Usually this command only considers internal non-memory cells. With
this option set, all cells are considered. For unknown cells all ports
are assumed to be bidirectional 'inout' ports.
-set_attr <name> <value>
-set_cell_attr <name> <value>
-set_wire_attr <name> <value>
set the specified attribute on all cells and/or wires that are part of
a logic loop. the special token {} in the value is replaced with a
unique identifier for the logic loop.
-select
replace the current selection with a selection of all cells and wires
that are part of a found logic loop
\end{lstlisting}
\section{script -- execute commands from script file}
\label{cmd:script}
\begin{lstlisting}[numbers=left,frame=single]
script <filename> [<from_label>:<to_label>]
This command executes the yosys commands in the specified file.
The 2nd argument can be used to only execute the section of the
file between the specified labels. An empty from label is synonymous
for the beginning of the file and an empty to label is synonymous
for the end of the file.
If only one label is specified (without ':') then only the block
marked with that label (until the next label) is executed.
\end{lstlisting}
\section{select -- modify and view the list of selected objects}
\label{cmd:select}
\begin{lstlisting}[numbers=left,frame=single]
select [ -add | -del | -set <name> ] {-read <filename> | <selection>}
select [ -assert-none | -assert-any ] {-read <filename> | <selection>}
select [ -list | -write <filename> | -count | -clear ]
select -module <modname>
Most commands use the list of currently selected objects to determine which part
of the design to operate on. This command can be used to modify and view this
list of selected objects.
Note that many commands support an optional [selection] argument that can be
used to override the global selection for the command. The syntax of this
optional argument is identical to the syntax of the <selection> argument
described here.
-add, -del
add or remove the given objects to the current selection.
without this options the current selection is replaced.
-set <name>
do not modify the current selection. instead save the new selection
under the given name (see @<name> below). to save the current selection,
use "select -set <name> %"
-assert-none
do not modify the current selection. instead assert that the given
selection is empty. i.e. produce an error if any object matching the
selection is found.
-assert-any
do not modify the current selection. instead assert that the given
selection is non-empty. i.e. produce an error if no object matching
the selection is found.
-assert-count N
do not modify the current selection. instead assert that the given
selection contains exactly N objects.
-list
list all objects in the current selection
-write <filename>
like -list but write the output to the specified file
-read <filename>
read the specified file (written by -write)
-count
count all objects in the current selection
-clear
clear the current selection. this effectively selects the whole
design. it also resets the selected module (see -module). use the
command 'select *' to select everything but stay in the current module.
-none
create an empty selection. the current module is unchanged.
-module <modname>
limit the current scope to the specified module.
the difference between this and simply selecting the module
is that all object names are interpreted relative to this
module after this command until the selection is cleared again.
When this command is called without an argument, the current selection
is displayed in a compact form (i.e. only the module name when a whole module
is selected).
The <selection> argument itself is a series of commands for a simple stack
machine. Each element on the stack represents a set of selected objects.
After this commands have been executed, the union of all remaining sets
on the stack is computed and used as selection for the command.
Pushing (selecting) object when not in -module mode:
<mod_pattern>
select the specified module(s)
<mod_pattern>/<obj_pattern>
select the specified object(s) from the module(s)
Pushing (selecting) object when in -module mode:
<obj_pattern>
select the specified object(s) from the current module
A <mod_pattern> can be a module name, wildcard expression (*, ?, [..])
matching module names, or one of the following:
A:<pattern>, A:<pattern>=<pattern>
all modules with an attribute matching the given pattern
in addition to = also <, <=, >=, and > are supported
An <obj_pattern> can be an object name, wildcard expression, or one of
the following:
w:<pattern>
all wires with a name matching the given wildcard pattern
i:<pattern>, o:<pattern>, x:<pattern>
all inputs (i:), outputs (o:) or any ports (x:) with matching names
s:<size>, s:<min>:<max>
all wires with a matching width
m:<pattern>
all memories with a name matching the given pattern
c:<pattern>
all cells with a name matching the given pattern
t:<pattern>
all cells with a type matching the given pattern
p:<pattern>
all processes with a name matching the given pattern
a:<pattern>
all objects with an attribute name matching the given pattern
a:<pattern>=<pattern>
all objects with a matching attribute name-value-pair.
in addition to = also <, <=, >=, and > are supported
r:<pattern>, r:<pattern>=<pattern>
cells with matching parameters. also with <, <=, >= and >.
n:<pattern>
all objects with a name matching the given pattern
(i.e. 'n:' is optional as it is the default matching rule)
@<name>
push the selection saved prior with 'select -set <name> ...'
The following actions can be performed on the top sets on the stack:
%
push a copy of the current selection to the stack
%%
replace the stack with a union of all elements on it
%n
replace top set with its invert
%u
replace the two top sets on the stack with their union
%i
replace the two top sets on the stack with their intersection
%d
pop the top set from the stack and subtract it from the new top
%D
like %d but swap the roles of two top sets on the stack
%c
create a copy of the top set from the stack and push it
%x[<num1>|*][.<num2>][:<rule>[:<rule>..]]
expand top set <num1> num times according to the specified rules.
(i.e. select all cells connected to selected wires and select all
wires connected to selected cells) The rules specify which cell
ports to use for this. the syntax for a rule is a '-' for exclusion
and a '+' for inclusion, followed by an optional comma separated
list of cell types followed by an optional comma separated list of
cell ports in square brackets. a rule can also be just a cell or wire
name that limits the expansion (is included but does not go beyond).
select at most <num2> objects. a warning message is printed when this
limit is reached. When '*' is used instead of <num1> then the process
is repeated until no further object are selected.
%ci[<num1>|*][.<num2>][:<rule>[:<rule>..]]
%co[<num1>|*][.<num2>][:<rule>[:<rule>..]]
similar to %x, but only select input (%ci) or output cones (%co)
%xe[...] %cie[...] %coe
like %x, %ci, and %co but only consider combinatorial cells
%a
expand top set by selecting all wires that are (at least in part)
aliases for selected wires.
%s
expand top set by adding all modules that implement cells in selected
modules
%m
expand top set by selecting all modules that contain selected objects
%M
select modules that implement selected cells
%C
select cells that implement selected modules
%R[<num>]
select <num> random objects from top selection (default 1)
Example: the following command selects all wires that are connected to a
'GATE' input of a 'SWITCH' cell:
select */t:SWITCH %x:+[GATE] */t:SWITCH %d
\end{lstlisting}
\section{setattr -- set/unset attributes on objects}
\label{cmd:setattr}
\begin{lstlisting}[numbers=left,frame=single]
setattr [ -mod ] [ -set name value | -unset name ]... [selection]
Set/unset the given attributes on the selected objects. String values must be
passed in double quotes (").
When called with -mod, this command will set and unset attributes on modules
instead of objects within modules.
\end{lstlisting}
\section{setparam -- set/unset parameters on objects}
\label{cmd:setparam}
\begin{lstlisting}[numbers=left,frame=single]
setparam [ -set name value | -unset name ]... [selection]
Set/unset the given parameters on the selected cells. String values must be
passed in double quotes (").
\end{lstlisting}
\section{setundef -- replace undef values with defined constants}
\label{cmd:setundef}
\begin{lstlisting}[numbers=left,frame=single]
setundef [options] [selection]
This command replaced undef (x) constants with defined (0/1) constants.
-undriven
also set undriven nets to constant values
-zero
replace with bits cleared (0)
-one
replace with bits set (1)
-random <seed>
replace with random bits using the specified integer als seed
value for the random number generator.
\end{lstlisting}
\section{share -- perform sat-based resource sharing}
\label{cmd:share}
\begin{lstlisting}[numbers=left,frame=single]
share [options] [selection]
This pass merges shareable resources into a single resource. A SAT solver
is used to determine if two resources are share-able.
-force
Per default the selection of cells that is considered for sharing is
narrowed using a list of cell types. With this option all selected
cells are considered for resource sharing.
IMPORTANT NOTE: If the -all option is used then no cells with internal
state must be selected!
-aggressive
Per default some heuristics are used to reduce the number of cells
considered for resource sharing to only large resources. This options
turns this heuristics off, resulting in much more cells being considered
for resource sharing.
-fast
Only consider the simple part of the control logic in SAT solving, resulting
in much easier SAT problems at the cost of maybe missing some opportunities
for resource sharing.
-limit N
Only perform the first N merges, then stop. This is useful for debugging.
\end{lstlisting}
\section{shell -- enter interactive command mode}
\label{cmd:shell}
\begin{lstlisting}[numbers=left,frame=single]
shell
This command enters the interactive command mode. This can be useful
in a script to interrupt the script at a certain point and allow for
interactive inspection or manual synthesis of the design at this point.
The command prompt of the interactive shell indicates the current
selection (see 'help select'):
yosys>
the entire design is selected
yosys*>
only part of the design is selected
yosys [modname]>
the entire module 'modname' is selected using 'select -module modname'
yosys [modname]*>
only part of current module 'modname' is selected
When in interactive shell, some errors (e.g. invalid command arguments)
do not terminate yosys but return to the command prompt.
This command is the default action if nothing else has been specified
on the command line.
Press Ctrl-D or type 'exit' to leave the interactive shell.
\end{lstlisting}
\section{show -- generate schematics using graphviz}
\label{cmd:show}
\begin{lstlisting}[numbers=left,frame=single]
show [options] [selection]
Create a graphviz DOT file for the selected part of the design and compile it
to a graphics file (usually SVG or PostScript).
-viewer <viewer>
Run the specified command with the graphics file as parameter.
-format <format>
Generate a graphics file in the specified format.
Usually <format> is 'svg' or 'ps'.
-lib <verilog_or_ilang_file>
Use the specified library file for determining whether cell ports are
inputs or outputs. This option can be used multiple times to specify
more than one library.
note: in most cases it is better to load the library before calling
show with 'read_verilog -lib <filename>'. it is also possible to
load liberty files with 'read_liberty -lib <filename>'.
-prefix <prefix>
generate <prefix>.* instead of ~/.yosys_show.*
-color <color> <object>
assign the specified color to the specified object. The object can be
a single selection wildcard expressions or a saved set of objects in
the @<name> syntax (see "help select" for details).
-label <text> <object>
assign the specified label text to the specified object. The object can
be a single selection wildcard expressions or a saved set of objects in
the @<name> syntax (see "help select" for details).
-colors <seed>
Randomly assign colors to the wires. The integer argument is the seed
for the random number generator. Change the seed value if the colored
graph still is ambiguous. A seed of zero deactivates the coloring.
-colorattr <attribute_name>
Use the specified attribute to assign colors. A unique color is
assigned to each unique value of this attribute.
-width
annotate busses with a label indicating the width of the bus.
-signed
mark ports (A, B) that are declared as signed (using the [AB]_SIGNED
cell parameter) with an asterisk next to the port name.
-stretch
stretch the graph so all inputs are on the left side and all outputs
(including inout ports) are on the right side.
-pause
wait for the use to press enter to before returning
-enum
enumerate objects with internal ($-prefixed) names
-long
do not abbreviate objects with internal ($-prefixed) names
-notitle
do not add the module name as graph title to the dot file
When no <format> is specified, 'dot' is used. When no <format> and <viewer> is
specified, 'xdot' is used to display the schematic.
The generated output files are '~/.yosys_show.dot' and '~/.yosys_show.<format>',
unless another prefix is specified using -prefix <prefix>.
Yosys on Windows and YosysJS use different defaults: The output is written
to 'show.dot' in the current directory and new viewer is launched.
\end{lstlisting}
\section{simplemap -- mapping simple coarse-grain cells}
\label{cmd:simplemap}
\begin{lstlisting}[numbers=left,frame=single]
simplemap [selection]
This pass maps a small selection of simple coarse-grain cells to yosys gate
primitives. The following internal cell types are mapped by this pass:
$not, $pos, $and, $or, $xor, $xnor
$reduce_and, $reduce_or, $reduce_xor, $reduce_xnor, $reduce_bool
$logic_not, $logic_and, $logic_or, $mux, $tribuf
$sr, $dff, $dffsr, $adff, $dlatch
\end{lstlisting}
\section{singleton -- create singleton modules}
\label{cmd:singleton}
\begin{lstlisting}[numbers=left,frame=single]
singleton [selection]
By default, a module that is instantiated by several other modules is only
kept once in the design. This preserves the original modularity of the design
and reduces the overall size of the design in memory. But it prevents certain
optimizations and other operations on the design. This pass creates singleton
modules for all selected cells. The created modules are marked with the
'singleton' attribute.
This commands only operates on modules that by themself have the 'singleton'
attribute set (the 'top' module is a singleton implicitly).
\end{lstlisting}
\section{splice -- create explicit splicing cells}
\label{cmd:splice}
\begin{lstlisting}[numbers=left,frame=single]
splice [options] [selection]
This command adds $slice and $concat cells to the design to make the splicing
of multi-bit signals explicit. This for example is useful for coarse grain
synthesis, where dedicated hardware is needed to splice signals.
-sel_by_cell
only select the cell ports to rewire by the cell. if the selection
contains a cell, than all cell inputs are rewired, if necessary.
-sel_by_wire
only select the cell ports to rewire by the wire. if the selection
contains a wire, than all cell ports driven by this wire are wired,
if necessary.
-sel_any_bit
it is sufficient if the driver of any bit of a cell port is selected.
by default all bits must be selected.
-wires
also add $slice and $concat cells to drive otherwise unused wires.
-no_outputs
do not rewire selected module outputs.
-port <name>
only rewire cell ports with the specified name. can be used multiple
times. implies -no_output.
-no_port <name>
do not rewire cell ports with the specified name. can be used multiple
times. can not be combined with -port <name>.
By default selected output wires and all cell ports of selected cells driven
by selected wires are rewired.
\end{lstlisting}
\section{splitnets -- split up multi-bit nets}
\label{cmd:splitnets}
\begin{lstlisting}[numbers=left,frame=single]
splitnets [options] [selection]
This command splits multi-bit nets into single-bit nets.
-format char1[char2[char3]]
the first char is inserted between the net name and the bit index, the
second char is appended to the netname. e.g. -format () creates net
names like 'mysignal(42)'. the 3rd character is the range separation
character when creating multi-bit wires. the default is '[]:'.
-ports
also split module ports. per default only internal signals are split.
-driver
don't blindly split nets in individual bits. instead look at the driver
and split nets so that no driver drives only part of a net.
\end{lstlisting}
\section{stat -- print some statistics}
\label{cmd:stat}
\begin{lstlisting}[numbers=left,frame=single]
stat [options] [selection]
Print some statistics (number of objects) on the selected portion of the
design.
-top <module>
print design hierarchy with this module as top. if the design is fully
selected and a module has the 'top' attribute set, this module is used
default value for this option.
-liberty <liberty_file>
use cell area information from the provided liberty file
-width
annotate internal cell types with their word width.
e.g. $add_8 for an 8 bit wide $add cell.
\end{lstlisting}
\section{submod -- moving part of a module to a new submodule}
\label{cmd:submod}
\begin{lstlisting}[numbers=left,frame=single]
submod [-copy] [selection]
This pass identifies all cells with the 'submod' attribute and moves them to
a newly created module. The value of the attribute is used as name for the
cell that replaces the group of cells with the same attribute value.
This pass can be used to create a design hierarchy in flat design. This can
be useful for analyzing or reverse-engineering a design.
This pass only operates on completely selected modules with no processes
or memories.
submod -name <name> [-copy] [selection]
As above, but don't use the 'submod' attribute but instead use the selection.
Only objects from one module might be selected. The value of the -name option
is used as the value of the 'submod' attribute above.
By default the cells are 'moved' from the source module and the source module
will use an instance of the new module after this command is finished. Call
with -copy to not modify the source module.
\end{lstlisting}
\section{synth -- generic synthesis script}
\label{cmd:synth}
\begin{lstlisting}[numbers=left,frame=single]
synth [options]
This command runs the default synthesis script. This command does not operate
on partly selected designs.
-top <module>
use the specified module as top module (default='top')
-encfile <file>
passed to 'fsm_recode' via 'fsm'
-nofsm
do not run FSM optimization
-noabc
do not run abc (as if yosys was compiled without ABC support)
-noalumacc
do not run 'alumacc' pass. i.e. keep arithmetic operators in
their direct form ($add, $sub, etc.).
-nordff
passed to 'memory'. prohibits merging of FFs into memory read ports
-run <from_label>[:<to_label>]
only run the commands between the labels (see below). an empty
from label is synonymous to 'begin', and empty to label is
synonymous to the end of the command list.
The following commands are executed by this synthesis command:
begin:
hierarchy -check [-top <top>]
coarse:
proc
opt_const
opt_clean
check
opt
wreduce
alumacc
share
opt
fsm
opt -fast
memory -nomap
opt_clean
fine:
opt -fast -full
memory_map
opt -full
techmap
opt -fast
abc -fast
opt -fast
check:
hierarchy -check
stat
check
\end{lstlisting}
\section{synth\_greenpak4 -- synthesis for GreenPAK4 FPGAs}
\label{cmd:synth_greenpak4}
\begin{lstlisting}[numbers=left,frame=single]
synth_greenpak4 [options]
This command runs synthesis for GreenPAK4 FPGAs. This work is experimental.
-top <module>
use the specified module as top module (default='top')
-blif <file>
write the design to the specified BLIF file. writing of an output file
is omitted if this parameter is not specified.
-edif <file>
write the design to the specified edif file. writing of an output file
is omitted if this parameter is not specified.
-run <from_label>:<to_label>
only run the commands between the labels (see below). an empty
from label is synonymous to 'begin', and empty to label is
synonymous to the end of the command list.
-noflatten
do not flatten design before synthesis
-retime
run 'abc' with -dff option
The following commands are executed by this synthesis command:
begin:
read_verilog -lib +/greenpak4/cells_sim.v
hierarchy -check -top <top>
flatten: (unless -noflatten)
proc
flatten
tribuf -logic
coarse:
synth -run coarse
fine:
opt -fast -mux_undef -undriven -fine
memory_map
opt -undriven -fine
techmap
dfflibmap -prepare -liberty +/greenpak4/gp_dff.lib
opt -fast
abc -dff (only if -retime)
map_luts:
nlutmap -luts 0,8,16,2
clean
map_cells:
techmap -map +/greenpak4/cells_map.v
clean
check:
hierarchy -check
stat
check -noinit
blif:
write_blif -gates -attr -param <file-name>
edif:
write_edif <file-name>
\end{lstlisting}
\section{synth\_ice40 -- synthesis for iCE40 FPGAs}
\label{cmd:synth_ice40}
\begin{lstlisting}[numbers=left,frame=single]
synth_ice40 [options]
This command runs synthesis for iCE40 FPGAs. This work is experimental.
-top <module>
use the specified module as top module (default='top')
-blif <file>
write the design to the specified BLIF file. writing of an output file
is omitted if this parameter is not specified.
-edif <file>
write the design to the specified edif file. writing of an output file
is omitted if this parameter is not specified.
-run <from_label>:<to_label>
only run the commands between the labels (see below). an empty
from label is synonymous to 'begin', and empty to label is
synonymous to the end of the command list.
-noflatten
do not flatten design before synthesis
-retime
run 'abc' with -dff option
-nocarry
do not use SB_CARRY cells in output netlist
-nobram
do not use SB_RAM40_4K* cells in output netlist
-abc2
run two passes of 'abc' for slightly improved logic density
The following commands are executed by this synthesis command:
begin:
read_verilog -lib +/ice40/cells_sim.v
hierarchy -check -top <top>
flatten: (unless -noflatten)
proc
flatten
tribuf -logic
coarse:
synth -run coarse
bram: (skip if -nobram)
memory_bram -rules +/ice40/brams.txt
techmap -map +/ice40/brams_map.v
fine:
opt -fast -mux_undef -undriven -fine
memory_map
opt -undriven -fine
techmap -map +/techmap.v [-map +/ice40/arith_map.v]
abc -dff (only if -retime)
ice40_opt
map_ffs:
dffsr2dff
dff2dffe -direct-match $_DFF_*
techmap -map +/ice40/cells_map.v
opt_const -mux_undef
simplemap
ice40_ffinit
ice40_ffssr
ice40_opt -full
map_luts:
abc (only if -abc2)
ice40_opt (only if -abc2)
abc -lut 4
clean
map_cells:
techmap -map +/ice40/cells_map.v
clean
check:
hierarchy -check
stat
check -noinit
blif:
write_blif -gates -attr -param <file-name>
edif:
write_edif <file-name>
\end{lstlisting}
\section{synth\_xilinx -- synthesis for Xilinx FPGAs}
\label{cmd:synth_xilinx}
\begin{lstlisting}[numbers=left,frame=single]
synth_xilinx [options]
This command runs synthesis for Xilinx FPGAs. This command does not operate on
partly selected designs. At the moment this command creates netlists that are
compatible with 7-Series Xilinx devices.
-top <module>
use the specified module as top module
-edif <file>
write the design to the specified edif file. writing of an output file
is omitted if this parameter is not specified.
-run <from_label>:<to_label>
only run the commands between the labels (see below). an empty
from label is synonymous to 'begin', and empty to label is
synonymous to the end of the command list.
-flatten
flatten design before synthesis
-retime
run 'abc' with -dff option
The following commands are executed by this synthesis command:
begin:
read_verilog -lib +/xilinx/cells_sim.v
read_verilog -lib +/xilinx/brams_bb.v
read_verilog -lib +/xilinx/drams_bb.v
hierarchy -check -top <top>
flatten: (only if -flatten)
proc
flatten
coarse:
synth -run coarse
bram:
memory_bram -rules +/xilinx/brams.txt
techmap -map +/xilinx/brams_map.v
dram:
memory_bram -rules +/xilinx/drams.txt
techmap -map +/xilinx/drams_map.v
fine:
opt -fast -full
memory_map
dffsr2dff
dff2dffe
opt -full
techmap -map +/techmap.v -map +/xilinx/arith_map.v
opt -fast
map_luts:
abc -luts 2:2,3,6:5,10,20 [-dff]
clean
map_cells:
techmap -map +/xilinx/cells_map.v
dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT
clean
check:
hierarchy -check
stat
check -noinit
edif: (only if -edif)
write_edif <file-name>
\end{lstlisting}
\section{tcl -- execute a TCL script file}
\label{cmd:tcl}
\begin{lstlisting}[numbers=left,frame=single]
tcl <filename>
This command executes the tcl commands in the specified file.
Use 'yosys cmd' to run the yosys command 'cmd' from tcl.
The tcl command 'yosys -import' can be used to import all yosys
commands directly as tcl commands to the tcl shell. The yosys
command 'proc' is wrapped using the tcl command 'procs' in order
to avoid a name collision with the tcl builtin command 'proc'.
\end{lstlisting}
\section{techmap -- generic technology mapper}
\label{cmd:techmap}
\begin{lstlisting}[numbers=left,frame=single]
techmap [-map filename] [selection]
This pass implements a very simple technology mapper that replaces cells in
the design with implementations given in form of a Verilog or ilang source
file.
-map filename
the library of cell implementations to be used.
without this parameter a builtin library is used that
transforms the internal RTL cells to the internal gate
library.
-map %<design-name>
like -map above, but with an in-memory design instead of a file.
-extern
load the cell implementations as separate modules into the design
instead of inlining them.
-max_iter <number>
only run the specified number of iterations.
-recursive
instead of the iterative breadth-first algorithm use a recursive
depth-first algorithm. both methods should yield equivalent results,
but may differ in performance.
-autoproc
Automatically call "proc" on implementations that contain processes.
-assert
this option will cause techmap to exit with an error if it can't map
a selected cell. only cell types that end on an underscore are accepted
as final cell types by this mode.
-D <define>, -I <incdir>
this options are passed as-is to the Verilog frontend for loading the
map file. Note that the Verilog frontend is also called with the
'-ignore_redef' option set.
When a module in the map file has the 'techmap_celltype' attribute set, it will
match cells with a type that match the text value of this attribute. Otherwise
the module name will be used to match the cell.
When a module in the map file has the 'techmap_simplemap' attribute set, techmap
will use 'simplemap' (see 'help simplemap') to map cells matching the module.
When a module in the map file has the 'techmap_maccmap' attribute set, techmap
will use 'maccmap' (see 'help maccmap') to map cells matching the module.
When a module in the map file has the 'techmap_wrap' attribute set, techmap
will create a wrapper for the cell and then run the command string that the
attribute is set to on the wrapper module.
All wires in the modules from the map file matching the pattern _TECHMAP_*
or *._TECHMAP_* are special wires that are used to pass instructions from
the mapping module to the techmap command. At the moment the following special
wires are supported:
_TECHMAP_FAIL_
When this wire is set to a non-zero constant value, techmap will not
use this module and instead try the next module with a matching
'techmap_celltype' attribute.
When such a wire exists but does not have a constant value after all
_TECHMAP_DO_* commands have been executed, an error is generated.
_TECHMAP_DO_*
This wires are evaluated in alphabetical order. The constant text value
of this wire is a yosys command (or sequence of commands) that is run
by techmap on the module. A common use case is to run 'proc' on modules
that are written using always-statements.
When such a wire has a non-constant value at the time it is to be
evaluated, an error is produced. That means it is possible for such a
wire to start out as non-constant and evaluate to a constant value
during processing of other _TECHMAP_DO_* commands.
A _TECHMAP_DO_* command may start with the special token 'CONSTMAP; '.
in this case techmap will create a copy for each distinct configuration
of constant inputs and shorted inputs at this point and import the
constant and connected bits into the map module. All further commands
are executed in this copy. This is a very convenient way of creating
optimized specializations of techmap modules without using the special
parameters described below.
A _TECHMAP_DO_* command may start with the special token 'RECURSION; '.
then techmap will recursively replace the cells in the module with their
implementation. This is not affected by the -max_iter option.
It is possible to combine both prefixes to 'RECURSION; CONSTMAP; '.
In addition to this special wires, techmap also supports special parameters in
modules in the map file:
_TECHMAP_CELLTYPE_
When a parameter with this name exists, it will be set to the type name
of the cell that matches the module.
_TECHMAP_CONSTMSK_<port-name>_
_TECHMAP_CONSTVAL_<port-name>_
When this pair of parameters is available in a module for a port, then
former has a 1-bit for each constant input bit and the latter has the
value for this bit. The unused bits of the latter are set to undef (x).
_TECHMAP_BITS_CONNMAP_
_TECHMAP_CONNMAP_<port-name>_
For an N-bit port, the _TECHMAP_CONNMAP_<port-name>_ parameter, if it
exists, will be set to an N*_TECHMAP_BITS_CONNMAP_ bit vector containing
N words (of _TECHMAP_BITS_CONNMAP_ bits each) that assign each single
bit driver a unique id. The values 0-3 are reserved for 0, 1, x, and z.
This can be used to detect shorted inputs.
When a module in the map file has a parameter where the according cell in the
design has a port, the module from the map file is only used if the port in
the design is connected to a constant value. The parameter is then set to the
constant value.
A cell with the name _TECHMAP_REPLACE_ in the map file will inherit the name
of the cell that is being replaced.
See 'help extract' for a pass that does the opposite thing.
See 'help flatten' for a pass that does flatten the design (which is
essentially techmap but using the design itself as map library).
\end{lstlisting}
\section{tee -- redirect command output to file}
\label{cmd:tee}
\begin{lstlisting}[numbers=left,frame=single]
tee [-q] [-o logfile|-a logfile] cmd
Execute the specified command, optionally writing the commands output to the
specified logfile(s).
-q
Do not print output to the normal destination (console and/or log file)
-o logfile
Write output to this file, truncate if exists.
-a logfile
Write output to this file, append if exists.
\end{lstlisting}
\section{test\_abcloop -- automatically test handling of loops in abc command}
\label{cmd:test_abcloop}
\begin{lstlisting}[numbers=left,frame=single]
test_abcloop [options]
Test handling of logic loops in ABC.
-n {integer}
create this number of circuits and test them (default = 100).
-s {positive_integer}
use this value as rng seed value (default = unix time).
\end{lstlisting}
\section{test\_autotb -- generate simple test benches}
\label{cmd:test_autotb}
\begin{lstlisting}[numbers=left,frame=single]
test_autotb [options] [filename]
Automatically create primitive Verilog test benches for all modules in the
design. The generated testbenches toggle the input pins of the module in
a semi-random manner and dumps the resulting output signals.
This can be used to check the synthesis results for simple circuits by
comparing the testbench output for the input files and the synthesis results.
The backend automatically detects clock signals. Additionally a signal can
be forced to be interpreted as clock signal by setting the attribute
'gentb_clock' on the signal.
The attribute 'gentb_constant' can be used to force a signal to a constant
value after initialization. This can e.g. be used to force a reset signal
low in order to explore more inner states in a state machine.
-n <int>
number of iterations the test bench should run (default = 1000)
\end{lstlisting}
\section{test\_cell -- automatically test the implementation of a cell type}
\label{cmd:test_cell}
\begin{lstlisting}[numbers=left,frame=single]
test_cell [options] {cell-types}
Tests the internal implementation of the given cell type (for example '$add')
by comparing SAT solver, EVAL and TECHMAP implementations of the cell types..
Run with 'all' instead of a cell type to run the test on all supported
cell types. Use for example 'all /$add' for all cell types except $add.
-n {integer}
create this number of cell instances and test them (default = 100).
-s {positive_integer}
use this value as rng seed value (default = unix time).
-f {ilang_file}
don't generate circuits. instead load the specified ilang file.
-w {filename_prefix}
don't test anything. just generate the circuits and write them
to ilang files with the specified prefix
-map {filename}
pass this option to techmap.
-simlib
use "techmap -map +/simlib.v -max_iter 2 -autoproc"
-aigmap
instead of calling "techmap", call "aigmap"
-muxdiv
when creating test benches with dividers, create an additional mux
to mask out the division-by-zero case
-script {script_file}
instead of calling "techmap", call "script {script_file}".
-const
set some input bits to random constant values
-nosat
do not check SAT model or run SAT equivalence checking
-noeval
do not check const-eval models
-v
print additional debug information to the console
-vlog {filename}
create a Verilog test bench to test simlib and write_verilog
\end{lstlisting}
\section{torder -- print cells in topological order}
\label{cmd:torder}
\begin{lstlisting}[numbers=left,frame=single]
torder [options] [selection]
This command prints the selected cells in topological order.
-stop <cell_type> <cell_port>
do not use the specified cell port in topological sorting
-noautostop
by default Q outputs of internal FF cells and memory read port outputs
are not used in topological sorting. this option deactivates that.
\end{lstlisting}
\section{trace -- redirect command output to file}
\label{cmd:trace}
\begin{lstlisting}[numbers=left,frame=single]
trace cmd
Execute the specified command, logging all changes the command performs on
the design in real time.
\end{lstlisting}
\section{tribuf -- infer tri-state buffers}
\label{cmd:tribuf}
\begin{lstlisting}[numbers=left,frame=single]
tribuf [options] [selection]
This pass transforms $mux cells with 'z' inputs to tristate buffers.
-merge
merge multiple tri-state buffers driving the same net
into a single buffer.
-logic
convert tri-state buffers that do not drive output ports
to non-tristate logic. this option implies -merge.
\end{lstlisting}
\section{verific -- load Verilog and VHDL designs using Verific}
\label{cmd:verific}
\begin{lstlisting}[numbers=left,frame=single]
verific {-vlog95|-vlog2k|-sv2005|-sv2009|-sv} <verilog-file>..
Load the specified Verilog/SystemVerilog files into Verific.
verific {-vhdl87|-vhdl93|-vhdl2k|-vhdl2008} <vhdl-file>..
Load the specified VHDL files into Verific.
verific -import [-gates] {-all | <top-module>..}
Elaborate the design for the specified top modules, import to Yosys and
reset the internal state of Verific. A gate-level netlist is created
when called with -gates.
Visit http://verific.com/ for more information on Verific.
\end{lstlisting}
\section{verilog\_defaults -- set default options for read\_verilog}
\label{cmd:verilog_defaults}
\begin{lstlisting}[numbers=left,frame=single]
verilog_defaults -add [options]
Add the specified options to the list of default options to read_verilog.
verilog_defaults -clear
Clear the list of Verilog default options.
verilog_defaults -push verilog_defaults -pop
Push or pop the list of default options to a stack. Note that -push does
not imply -clear.
\end{lstlisting}
\section{vhdl2verilog -- importing VHDL designs using vhdl2verilog}
\label{cmd:vhdl2verilog}
\begin{lstlisting}[numbers=left,frame=single]
vhdl2verilog [options] <vhdl-file>..
This command reads VHDL source files using the 'vhdl2verilog' tool and the
Yosys Verilog frontend.
-out <out_file>
do not import the vhdl2verilog output. instead write it to the
specified file.
-vhdl2verilog_dir <directory>
do use the specified vhdl2verilog installation. this is the directory
that contains the setup_env.sh file. when this option is not present,
it is assumed that vhdl2verilog is in the PATH environment variable.
-top <top-entity-name>
The name of the top entity. This option is mandatory.
The following options are passed as-is to vhdl2verilog:
-arch <architecture_name>
-unroll_generate
-nogenericeval
-nouniquify
-oldparser
-suppress <list>
-quiet
-nobanner
-mapfile <file>
vhdl2verilog can be obtained from:
http://www.edautils.com/vhdl2verilog.html
\end{lstlisting}
\section{wreduce -- reduce the word size of operations if possible}
\label{cmd:wreduce}
\begin{lstlisting}[numbers=left,frame=single]
wreduce [options] [selection]
This command reduces the word size of operations. For example it will replace
the 32 bit adders in the following code with adders of more appropriate widths:
module test(input [3:0] a, b, c, output [7:0] y);
assign y = a + b + c + 1;
endmodule
\end{lstlisting}
\section{write\_blif -- write design to BLIF file}
\label{cmd:write_blif}
\begin{lstlisting}[numbers=left,frame=single]
write_blif [options] [filename]
Write the current design to an BLIF file.
-top top_module
set the specified module as design top module
-buf <cell-type> <in-port> <out-port>
use cells of type <cell-type> with the specified port names for buffers
-unbuf <cell-type> <in-port> <out-port>
replace buffer cells with the specified name and port names with
a .names statement that models a buffer
-true <cell-type> <out-port>
-false <cell-type> <out-port>
-undef <cell-type> <out-port>
use the specified cell types to drive nets that are constant 1, 0, or
undefined. when '-' is used as <cell-type>, then <out-port> specifies
the wire name to be used for the constant signal and no cell driving
that wire is generated.
The following options can be useful when the generated file is not going to be
read by a BLIF parser but a custom tool. It is recommended to not name the output
file *.blif when any of this options is used.
-icells
do not translate Yosys's internal gates to generic BLIF logic
functions. Instead create .subckt or .gate lines for all cells.
-gates
print .gate instead of .subckt lines for all cells that are not
instantiations of other modules from this design.
-conn
do not generate buffers for connected wires. instead use the
non-standard .conn statement.
-attr
use the non-standard .attr statement to write cell attributes
-param
use the non-standard .param statement to write cell parameters
-cname
use the non-standard .cname statement to write cell names
-blackbox
write blackbox cells with .blackbox statement.
-impltf
do not write definitions for the $true, $false and $undef wires.
\end{lstlisting}
\section{write\_btor -- write design to BTOR file}
\label{cmd:write_btor}
\begin{lstlisting}[numbers=left,frame=single]
write_btor [filename]
Write the current design to an BTOR file.
\end{lstlisting}
\section{write\_edif -- write design to EDIF netlist file}
\label{cmd:write_edif}
\begin{lstlisting}[numbers=left,frame=single]
write_edif [options] [filename]
Write the current design to an EDIF netlist file.
-top top_module
set the specified module as design top module
Unfortunately there are different "flavors" of the EDIF file format. This
command generates EDIF files for the Xilinx place&route tools. It might be
necessary to make small modifications to this command when a different tool
is targeted.
\end{lstlisting}
\section{write\_file -- write a text to a file}
\label{cmd:write_file}
\begin{lstlisting}[numbers=left,frame=single]
write_file [options] output_file [input_file]
Write the text from the input file to the output file.
-a
Append to output file (instead of overwriting)
Inside a script the input file can also can a here-document:
write_file hello.txt <<EOT
Hello World!
EOT
\end{lstlisting}
\section{write\_ilang -- write design to ilang file}
\label{cmd:write_ilang}
\begin{lstlisting}[numbers=left,frame=single]
write_ilang [filename]
Write the current design to an 'ilang' file. (ilang is a text representation
of a design in yosys's internal format.)
-selected
only write selected parts of the design.
\end{lstlisting}
\section{write\_intersynth -- write design to InterSynth netlist file}
\label{cmd:write_intersynth}
\begin{lstlisting}[numbers=left,frame=single]
write_intersynth [options] [filename]
Write the current design to an 'intersynth' netlist file. InterSynth is
a tool for Coarse-Grain Example-Driven Interconnect Synthesis.
-notypes
do not generate celltypes and conntypes commands. i.e. just output
the netlists. this is used for postsilicon synthesis.
-lib <verilog_or_ilang_file>
Use the specified library file for determining whether cell ports are
inputs or outputs. This option can be used multiple times to specify
more than one library.
-selected
only write selected modules. modules must be selected entirely or
not at all.
http://www.clifford.at/intersynth/
\end{lstlisting}
\section{write\_json -- write design to a JSON file}
\label{cmd:write_json}
\begin{lstlisting}[numbers=left,frame=single]
write_json [options] [filename]
Write a JSON netlist of the current design.
-aig
include AIG models for the different gate types
The general syntax of the JSON output created by this command is as follows:
{
"modules": {
<module_name>: {
"ports": {
<port_name>: <port_details>,
...
},
"cells": {
<cell_name>: <cell_details>,
...
},
"netnames": {
<net_name>: <net_details>,
...
}
}
},
"models": {
...
},
}
Where <port_details> is:
{
"direction": <"input" | "output" | "inout">,
"bits": <bit_vector>
}
And <cell_details> is:
{
"hide_name": <1 | 0>,
"type": <cell_type>,
"parameters": {
<parameter_name>: <parameter_value>,
...
},
"attributes": {
<attribute_name>: <attribute_value>,
...
},
"port_directions": {
<port_name>: <"input" | "output" | "inout">,
...
},
"connections": {
<port_name>: <bit_vector>,
...
},
}
And <net_details> is:
{
"hide_name": <1 | 0>,
"bits": <bit_vector>
}
The "hide_name" fields are set to 1 when the name of this cell or net is
automatically created and is likely not of interest for a regular user.
The "port_directions" section is only included for cells for which the
interface is known.
Module and cell ports and nets can be single bit wide or vectors of multiple
bits. Each individual signal bit is assigned a unique integer. The <bit_vector>
values referenced above are vectors of this integers. Signal bits that are
connected to a constant driver are denoted as string "0" or "1" instead of
a number.
For example the following Verilog code:
module test(input x, y);
(* keep *) foo #(.P(42), .Q(1337))
foo_inst (.A({x, y}), .B({y, x}), .C({4'd10, {4{x}}}));
endmodule
Translates to the following JSON output:
{
"modules": {
"test": {
"ports": {
"x": {
"direction": "input",
"bits": [ 2 ]
},
"y": {
"direction": "input",
"bits": [ 3 ]
}
},
"cells": {
"foo_inst": {
"hide_name": 0,
"type": "foo",
"parameters": {
"Q": 1337,
"P": 42
},
"attributes": {
"keep": 1,
"src": "test.v:2"
},
"connections": {
"C": [ 2, 2, 2, 2, "0", "1", "0", "1" ],
"B": [ 2, 3 ],
"A": [ 3, 2 ]
}
}
},
"netnames": {
"y": {
"hide_name": 0,
"bits": [ 3 ],
"attributes": {
"src": "test.v:1"
}
},
"x": {
"hide_name": 0,
"bits": [ 2 ],
"attributes": {
"src": "test.v:1"
}
}
}
}
}
}
The models are given as And-Inverter-Graphs (AIGs) in the following form:
"models": {
<model_name>: [
/* 0 */ [ <node-spec> ],
/* 1 */ [ <node-spec> ],
/* 2 */ [ <node-spec> ],
...
],
...
},
The following node-types may be used:
[ "port", <portname>, <bitindex>, <out-list> ]
- the value of the specified input port bit
[ "nport", <portname>, <bitindex>, <out-list> ]
- the inverted value of the specified input port bit
[ "and", <node-index>, <node-index>, <out-list> ]
- the ANDed value of the specified nodes
[ "nand", <node-index>, <node-index>, <out-list> ]
- the inverted ANDed value of the specified nodes
[ "true", <out-list> ]
- the constant value 1
[ "false", <out-list> ]
- the constant value 0
All nodes appear in topological order. I.e. only nodes with smaller indices
are referenced by "and" and "nand" nodes.
The optional <out-list> at the end of a node specification is a list of
output portname and bitindex pairs, specifying the outputs driven by this node.
For example, the following is the model for a 3-input 3-output $reduce_and cell
inferred by the following code:
module test(input [2:0] in, output [2:0] out);
assign in = &out;
endmodule
"$reduce_and:3U:3": [
/* 0 */ [ "port", "A", 0 ],
/* 1 */ [ "port", "A", 1 ],
/* 2 */ [ "and", 0, 1 ],
/* 3 */ [ "port", "A", 2 ],
/* 4 */ [ "and", 2, 3, "Y", 0 ],
/* 5 */ [ "false", "Y", 1, "Y", 2 ]
]
Future version of Yosys might add support for additional fields in the JSON
format. A program processing this format must ignore all unknown fields.
\end{lstlisting}
\section{write\_smt2 -- write design to SMT-LIBv2 file}
\label{cmd:write_smt2}
\begin{lstlisting}[numbers=left,frame=single]
write_smt2 [options] [filename]
Write a SMT-LIBv2 [1] description of the current design. For a module with name
'<mod>' this will declare the sort '<mod>_s' (state of the module) and the
functions operating on that state.
The '<mod>_s' sort represents a module state. Additional '<mod>_n' functions
are provided that can be used to access the values of the signals in the module.
Only ports, and signals with the 'keep' attribute set are made available via
such functions. Without the -bv option, multi-bit wires are exported as
separate functions of type Bool for the individual bits. With the -bv option
multi-bit wires are exported as single functions of type BitVec.
The '<mod>_t' function evaluates to 'true' when the given pair of states
describes a valid state transition.
The '<mod>_a' function evaluates to 'true' when the given state satisfies
the asserts in the module.
The '<mod>_u' function evaluates to 'true' when the given state satisfies
the assumptions in the module.
The '<mod>_i' function evaluates to 'true' when the given state conforms
to the initial state.
-verbose
this will print the recursive walk used to export the modules.
-bv
enable support for BitVec (FixedSizeBitVectors theory). with this
option set multi-bit wires are represented using the BitVec sort and
support for coarse grain cells (incl. arithmetic) is enabled.
-mem
enable support for memories (via ArraysEx theory). this option
also implies -bv. only $mem cells without merged registers in
read ports are supported. call "memory" with -nordff to make sure
that no registers are merged into $mem read ports. '<mod>_m' functions
will be generated for accessing the arrays that are used to represent
memories.
-regs
also create '<mod>_n' functions for all registers.
-wires
also create '<mod>_n' functions for all public wires.
-tpl <template_file>
use the given template file. the line containing only the token '%%'
is replaced with the regular output of this command.
[1] For more information on SMT-LIBv2 visit http://smt-lib.org/ or read David
R. Cok's tutorial: http://www.grammatech.com/resources/smt/SMTLIBTutorial.pdf
---------------------------------------------------------------------------
Example:
Consider the following module (test.v). We want to prove that the output can
never transition from a non-zero value to a zero value.
module test(input clk, output reg [3:0] y);
always @(posedge clk)
y <= (y << 1) | ^y;
endmodule
For this proof we create the following template (test.tpl).
; we need QF_UFBV for this poof
(set-logic QF_UFBV)
; insert the auto-generated code here
%%
; declare two state variables s1 and s2
(declare-fun s1 () test_s)
(declare-fun s2 () test_s)
; state s2 is the successor of state s1
(assert (test_t s1 s2))
; we are looking for a model with y non-zero in s1
(assert (distinct (|test_n y| s1) #b0000))
; we are looking for a model with y zero in s2
(assert (= (|test_n y| s2) #b0000))
; is there such a model?
(check-sat)
The following yosys script will create a 'test.smt2' file for our proof:
read_verilog test.v
hierarchy -check; proc; opt; check -assert
write_smt2 -bv -tpl test.tpl test.smt2
Running 'cvc4 test.smt2' will print 'unsat' because y can never transition
from non-zero to zero in the test design.
\end{lstlisting}
\section{write\_smv -- write design to SMV file}
\label{cmd:write_smv}
\begin{lstlisting}[numbers=left,frame=single]
write_smv [options] [filename]
Write an SMV description of the current design.
-verbose
this will print the recursive walk used to export the modules.
-tpl <template_file>
use the given template file. the line containing only the token '%%'
is replaced with the regular output of this command.
THIS COMMAND IS UNDER CONSTRUCTION
\end{lstlisting}
\section{write\_spice -- write design to SPICE netlist file}
\label{cmd:write_spice}
\begin{lstlisting}[numbers=left,frame=single]
write_spice [options] [filename]
Write the current design to an SPICE netlist file.
-big_endian
generate multi-bit ports in MSB first order
(default is LSB first)
-neg net_name
set the net name for constant 0 (default: Vss)
-pos net_name
set the net name for constant 1 (default: Vdd)
-nc_prefix
prefix for not-connected nets (default: _NC)
-top top_module
set the specified module as design top module
\end{lstlisting}
\section{write\_verilog -- write design to Verilog file}
\label{cmd:write_verilog}
\begin{lstlisting}[numbers=left,frame=single]
write_verilog [options] [filename]
Write the current design to a Verilog file.
-norename
without this option all internal object names (the ones with a dollar
instead of a backslash prefix) are changed to short names in the
format '_<number>_'.
-noattr
with this option no attributes are included in the output
-attr2comment
with this option attributes are included as comments in the output
-noexpr
without this option all internal cells are converted to Verilog
expressions.
-blackboxes
usually modules with the 'blackbox' attribute are ignored. with
this option set only the modules with the 'blackbox' attribute
are written to the output file.
-selected
only write selected modules. modules must be selected entirely or
not at all.
\end{lstlisting}
