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module \$pmux (A, B, S, Y);

wire [1023:0] _TECHMAP_DO_ = "proc; clean";

parameter WIDTH = 1;
parameter S_WIDTH = 1;

input [WIDTH-1:0] A;
input [WIDTH*S_WIDTH-1:0] B;
input [S_WIDTH-1:0] S;
output reg [WIDTH-1:0] Y;

integer i;

always @* begin
	Y <= A;
	for (i = 0; i < S_WIDTH; i=i+1)
		if (S[i]) Y <= B[WIDTH*i +: WIDTH];
end

endmodule
an>IREG_PRE_B("FALSE"), .IS_CLK_INVERTED(!CLKPOL2), .OREG_A("FALSE"), .OREG_B("FALSE") ) _TECHMAP_REPLACE_ ( .ADDR_A({11'b0, A1ADDR}), .BWE_A(9'b0), .DIN_A(72'b0), .EN_A(A1EN), .RDB_WR_A(1'b0), .INJECT_DBITERR_A(1'b0), .INJECT_SBITERR_A(1'b0), .RST_A(1'b0), .DOUT_A(A1DATA), .ADDR_B({11'b0, B1ADDR}), .BWE_B(B1EN), .DIN_B(B1DATA), .EN_B(|B1EN), .RDB_WR_B(1'b1), .INJECT_DBITERR_B(1'b0), .INJECT_SBITERR_B(1'b0), .RST_B(1'b0), .CLK(CLK2), .SLEEP(1'b0) ); endmodule