#! /bin/sh . ../../testenv.sh analyze test.vhd elab_simulate test clean echo "Test successful" >

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path: root/tests/asicworld/code_tidbits_wire_example.v

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module wire_example( a, b, y);
  input a, b;
  output y;

  wire a, b, y;

  assign y = a & b;

endmodule