tests/asicworld/code_verilog_tutorial_comment.v


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25pre { line-height: 125%; margin: 0; /* This is a
  Multi line comment
  example */
module addbit (
a,
b,
ci,
sum,
co);

// Input Ports  Single line comment
input           a;
input           b;
input           ci;
// Output ports
output         sum;
output         co;
// Data Types      
wire            a;
wire            b;
wire            ci;
wire            sum;
wire            co; 

endmodule