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author | root <root@artemis.panaceas.org> | 2015-12-25 04:40:36 +0000 |
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committer | root <root@artemis.panaceas.org> | 2015-12-25 04:40:36 +0000 |
commit | 849369d6c66d3054688672f97d31fceb8e8230fb (patch) | |
tree | 6135abc790ca67dedbe07c39806591e70eda81ce /arch/arm/plat-mxc/include/mach/irqs.h | |
download | linux-3.0.35-kobo-849369d6c66d3054688672f97d31fceb8e8230fb.tar.gz linux-3.0.35-kobo-849369d6c66d3054688672f97d31fceb8e8230fb.tar.bz2 linux-3.0.35-kobo-849369d6c66d3054688672f97d31fceb8e8230fb.zip |
initial_commit
Diffstat (limited to 'arch/arm/plat-mxc/include/mach/irqs.h')
-rw-r--r-- | arch/arm/plat-mxc/include/mach/irqs.h | 91 |
1 files changed, 91 insertions, 0 deletions
diff --git a/arch/arm/plat-mxc/include/mach/irqs.h b/arch/arm/plat-mxc/include/mach/irqs.h new file mode 100644 index 00000000..62282a95 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/irqs.h @@ -0,0 +1,91 @@ +/* + * Copyright 2004-2013 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_MXC_IRQS_H__ +#define __ASM_ARCH_MXC_IRQS_H__ + +/* + * SoCs with TZIC interrupt controller have 128 IRQs, those with AVIC have 64 + */ +#ifdef CONFIG_MXC_TZIC +#define MXC_INTERNAL_IRQS 128 +#elif defined CONFIG_ARM_GIC +/* assuem 256 is enough for GIC */ +#define MXC_INTERNAL_IRQS 256 +#else +#define MXC_INTERNAL_IRQS 64 +#endif + +#define MXC_GPIO_IRQ_START MXC_INTERNAL_IRQS + +/* these are ordered by size to support multi-SoC kernels */ +#if defined CONFIG_SOC_IMX53 +#define MXC_GPIO_IRQS (32 * 7) +#elif defined CONFIG_ARCH_MX2 +#define MXC_GPIO_IRQS (32 * 6) +#elif defined CONFIG_SOC_IMX50 +#define MXC_GPIO_IRQS (32 * 6) +#elif defined CONFIG_ARCH_MX1 +#define MXC_GPIO_IRQS (32 * 4) +#elif defined CONFIG_ARCH_MX25 +#define MXC_GPIO_IRQS (32 * 4) +#elif defined CONFIG_SOC_IMX51 +#define MXC_GPIO_IRQS (32 * 4) +#elif defined CONFIG_ARCH_MX3 +#define MXC_GPIO_IRQS (32 * 3) +#elif defined CONFIG_ARCH_MX6 +#define MXC_GPIO_IRQS (32 * 7) +#endif + +/* + * The next 16 interrupts are for board specific purposes. Since + * the kernel can only run on one machine at a time, we can re-use + * these. If you need more, increase MXC_BOARD_IRQS, but keep it + * within sensible limits. + */ +#define MXC_BOARD_IRQ_START (MXC_INTERNAL_IRQS + MXC_GPIO_IRQS) + +#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1 +#define MXC_BOARD_IRQS 80 +#else +#define MXC_BOARD_IRQS 16 +#endif + +#define MXC_IPU_IRQ_START (MXC_BOARD_IRQ_START + MXC_BOARD_IRQS) + +#ifdef CONFIG_MX3_IPU_IRQS +#define MX3_IPU_IRQS CONFIG_MX3_IPU_IRQS +#else +#define MX3_IPU_IRQS 0 +#endif + +#ifdef CONFIG_ARCH_MX5 +#define MX5_IPU_IRQS (32*15) +#else +#define MX5_IPU_IRQS 0 +#endif + +#ifdef CONFIG_ARCH_MX6 +#define MX6_MSI_IRQS 128 +#else +#define MX6_MSI_IRQS 0 +#endif + +#define IRQ_IMX_MSI_0 (MXC_IPU_IRQ_START + MX3_IPU_IRQS + MX5_IPU_IRQS) +#define NR_IRQS (IRQ_IMX_MSI_0 + MX6_MSI_IRQS) + +extern int imx_irq_set_priority(unsigned char irq, unsigned char prio); + +/* all normal IRQs can be FIQs */ +#define FIQ_START 0 +/* switch between IRQ and FIQ */ +extern int mxc_set_irq_fiq(unsigned int irq, unsigned int type); + +#endif /* __ASM_ARCH_MXC_IRQS_H__ */ |