diff options
Diffstat (limited to 'arch/arm/plat-mxc')
208 files changed, 49404 insertions, 0 deletions
diff --git a/arch/arm/plat-mxc/3ds_debugboard.c b/arch/arm/plat-mxc/3ds_debugboard.c new file mode 100644 index 00000000..f0ba0726 --- /dev/null +++ b/arch/arm/plat-mxc/3ds_debugboard.c @@ -0,0 +1,196 @@ +/* + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2010 Jason Wang <jason77.wang@gmail.com> + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/io.h> +#include <linux/platform_device.h> +#include <linux/gpio.h> +#include <linux/smsc911x.h> + +#include <mach/hardware.h> + +/* LAN9217 ethernet base address */ +#define LAN9217_BASE_ADDR(n) (n + 0x0) +/* External UART */ +#define UARTA_BASE_ADDR(n) (n + 0x8000) +#define UARTB_BASE_ADDR(n) (n + 0x10000) + +#define BOARD_IO_ADDR(n) (n + 0x20000) +/* LED switchs */ +#define LED_SWITCH_REG 0x00 +/* buttons */ +#define SWITCH_BUTTONS_REG 0x08 +/* status, interrupt */ +#define INTR_STATUS_REG 0x10 +#define INTR_MASK_REG 0x38 +#define INTR_RESET_REG 0x20 +/* magic word for debug CPLD */ +#define MAGIC_NUMBER1_REG 0x40 +#define MAGIC_NUMBER2_REG 0x48 +/* CPLD code version */ +#define CPLD_CODE_VER_REG 0x50 +/* magic word for debug CPLD */ +#define MAGIC_NUMBER3_REG 0x58 +/* module reset register*/ +#define MODULE_RESET_REG 0x60 +/* CPU ID and Personality ID */ +#define MCU_BOARD_ID_REG 0x68 + +#define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_BOARD_IRQ_START) +#define MXC_IRQ_TO_GPIO(irq) ((irq) - MXC_INTERNAL_IRQS) + +#define MXC_EXP_IO_BASE (MXC_BOARD_IRQ_START) +#define MXC_MAX_EXP_IO_LINES 16 + +/* interrupts like external uart , external ethernet etc*/ +#define EXPIO_INT_ENET (MXC_BOARD_IRQ_START + 0) +#define EXPIO_INT_XUART_A (MXC_BOARD_IRQ_START + 1) +#define EXPIO_INT_XUART_B (MXC_BOARD_IRQ_START + 2) +#define EXPIO_INT_BUTTON_A (MXC_BOARD_IRQ_START + 3) +#define EXPIO_INT_BUTTON_B (MXC_BOARD_IRQ_START + 4) + +static void __iomem *brd_io; + +static struct resource smsc911x_resources[] = { + { + .flags = IORESOURCE_MEM, + } , { + .start = EXPIO_INT_ENET, + .end = EXPIO_INT_ENET, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct smsc911x_platform_config smsc911x_config = { + .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, + .flags = SMSC911X_USE_32BIT | SMSC911X_FORCE_INTERNAL_PHY, +}; + +static struct platform_device smsc_lan9217_device = { + .name = "smsc911x", + .id = 0, + .dev = { + .platform_data = &smsc911x_config, + }, + .num_resources = ARRAY_SIZE(smsc911x_resources), + .resource = smsc911x_resources, +}; + +static void mxc_expio_irq_handler(u32 irq, struct irq_desc *desc) +{ + u32 imr_val; + u32 int_valid; + u32 expio_irq; + + /* irq = gpio irq number */ + desc->irq_data.chip->irq_mask(&desc->irq_data); + + imr_val = __raw_readw(brd_io + INTR_MASK_REG); + int_valid = __raw_readw(brd_io + INTR_STATUS_REG) & ~imr_val; + + expio_irq = MXC_BOARD_IRQ_START; + for (; int_valid != 0; int_valid >>= 1, expio_irq++) { + if ((int_valid & 1) == 0) + continue; + generic_handle_irq(expio_irq); + } + + desc->irq_data.chip->irq_ack(&desc->irq_data); + desc->irq_data.chip->irq_unmask(&desc->irq_data); +} + +/* + * Disable an expio pin's interrupt by setting the bit in the imr. + * Irq is an expio virtual irq number + */ +static void expio_mask_irq(struct irq_data *d) +{ + u16 reg; + u32 expio = MXC_IRQ_TO_EXPIO(d->irq); + + reg = __raw_readw(brd_io + INTR_MASK_REG); + reg |= (1 << expio); + __raw_writew(reg, brd_io + INTR_MASK_REG); +} + +static void expio_ack_irq(struct irq_data *d) +{ + u32 expio = MXC_IRQ_TO_EXPIO(d->irq); + + __raw_writew(1 << expio, brd_io + INTR_RESET_REG); + __raw_writew(0, brd_io + INTR_RESET_REG); + expio_mask_irq(d); +} + +static void expio_unmask_irq(struct irq_data *d) +{ + u16 reg; + u32 expio = MXC_IRQ_TO_EXPIO(d->irq); + + reg = __raw_readw(brd_io + INTR_MASK_REG); + reg &= ~(1 << expio); + __raw_writew(reg, brd_io + INTR_MASK_REG); +} + +static struct irq_chip expio_irq_chip = { + .irq_ack = expio_ack_irq, + .irq_mask = expio_mask_irq, + .irq_unmask = expio_unmask_irq, +}; + +int __init mxc_expio_init(u32 base, u32 p_irq) +{ + int i; + + brd_io = ioremap(BOARD_IO_ADDR(base), SZ_4K); + if (brd_io == NULL) + return -ENOMEM; + + if ((__raw_readw(brd_io + MAGIC_NUMBER1_REG) != 0xAAAA) || + (__raw_readw(brd_io + MAGIC_NUMBER2_REG) != 0x5555) || + (__raw_readw(brd_io + MAGIC_NUMBER3_REG) != 0xCAFE)) { + pr_info("3-Stack Debug board not detected\n"); + iounmap(brd_io); + brd_io = NULL; + return -ENODEV; + } + + pr_info("3-Stack Debug board detected, rev = 0x%04X\n", + readw(brd_io + CPLD_CODE_VER_REG)); + + /* + * Configure INT line as GPIO input + */ + gpio_request(MXC_IRQ_TO_GPIO(p_irq), "expio_pirq"); + gpio_direction_input(MXC_IRQ_TO_GPIO(p_irq)); + + /* disable the interrupt and clear the status */ + __raw_writew(0, brd_io + INTR_MASK_REG); + __raw_writew(0xFFFF, brd_io + INTR_RESET_REG); + __raw_writew(0, brd_io + INTR_RESET_REG); + __raw_writew(0x1F, brd_io + INTR_MASK_REG); + for (i = MXC_EXP_IO_BASE; + i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES); i++) { + irq_set_chip_and_handler(i, &expio_irq_chip, handle_level_irq); + set_irq_flags(i, IRQF_VALID); + } + irq_set_irq_type(p_irq, IRQF_TRIGGER_LOW); + irq_set_chained_handler(p_irq, mxc_expio_irq_handler); + + /* Register Lan device on the debugboard */ + smsc911x_resources[0].start = LAN9217_BASE_ADDR(base); + smsc911x_resources[0].end = LAN9217_BASE_ADDR(base) + 0x100 - 1; + platform_device_register(&smsc_lan9217_device); + + return 0; +} diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig new file mode 100755 index 00000000..32408ed9 --- /dev/null +++ b/arch/arm/plat-mxc/Kconfig @@ -0,0 +1,173 @@ +if ARCH_MXC + +source "arch/arm/plat-mxc/devices/Kconfig" + +menu "Freescale MXC Implementations" + +config ARCH_MX50_SUPPORTED + bool + +config ARCH_MX53_SUPPORTED + bool + +choice + prompt "Freescale CPU family:" + default ARCH_MX3 + +config ARCH_MX1 + bool "MX1-based" + help + This enables support for systems based on the Freescale i.MX1 family + +config ARCH_MX2 + bool "MX2-based" + help + This enables support for systems based on the Freescale i.MX2 family + +config ARCH_MX25 + bool "MX25-based" + help + This enables support for systems based on the Freescale i.MX25 family + +config ARCH_MX3 + bool "MX3-based" + help + This enables support for systems based on the Freescale i.MX3 family + +config ARCH_MX503 + bool "i.MX50 + i.MX53" + select ARCH_MX50_SUPPORTED + select ARCH_MX53_SUPPORTED + help + This enables support for machines using Freescale's i.MX50 and i.MX51 + processors. + +config ARCH_MX51 + bool "i.MX51" + select ARCH_MX51_SUPPORTED + help + This enables support for systems based on the Freescale i.MX51 family + +config ARCH_MX6 + bool "MX6-based" + select CPU_V7 + help + This enable support for systems based on the Freescale i.MX 6 Series family + +endchoice + +source "arch/arm/mach-imx/Kconfig" +source "arch/arm/mach-mx5/Kconfig" +source "arch/arm/mach-mx6/Kconfig" + +endmenu +## Freescale private USB driver support +# set if we need the 1504 transceiver +config ISP1504_MXC + bool + default y + +# set if we need the UTMI transceiver +config UTMI_MXC + bool + default y + depends on ARCH_MX25 || ARCH_MX35 || ARCH_MX37 || ARCH_MX5 + +config MXC_IRQ_PRIOR + bool "Use IRQ priority" + help + Select this if you want to use prioritized IRQ handling. + This feature prevents higher priority ISR to be interrupted + by lower priority IRQ even IRQF_DISABLED flag is not set. + This may be useful in embedded applications, where are strong + requirements for timing. + Say N here, unless you have a specialized requirement. + +config MXC_TZIC + bool + +config MXC_AVIC + bool + +config MXC_PWM + tristate "Enable PWM driver" + select HAVE_PWM + help + Enable support for the i.MX PWM controller(s). + +config MXC_DEBUG_BOARD + bool "Enable MXC debug board(for 3-stack)" + help + The debug board is an integral part of the MXC 3-stack(PDK) + platforms, it can be attached or removed from the peripheral + board. On debug board, several debug devices(ethernet, UART, + buttons, LEDs and JTAG) are implemented. Between the MCU and + these devices, a CPLD is added as a bridge which performs + data/address de-multiplexing and decode, signal level shift, + interrupt control and various board functions. + +config HAVE_EPIT + bool + +config MXC_REBOOT_MFGMODE + bool "Enable reboot to MFG mode function" + help + Enable this config to perform "reboot download" to enter download mode. + +config MXC_REBOOT_ANDROID_CMD + bool "Enable reboot to android recovery and android fastboot" + help + Enable this config to use "reboot fastboot", "reboot recovery" to + enter fastboot and recovery mode. + +config MXC_USE_EPIT + bool "Use EPIT instead of GPT" + depends on HAVE_EPIT + help + Use EPIT as the system timer on systems that have it. Normally you + don't have a reason to do so as the EPIT has the same features and + uses the same clocks as the GPT. Anyway, on some systems the GPT + may be in use for other purposes. + +config MXC_ULPI + bool + +config ARCH_HAS_RNGA + bool + +config ARCH_HAS_RNGC + bool + +config IMX_HAVE_IOMUX_V1 + bool + +config ARCH_MXC_IOMUX_V3 + bool + +config ARCH_MXC_AUDMUX_V1 + bool + +config ARCH_MXC_AUDMUX_V2 + bool + +config IRAM_ALLOC + bool + default y + select GENERIC_ALLOCATOR + +config CLK_DEBUG + bool "clock debug information export to user space" + depends on PM_DEBUG && DEBUG_FS + default n + help + export clk debug information to user space + +config DMA_ZONE_SIZE + int "DMA memory zone size" + range 0 184 + default 24 + help + This is the size in MB for the DMA zone. The DMA zone is used for + dedicated memory for large contiguous video buffers + +endif diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile new file mode 100755 index 00000000..1aa17802 --- /dev/null +++ b/arch/arm/plat-mxc/Makefile @@ -0,0 +1,40 @@ +# +# Makefile for the linux kernel. +# + +# Common support +obj-y := clock.o gpio.o time.o devices.o cpu.o system.o irq-common.o usb_common.o usb_wakeup.o fuse.o + +# MX51 uses the TZIC interrupt controller, older platforms use AVIC +obj-$(CONFIG_MXC_TZIC) += tzic.o +obj-$(CONFIG_MXC_AVIC) += avic.o + +obj-$(CONFIG_IMX_HAVE_IOMUX_V1) += iomux-v1.o +obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o +obj-$(CONFIG_IRAM_ALLOC) += iram_alloc.o +obj-$(CONFIG_MXC_PWM) += pwm.o +obj-$(CONFIG_MXC_ULPI) += ulpi.o +obj-$(CONFIG_MXC_USE_EPIT) += epit.o +obj-$(CONFIG_ARCH_MXC_AUDMUX_V1) += audmux-v1.o +obj-$(CONFIG_ARCH_MXC_AUDMUX_V2) += audmux-v2.o +obj-$(CONFIG_MXC_DEBUG_BOARD) += 3ds_debugboard.o +obj-$(CONFIG_CPU_FREQ_IMX) += cpufreq.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_AHCI) += ahci_sata.o +ifdef CONFIG_SND_IMX_SOC +obj-y += ssi-fiq.o +obj-y += ssi-fiq-ksym.o +endif + +obj-y += devices/ + +obj-$(CONFIG_ARCH_MX5) += dvfs_core.o +obj-$(CONFIG_ARCH_MX6) += dvfs_core.o + +# DVFS-PER support +obj-$(CONFIG_MXC_DVFS_PER) += dvfs_per.o + +# USB support +obj-$(CONFIG_ISP1504_MXC) += isp1504xc.o +obj-$(CONFIG_USB) += utmixc.o +obj-$(CONFIG_USB) += serialxc.o +obj-$(CONFIG_USB) += usb_hsic_xcvr.o diff --git a/arch/arm/plat-mxc/ahci_sata.c b/arch/arm/plat-mxc/ahci_sata.c new file mode 100644 index 00000000..de172a94 --- /dev/null +++ b/arch/arm/plat-mxc/ahci_sata.c @@ -0,0 +1,194 @@ +/* + * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <asm/errno.h> +#include <linux/io.h> +#include <linux/clk.h> +#include <linux/kernel.h> +#include <linux/delay.h> + +#include <mach/hardware.h> +#include <mach/ahci_sata.h> + +int write_phy_ctl_ack_polling(u32 data, void __iomem *mmio, + int max_iterations, u32 exp_val) +{ + u32 i, val; + + writel(data, mmio + PORT_PHY_CTL); + + for (i = 0; i < max_iterations + 1; i++) { + val = readl(mmio + PORT_PHY_SR); + val = (val >> PORT_PHY_STAT_ACK_LOC) & 0x1; + if (val == exp_val) + return 0; + if (i == max_iterations) { + pr_err("Wait for CR ACK error!\n"); + return 1; + } + usleep_range(100, 200); + } + return 0; +} + +int sata_phy_cr_addr(u32 addr, void __iomem *mmio) +{ + u32 temp_wr_data; + + /* write addr */ + temp_wr_data = addr; + writel(temp_wr_data, mmio + PORT_PHY_CTL); + + /* capture addr */ + temp_wr_data |= PORT_PHY_CTL_CAP_ADR_LOC; + + /* wait for ack */ + if (write_phy_ctl_ack_polling(temp_wr_data, mmio, 100, 1)) + return 1; + + /* deassert cap addr */ + temp_wr_data &= 0xffff; + + /* wait for ack de-assetion */ + if (write_phy_ctl_ack_polling(temp_wr_data, mmio, 100, 0)) + return 1; + + return 0; +} + +int sata_phy_cr_write(u32 data, void __iomem *mmio) +{ + u32 temp_wr_data; + + /* write data */ + temp_wr_data = data; + + /* capture data */ + temp_wr_data |= PORT_PHY_CTL_CAP_DAT_LOC; + + /* wait for ack */ + if (write_phy_ctl_ack_polling(temp_wr_data, mmio, 100, 1)) + return 1; + + /* deassert cap data */ + temp_wr_data &= 0xffff; + + /* wait for ack de-assetion */ + if (write_phy_ctl_ack_polling(temp_wr_data, mmio, 100, 0)) + return 1; + + /* assert wr signal */ + temp_wr_data |= PORT_PHY_CTL_WRITE_LOC; + + /* wait for ack */ + if (write_phy_ctl_ack_polling(temp_wr_data, mmio, 100, 1)) + return 1; + + /* deassert wr _signal */ + temp_wr_data = 0x0; + + /* wait for ack de-assetion */ + if (write_phy_ctl_ack_polling(temp_wr_data, mmio, 100, 0)) + return 1; + + return 0; +} + +int sata_phy_cr_read(u32 *data, void __iomem *mmio) +{ + u32 temp_rd_data, temp_wr_data; + + /* assert rd signal */ + temp_wr_data = PORT_PHY_CTL_READ_LOC; + + /* wait for ack */ + if (write_phy_ctl_ack_polling(temp_wr_data, mmio, 100, 1)) + return 1; + + /* after got ack return data */ + temp_rd_data = readl(mmio + PORT_PHY_SR); + *data = (temp_rd_data & 0xffff); + + /* deassert rd _signal */ + temp_wr_data = 0x0 ; + + /* wait for ack de-assetion */ + if (write_phy_ctl_ack_polling(temp_wr_data, mmio, 100, 0)) + return 1; + + return 0; +} + +/* AHCI module Initialization, if return 0, initialization is successful. */ +int sata_init(void __iomem *addr, unsigned long timer1ms) +{ + u32 tmpdata; + int iterations = 20; + + /* + * Make sure that SATA PHY is enabled + * The PDDQ mode is disabled. + */ + tmpdata = readl(addr + PORT_PHY_CTL); + writel(tmpdata & (~PORT_PHY_CTL_PDDQ_LOC), addr + PORT_PHY_CTL); + + /* Reset HBA */ + writel(HOST_RESET, addr + HOST_CTL); + + tmpdata = 0; + while (readl(addr + HOST_CAP) == 0) { + tmpdata++; + if (tmpdata > 100000) { + pr_err("Can't recover from RESET HBA!\n"); + break; + } + } + + tmpdata = readl(addr + HOST_CAP); + if (!(tmpdata & HOST_CAP_SSS)) { + tmpdata |= HOST_CAP_SSS; + writel(tmpdata, addr + HOST_CAP); + } + + if (!(readl(addr + HOST_PORTS_IMPL) & 0x1)) + writel((readl(addr + HOST_PORTS_IMPL) | 0x1), + addr + HOST_PORTS_IMPL); + + writel(timer1ms, addr + HOST_TIMER1MS); + + /* Release resources when there is no device on the port */ + do { + if ((readl(addr + PORT_SATA_SR) & 0xF) == 0) + usleep_range(1000, 2000); + else + break; + + if (iterations == 0) { + pr_info("No sata disk.\n"); + /* Enter into PDDQ mode, save power */ + tmpdata = readl(addr + PORT_PHY_CTL); + writel(tmpdata | PORT_PHY_CTL_PDDQ_LOC, + addr + PORT_PHY_CTL); + return -ENODEV; + } + } while (iterations-- > 0); + + return 0; +} diff --git a/arch/arm/plat-mxc/audmux-v1.c b/arch/arm/plat-mxc/audmux-v1.c new file mode 100644 index 00000000..1180bef7 --- /dev/null +++ b/arch/arm/plat-mxc/audmux-v1.c @@ -0,0 +1,64 @@ +/* + * Copyright 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> + * + * Initial development of this code was funded by + * Phytec Messtechnik GmbH, http://www.phytec.de + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/module.h> +#include <linux/err.h> +#include <linux/io.h> +#include <linux/clk.h> +#include <mach/audmux.h> +#include <mach/hardware.h> + +static void __iomem *audmux_base; + +static unsigned char port_mapping[] = { + 0x0, 0x4, 0x8, 0x10, 0x14, 0x1c, +}; + +int mxc_audmux_v1_configure_port(unsigned int port, unsigned int pcr) +{ + if (!audmux_base) { + printk("%s: not configured\n", __func__); + return -ENOSYS; + } + + if (port >= ARRAY_SIZE(port_mapping)) + return -EINVAL; + + writel(pcr, audmux_base + port_mapping[port]); + + return 0; +} +EXPORT_SYMBOL_GPL(mxc_audmux_v1_configure_port); + +static int mxc_audmux_v1_init(void) +{ +#ifdef CONFIG_MACH_MX21 + if (cpu_is_mx21()) + audmux_base = MX21_IO_ADDRESS(MX21_AUDMUX_BASE_ADDR); + else +#endif +#ifdef CONFIG_MACH_MX27 + if (cpu_is_mx27()) + audmux_base = MX27_IO_ADDRESS(MX27_AUDMUX_BASE_ADDR); + else +#endif + (void)0; + + return 0; +} + +postcore_initcall(mxc_audmux_v1_init); diff --git a/arch/arm/plat-mxc/audmux-v2.c b/arch/arm/plat-mxc/audmux-v2.c new file mode 100644 index 00000000..c36ddb34 --- /dev/null +++ b/arch/arm/plat-mxc/audmux-v2.c @@ -0,0 +1,234 @@ +/* + * Copyright 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> + * + * Initial development of this code was funded by + * Phytec Messtechnik GmbH, http://www.phytec.de + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/module.h> +#include <linux/err.h> +#include <linux/io.h> +#include <linux/clk.h> +#include <linux/debugfs.h> +#include <linux/slab.h> +#include <mach/audmux.h> +#include <mach/hardware.h> + +static struct clk *audmux_clk; +static void __iomem *audmux_base; + +#define MXC_AUDMUX_V2_PTCR(x) ((x) * 8) +#define MXC_AUDMUX_V2_PDCR(x) ((x) * 8 + 4) + +#ifdef CONFIG_DEBUG_FS +static struct dentry *audmux_debugfs_root; + +static int audmux_open_file(struct inode *inode, struct file *file) +{ + file->private_data = inode->i_private; + return 0; +} + +/* There is an annoying discontinuity in the SSI numbering with regard + * to the Linux number of the devices */ +static const char *audmux_port_string(int port) +{ + switch (port) { + case MX31_AUDMUX_PORT1_SSI0: + return "imx-ssi.0"; + case MX31_AUDMUX_PORT2_SSI1: + return "imx-ssi.1"; + case MX31_AUDMUX_PORT3_SSI_PINS_3: + return "SSI3"; + case MX31_AUDMUX_PORT4_SSI_PINS_4: + return "SSI4"; + case MX31_AUDMUX_PORT5_SSI_PINS_5: + return "SSI5"; + case MX31_AUDMUX_PORT6_SSI_PINS_6: + return "SSI6"; + default: + return "UNKNOWN"; + } +} + +static ssize_t audmux_read_file(struct file *file, char __user *user_buf, + size_t count, loff_t *ppos) +{ + ssize_t ret; + char *buf = kmalloc(PAGE_SIZE, GFP_KERNEL); + int port = (int)file->private_data; + u32 pdcr, ptcr; + + if (!buf) + return -ENOMEM; + + if (audmux_clk) + clk_enable(audmux_clk); + + ptcr = readl(audmux_base + MXC_AUDMUX_V2_PTCR(port)); + pdcr = readl(audmux_base + MXC_AUDMUX_V2_PDCR(port)); + + if (audmux_clk) + clk_disable(audmux_clk); + + ret = snprintf(buf, PAGE_SIZE, "PDCR: %08x\nPTCR: %08x\n", + pdcr, ptcr); + + if (ptcr & MXC_AUDMUX_V2_PTCR_TFSDIR) + ret += snprintf(buf + ret, PAGE_SIZE - ret, + "TxFS output from %s, ", + audmux_port_string((ptcr >> 27) & 0x7)); + else + ret += snprintf(buf + ret, PAGE_SIZE - ret, + "TxFS input, "); + + if (ptcr & MXC_AUDMUX_V2_PTCR_TCLKDIR) + ret += snprintf(buf + ret, PAGE_SIZE - ret, + "TxClk output from %s", + audmux_port_string((ptcr >> 22) & 0x7)); + else + ret += snprintf(buf + ret, PAGE_SIZE - ret, + "TxClk input"); + + ret += snprintf(buf + ret, PAGE_SIZE - ret, "\n"); + + if (ptcr & MXC_AUDMUX_V2_PTCR_SYN) { + ret += snprintf(buf + ret, PAGE_SIZE - ret, + "Port is symmetric"); + } else { + if (ptcr & MXC_AUDMUX_V2_PTCR_RFSDIR) + ret += snprintf(buf + ret, PAGE_SIZE - ret, + "RxFS output from %s, ", + audmux_port_string((ptcr >> 17) & 0x7)); + else + ret += snprintf(buf + ret, PAGE_SIZE - ret, + "RxFS input, "); + + if (ptcr & MXC_AUDMUX_V2_PTCR_RCLKDIR) + ret += snprintf(buf + ret, PAGE_SIZE - ret, + "RxClk output from %s", + audmux_port_string((ptcr >> 12) & 0x7)); + else + ret += snprintf(buf + ret, PAGE_SIZE - ret, + "RxClk input"); + } + + ret += snprintf(buf + ret, PAGE_SIZE - ret, + "\nData received from %s\n", + audmux_port_string((pdcr >> 13) & 0x7)); + + ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret); + + kfree(buf); + + return ret; +} + +static const struct file_operations audmux_debugfs_fops = { + .open = audmux_open_file, + .read = audmux_read_file, + .llseek = default_llseek, +}; + +static void audmux_debugfs_init(void) +{ + int i; + char buf[20]; + + audmux_debugfs_root = debugfs_create_dir("audmux", NULL); + if (!audmux_debugfs_root) { + pr_warning("Failed to create AUDMUX debugfs root\n"); + return; + } + + for (i = 1; i < 8; i++) { + snprintf(buf, sizeof(buf), "ssi%d", i); + if (!debugfs_create_file(buf, 0444, audmux_debugfs_root, + (void *)i, &audmux_debugfs_fops)) + pr_warning("Failed to create AUDMUX port %d debugfs file\n", + i); + } +} +#else +static inline void audmux_debugfs_init(void) +{ +} +#endif + +int mxc_audmux_v2_configure_port(unsigned int port, unsigned int ptcr, + unsigned int pdcr) +{ + if (!audmux_base) + return -ENOSYS; + + if (audmux_clk) + clk_enable(audmux_clk); + + writel(ptcr, audmux_base + MXC_AUDMUX_V2_PTCR(port)); + writel(pdcr, audmux_base + MXC_AUDMUX_V2_PDCR(port)); + + if (audmux_clk) + clk_disable(audmux_clk); + + return 0; +} +EXPORT_SYMBOL_GPL(mxc_audmux_v2_configure_port); + +static int mxc_audmux_v2_init(void) +{ + int ret = -1; + +#if defined(CONFIG_ARCH_MX6) + audmux_base = MX6_IO_ADDRESS(MX6Q_AUDMUX_BASE_ADDR); + ret = 0; +#endif +#if defined(CONFIG_ARCH_MX5) + if (cpu_is_mx51()) { + audmux_base = MX51_IO_ADDRESS(MX51_AUDMUX_BASE_ADDR); + ret = 0; + return ret; + } +#endif +#if defined(CONFIG_ARCH_MX3) + if (cpu_is_mx31()) + audmux_base = MX31_IO_ADDRESS(MX31_AUDMUX_BASE_ADDR); + + else if (cpu_is_mx35()) { + audmux_clk = clk_get(NULL, "audmux"); + if (IS_ERR(audmux_clk)) { + ret = PTR_ERR(audmux_clk); + printk(KERN_ERR "%s: cannot get clock: %d\n", __func__, + ret); + return ret; + } + audmux_base = MX35_IO_ADDRESS(MX35_AUDMUX_BASE_ADDR); + } +#endif +#if defined(CONFIG_SOC_IMX25) + if (cpu_is_mx25()) { + audmux_clk = clk_get(NULL, "audmux"); + if (IS_ERR(audmux_clk)) { + ret = PTR_ERR(audmux_clk); + printk(KERN_ERR "%s: cannot get clock: %d\n", __func__, + ret); + return ret; + } + audmux_base = MX25_IO_ADDRESS(MX25_AUDMUX_BASE_ADDR); + } +#endif /* if defined(CONFIG_SOC_IMX25) */ + audmux_debugfs_init(); + + return 0; +} + +postcore_initcall(mxc_audmux_v2_init); diff --git a/arch/arm/plat-mxc/avic.c b/arch/arm/plat-mxc/avic.c new file mode 100644 index 00000000..09e2bd0f --- /dev/null +++ b/arch/arm/plat-mxc/avic.c @@ -0,0 +1,158 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008 Juergen Beisert, kernel@pengutronix.de + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#include <linux/module.h> +#include <linux/irq.h> +#include <linux/io.h> +#include <mach/common.h> +#include <asm/mach/irq.h> +#include <mach/hardware.h> + +#include "irq-common.h" + +#define AVIC_INTCNTL 0x00 /* int control reg */ +#define AVIC_NIMASK 0x04 /* int mask reg */ +#define AVIC_INTENNUM 0x08 /* int enable number reg */ +#define AVIC_INTDISNUM 0x0C /* int disable number reg */ +#define AVIC_INTENABLEH 0x10 /* int enable reg high */ +#define AVIC_INTENABLEL 0x14 /* int enable reg low */ +#define AVIC_INTTYPEH 0x18 /* int type reg high */ +#define AVIC_INTTYPEL 0x1C /* int type reg low */ +#define AVIC_NIPRIORITY(x) (0x20 + 4 * (7 - (x))) /* int priority */ +#define AVIC_NIVECSR 0x40 /* norm int vector/status */ +#define AVIC_FIVECSR 0x44 /* fast int vector/status */ +#define AVIC_INTSRCH 0x48 /* int source reg high */ +#define AVIC_INTSRCL 0x4C /* int source reg low */ +#define AVIC_INTFRCH 0x50 /* int force reg high */ +#define AVIC_INTFRCL 0x54 /* int force reg low */ +#define AVIC_NIPNDH 0x58 /* norm int pending high */ +#define AVIC_NIPNDL 0x5C /* norm int pending low */ +#define AVIC_FIPNDH 0x60 /* fast int pending high */ +#define AVIC_FIPNDL 0x64 /* fast int pending low */ + +void __iomem *avic_base; + +#ifdef CONFIG_MXC_IRQ_PRIOR +static int avic_irq_set_priority(unsigned char irq, unsigned char prio) +{ + unsigned int temp; + unsigned int mask = 0x0F << irq % 8 * 4; + + if (irq >= MXC_INTERNAL_IRQS) + return -EINVAL;; + + temp = __raw_readl(avic_base + AVIC_NIPRIORITY(irq / 8)); + temp &= ~mask; + temp |= prio & mask; + + __raw_writel(temp, avic_base + AVIC_NIPRIORITY(irq / 8)); + + return 0; +} +#endif + +#ifdef CONFIG_FIQ +static int avic_set_irq_fiq(unsigned int irq, unsigned int type) +{ + unsigned int irqt; + + if (irq >= MXC_INTERNAL_IRQS) + return -EINVAL; + + if (irq < MXC_INTERNAL_IRQS / 2) { + irqt = __raw_readl(avic_base + AVIC_INTTYPEL) & ~(1 << irq); + __raw_writel(irqt | (!!type << irq), avic_base + AVIC_INTTYPEL); + } else { + irq -= MXC_INTERNAL_IRQS / 2; + irqt = __raw_readl(avic_base + AVIC_INTTYPEH) & ~(1 << irq); + __raw_writel(irqt | (!!type << irq), avic_base + AVIC_INTTYPEH); + } + + return 0; +} +#endif /* CONFIG_FIQ */ + +/* Disable interrupt number "irq" in the AVIC */ +static void mxc_mask_irq(struct irq_data *d) +{ + __raw_writel(d->irq, avic_base + AVIC_INTDISNUM); +} + +/* Enable interrupt number "irq" in the AVIC */ +static void mxc_unmask_irq(struct irq_data *d) +{ + __raw_writel(d->irq, avic_base + AVIC_INTENNUM); +} + +static struct mxc_irq_chip mxc_avic_chip = { + .base = { + .irq_ack = mxc_mask_irq, + .irq_mask = mxc_mask_irq, + .irq_unmask = mxc_unmask_irq, + }, +#ifdef CONFIG_MXC_IRQ_PRIOR + .set_priority = avic_irq_set_priority, +#endif +#ifdef CONFIG_FIQ + .set_irq_fiq = avic_set_irq_fiq, +#endif +}; + +/* + * This function initializes the AVIC hardware and disables all the + * interrupts. It registers the interrupt enable and disable functions + * to the kernel for each interrupt source. + */ +void __init mxc_init_irq(void __iomem *irqbase) +{ + int i; + + avic_base = irqbase; + + /* put the AVIC into the reset value with + * all interrupts disabled + */ + __raw_writel(0, avic_base + AVIC_INTCNTL); + __raw_writel(0x1f, avic_base + AVIC_NIMASK); + + /* disable all interrupts */ + __raw_writel(0, avic_base + AVIC_INTENABLEH); + __raw_writel(0, avic_base + AVIC_INTENABLEL); + + /* all IRQ no FIQ */ + __raw_writel(0, avic_base + AVIC_INTTYPEH); + __raw_writel(0, avic_base + AVIC_INTTYPEL); + for (i = 0; i < MXC_INTERNAL_IRQS; i++) { + irq_set_chip_and_handler(i, &mxc_avic_chip.base, + handle_level_irq); + set_irq_flags(i, IRQF_VALID); + } + + /* Set default priority value (0) for all IRQ's */ + for (i = 0; i < 8; i++) + __raw_writel(0, avic_base + AVIC_NIPRIORITY(i)); + +#ifdef CONFIG_FIQ + /* Initialize FIQ */ + init_FIQ(); +#endif + + printk(KERN_INFO "MXC IRQ initialized\n"); +} + diff --git a/arch/arm/plat-mxc/clock.c b/arch/arm/plat-mxc/clock.c new file mode 100755 index 00000000..93347eb1 --- /dev/null +++ b/arch/arm/plat-mxc/clock.c @@ -0,0 +1,437 @@ +/* + * Based on arch/arm/plat-omap/clock.c + * + * Copyright (C) 2004 - 2005 Nokia corporation + * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> + * Modified for omap shared clock framework by Tony Lindgren <tony@atomide.com> + * Copyright 2007-2012 Freescale Semiconductor, Inc. + * Copyright 2008 Juergen Beisert, kernel@pengutronix.de + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +/* #define DEBUG */ + +#include <linux/clk.h> +#include <linux/err.h> +#include <linux/errno.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/kernel.h> +#include <linux/list.h> +#include <linux/module.h> +#include <linux/mutex.h> +#include <linux/platform_device.h> +#include <linux/proc_fs.h> +#include <linux/semaphore.h> +#include <linux/string.h> +#include <linux/slab.h> +#include <linux/debugfs.h> +#include <linux/hardirq.h> + +#include <mach/clock.h> +#include <mach/hardware.h> + +extern int dvfs_core_is_active; +extern void bus_freq_update(struct clk *clk, bool flag); + +static LIST_HEAD(clocks); +static DEFINE_MUTEX(clocks_mutex); + +/*------------------------------------------------------------------------- + * Standard clock functions defined in include/linux/clk.h + *-------------------------------------------------------------------------*/ + +static void __clk_disable(struct clk *clk) +{ + if (clk == NULL || IS_ERR(clk)) + return; + + if (!clk->usecount) { + WARN(1, "clock enable/disable mismatch! clk %s\n", clk->name); + return; + } + + if (!(--clk->usecount)) { + if (clk->disable) + clk->disable(clk); + __clk_disable(clk->parent); + __clk_disable(clk->secondary); + } +} + +static int __clk_enable(struct clk *clk) +{ + if (clk == NULL || IS_ERR(clk)) + return -EINVAL; + + if (clk->usecount++ == 0) { + __clk_enable(clk->parent); + __clk_enable(clk->secondary); + + if (clk->enable) + clk->enable(clk); + } + return 0; +} + +/* This function increments the reference count on the clock and enables the + * clock if not already enabled. The parent clock tree is recursively enabled + */ +int clk_enable(struct clk *clk) +{ + /* unsigned long flags; */ + int ret = 0; + + if (in_interrupt()) { + printk(KERN_ERR " clk_enable cannot be called in an interrupt context\n"); + dump_stack(); + BUG(); + } + + if (clk == NULL || IS_ERR(clk)) + return -EINVAL; + + if ((clk->flags & AHB_HIGH_SET_POINT) || + (clk->flags & AHB_MED_SET_POINT) || + (clk->flags & AHB_AUDIO_SET_POINT) || + (clk->flags & CPU_FREQ_TRIG_UPDATE)) + bus_freq_update(clk, true); + + mutex_lock(&clocks_mutex); + ret = __clk_enable(clk); + mutex_unlock(&clocks_mutex); + + return ret; +} +EXPORT_SYMBOL(clk_enable); + +/* This function decrements the reference count on the clock and disables + * the clock when reference count is 0. The parent clock tree is + * recursively disabled + */ +void clk_disable(struct clk *clk) +{ + /* unsigned long flags; */ + + if (in_interrupt()) { + printk(KERN_ERR " clk_disable cannot be called in an interrupt context\n"); + dump_stack(); + BUG(); + } + + if (clk == NULL || IS_ERR(clk)) + return; + + mutex_lock(&clocks_mutex); + __clk_disable(clk); + mutex_unlock(&clocks_mutex); + + if ((clk->flags & AHB_HIGH_SET_POINT) || + (clk->flags & AHB_MED_SET_POINT) || + (clk->flags & AHB_AUDIO_SET_POINT) || + (clk->flags & CPU_FREQ_TRIG_UPDATE)) + bus_freq_update(clk, false); +} + +EXPORT_SYMBOL(clk_disable); + +/*! + * @brief Function to get the usage count for the requested clock. + * + * This function returns the reference count for the clock. + * + * @param clk Handle to clock to disable. + * + * @return Returns the usage count for the requested clock. + */ +int clk_get_usecount(struct clk *clk) +{ + if (clk == NULL || IS_ERR(clk)) + return 0; + + return clk->usecount; +} + +EXPORT_SYMBOL(clk_get_usecount); + +/* Retrieve the *current* clock rate. If the clock itself + * does not provide a special calculation routine, ask + * its parent and so on, until one is able to return + * a valid clock rate + */ +unsigned long clk_get_rate(struct clk *clk) +{ + if (clk == NULL || IS_ERR(clk)) + return 0UL; + + if (clk->get_rate) + return clk->get_rate(clk); + + return clk_get_rate(clk->parent); +} +EXPORT_SYMBOL(clk_get_rate); + +/* Round the requested clock rate to the nearest supported + * rate that is less than or equal to the requested rate. + * This is dependent on the clock's current parent. + */ +long clk_round_rate(struct clk *clk, unsigned long rate) +{ + if (clk == NULL || IS_ERR(clk) || !clk->round_rate) + return 0; + + return clk->round_rate(clk, rate); +} +EXPORT_SYMBOL(clk_round_rate); + +/* Set the clock to the requested clock rate. The rate must + * match a supported rate exactly based on what clk_round_rate returns + */ +int clk_set_rate(struct clk *clk, unsigned long rate) +{ + int ret = -EINVAL; + + if (clk == NULL || IS_ERR(clk) || clk->set_rate == NULL || rate == 0) + return ret; + + mutex_lock(&clocks_mutex); + ret = clk->set_rate(clk, rate); + mutex_unlock(&clocks_mutex); + + return ret; +} +EXPORT_SYMBOL(clk_set_rate); + +/* Set the clock's parent to another clock source */ +int clk_set_parent(struct clk *clk, struct clk *parent) +{ + int ret = -EINVAL; + struct clk *old; + + if (clk == NULL || IS_ERR(clk) || parent == NULL || + IS_ERR(parent) || clk->set_parent == NULL) + return ret; + + mutex_lock(&clocks_mutex); + + if (clk->usecount) { + if (in_interrupt()) { + printk(KERN_ERR " clk_enable cannot be called in an interrupt context\n"); + dump_stack(); + mutex_unlock(&clocks_mutex); + BUG(); + } + __clk_enable(parent); + } + + ret = clk->set_parent(clk, parent); + if (ret == 0) { + old = clk->parent; + clk->parent = parent; + } else { + old = parent; + } + if (clk->usecount) + __clk_disable(old); + + mutex_unlock(&clocks_mutex); + + return ret; +} +EXPORT_SYMBOL(clk_set_parent); + +/* Retrieve the clock's parent clock source */ +struct clk *clk_get_parent(struct clk *clk) +{ + struct clk *ret = NULL; + + if (clk == NULL || IS_ERR(clk)) + return ret; + + return clk->parent; +} +EXPORT_SYMBOL(clk_get_parent); + +/* + * Get the resulting clock rate from a PLL register value and the input + * frequency. PLLs with this register layout can at least be found on + * MX1, MX21, MX27 and MX31 + * + * mfi + mfn / (mfd + 1) + * f = 2 * f_ref * -------------------- + * pd + 1 + */ +unsigned long mxc_decode_pll(unsigned int reg_val, u32 freq) +{ + long long ll; + int mfn_abs; + unsigned int mfi, mfn, mfd, pd; + + mfi = (reg_val >> 10) & 0xf; + mfn = reg_val & 0x3ff; + mfd = (reg_val >> 16) & 0x3ff; + pd = (reg_val >> 26) & 0xf; + + mfi = mfi <= 5 ? 5 : mfi; + + mfn_abs = mfn; + + /* On all i.MXs except i.MX1 and i.MX21 mfn is a 10bit + * 2's complements number + */ + if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200) + mfn_abs = 0x400 - mfn; + + freq *= 2; + freq /= pd + 1; + + ll = (unsigned long long)freq * mfn_abs; + + do_div(ll, mfd + 1); + + if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200) + ll = -ll; + + ll = (freq * mfi) + ll; + + return ll; +} + +#ifdef CONFIG_CLK_DEBUG +/* + * debugfs support to trace clock tree hierarchy and attributes + */ +static int clk_debug_rate_get(void *data, u64 *val) +{ + struct clk *clk = data; + + *val = (u64)clk_get_rate(clk); + return 0; +} +DEFINE_SIMPLE_ATTRIBUTE(clk_debug_rate_fops, clk_debug_rate_get, NULL, + "%llu\n"); + + +static struct dentry *clk_root; +static int clk_debug_register_one(struct clk *clk) +{ + int err; + struct dentry *d, *child, *child_tmp; + struct clk *pa = clk_get_parent(clk); + + if (pa && !IS_ERR(pa)) + d = debugfs_create_dir(clk->name, pa->dentry); + else { + if (!clk_root) + clk_root = debugfs_create_dir("clock", NULL); + if (!clk_root) + return -ENOMEM; + d = debugfs_create_dir(clk->name, clk_root); + } + + if (!d) + return -ENOMEM; + + clk->dentry = d; + + d = debugfs_create_u8("usecount", S_IRUGO, clk->dentry, + (u8 *)&clk->usecount); + if (!d) { + err = -ENOMEM; + goto err_out; + } + + d = debugfs_create_file("rate", S_IRUGO, clk->dentry, (void *)clk, + &clk_debug_rate_fops); + if (!d) { + err = -ENOMEM; + goto err_out; + } + + d = debugfs_create_u32("flags", S_IRUGO, clk->dentry, + (u32 *)&clk->flags); + if (!d) { + err = -ENOMEM; + goto err_out; + } + + return 0; + +err_out: + d = clk->dentry; + list_for_each_entry_safe(child, child_tmp, &d->d_subdirs, d_u.d_child) + debugfs_remove(child); + debugfs_remove(clk->dentry); + return err; +} + +struct preinit_clk { + struct list_head list; + struct clk *clk; +}; +static LIST_HEAD(preinit_clks); +static DEFINE_MUTEX(preinit_lock); +static int init_done; + +void clk_debug_register(struct clk *clk) +{ + int err; + struct clk *pa; + + if (init_done) { + pa = clk_get_parent(clk); + + if (pa && !IS_ERR(pa) && !pa->dentry) + clk_debug_register(pa); + + if (!clk->dentry) { + err = clk_debug_register_one(clk); + if (err) + return; + } + } else { + struct preinit_clk *p; + mutex_lock(&preinit_lock); + p = kmalloc(sizeof(*p), GFP_KERNEL); + if (p) { + p->clk = clk; + list_add(&p->list, &preinit_clks); + } + mutex_unlock(&preinit_lock); + } +} +EXPORT_SYMBOL_GPL(clk_debug_register); + +static int __init clk_debugfs_init(void) +{ + struct preinit_clk *pclk, *tmp; + + init_done = 1; + + mutex_lock(&preinit_lock); + list_for_each_entry(pclk, &preinit_clks, list) { + clk_debug_register(pclk->clk); + } + + list_for_each_entry_safe(pclk, tmp, &preinit_clks, list) { + list_del(&pclk->list); + kfree(pclk); + } + mutex_unlock(&preinit_lock); + return 0; +} +late_initcall(clk_debugfs_init); +#endif diff --git a/arch/arm/plat-mxc/cpu.c b/arch/arm/plat-mxc/cpu.c new file mode 100755 index 00000000..eb163abd --- /dev/null +++ b/arch/arm/plat-mxc/cpu.c @@ -0,0 +1,90 @@ +/* + * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <linux/module.h> +#include <mach/clock.h> +#include <mach/hardware.h> + +unsigned int __mxc_cpu_type; +EXPORT_SYMBOL(__mxc_cpu_type); +extern int mxc_early_serial_console_init(unsigned long base, struct clk *clk); +void (*set_num_cpu_op)(int num); + +void mxc_set_cpu_type(unsigned int type) +{ + __mxc_cpu_type = type; +} + +void imx_print_silicon_rev(const char *cpu, int srev) +{ + if (srev == IMX_CHIP_REVISION_UNKNOWN) + pr_info("CPU identified as %s, unknown revision\n", cpu); + else + pr_info("CPU identified as %s, silicon rev %d.%d\n", + cpu, (srev >> 4) & 0xf, srev & 0xf); +} + +int mxc_jtag_enabled; /* OFF: 0 (default), ON: 1 */ +int uart_at_24; /* OFF: 0 (default); ON: 1 */ +/* + * Here are the JTAG options from the command line. By default JTAG + * is OFF which means JTAG is not connected and WFI is enabled + * + * "on" -- JTAG is connected, so WFI is disabled + * "off" -- JTAG is disconnected, so WFI is enabled + */ + +static int __init jtag_wfi_setup(char *p) +{ + if (memcmp(p, "on", 2) == 0) { + mxc_jtag_enabled = 1; + p += 2; + } else if (memcmp(p, "off", 3) == 0) { + mxc_jtag_enabled = 0; + p += 3; + } + return 0; +} +early_param("jtag", jtag_wfi_setup); + + +static int __init setup_debug_uart(char *p) +{ + uart_at_24 = 1; + return 0; +} + +early_param("debug_uart", setup_debug_uart); + +/** + * early_console_setup - setup debugging console + * + * Consoles started here require little enough setup that we can start using + * them very early in the boot process, either right after the machine + * vector initialization, or even before if the drivers can detect their hw. + * + * Returns non-zero if a console couldn't be setup. + * This function is developed based on + * early_console_setup function as defined in arch/ia64/kernel/setup.c + */ +void __init early_console_setup(unsigned long base, struct clk *clk) +{ +#ifdef CONFIG_SERIAL_IMX_CONSOLE + mxc_early_serial_console_init(base, clk); +#endif +} diff --git a/arch/arm/plat-mxc/cpufreq.c b/arch/arm/plat-mxc/cpufreq.c new file mode 100755 index 00000000..01ba0b3f --- /dev/null +++ b/arch/arm/plat-mxc/cpufreq.c @@ -0,0 +1,535 @@ +/* + * Copyright (C) 2010-2013 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/* + * A driver for the Freescale Semiconductor i.MXC CPUfreq module. + * The CPUFREQ driver is for controlling CPU frequency. It allows you to change + * the CPU clock speed on the fly. + */ +#include <linux/cpufreq.h> +#include <linux/clk.h> +#include <linux/err.h> +#include <linux/slab.h> +#include <linux/regulator/consumer.h> +#include <linux/delay.h> +#include <linux/io.h> +#include <linux/suspend.h> +#include <asm/smp_plat.h> +#include <asm/cpu.h> + +#include <mach/hardware.h> +#include <mach/clock.h> + +#define CLK32_FREQ 32768 +#define NANOSECOND (1000 * 1000 * 1000) + + +static int cpu_freq_khz_min; +static int cpu_freq_khz_max; + +static struct clk *cpu_clk; +static struct cpufreq_frequency_table *imx_freq_table; + +static int cpu_op_nr; +static struct cpu_op *cpu_op_tbl; +static u32 pre_suspend_rate; +static bool cpufreq_suspend; +static struct mutex set_cpufreq_lock; + +extern struct regulator *cpu_regulator; +extern struct regulator *soc_regulator; +extern struct regulator *pu_regulator; +extern int dvfs_core_is_active; +extern struct cpu_op *(*get_cpu_op)(int *op); +extern void bus_freq_update(struct clk *clk, bool flag); +extern void mx6_arm_regulator_bypass(void); +extern void mx6_soc_pu_regulator_bypass(void); + +int set_cpu_freq(int freq) +{ + int i, ret = 0; + int org_cpu_rate; + int gp_volt = 0, org_gp_volt = 0; + int soc_volt = 0, org_soc_volt = 0; + int pu_volt = 0, org_pu_volt = 0; + + org_cpu_rate = clk_get_rate(cpu_clk); + if (org_cpu_rate == freq) + return ret; + + for (i = 0; i < cpu_op_nr; i++) { + if (freq == cpu_op_tbl[i].cpu_rate) { + gp_volt = cpu_op_tbl[i].cpu_voltage; + soc_volt = cpu_op_tbl[i].soc_voltage; + pu_volt = cpu_op_tbl[i].pu_voltage; + } + if (org_cpu_rate == cpu_op_tbl[i].cpu_rate) { + org_gp_volt = cpu_op_tbl[i].cpu_voltage; + org_soc_volt = cpu_op_tbl[i].soc_voltage; + org_pu_volt = cpu_op_tbl[i].pu_voltage; + } + } + if (gp_volt == 0) + return ret; + /*Set the voltage for the GP domain. */ + if (freq > org_cpu_rate) { + /* Check if the bus freq needs to be increased first */ + bus_freq_update(cpu_clk, true); + + if (!IS_ERR(soc_regulator)) { + ret = regulator_set_voltage(soc_regulator, soc_volt, + soc_volt); + if (ret < 0) { + printk(KERN_ERR + "COULD NOT SET SOC VOLTAGE!!!!\n"); + goto err1; + } + } + /*if pu_regulator is enabled, it will be tracked with VDDARM*/ + if (!IS_ERR(pu_regulator) && + regulator_is_enabled(pu_regulator)) { + ret = regulator_set_voltage(pu_regulator, pu_volt, + pu_volt); + if (ret < 0) { + printk(KERN_ERR + "COULD NOT SET PU VOLTAGE!!!!\n"); + goto err2; + } + } + if (!IS_ERR(cpu_regulator)) + { + ret = regulator_set_voltage(cpu_regulator, gp_volt, + gp_volt); + if (ret < 0) { + printk(KERN_ERR "COULD NOT SET GP VOLTAGE!!!!\n"); + goto err3; + } + } + udelay(50); + } + ret = clk_set_rate(cpu_clk, freq); + if (ret != 0) { + printk(KERN_ERR "cannot set CPU clock rate\n"); + goto err4; + } + + if (freq < org_cpu_rate) { + if (!IS_ERR(cpu_regulator)) { + ret = regulator_set_voltage(cpu_regulator, gp_volt, + gp_volt); + if (ret < 0) { + printk(KERN_ERR "COULD NOT SET GP VOLTAGE!!!!\n"); + goto err5; + } + } + if (!IS_ERR(soc_regulator)) { + ret = regulator_set_voltage(soc_regulator, soc_volt, + soc_volt); + if (ret < 0) { + printk(KERN_ERR + "COULD NOT SET SOC VOLTAGE BACK!!!!\n"); + goto err6; + } + } + /*if pu_regulator is enabled, it will be tracked with VDDARM*/ + if (!IS_ERR(pu_regulator) && + regulator_is_enabled(pu_regulator)) { + ret = regulator_set_voltage(pu_regulator, pu_volt, + pu_volt); + if (ret < 0) { + printk(KERN_ERR + "COULD NOT SET PU VOLTAGE!!!!\n"); + goto err7; + } + } + /* Check if the bus freq can be decreased.*/ + if (freq == cpu_op_tbl[cpu_op_nr - 1].cpu_rate) + bus_freq_update(cpu_clk, false); + } + + return ret; + /*Restore back if any regulator or clock rate set fail.*/ +err7: + ret = regulator_set_voltage(soc_regulator, org_soc_volt, + org_soc_volt); + if (ret < 0) { + printk(KERN_ERR "COULD NOT RESTORE SOC VOLTAGE!!!!\n"); + goto err7; + } + +err6: + ret = regulator_set_voltage(cpu_regulator, org_gp_volt, org_gp_volt); + if (ret < 0) { + printk(KERN_ERR "COULD NOT RESTORE GP VOLTAGE!!!!\n"); + goto err6; + } + +err5: + ret = clk_set_rate(cpu_clk, org_cpu_rate); + if (ret != 0) { + printk(KERN_ERR "cannot restore CPU clock rate\n"); + goto err5; + } + return -1; + +err4: + ret = regulator_set_voltage(cpu_regulator, org_gp_volt, org_gp_volt); + if (ret < 0) { + printk(KERN_ERR "COULD NOT RESTORE GP VOLTAGE!!!!\n"); + goto err4; + } + +err3: + if (!IS_ERR(pu_regulator) && + regulator_is_enabled(pu_regulator)) { + ret = regulator_set_voltage(pu_regulator, org_pu_volt, org_pu_volt); + if (ret < 0) { + printk(KERN_ERR "COULD NOT RESTORE PU VOLTAGE!!!!\n"); + goto err3; + } + } +err2: + ret = regulator_set_voltage(soc_regulator, org_soc_volt, + org_soc_volt); + if (ret < 0) { + printk(KERN_ERR "COULD NOT RESTORE SOC VOLTAGE!!!!\n"); + goto err2; + } +err1: + return -1; + +} + +static int mxc_verify_speed(struct cpufreq_policy *policy) +{ + if (policy->cpu > num_possible_cpus()) + return -EINVAL; + + return cpufreq_frequency_table_verify(policy, imx_freq_table); +} + +static unsigned int mxc_get_speed(unsigned int cpu) +{ + if (cpu > num_possible_cpus()) + return 0; + + return clk_get_rate(cpu_clk) / 1000; +} + +static int mxc_set_target(struct cpufreq_policy *policy, + unsigned int target_freq, unsigned int relation) +{ + struct cpufreq_freqs freqs; + int freq_Hz; + int ret = 0; + unsigned int index; + int i, num_cpus; + + num_cpus = num_possible_cpus(); + if (policy->cpu > num_cpus) + return 0; + if (dvfs_core_is_active) { + struct cpufreq_freqs freqs; + + freqs.old = policy->cur; + freqs.new = clk_get_rate(cpu_clk) / 1000; + freqs.cpu = policy->cpu; + freqs.flags = 0; + cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); + cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); + + pr_debug("DVFS core is active, cannot change FREQ using CPUFREQ\n"); + return ret; + } + + mutex_lock(&set_cpufreq_lock); + if (cpufreq_suspend) { + mutex_unlock(&set_cpufreq_lock); + return ret; + } + cpufreq_frequency_table_target(policy, imx_freq_table, + target_freq, relation, &index); + freq_Hz = imx_freq_table[index].frequency * 1000; + + freqs.old = clk_get_rate(cpu_clk) / 1000; + freqs.new = freq_Hz / 1000; + freqs.cpu = policy->cpu; + freqs.flags = 0; + for (i = 0; i < num_cpus; i++) { + freqs.cpu = i; + cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); + } + ret = set_cpu_freq(freq_Hz); + if (ret) { + /*restore cpufreq and tell cpufreq core if set fail*/ + freqs.old = clk_get_rate(cpu_clk) / 1000; + freqs.new = freqs.old; + freqs.cpu = policy->cpu; + freqs.flags = 0; + for (i = 0; i < num_cpus; i++) { + freqs.cpu = i; + cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); + } + goto Set_finish; + } +#ifdef CONFIG_SMP + /* Loops per jiffy is not updated by the CPUFREQ driver for SMP systems. + * So update it for all CPUs. + */ + + for_each_possible_cpu(i) + per_cpu(cpu_data, i).loops_per_jiffy = + cpufreq_scale(per_cpu(cpu_data, i).loops_per_jiffy, + freqs.old, freqs.new); + /* Update global loops_per_jiffy to cpu0's loops_per_jiffy, + * as all CPUs are running at same freq */ + loops_per_jiffy = per_cpu(cpu_data, 0).loops_per_jiffy; +#endif +Set_finish: + for (i = 0; i < num_cpus; i++) { + freqs.cpu = i; + cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); + } + mutex_unlock(&set_cpufreq_lock); + + return ret; +} + +static int __devinit mxc_cpufreq_init(struct cpufreq_policy *policy) +{ + int ret; + int i; + + printk(KERN_INFO "i.MXC CPU frequency driver\n"); + + if (policy->cpu >= num_possible_cpus()) + return -EINVAL; + + if (!get_cpu_op) + return -EINVAL; + + cpu_clk = clk_get(NULL, "cpu_clk"); + if (IS_ERR(cpu_clk)) { + printk(KERN_ERR "%s: failed to get cpu clock\n", __func__); + return PTR_ERR(cpu_clk); + } + + cpu_op_tbl = get_cpu_op(&cpu_op_nr); + + cpu_freq_khz_min = cpu_op_tbl[0].cpu_rate / 1000; + cpu_freq_khz_max = cpu_op_tbl[0].cpu_rate / 1000; + + if (imx_freq_table == NULL) { + imx_freq_table = kmalloc( + sizeof(struct cpufreq_frequency_table) * (cpu_op_nr + 1), + GFP_KERNEL); + if (!imx_freq_table) { + ret = -ENOMEM; + goto err1; + } + + for (i = 0; i < cpu_op_nr; i++) { + imx_freq_table[i].index = i; + imx_freq_table[i].frequency = cpu_op_tbl[i].cpu_rate / 1000; + + if ((cpu_op_tbl[i].cpu_rate / 1000) < cpu_freq_khz_min) + cpu_freq_khz_min = cpu_op_tbl[i].cpu_rate / 1000; + + if ((cpu_op_tbl[i].cpu_rate / 1000) > cpu_freq_khz_max) + cpu_freq_khz_max = cpu_op_tbl[i].cpu_rate / 1000; + } + + imx_freq_table[i].index = i; + imx_freq_table[i].frequency = CPUFREQ_TABLE_END; + } + policy->cur = clk_get_rate(cpu_clk) / 1000; + policy->min = policy->cpuinfo.min_freq = cpu_freq_khz_min; + policy->max = policy->cpuinfo.max_freq = cpu_freq_khz_max; + + /* All processors share the same frequency and voltage. + * So all frequencies need to be scaled together. + */ + if (is_smp()) { + policy->shared_type = CPUFREQ_SHARED_TYPE_ANY; + cpumask_setall(policy->cpus); + } + + /* Manual states, that PLL stabilizes in two CLK32 periods */ + policy->cpuinfo.transition_latency = 2 * NANOSECOND / CLK32_FREQ; + + ret = cpufreq_frequency_table_cpuinfo(policy, imx_freq_table); + + if (ret < 0) { + printk(KERN_ERR "%s: failed to register i.MXC CPUfreq with error code %d\n", + __func__, ret); + goto err; + } + + cpufreq_frequency_table_get_attr(imx_freq_table, policy->cpu); + return 0; +err: + kfree(imx_freq_table); +err1: + clk_put(cpu_clk); + return ret; +} + +static int mxc_cpufreq_exit(struct cpufreq_policy *policy) +{ + cpufreq_frequency_table_put_attr(policy->cpu); + + if (policy->cpu == 0) { + set_cpu_freq(cpu_freq_khz_max * 1000); + clk_put(cpu_clk); + kfree(imx_freq_table); + } + return 0; +} + +static struct freq_attr *imx_cpufreq_attr[] = { + &cpufreq_freq_attr_scaling_available_freqs, + NULL, +}; +static struct cpufreq_driver mxc_driver = { + .flags = CPUFREQ_STICKY, + .verify = mxc_verify_speed, + .target = mxc_set_target, + .get = mxc_get_speed, + .init = mxc_cpufreq_init, + .exit = mxc_cpufreq_exit, + .name = "imx", + .attr = imx_cpufreq_attr, +}; + +static int cpufreq_pm_notify(struct notifier_block *nb, unsigned long event, + void *dummy) +{ + unsigned int i; + int num_cpus; + int ret; + struct cpufreq_freqs freqs; + + num_cpus = num_possible_cpus(); + mutex_lock(&set_cpufreq_lock); + if (event == PM_SUSPEND_PREPARE) { + pre_suspend_rate = clk_get_rate(cpu_clk); + if (pre_suspend_rate != (imx_freq_table[0].frequency * 1000)) { + /*notify cpufreq core will raise up cpufreq to highest*/ + freqs.old = pre_suspend_rate / 1000; + freqs.new = imx_freq_table[0].frequency; + freqs.flags = 0; + for (i = 0; i < num_cpus; i++) { + freqs.cpu = i; + cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); + } + ret = set_cpu_freq(imx_freq_table[0].frequency * 1000); + /*restore cpufreq and tell cpufreq core if set fail*/ + if (ret) { + freqs.old = clk_get_rate(cpu_clk)/1000; + freqs.new = freqs.old; + freqs.flags = 0; + for (i = 0; i < num_cpus; i++) { + freqs.cpu = i; + cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); + } + goto Notify_finish;/*if update freq error,return*/ + } +#ifdef CONFIG_SMP + for_each_possible_cpu(i) + per_cpu(cpu_data, i).loops_per_jiffy = + cpufreq_scale(per_cpu(cpu_data, i).loops_per_jiffy, + pre_suspend_rate / 1000, imx_freq_table[0].frequency); + loops_per_jiffy = per_cpu(cpu_data, 0).loops_per_jiffy; +#else + loops_per_jiffy = cpufreq_scale(loops_per_jiffy, + pre_suspend_rate / 1000, imx_freq_table[0].frequency); +#endif + for (i = 0; i < num_cpus; i++) { + freqs.cpu = i; + cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); + } + } + cpufreq_suspend = true; + } else if (event == PM_POST_SUSPEND) { + if (clk_get_rate(cpu_clk) != pre_suspend_rate) { + /*notify cpufreq core will restore rate before suspend*/ + freqs.old = imx_freq_table[0].frequency; + freqs.new = pre_suspend_rate / 1000; + freqs.flags = 0; + for (i = 0; i < num_cpus; i++) { + freqs.cpu = i; + cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); + } + ret = set_cpu_freq(pre_suspend_rate); + /*restore cpufreq and tell cpufreq core if set fail*/ + if (ret) { + freqs.old = clk_get_rate(cpu_clk)/1000; + freqs.new = freqs.old; + freqs.flags = 0; + for (i = 0; i < num_cpus; i++) { + freqs.cpu = i; + cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); + } + goto Notify_finish;/*if update freq error,return*/ + } +#ifdef CONFIG_SMP + for_each_possible_cpu(i) + per_cpu(cpu_data, i).loops_per_jiffy = + cpufreq_scale(per_cpu(cpu_data, i).loops_per_jiffy, + imx_freq_table[0].frequency, pre_suspend_rate / 1000); + loops_per_jiffy = per_cpu(cpu_data, 0).loops_per_jiffy; +#else + loops_per_jiffy = cpufreq_scale(loops_per_jiffy, + imx_freq_table[0].frequency, pre_suspend_rate / 1000); +#endif + for (i = 0; i < num_cpus; i++) { + freqs.cpu = i; + cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); + } + } + cpufreq_suspend = false; + } + mutex_unlock(&set_cpufreq_lock); + return NOTIFY_OK; + +Notify_finish: + for (i = 0; i < num_cpus; i++) { + freqs.cpu = i; + cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); + } + mutex_unlock(&set_cpufreq_lock); + return NOTIFY_OK; +} +static struct notifier_block imx_cpufreq_pm_notifier = { + .notifier_call = cpufreq_pm_notify, +}; +extern void mx6_cpu_regulator_init(void); +static int __init mxc_cpufreq_driver_init(void) +{ + mx6_cpu_regulator_init(); + mutex_init(&set_cpufreq_lock); + register_pm_notifier(&imx_cpufreq_pm_notifier); + return cpufreq_register_driver(&mxc_driver); +} + +static void mxc_cpufreq_driver_exit(void) +{ + cpufreq_unregister_driver(&mxc_driver); +} + +module_init(mxc_cpufreq_driver_init); +module_exit(mxc_cpufreq_driver_exit); + +MODULE_AUTHOR("Freescale Semiconductor Inc. Yong Shen <yong.shen@linaro.org>"); +MODULE_DESCRIPTION("CPUfreq driver for i.MX"); +MODULE_LICENSE("GPL"); diff --git a/arch/arm/plat-mxc/devices.c b/arch/arm/plat-mxc/devices.c new file mode 100644 index 00000000..eee1b609 --- /dev/null +++ b/arch/arm/plat-mxc/devices.c @@ -0,0 +1,91 @@ +/* + * Copyright 2008 Sascha Hauer, kernel@pengutronix.de + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, + * Boston, MA 02110-1301, USA. + */ + +#include <linux/kernel.h> +#include <linux/slab.h> +#include <linux/init.h> +#include <linux/err.h> +#include <linux/platform_device.h> +#include <mach/common.h> + +int __init mxc_register_device(struct platform_device *pdev, void *data) +{ + int ret; + + pdev->dev.platform_data = data; + + ret = platform_device_register(pdev); + if (ret) + pr_debug("Unable to register platform device '%s': %d\n", + pdev->name, ret); + + return ret; +} + +struct platform_device *__init imx_add_platform_device_dmamask( + const char *name, int id, + const struct resource *res, unsigned int num_resources, + const void *data, size_t size_data, u64 dmamask) +{ + int ret = -ENOMEM; + struct platform_device *pdev; + + pdev = platform_device_alloc(name, id); + if (!pdev) + goto err; + + if (dmamask) { + /* + * This memory isn't freed when the device is put, + * I don't have a nice idea for that though. Conceptually + * dma_mask in struct device should not be a pointer. + * See http://thread.gmane.org/gmane.linux.kernel.pci/9081 + */ + pdev->dev.dma_mask = + kmalloc(sizeof(*pdev->dev.dma_mask), GFP_KERNEL); + if (!pdev->dev.dma_mask) + /* ret is still -ENOMEM; */ + goto err; + + *pdev->dev.dma_mask = dmamask; + pdev->dev.coherent_dma_mask = dmamask; + } + + if (res) { + ret = platform_device_add_resources(pdev, res, num_resources); + if (ret) + goto err; + } + + if (data) { + ret = platform_device_add_data(pdev, data, size_data); + if (ret) + goto err; + } + + ret = platform_device_add(pdev); + if (ret) { +err: + if (dmamask) + kfree(pdev->dev.dma_mask); + platform_device_put(pdev); + return ERR_PTR(ret); + } + + return pdev; +} diff --git a/arch/arm/plat-mxc/devices/Kconfig b/arch/arm/plat-mxc/devices/Kconfig new file mode 100755 index 00000000..2e666bac --- /dev/null +++ b/arch/arm/plat-mxc/devices/Kconfig @@ -0,0 +1,190 @@ +config IMX_HAVE_PLATFORM_DMA + bool + +config IMX_HAVE_PLATFORM_MXC_MLB + bool + +config IMX_HAVE_PLATFORM_FEC + bool + default y if ARCH_MX25 || SOC_IMX27 || SOC_IMX35 || SOC_IMX51 || SOC_IMX53 + +config IMX_HAVE_PLATFORM_FLEXCAN + select HAVE_CAN_FLEXCAN if CAN + bool + +config IMX_HAVE_PLATFORM_FSL_USB2_UDC + bool + +config IMX_HAVE_PLATFORM_GPIO_KEYS + bool + default y if SOC_IMX51 + +config IMX_HAVE_PLATFORM_GPMI_NFC + bool + +config IMX_HAVE_PLATFORM_IMX21_HCD + bool + +config IMX_HAVE_PLATFORM_IMX2_WDT + bool + +config IMX_HAVE_PLATFORM_IMXDI_RTC + bool + +config IMX_HAVE_PLATFORM_IMX_SRTC + bool + +config IMX_HAVE_PLATFORM_IMX_SNVS_RTC + bool + +config IMX_HAVE_PLATFORM_IMX_CAAM + bool + default y if SOC_IMX6Q + +config IMX_HAVE_PLATFORM_IMX_FB + bool + select HAVE_FB_IMX + +config IMX_HAVE_PLATFORM_IMX_I2C + bool + +config IMX_HAVE_PLATFORM_IMX_KEYPAD + bool + +config IMX_HAVE_PLATFORM_IMX_SSI + bool + +config IMX_HAVE_PLATFORM_IMX_ESAI + bool + +config IMX_HAVE_PLATFORM_IMX_UART + bool + +config IMX_HAVE_PLATFORM_IMX_UDC + bool + +config IMX_HAVE_PLATFORM_IPU_CORE + bool + +config IMX_HAVE_PLATFORM_MX1_CAMERA + bool + +config IMX_HAVE_PLATFORM_MX2_CAMERA + bool + +config IMX_HAVE_PLATFORM_MXC_EHCI + bool + +config IMX_HAVE_PLATFORM_MXC_MMC + bool + +config IMX_HAVE_PLATFORM_MXC_NAND + bool + +config IMX_HAVE_PLATFORM_MXC_PWM + bool + +config IMX_HAVE_PLATFORM_MXC_RNGA + bool + select ARCH_HAS_RNGA + +config IMX_HAVE_PLATFORM_MXC_RTC + bool + +config IMX_HAVE_PLATFORM_MXC_W1 + bool + +config IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX + bool + +config IMX_HAVE_PLATFORM_SPI_IMX + bool + +config IMX_HAVE_PLATFORM_IMX_IPUV3 + bool + +config IMX_HAVE_PLATFORM_IMX_TVE + bool + +config IMX_HAVE_PLATFORM_IMX_VPU + bool + +config IMX_HAVE_PLATFORM_IMX_DVFS + bool + +config IMX_HAVE_PLATFORM_AHCI + bool + +config IMX_HAVE_PLATFORM_IMX_IIM + bool + +config IMX_HAVE_PLATFORM_MXC_GPU + bool +config IMX_HAVE_PLATFORM_IMX_OCOTP + bool + +config IMX_HAVE_PLATFORM_IMX_VIIM + bool + +config IMX_HAVE_PLATFORM_IMX_DCP + bool + +config IMX_HAVE_PLATFORM_RANDOM_RNGC + bool + +config IMX_HAVE_PLATFORM_PERFMON + bool + +config IMX_HAVE_PLATFORM_LDB + bool + +config IMX_HAVE_PLATFORM_IMX_PXP + bool + +config IMX_HAVE_PLATFORM_IMX_ELCDIF + bool + +config IMX_HAVE_PLATFORM_IMX_EPDC + bool + +config IMX_HAVE_PLATFORM_IMX_SPDC + bool + +config IMX_HAVE_PLATFORM_IMX_SPDIF + bool + +config IMX_HAVE_PLATFORM_VIV_GPU + bool + +config IMX_HAVE_PLATFORM_MXC_HDMI + bool + +config IMX_HAVE_PLATFORM_IMX_ANATOP_THERMAL + bool + +config IMX_HAVE_PLATFORM_FSL_OTG + bool + +config IMX_HAVE_PLATFORM_FSL_USB_WAKEUP + bool + +config IMX_HAVE_PLATFORM_IMX_PM + bool + +config IMX_HAVE_PLATFORM_IMX_ASRC + bool + +config IMX_HAVE_PLATFORM_IMX_MIPI_DSI + bool + +config IMX_HAVE_PLATFORM_IMX_MIPI_CSI2 + bool + +config IMX_HAVE_PLATFORM_IMX_VDOA + bool + +config IMX_HAVE_PLATFORM_IMX_PCIE + bool + +config IMX_HAVE_PLATFORM_IMX_FSL_CSI + bool diff --git a/arch/arm/plat-mxc/devices/Makefile b/arch/arm/plat-mxc/devices/Makefile new file mode 100755 index 00000000..102eeaaf --- /dev/null +++ b/arch/arm/plat-mxc/devices/Makefile @@ -0,0 +1,70 @@ +obj-$(CONFIG_IMX_HAVE_PLATFORM_DMA) += platform-dma.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_MLB) += platform-mxc_mlb.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_FEC) += platform-fec.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_FLEXCAN) += platform-flexcan.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_FSL_USB2_UDC) += platform-fsl-usb2-udc.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_GPIO_KEYS) += platform-gpio_keys.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_GPMI_NFC) += platform-imx-gpmi-nfc.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX21_HCD) += platform-imx21-hcd.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX2_WDT) += platform-imx2-wdt.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_IMXDI_RTC) += platform-imxdi_rtc.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_SRTC) += platform-imx_srtc.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_SNVS_RTC) += platform-imx_snvs_rtc.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_CAAM) += platform-imx-caam.o +obj-y += platform-imx-dma.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_FB) += platform-imx-fb.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_I2C) += platform-imx-i2c.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_KEYPAD) += platform-imx-keypad.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_SSI) += platform-imx-ssi.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_ESAI) += platform-imx-esai.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UART) += platform-imx-uart.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UDC) += platform-imx_udc.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_IPU_CORE) += platform-ipu-core.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_MX1_CAMERA) += platform-mx1-camera.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_MX2_CAMERA) += platform-mx2-camera.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_EHCI) += platform-mxc-ehci.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_MMC) += platform-mxc-mmc.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_NAND) += platform-mxc_nand.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_PWM) += platform-mxc_pwm.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_RNGA) += platform-mxc_rnga.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_RTC) += platform-mxc_rtc.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_W1) += platform-mxc_w1.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX) += platform-sdhci-esdhc-imx.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_SPI_IMX) += platform-spi_imx.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_IPUV3) += platform-imx_ipuv3.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_TVE) += platform-imx_tve.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_VPU) += platform-imx_vpu.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_DVFS) += platform-imx_dvfs.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_AHCI) += platform-ahci-imx.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_IIM) += platform-imx-iim.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_GPU) += platform-mxc_gpu.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_OCOTP) += platform-imx-ocotp.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_VIIM) += platform-imx-viim.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_DCP) += platform-imx-dcp.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_RANDOM_RNGC) += platform-imx-rngb.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_PERFMON) += platform-imx-perfmon.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_LDB) += platform-imx_ldb.o +obj-y += platform-imx-scc2.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_PXP) += platform-imx-pxp.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_EPDC) += platform-imx-epdc-fb.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_SPDC) += platform-imx-spdc-fb.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_ELCDIF) += platform-imx-elcdif-fb.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_SPDIF) += platform-imx-spdif.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_SPDIF) += platform-imx-spdif-dai.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_SPDIF) += platform-imx-spdif-audio.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_VIV_GPU) += platform-viv_gpu.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_ANATOP_THERMAL) += platform-imx-anatop-thermal.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_FSL_OTG) += platform-fsl-usb2-otg.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_FSL_USB_WAKEUP) += platform-fsl-usb2-wakeup.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_PM) += platform-imx-pm.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_HDMI) += platform-mxc_hdmi.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_HDMI) += platform-mxc-hdmi-core.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_HDMI) += platform-imx-hdmi-soc.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_HDMI) += platform-imx-hdmi-soc-dai.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_ASRC) += platform-imx-asrc.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_MIPI_DSI) += platform-imx-mipi_dsi.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_MIPI_CSI2) += platform-imx-mipi_csi2.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_VDOA) += platform-imx-vdoa.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_PCIE) += platform-imx-pcie.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_FSL_CSI) += platform-imx-fsl-csi.o +obj-y += platform-imx-pmu.o diff --git a/arch/arm/plat-mxc/devices/platform-ahci-imx.c b/arch/arm/plat-mxc/devices/platform-ahci-imx.c new file mode 100755 index 00000000..90d994c2 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-ahci-imx.c @@ -0,0 +1,63 @@ +/* + * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <asm/sizes.h> +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx_ahci_data_entry_single(soc) \ + { \ + .iobase = soc ## _SATA_BASE_ADDR, \ + .irq = soc ## _INT_SATA, \ + } + +#ifdef CONFIG_SOC_IMX53 +const struct imx_ahci_data imx53_ahci_data __initconst = + imx_ahci_data_entry_single(MX53); +#endif + +#ifdef CONFIG_SOC_IMX6Q +const struct imx_ahci_data imx6q_ahci_data __initconst = + imx_ahci_data_entry_single(MX6Q); +#endif + +struct platform_device *__init imx_add_ahci( + const struct imx_ahci_data *data, + const struct ahci_platform_data *pdata) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + + if (!fuse_dev_is_available(MXC_DEV_SATA)) + return ERR_PTR(-ENODEV); + + return imx_add_platform_device_dmamask("ahci", 0 /* -1? */, + res, ARRAY_SIZE(res), + pdata, sizeof(*pdata), DMA_BIT_MASK(32)); +} diff --git a/arch/arm/plat-mxc/devices/platform-dma.c b/arch/arm/plat-mxc/devices/platform-dma.c new file mode 100644 index 00000000..7f731954 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-dma.c @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <linux/compiler.h> +#include <linux/err.h> +#include <linux/init.h> + +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#ifdef CONFIG_SOC_IMX50 +const struct imx_dma_res_data imx50_dma_res_data __initconst = { + .iobase = MX50_APBHDMA_BASE_ADDR, +}; +#endif + +#ifdef CONFIG_SOC_IMX6Q +const struct imx_dma_res_data imx6q_dma_res_data __initconst = { + .iobase = APBH_DMA_ARB_BASE_ADDR, +}; +#endif + +struct platform_device *__init imx_add_dma( + const struct imx_dma_res_data *data) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + SZ_8K - 1, + .flags = IORESOURCE_MEM, + }, + }; + + return imx_add_platform_device_dmamask("mxs-dma-apbh", -1, + res, ARRAY_SIZE(res), NULL, 0, + DMA_BIT_MASK(32)); +} diff --git a/arch/arm/plat-mxc/devices/platform-fec.c b/arch/arm/plat-mxc/devices/platform-fec.c new file mode 100644 index 00000000..0a03ea9b --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-fec.c @@ -0,0 +1,83 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + * + * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. + */ +#include <linux/dma-mapping.h> +#include <asm/sizes.h> +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx_fec_data_entry_single(soc, _devid) \ + { \ + .iobase = soc ## _FEC_BASE_ADDR, \ + .irq = soc ## _INT_FEC, \ + .devid = _devid, \ + } + +#ifdef CONFIG_SOC_IMX25 +const struct imx_fec_data imx25_fec_data __initconst = + imx_fec_data_entry_single(MX25, "imx28-fec"); +#endif /* ifdef CONFIG_SOC_IMX25 */ + +#ifdef CONFIG_SOC_IMX27 +const struct imx_fec_data imx27_fec_data __initconst = + imx_fec_data_entry_single(MX27, "imx28-fec"); +#endif /* ifdef CONFIG_SOC_IMX27 */ + +#ifdef CONFIG_SOC_IMX35 +const struct imx_fec_data imx35_fec_data __initconst = + imx_fec_data_entry_single(MX35, "imx28-fec"); +#endif + +#ifdef CONFIG_SOC_IMX50 +const struct imx_fec_data imx50_fec_data __initconst = + imx_fec_data_entry_single(MX50, "fec"); +#endif + +#ifdef CONFIG_SOC_IMX51 +const struct imx_fec_data imx51_fec_data __initconst = + imx_fec_data_entry_single(MX51, "fec"); +#endif + +#ifdef CONFIG_SOC_IMX53 +const struct imx_fec_data imx53_fec_data __initconst = + imx_fec_data_entry_single(MX53, "fec"); +#endif + +#ifdef CONFIG_SOC_IMX6Q +const struct imx_fec_data imx6q_fec_data __initconst = + imx_fec_data_entry_single(MX6Q, "enet"); + +const struct imx_fec_data imx6sl_fec_data __initconst = + imx_fec_data_entry_single(MX6DL, "fec"); +#endif + +struct platform_device *__init imx_add_fec( + const struct imx_fec_data *data, + const struct fec_platform_data *pdata) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + + if (!fuse_dev_is_available(MXC_DEV_ENET)) + return ERR_PTR(-ENODEV); + + return imx_add_platform_device_dmamask(data->devid, 0, + res, ARRAY_SIZE(res), + pdata, sizeof(*pdata), DMA_BIT_MASK(32)); +} diff --git a/arch/arm/plat-mxc/devices/platform-flexcan.c b/arch/arm/plat-mxc/devices/platform-flexcan.c new file mode 100644 index 00000000..d660237b --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-flexcan.c @@ -0,0 +1,68 @@ +/* + * Copyright (C) 2010 Pengutronix, Marc Kleine-Budde <kernel@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx_flexcan_data_entry_single(soc, _devid, _id, _hwid, _size) \ + { \ + .devid = _devid, \ + .id = _id, \ + .iobase = soc ## _CAN ## _hwid ## _BASE_ADDR, \ + .iosize = _size, \ + .irq = soc ## _INT_CAN ## _hwid, \ + } + +#define imx_flexcan_data_entry(soc, _devid, _id, _hwid, _size) \ + [_id] = imx_flexcan_data_entry_single(soc, _devid, _id, _hwid, _size) + +#ifdef CONFIG_SOC_IMX25 +const struct imx_flexcan_data imx25_flexcan_data[] __initconst = { +#define imx25_flexcan_data_entry(_id, _hwid) \ + imx_flexcan_data_entry(MX25, "imx25-flexcan", _id, _hwid, SZ_16K) + imx25_flexcan_data_entry(0, 1), + imx25_flexcan_data_entry(1, 2), +}; +#endif /* ifdef CONFIG_SOC_IMX25 */ + +#ifdef CONFIG_SOC_IMX35 +const struct imx_flexcan_data imx35_flexcan_data[] __initconst = { +#define imx35_flexcan_data_entry(_id, _hwid) \ + imx_flexcan_data_entry(MX35, "imx35-flexcan", _id, _hwid, SZ_16K) + imx35_flexcan_data_entry(0, 1), + imx35_flexcan_data_entry(1, 2), +}; +#endif /* ifdef CONFIG_SOC_IMX35 */ + +#ifdef CONFIG_SOC_IMX6Q +const struct imx_flexcan_data imx6q_flexcan_data[] __initconst = { +#define imx6q_flexcan_data_entry(_id, _hwid) \ + imx_flexcan_data_entry(MX6Q, "imx6q-flexcan", _id, _hwid, SZ_16K) + imx6q_flexcan_data_entry(0, 1), + imx6q_flexcan_data_entry(1, 2), +}; +#endif /* ifdef CONFIG_SOC_IMX6Q*/ + +struct platform_device *__init imx_add_flexcan( + const struct imx_flexcan_data *data, + const struct flexcan_platform_data *pdata) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + data->iosize - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + + return imx_add_platform_device(data->devid, data->id, + res, ARRAY_SIZE(res), pdata, sizeof(*pdata)); +} diff --git a/arch/arm/plat-mxc/devices/platform-fsl-usb2-otg.c b/arch/arm/plat-mxc/devices/platform-fsl-usb2-otg.c new file mode 100644 index 00000000..cbb56ff0 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-fsl-usb2-otg.c @@ -0,0 +1,90 @@ +/* + * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. All Rights Reserved. + * + * Based on Uwe Kleine-Koenig's platform-fsl-usb2-udc.c + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx_fsl_usb2_otg_data_entry_single(soc) \ + { \ + .iobase = soc ## _USB_OTG_BASE_ADDR, \ + .irq = soc ## _INT_USB_OTG, \ + } + + +#ifdef CONFIG_SOC_IMX6Q +const struct imx_fsl_usb2_otg_data imx6q_fsl_usb2_otg_data __initconst = + imx_fsl_usb2_otg_data_entry_single(MX6Q); +#endif /* ifdef CONFIG_SOC_IMX6Q */ + +struct platform_device *__init imx_add_fsl_usb2_otg( + const struct imx_fsl_usb2_otg_data *data, + const struct fsl_usb2_platform_data *pdata) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + SZ_512 - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + + int ret = -ENOMEM; + const char *name = "fsl-usb2-otg"; + int id = -1; + unsigned int num_resources = ARRAY_SIZE(res); + size_t size_data = sizeof(*pdata); + u64 dmamask = DMA_BIT_MASK(32); + struct platform_device *pdev; + + pdev = platform_device_alloc(name, id); + if (!pdev) + goto err; + + if (dmamask) { + /* + * This memory isn't freed when the device is put, + * I don't have a nice idea for that though. Conceptually + * dma_mask in struct device should not be a pointer. + * See http://thread.gmane.org/gmane.linux.kernel.pci/9081 + */ + pdev->dev.dma_mask = + kmalloc(sizeof(*pdev->dev.dma_mask), GFP_KERNEL); + if (!pdev->dev.dma_mask) + /* ret is still -ENOMEM; */ + goto err; + + *pdev->dev.dma_mask = dmamask; + pdev->dev.coherent_dma_mask = dmamask; + } + + ret = platform_device_add_resources(pdev, res, num_resources); + if (ret) + goto err; + + if (data) { + ret = platform_device_add_data(pdev, pdata, size_data); + if (ret) + goto err; + } + + return pdev; +err: + if (dmamask) + kfree(pdev->dev.dma_mask); + platform_device_put(pdev); + return ERR_PTR(ret); +} +EXPORT_SYMBOL(imx_add_fsl_usb2_otg); + diff --git a/arch/arm/plat-mxc/devices/platform-fsl-usb2-udc.c b/arch/arm/plat-mxc/devices/platform-fsl-usb2-udc.c new file mode 100644 index 00000000..6e65a91c --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-fsl-usb2-udc.c @@ -0,0 +1,110 @@ +/* + * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. All Rights Reserved. + * + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <linux/dma-mapping.h> +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx_fsl_usb2_udc_data_entry_single(soc) \ + { \ + .iobase = soc ## _USB_OTG_BASE_ADDR, \ + .irq = soc ## _INT_USB_OTG, \ + } + +#ifdef CONFIG_SOC_IMX25 +const struct imx_fsl_usb2_udc_data imx25_fsl_usb2_udc_data __initconst = + imx_fsl_usb2_udc_data_entry_single(MX25); +#endif /* ifdef CONFIG_SOC_IMX25 */ + +#ifdef CONFIG_SOC_IMX27 +const struct imx_fsl_usb2_udc_data imx27_fsl_usb2_udc_data __initconst = + imx_fsl_usb2_udc_data_entry_single(MX27); +#endif /* ifdef CONFIG_SOC_IMX27 */ + +#ifdef CONFIG_SOC_IMX31 +const struct imx_fsl_usb2_udc_data imx31_fsl_usb2_udc_data __initconst = + imx_fsl_usb2_udc_data_entry_single(MX31); +#endif /* ifdef CONFIG_SOC_IMX31 */ + +#ifdef CONFIG_SOC_IMX35 +const struct imx_fsl_usb2_udc_data imx35_fsl_usb2_udc_data __initconst = + imx_fsl_usb2_udc_data_entry_single(MX35); +#endif /* ifdef CONFIG_SOC_IMX35 */ + +#ifdef CONFIG_SOC_IMX6Q +const struct imx_fsl_usb2_udc_data imx6q_fsl_usb2_udc_data __initconst = + imx_fsl_usb2_udc_data_entry_single(MX6Q); +#endif /* ifdef CONFIG_SOC_IMX6Q */ + +struct platform_device *__init imx_add_fsl_usb2_udc( + const struct imx_fsl_usb2_udc_data *data, + const struct fsl_usb2_platform_data *pdata) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + SZ_512 - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + + int ret = -ENOMEM; + const char *name = "fsl-usb2-udc"; + int id = -1; + unsigned int num_resources = ARRAY_SIZE(res); + size_t size_data = sizeof(*pdata); + u64 dmamask = DMA_BIT_MASK(32); + struct platform_device *pdev; + + pdev = platform_device_alloc(name, id); + if (!pdev) + goto err; + + if (dmamask) { + /* + * This memory isn't freed when the device is put, + * I don't have a nice idea for that though. Conceptually + * dma_mask in struct device should not be a pointer. + * See http://thread.gmane.org/gmane.linux.kernel.pci/9081 + */ + pdev->dev.dma_mask = + kmalloc(sizeof(*pdev->dev.dma_mask), GFP_KERNEL); + if (!pdev->dev.dma_mask) + /* ret is still -ENOMEM; */ + goto err; + + *pdev->dev.dma_mask = dmamask; + pdev->dev.coherent_dma_mask = dmamask; + } + + ret = platform_device_add_resources(pdev, res, num_resources); + if (ret) + goto err; + + if (data) { + ret = platform_device_add_data(pdev, pdata, size_data); + if (ret) + goto err; + } + + return pdev; + +err: + if (dmamask) + kfree(pdev->dev.dma_mask); + platform_device_put(pdev); + return ERR_PTR(ret); +} +EXPORT_SYMBOL(imx_add_fsl_usb2_udc); + diff --git a/arch/arm/plat-mxc/devices/platform-fsl-usb2-wakeup.c b/arch/arm/plat-mxc/devices/platform-fsl-usb2-wakeup.c new file mode 100644 index 00000000..3dacd287 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-fsl-usb2-wakeup.c @@ -0,0 +1,55 @@ +/* + * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. All Rights Reserved. + * + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <mach/hardware.h> +#include <mach/devices-common.h> +#define imx_fsl_usb2_wakeup_data_entry_single(soc, _id, hs) \ + { \ + .id = _id, \ + .irq_phy = soc ## _INT_USB_PHY ## _id, \ + .irq_core = soc ## _INT_USB_ ## hs, \ + } + +#ifdef CONFIG_SOC_IMX6Q +const struct imx_fsl_usb2_wakeup_data imx6q_fsl_otg_wakeup_data __initconst = + imx_fsl_usb2_wakeup_data_entry_single(MX6Q, 0, OTG); +const struct imx_fsl_usb2_wakeup_data imx6q_fsl_hs_wakeup_data[] __initconst = { + imx_fsl_usb2_wakeup_data_entry_single(MX6Q, 1, HS1), + imx_fsl_usb2_wakeup_data_entry_single(MX6Q, 2, HS2), + imx_fsl_usb2_wakeup_data_entry_single(MX6Q, 3, HS3), +}; + +const struct imx_fsl_usb2_wakeup_data imx6sl_fsl_hs_wakeup_data[] __initconst = { + imx_fsl_usb2_wakeup_data_entry_single(MX6SL, 1, HS1), + imx_fsl_usb2_wakeup_data_entry_single(MX6SL, 2, HS2), + imx_fsl_usb2_wakeup_data_entry_single(MX6SL, 3, HS3), +}; +#endif /* ifdef CONFIG_SOC_IMX6Q */ + +struct platform_device *__init imx_add_fsl_usb2_wakeup( + const struct imx_fsl_usb2_wakeup_data *data, + const struct fsl_usb2_wakeup_platform_data *pdata) +{ + struct resource res[] = { + { + .start = data->irq_phy, + .end = data->irq_phy, + .flags = IORESOURCE_IRQ, + }, { + .start = data->irq_core, + .end = data->irq_core, + .flags = IORESOURCE_IRQ, + }, + }; + return imx_add_platform_device_dmamask("usb-wakeup", data->id, + res, ARRAY_SIZE(res), + pdata, sizeof(*pdata), DMA_BIT_MASK(32)); +} +EXPORT_SYMBOL(imx_add_fsl_usb2_wakeup); diff --git a/arch/arm/plat-mxc/devices/platform-gpio_keys.c b/arch/arm/plat-mxc/devices/platform-gpio_keys.c new file mode 100644 index 00000000..1c53a532 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-gpio_keys.c @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, + * Boston, MA 02110-1301, USA. + */ +#include <asm/sizes.h> +#include <mach/hardware.h> +#include <mach/devices-common.h> + +struct platform_device *__init imx_add_gpio_keys( + const struct gpio_keys_platform_data *pdata) +{ + return imx_add_platform_device("gpio-keys", -1, NULL, + 0, pdata, sizeof(*pdata)); +} diff --git a/arch/arm/plat-mxc/devices/platform-imx-anatop-thermal.c b/arch/arm/plat-mxc/devices/platform-imx-anatop-thermal.c new file mode 100644 index 00000000..352d0f0c --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx-anatop-thermal.c @@ -0,0 +1,59 @@ +/* + * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx_anatop_thermal_imx_data_entry_single(soc) \ + { \ + .iobase = ANATOP_BASE_ADDR, \ + .calibration_addr = OCOTP_BASE_ADDR + 0x4E0, \ + .irq = MXC_INT_ANATOP_TEMPSNSR \ + } + +#ifdef CONFIG_SOC_IMX6Q +const struct imx_anatop_thermal_imx_data imx6q_anatop_thermal_imx_data __initconst = + imx_anatop_thermal_imx_data_entry_single(MX6Q); +#endif /* ifdef CONFIG_SOC_IMX6Q */ + +struct platform_device *__init imx_add_anatop_thermal_imx( + const struct imx_anatop_thermal_imx_data *data, + const struct anatop_thermal_platform_data *pdata) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = data->calibration_addr, + .end = data->calibration_addr + SZ_4 - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + + return imx_add_platform_device("anatop_thermal", 0, + res, ARRAY_SIZE(res), NULL, 0); +} diff --git a/arch/arm/plat-mxc/devices/platform-imx-asrc.c b/arch/arm/plat-mxc/devices/platform-imx-asrc.c new file mode 100644 index 00000000..c112a9ba --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx-asrc.c @@ -0,0 +1,72 @@ +/* + * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx_imx_asrc_data_entry(soc, _id, _size) \ + [_id] = { \ + .id = _id, \ + .iobase = soc ## _ASRC ## _BASE_ADDR, \ + .iosize = _size, \ + .irq = soc ## _INT_ASRC, \ + .dmatx1 = soc ## _DMA_REQ_ASRC## _TX1, \ + .dmarx1 = soc ## _DMA_REQ_ASRC## _RX1, \ + .dmatx2 = soc ## _DMA_REQ_ASRC## _TX2, \ + .dmarx2 = soc ## _DMA_REQ_ASRC## _RX2, \ + .dmatx3 = soc ## _DMA_REQ_ASRC## _TX3, \ + .dmarx3 = soc ## _DMA_REQ_ASRC## _RX3, \ + } + +#ifdef CONFIG_SOC_IMX53 +const struct imx_imx_asrc_data imx53_imx_asrc_data[] __initconst = { +#define imx53_imx_asrc_data_entry(_id) \ + imx_imx_asrc_data_entry(MX53, _id, SZ_4K) + imx53_imx_asrc_data_entry(0), +}; +#endif /* ifdef CONFIG_SOC_IMX6Q */ + +#ifdef CONFIG_SOC_IMX6Q +const struct imx_imx_asrc_data imx6q_imx_asrc_data[] __initconst = { +#define imx6q_imx_asrc_data_entry(_id) \ + imx_imx_asrc_data_entry(MX6Q, _id, SZ_4K) + imx6q_imx_asrc_data_entry(0), +}; +#endif /* ifdef CONFIG_SOC_IMX6Q */ + +struct platform_device *__init imx_add_imx_asrc( + const struct imx_imx_asrc_data *data, + const struct imx_asrc_platform_data *pdata) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + data->iosize - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, +#define DMARES(_name) { \ + .name = #_name, \ + .start = data->dma ## _name, \ + .end = data->dma ## _name, \ + .flags = IORESOURCE_DMA, \ +} + DMARES(tx1), + DMARES(rx1), + DMARES(tx2), + DMARES(rx2), + DMARES(tx3), + DMARES(rx3), + }; + + return imx_add_platform_device("mxc_asrc", data->id, + res, ARRAY_SIZE(res), + pdata, sizeof(*pdata)); +} diff --git a/arch/arm/plat-mxc/devices/platform-imx-caam.c b/arch/arm/plat-mxc/devices/platform-imx-caam.c new file mode 100644 index 00000000..aaaf501f --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx-caam.c @@ -0,0 +1,107 @@ +/* + * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <asm/sizes.h> +#include <mach/hardware.h> +#include <mach/devices-common.h> + +/* + * security violation interrupt is used as CAAM base _INT_SNVS_SEC + * SNVS consolidated = _INT_SNVS + * JR0 = MXC_INT_CAAM_INT0_NUM + * JR1 = MXC_INT_CAAM_INT1_NUM + */ + +const struct imx_caam_data imx6q_imx_caam_data __initconst = { + .iobase_caam = MXC_CAAM_BASE_ADDR, + .iobase_caam_sm = CAAM_SECMEM_BASE_ADDR, + .iobase_snvs = MX6Q_SNVS_BASE_ADDR, + .irq_sec_vio = MXC_INT_SNVS_SEC, + .irq_snvs = MX6Q_INT_SNVS, + .jr[0].offset_jr = 0x1000, + .jr[0].irq_jr = MXC_INT_CAAM_INT0_NUM, + .jr[1].offset_jr = 0x2000, + .jr[1].irq_jr = MXC_INT_CAAM_INT1_NUM, +}; + +struct platform_device *__init imx_add_caam( + const struct imx_caam_data *data) +{ + u32 res_count = 0; + struct resource res[] = { + { + /* Define base range for entire CAAM register map */ + .name = "iobase_caam", + .start = data->iobase_caam, + .end = data->iobase_caam + SZ_64K - 1, + .flags = IORESOURCE_MEM, + }, { + /* Define range for secure memory */ + .name = "iobase_caam_sm", + .start = data->iobase_caam_sm, + .end = data->iobase_caam_sm + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, { + /* Define range for SNVS */ + .name = "iobase_snvs", + .start = data->iobase_snvs, + .end = data->iobase_snvs + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, { + /* Define interrupt for security violations */ + .name = "irq_sec_vio", + .start = data->irq_sec_vio, + .end = data->irq_sec_vio, + .flags = IORESOURCE_IRQ, + }, { + /* Define general SNVS interrupt */ + .name = "irq_snvs", + .start = data->irq_snvs, + .end = data->irq_snvs, + .flags = IORESOURCE_IRQ, + }, { + .name = "offset_jr0", + .start = data->jr[0].offset_jr, + .end = data->jr[0].offset_jr, + .flags = IORESOURCE_MEM, + }, { + .name = "irq_jr0", + .start = data->jr[0].irq_jr, + .end = data->jr[0].irq_jr, + .flags = IORESOURCE_IRQ, + }, { + .name = "offset_jr1", + .start = data->jr[1].offset_jr, + .end = data->jr[1].offset_jr, + .flags = IORESOURCE_MEM, + }, { + .name = "irq_jr1", + .start = data->jr[1].irq_jr, + .end = data->jr[1].irq_jr, + .flags = IORESOURCE_IRQ, + }, + }; + + res_count = ARRAY_SIZE(res); + BUG_ON(!res_count); + + return imx_add_platform_device("caam", 0, + res, ARRAY_SIZE(res), NULL, 0); +} diff --git a/arch/arm/plat-mxc/devices/platform-imx-dcp.c b/arch/arm/plat-mxc/devices/platform-imx-dcp.c new file mode 100755 index 00000000..a77840b9 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx-dcp.c @@ -0,0 +1,71 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ +#include <asm/sizes.h> +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#ifdef CONFIG_SOC_IMX50 +#define imx_dcp_data_entry_single(soc) \ +{ \ + .iobase = soc ## _DCP_BASE_ADDR, \ + .irq1 = soc ## _INT_DCP_CHAN0, \ + .irq2 = soc ## _INT_DCP_CHAN1_3, \ +} + +const struct imx_dcp_data imx50_dcp_data __initconst = + imx_dcp_data_entry_single(MX50); +#endif /* ifdef CONFIG_SOC_IMX50 */ + +#ifdef CONFIG_SOC_IMX6SL +#define imx_dcp_data_entry_single(soc) \ +{ \ + .iobase = soc ## _DCP_BASE_ADDR, \ + .irq1 = soc ## _INT_DCP_CH0, \ + .irq2 = soc ## _INT_DCP_GEN, \ +} + +const struct imx_dcp_data imx6sl_dcp_data __initconst = + imx_dcp_data_entry_single(MX6SL); +#endif /* ifdef CONFIG_SOC_IMX6SL */ + +struct platform_device *__init imx_add_dcp( + const struct imx_dcp_data *data) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + SZ_8K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = data->irq1, + .end = data->irq1, + .flags = IORESOURCE_IRQ, + }, + { + .start = data->irq2, + .end = data->irq2, + .flags = IORESOURCE_IRQ, + }, + }; + + return imx_add_platform_device_dmamask("dcp", 0, + res, ARRAY_SIZE(res), NULL, 0, DMA_BIT_MASK(32)); +} diff --git a/arch/arm/plat-mxc/devices/platform-imx-dma.c b/arch/arm/plat-mxc/devices/platform-imx-dma.c new file mode 100755 index 00000000..e7caaf4c --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx-dma.c @@ -0,0 +1,282 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <linux/compiler.h> +#include <linux/err.h> +#include <linux/init.h> + +#include <mach/hardware.h> +#include <mach/devices-common.h> +#include <mach/sdma.h> + +struct imx_imx_sdma_data { + resource_size_t iobase; + resource_size_t irq; + struct sdma_platform_data pdata; +}; + +#define imx_imx_sdma_data_entry_single(soc, _sdma_version, _cpu_name, _to_version)\ + { \ + .iobase = soc ## _SDMA ## _BASE_ADDR, \ + .irq = soc ## _INT_SDMA, \ + .pdata = { \ + .sdma_version = _sdma_version, \ + .cpu_name = _cpu_name, \ + .to_version = _to_version, \ + }, \ + } + +#ifdef CONFIG_SOC_IMX25 +struct imx_imx_sdma_data imx25_imx_sdma_data __initconst = + imx_imx_sdma_data_entry_single(MX25, 1, "imx25", 0); +#endif /* ifdef CONFIG_SOC_IMX25 */ + +#ifdef CONFIG_SOC_IMX31 +struct imx_imx_sdma_data imx31_imx_sdma_data __initdata = + imx_imx_sdma_data_entry_single(MX31, 1, "imx31", 0); +#endif /* ifdef CONFIG_SOC_IMX31 */ + +#ifdef CONFIG_SOC_IMX35 +struct imx_imx_sdma_data imx35_imx_sdma_data __initdata = + imx_imx_sdma_data_entry_single(MX35, 2, "imx35", 0); +#endif /* ifdef CONFIG_SOC_IMX35 */ + +#ifdef CONFIG_SOC_IMX51 +struct imx_imx_sdma_data imx51_imx_sdma_data __initconst = + imx_imx_sdma_data_entry_single(MX51, 2, "imx51", 0); +#endif /* ifdef CONFIG_SOC_IMX51 */ + +#ifdef CONFIG_SOC_IMX53 +struct imx_imx_sdma_data imx53_imx_sdma_data __initconst = + imx_imx_sdma_data_entry_single(MX53, 2, "imx53", 1); +#endif /* ifdef CONFIG_SOC_IMX51 */ + +#ifdef CONFIG_SOC_IMX6Q +struct imx_imx_sdma_data imx6q_imx_sdma_data __initconst = + imx_imx_sdma_data_entry_single(MX6Q, 2, "imx6q", 1); +#endif /* ifdef CONFIG_SOC_IMX6Q */ + +static struct platform_device __init __maybe_unused *imx_add_imx_sdma( + const struct imx_imx_sdma_data *data) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + + return imx_add_platform_device("imx-sdma", -1, + res, ARRAY_SIZE(res), + &data->pdata, sizeof(data->pdata)); +} + +static struct platform_device __init __maybe_unused *imx_add_imx_dma(void) +{ + return imx_add_platform_device("imx-dma", -1, NULL, 0, NULL, 0); +} + +#ifdef CONFIG_SOC_IMX25 +static struct sdma_script_start_addrs addr_imx25_to1 = { + .ap_2_ap_addr = 729, + .uart_2_mcu_addr = 904, + .per_2_app_addr = 1255, + .mcu_2_app_addr = 834, + .uartsh_2_mcu_addr = 1120, + .per_2_shp_addr = 1329, + .mcu_2_shp_addr = 1048, + .ata_2_mcu_addr = 1560, + .mcu_2_ata_addr = 1479, + .app_2_per_addr = 1189, + .app_2_mcu_addr = 770, + .shp_2_per_addr = 1407, + .shp_2_mcu_addr = 979, +}; +#endif + +#ifdef CONFIG_SOC_IMX31 +static struct sdma_script_start_addrs addr_imx31_to1 = { + .per_2_per_addr = 1677, +}; + +static struct sdma_script_start_addrs addr_imx31_to2 = { + .ap_2_ap_addr = 423, + .ap_2_bp_addr = 829, + .bp_2_ap_addr = 1029, +}; +#endif + +#ifdef CONFIG_SOC_IMX35 +static struct sdma_script_start_addrs addr_imx35_to1 = { + .ap_2_ap_addr = 642, + .uart_2_mcu_addr = 817, + .mcu_2_app_addr = 747, + .uartsh_2_mcu_addr = 1183, + .per_2_shp_addr = 1033, + .mcu_2_shp_addr = 961, + .ata_2_mcu_addr = 1333, + .mcu_2_ata_addr = 1252, + .app_2_mcu_addr = 683, + .shp_2_per_addr = 1111, + .shp_2_mcu_addr = 892, +}; + +static struct sdma_script_start_addrs addr_imx35_to2 = { + .ap_2_ap_addr = 729, + .uart_2_mcu_addr = 904, + .per_2_app_addr = 1597, + .mcu_2_app_addr = 834, + .uartsh_2_mcu_addr = 1270, + .per_2_shp_addr = 1120, + .mcu_2_shp_addr = 1048, + .ata_2_mcu_addr = 1429, + .mcu_2_ata_addr = 1339, + .app_2_per_addr = 1531, + .app_2_mcu_addr = 770, + .shp_2_per_addr = 1198, + .shp_2_mcu_addr = 979, +}; +#endif + +#ifdef CONFIG_SOC_IMX51 +static struct sdma_script_start_addrs addr_imx51_to3 = { + .ap_2_ap_addr = 642, + .uart_2_mcu_addr = 817, + .mcu_2_app_addr = 747, + .mcu_2_shp_addr = 961, + .ata_2_mcu_addr = 1473, + .mcu_2_ata_addr = 1392, + .app_2_per_addr = 1033, + .app_2_mcu_addr = 683, + .shp_2_per_addr = 1251, + .shp_2_mcu_addr = 892, +}; +#endif + +#ifdef CONFIG_SOC_IMX53 +static struct sdma_script_start_addrs addr_imx53_to1 = { + .ap_2_ap_addr = 642, + .uart_2_mcu_addr = 817, + .mcu_2_app_addr = 747, + .per_2_per_addr = 6331, + .uartsh_2_mcu_addr = 1032, + .mcu_2_shp_addr = 960, + .app_2_mcu_addr = 683, + .shp_2_mcu_addr = 891, + .spdif_2_mcu_addr = 1100, + .mcu_2_spdif_addr = 1134, +}; +#endif + +#ifdef CONFIG_SOC_IMX6Q +static struct sdma_script_start_addrs addr_imx6q_to1 = { + .ap_2_ap_addr = 642, + .uart_2_mcu_addr = 817, + .mcu_2_app_addr = 747, + .per_2_per_addr = 6331, + .uartsh_2_mcu_addr = 1032, + .mcu_2_shp_addr = 960, + .app_2_mcu_addr = 683, + .shp_2_mcu_addr = 891, + .spdif_2_mcu_addr = 1100, + .mcu_2_spdif_addr = 1134, + .mcu_2_ssish_addr = 6242, + .ssish_2_mcu_addr = 6678, +}; +#endif + +static int __init imxXX_add_imx_dma(void) +{ + struct platform_device *ret; + +#if defined(CONFIG_SOC_IMX21) || defined(CONFIG_SOC_IMX27) + if (cpu_is_mx21() || cpu_is_mx27()) + ret = imx_add_imx_dma(); + else +#endif + +#if defined(CONFIG_SOC_IMX25) + if (cpu_is_mx25()) { + imx25_imx_sdma_data.pdata.script_addrs = &addr_imx25_to1; + ret = imx_add_imx_sdma(&imx25_imx_sdma_data); + } else +#endif + +#if defined(CONFIG_SOC_IMX31) + if (cpu_is_mx31()) { + int to_version = mx31_revision() >> 4; + imx31_imx_sdma_data.pdata.to_version = to_version; + if (to_version == 1) + imx31_imx_sdma_data.pdata.script_addrs = + &addr_imx31_to1; + else + imx31_imx_sdma_data.pdata.script_addrs = + &addr_imx31_to2; + ret = imx_add_imx_sdma(&imx31_imx_sdma_data); + } else +#endif + +#if defined(CONFIG_SOC_IMX35) + if (cpu_is_mx35()) { + int to_version = mx35_revision() >> 4; + imx35_imx_sdma_data.pdata.to_version = to_version; + if (to_version == 1) + imx35_imx_sdma_data.pdata.script_addrs = + &addr_imx35_to1; + else + imx35_imx_sdma_data.pdata.script_addrs = + &addr_imx35_to2; + ret = imx_add_imx_sdma(&imx35_imx_sdma_data); + } else +#endif + +#if defined(CONFIG_SOC_IMX51) + if (cpu_is_mx51()) { + int to_version = mx51_revision() >> 4; + imx51_imx_sdma_data.pdata.to_version = to_version; + if (to_version == 3) + imx51_imx_sdma_data.pdata.script_addrs = + &addr_imx51_to3; + ret = imx_add_imx_sdma(&imx51_imx_sdma_data); + } else +#endif +#if defined(CONFIG_SOC_IMX53) + if (cpu_is_mx53()) { + int to_version = 1; + imx53_imx_sdma_data.pdata.to_version = to_version; + if (to_version == 1) + imx53_imx_sdma_data.pdata.script_addrs = + &addr_imx53_to1; + ret = imx_add_imx_sdma(&imx53_imx_sdma_data); + } else +#endif +#if defined(CONFIG_ARCH_MX6) + int to_version = 1; + imx6q_imx_sdma_data.pdata.to_version = to_version; + if (to_version == 1) + imx6q_imx_sdma_data.pdata.script_addrs = + &addr_imx6q_to1; + ret = imx_add_imx_sdma(&imx6q_imx_sdma_data); + if (IS_ERR(ret)) + return PTR_ERR(ret); + + return 0; +#endif + ret = ERR_PTR(-ENODEV); + + if (IS_ERR(ret)) + return PTR_ERR(ret); + + return 0; +} +arch_initcall(imxXX_add_imx_dma); diff --git a/arch/arm/plat-mxc/devices/platform-imx-elcdif-fb.c b/arch/arm/plat-mxc/devices/platform-imx-elcdif-fb.c new file mode 100644 index 00000000..62cf9c6d --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx-elcdif-fb.c @@ -0,0 +1,58 @@ +/* + * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <asm/sizes.h> +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx_elcdif_data_entry_single(soc, size) \ + { \ + .iobase = soc ## _ELCDIF_BASE_ADDR, \ + .irq = soc ## _INT_ELCDIF, \ + .iosize = size, \ + } + +#ifdef CONFIG_IMX_HAVE_PLATFORM_IMX_ELCDIF //[ +#ifdef CONFIG_SOC_IMX6SL +const struct imx_elcdif_data imx6dl_elcdif_data __initconst = + imx_elcdif_data_entry_single(MX6DL, SZ_16K); +#endif + +struct platform_device *__init imx_add_imx_elcdif( + const struct imx_elcdif_data *data, + const struct mxc_fb_platform_data *pdata) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + data->iosize - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + + return imx_add_platform_device_dmamask("mxc_elcdif_fb", -1, + res, ARRAY_SIZE(res), pdata, sizeof(*pdata), DMA_BIT_MASK(32)); +} +#endif //]CONFIG_IMX_HAVE_PLATFORM_IMX_ELCDIF + diff --git a/arch/arm/plat-mxc/devices/platform-imx-epdc-fb.c b/arch/arm/plat-mxc/devices/platform-imx-epdc-fb.c new file mode 100644 index 00000000..459e6cc3 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx-epdc-fb.c @@ -0,0 +1,64 @@ +/* + * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <asm/sizes.h> +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx_epdc_data_entry_single(soc, size) \ + { \ + .iobase = soc ## _EPDC_BASE_ADDR, \ + .irq = soc ## _INT_EPDC, \ + .iosize = size, \ + } + +#ifdef CONFIG_SOC_IMX50 +const struct imx_epdc_data imx50_epdc_data __initconst = + imx_epdc_data_entry_single(MX50, SZ_4K); +#endif + +#ifdef CONFIG_SOC_IMX6Q +const struct imx_epdc_data imx6dl_epdc_data __initconst = + imx_epdc_data_entry_single(MX6DL, SZ_16K); +#endif + +struct platform_device *__init imx_add_imx_epdc( + const struct imx_epdc_data *data, + const struct imx_epdc_fb_platform_data *pdata) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + data->iosize - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + + if (!fuse_dev_is_available(MXC_DEV_EPDC)) + return ERR_PTR(-ENODEV); + + return imx_add_platform_device_dmamask("imx_epdc_fb", -1, + res, ARRAY_SIZE(res), pdata, sizeof(*pdata), DMA_BIT_MASK(32)); +} + diff --git a/arch/arm/plat-mxc/devices/platform-imx-esai.c b/arch/arm/plat-mxc/devices/platform-imx-esai.c new file mode 100644 index 00000000..03bd53ba --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx-esai.c @@ -0,0 +1,75 @@ +/* + * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ + +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx53_esai_data_entry(soc, _id, _size) \ + [_id] = { \ + .id = _id, \ + .iobase = MX53_ESAI_BASE_ADDR, \ + .iosize = _size, \ + .irq = MX53_INT_ESAI, \ + .dmatx = soc ## _DMA_REQ_ESAI ## _TX, \ + .dmarx = soc ## _DMA_REQ_ESAI ## _RX, \ + } + +#define imx6q_esai_data_entry(soc, _id, _size) \ + [_id] = { \ + .id = _id, \ + .iobase = ESAI1_BASE_ADDR, \ + .iosize = _size, \ + .irq = MXC_INT_ESAI, \ + .dmatx = soc ## _DMA_REQ_ESAI ## _TX, \ + .dmarx = soc ## _DMA_REQ_ESAI ## _RX, \ + } + +#ifdef CONFIG_SOC_IMX53 +const struct imx_imx_esai_data imx53_imx_esai_data[] __initconst = { +#define imx53_imx_esai_data_entry(_id) \ + imx53_esai_data_entry(MX53, _id, SZ_4K) + imx53_imx_esai_data_entry(0), +}; +#endif /* ifdef CONFIG_SOC_IMX53 */ + +#ifdef CONFIG_SOC_IMX6Q +const struct imx_imx_esai_data imx6q_imx_esai_data[] __initconst = { +#define imx6q_imx_esai_data_entry(_id) \ + imx6q_esai_data_entry(MX6Q, _id, SZ_4K) + imx6q_imx_esai_data_entry(0), +}; +#endif /* ifdef CONFIG_SOC_IMX6Q */ + +struct platform_device *__init imx_add_imx_esai( + const struct imx_imx_esai_data *data, + const struct imx_esai_platform_data *pdata) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + data->iosize - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, +#define DMARES(_name) { \ + .name = #_name, \ + .start = data->dma ## _name, \ + .end = data->dma ## _name, \ + .flags = IORESOURCE_DMA, \ +} + DMARES(tx), + DMARES(rx), + }; + + return imx_add_platform_device("imx-esai", data->id, + res, ARRAY_SIZE(res), + pdata, sizeof(*pdata)); +} diff --git a/arch/arm/plat-mxc/devices/platform-imx-fb.c b/arch/arm/plat-mxc/devices/platform-imx-fb.c new file mode 100644 index 00000000..2b0b5e0a --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx-fb.c @@ -0,0 +1,58 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <linux/dma-mapping.h> +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx_imx_fb_data_entry_single(soc, _size) \ + { \ + .iobase = soc ## _LCDC_BASE_ADDR, \ + .iosize = _size, \ + .irq = soc ## _INT_LCDC, \ + } + +#ifdef CONFIG_SOC_IMX1 +const struct imx_imx_fb_data imx1_imx_fb_data __initconst = + imx_imx_fb_data_entry_single(MX1, SZ_4K); +#endif /* ifdef CONFIG_SOC_IMX1 */ + +#ifdef CONFIG_SOC_IMX21 +const struct imx_imx_fb_data imx21_imx_fb_data __initconst = + imx_imx_fb_data_entry_single(MX21, SZ_4K); +#endif /* ifdef CONFIG_SOC_IMX21 */ + +#ifdef CONFIG_SOC_IMX25 +const struct imx_imx_fb_data imx25_imx_fb_data __initconst = + imx_imx_fb_data_entry_single(MX25, SZ_16K); +#endif /* ifdef CONFIG_SOC_IMX25 */ + +#ifdef CONFIG_SOC_IMX27 +const struct imx_imx_fb_data imx27_imx_fb_data __initconst = + imx_imx_fb_data_entry_single(MX27, SZ_4K); +#endif /* ifdef CONFIG_SOC_IMX27 */ + +struct platform_device *__init imx_add_imx_fb( + const struct imx_imx_fb_data *data, + const struct imx_fb_platform_data *pdata) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + data->iosize - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + return imx_add_platform_device_dmamask("imx-fb", 0, + res, ARRAY_SIZE(res), + pdata, sizeof(*pdata), DMA_BIT_MASK(32)); +} diff --git a/arch/arm/plat-mxc/devices/platform-imx-fsl-csi.c b/arch/arm/plat-mxc/devices/platform-imx-fsl-csi.c new file mode 100644 index 00000000..8b6601cc --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx-fsl-csi.c @@ -0,0 +1,55 @@ +/* + * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <asm/sizes.h> +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx_fsl_csi_data_entry_single(soc, size) \ + { \ + .iobase = soc ## _CSI_BASE_ADDR, \ + .irq = soc ## _INT_CSI, \ + .iosize = size, \ + } + +#ifdef CONFIG_SOC_IMX6SL +const struct imx_fsl_csi_data imx6sl_csi_data __initconst = + imx_fsl_csi_data_entry_single(MX6SL, SZ_16K); +#endif + +struct platform_device *__init imx_add_fsl_csi( + const struct imx_fsl_csi_data *data) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + data->iosize - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + + return imx_add_platform_device("fsl_csi", -1, + res, ARRAY_SIZE(res), NULL, 0); +} + diff --git a/arch/arm/plat-mxc/devices/platform-imx-gpmi-nfc.c b/arch/arm/plat-mxc/devices/platform-imx-gpmi-nfc.c new file mode 100644 index 00000000..a1e297d5 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx-gpmi-nfc.c @@ -0,0 +1,109 @@ +/* + * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ +#include <linux/mtd/gpmi-nand.h> +#include <asm/sizes.h> +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#ifdef CONFIG_SOC_IMX50 +struct platform_device *__init +imx_add_gpmi(const struct gpmi_nfc_platform_data *platform_data) +{ + struct resource res[] = { + { /* GPMI */ + .name = GPMI_NFC_GPMI_REGS_ADDR_RES_NAME, + .flags = IORESOURCE_MEM, + .start = MX50_GPMI_BASE_ADDR, + .end = MX50_GPMI_BASE_ADDR + SZ_8K - 1, + }, { + .name = GPMI_NFC_GPMI_INTERRUPT_RES_NAME, + .flags = IORESOURCE_IRQ, + .start = MX50_INT_RAWNAND_GPMI, + .end = MX50_INT_RAWNAND_GPMI, + }, { /* BCH */ + .name = GPMI_NFC_BCH_REGS_ADDR_RES_NAME, + .flags = IORESOURCE_MEM, + .start = MX50_BCH_BASE_ADDR, + .end = MX50_BCH_BASE_ADDR + SZ_8K - 1, + }, { + .name = GPMI_NFC_BCH_INTERRUPT_RES_NAME, + .flags = IORESOURCE_IRQ, + .start = MX50_INT_RAWNAND_BCH, + .end = MX50_INT_RAWNAND_BCH, + }, { /* DMA */ + .name = GPMI_NFC_DMA_CHANNELS_RES_NAME, + .flags = IORESOURCE_DMA, + .start = MX50_DMA_CHANNEL_AHB_APBH_GPMI0, + .end = MX50_DMA_CHANNEL_AHB_APBH_GPMI7, + }, { + .name = GPMI_NFC_DMA_INTERRUPT_RES_NAME, + .flags = IORESOURCE_IRQ, + .start = MX50_INT_APBHDMA_CHAN0, + .end = MX50_INT_APBHDMA_CHAN7, + }, }; + + return imx_add_platform_device_dmamask("imx50-gpmi-nfc", 0, + res, ARRAY_SIZE(res), platform_data, + sizeof(*platform_data), DMA_BIT_MASK(32)); +} +#endif /* ifdef CONFIG_SOC_IMX50 */ + +#ifdef CONFIG_SOC_IMX6Q +struct platform_device *__init +imx_add_gpmi(const struct gpmi_nand_platform_data *platform_data) +{ + struct resource res[] = { + { /* GPMI */ + .name = GPMI_NAND_GPMI_REGS_ADDR_RES_NAME, + .flags = IORESOURCE_MEM, + .start = MX6Q_GPMI_BASE_ADDR, + .end = MX6Q_GPMI_BASE_ADDR + SZ_8K - 1, + }, { + .name = GPMI_NAND_GPMI_INTERRUPT_RES_NAME, + .flags = IORESOURCE_IRQ, + .start = MXC_INT_RAWNAND_GPMI, + .end = MXC_INT_RAWNAND_GPMI, + }, { /* BCH */ + .name = GPMI_NAND_BCH_REGS_ADDR_RES_NAME, + .flags = IORESOURCE_MEM, + .start = MX6Q_BCH_BASE_ADDR, + .end = MX6Q_BCH_BASE_ADDR + SZ_8K - 1, + }, { + .name = GPMI_NAND_BCH_INTERRUPT_RES_NAME, + .flags = IORESOURCE_IRQ, + .start = MXC_INT_RAWNAND_BCH, + .end = MXC_INT_RAWNAND_BCH, + }, { /* DMA */ + .name = GPMI_NAND_DMA_CHANNELS_RES_NAME, + .flags = IORESOURCE_DMA, + .start = MX6Q_DMA_CHANNEL_AHB_APBH_GPMI0, + .end = MX6Q_DMA_CHANNEL_AHB_APBH_GPMI7, + }, { + .name = GPMI_NAND_DMA_INTERRUPT_RES_NAME, + .flags = IORESOURCE_IRQ, + .start = MXC_INT_APBHDMA_DMA, + .end = MXC_INT_APBHDMA_DMA, + }, }; + + return imx_add_platform_device_dmamask("imx6q-gpmi-nand", 0, + res, ARRAY_SIZE(res), platform_data, + sizeof(*platform_data), DMA_BIT_MASK(32)); +} +#endif diff --git a/arch/arm/plat-mxc/devices/platform-imx-hdmi-soc-dai.c b/arch/arm/plat-mxc/devices/platform-imx-hdmi-soc-dai.c new file mode 100644 index 00000000..26f4ae71 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx-hdmi-soc-dai.c @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx_hdmi_soc_data_entry_single(soc) \ + { \ + .irq = soc ## _INT_HDMI_TX, \ + } + +#ifdef CONFIG_SOC_IMX6Q +const struct imx_hdmi_soc_data imx6q_imx_hdmi_soc_dai_data __initconst = + imx_hdmi_soc_data_entry_single(MX6Q); +#endif + +struct platform_device *__init imx_add_hdmi_soc_dai( + const struct imx_hdmi_soc_data *data) +{ + struct resource res[] = { + { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + + if (!fuse_dev_is_available(MXC_DEV_HDMI)) + return ERR_PTR(-ENODEV); + + return imx_add_platform_device("imx-hdmi-soc-dai", 0, + res, ARRAY_SIZE(res), NULL, 0); +} diff --git a/arch/arm/plat-mxc/devices/platform-imx-hdmi-soc.c b/arch/arm/plat-mxc/devices/platform-imx-hdmi-soc.c new file mode 100644 index 00000000..7be6756c --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx-hdmi-soc.c @@ -0,0 +1,33 @@ +/* + * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <mach/hardware.h> +#include <mach/devices-common.h> + +struct platform_device *__init imx_add_hdmi_soc(void) +{ + + if (!fuse_dev_is_available(MXC_DEV_HDMI)) + return ERR_PTR(-ENODEV); + + return imx_add_platform_device("mxc_hdmi_soc", 0, + NULL, 0, NULL, 0); +} + diff --git a/arch/arm/plat-mxc/devices/platform-imx-i2c.c b/arch/arm/plat-mxc/devices/platform-imx-i2c.c new file mode 100755 index 00000000..d11f52da --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx-i2c.c @@ -0,0 +1,130 @@ +/* + * Copyright (C) 2009-2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx_imx_i2c_data_entry_single(soc, _id, _hwid, _size) \ + { \ + .id = _id, \ + .iobase = soc ## _I2C ## _hwid ## _BASE_ADDR, \ + .iosize = _size, \ + .irq = soc ## _INT_I2C ## _hwid, \ + } + +#define imx_imx_i2c_data_entry(soc, _id, _hwid, _size) \ + [_id] = imx_imx_i2c_data_entry_single(soc, _id, _hwid, _size) + +#ifdef CONFIG_SOC_IMX1 +const struct imx_imx_i2c_data imx1_imx_i2c_data __initconst = + imx_imx_i2c_data_entry_single(MX1, 0, , SZ_4K); +#endif /* ifdef CONFIG_SOC_IMX1 */ + +#ifdef CONFIG_SOC_IMX21 +const struct imx_imx_i2c_data imx21_imx_i2c_data __initconst = + imx_imx_i2c_data_entry_single(MX21, 0, , SZ_4K); +#endif /* ifdef CONFIG_SOC_IMX21 */ + +#ifdef CONFIG_SOC_IMX25 +const struct imx_imx_i2c_data imx25_imx_i2c_data[] __initconst = { +#define imx25_imx_i2c_data_entry(_id, _hwid) \ + imx_imx_i2c_data_entry(MX25, _id, _hwid, SZ_16K) + imx25_imx_i2c_data_entry(0, 1), + imx25_imx_i2c_data_entry(1, 2), + imx25_imx_i2c_data_entry(2, 3), +}; +#endif /* ifdef CONFIG_SOC_IMX25 */ + +#ifdef CONFIG_SOC_IMX27 +const struct imx_imx_i2c_data imx27_imx_i2c_data[] __initconst = { +#define imx27_imx_i2c_data_entry(_id, _hwid) \ + imx_imx_i2c_data_entry(MX27, _id, _hwid, SZ_4K) + imx27_imx_i2c_data_entry(0, 1), + imx27_imx_i2c_data_entry(1, 2), +}; +#endif /* ifdef CONFIG_SOC_IMX27 */ + +#ifdef CONFIG_SOC_IMX31 +const struct imx_imx_i2c_data imx31_imx_i2c_data[] __initconst = { +#define imx31_imx_i2c_data_entry(_id, _hwid) \ + imx_imx_i2c_data_entry(MX31, _id, _hwid, SZ_4K) + imx31_imx_i2c_data_entry(0, 1), + imx31_imx_i2c_data_entry(1, 2), + imx31_imx_i2c_data_entry(2, 3), +}; +#endif /* ifdef CONFIG_SOC_IMX31 */ + +#ifdef CONFIG_SOC_IMX35 +const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst = { +#define imx35_imx_i2c_data_entry(_id, _hwid) \ + imx_imx_i2c_data_entry(MX35, _id, _hwid, SZ_4K) + imx35_imx_i2c_data_entry(0, 1), + imx35_imx_i2c_data_entry(1, 2), + imx35_imx_i2c_data_entry(2, 3), +}; +#endif /* ifdef CONFIG_SOC_IMX35 */ + +#ifdef CONFIG_SOC_IMX50 +const struct imx_imx_i2c_data imx50_imx_i2c_data[] __initconst = { +#define imx50_imx_i2c_data_entry(_id, _hwid) \ + imx_imx_i2c_data_entry(MX50, _id, _hwid, SZ_4K) + imx50_imx_i2c_data_entry(0, 1), + imx50_imx_i2c_data_entry(1, 2), + imx50_imx_i2c_data_entry(2, 3), +}; +#endif /* ifdef CONFIG_SOC_IMX51 */ + +#ifdef CONFIG_SOC_IMX51 +const struct imx_imx_i2c_data imx51_imx_i2c_data[] __initconst = { +#define imx51_imx_i2c_data_entry(_id, _hwid) \ + imx_imx_i2c_data_entry(MX51, _id, _hwid, SZ_4K) + imx51_imx_i2c_data_entry(0, 1), + imx51_imx_i2c_data_entry(1, 2), +}; +#endif /* ifdef CONFIG_SOC_IMX51 */ + +#ifdef CONFIG_SOC_IMX53 +const struct imx_imx_i2c_data imx53_imx_i2c_data[] __initconst = { +#define imx53_imx_i2c_data_entry(_id, _hwid) \ + imx_imx_i2c_data_entry(MX53, _id, _hwid, SZ_4K) + imx53_imx_i2c_data_entry(0, 1), + imx53_imx_i2c_data_entry(1, 2), + imx53_imx_i2c_data_entry(2, 3), +}; +#endif /* ifdef CONFIG_SOC_IMX51 */ + +#ifdef CONFIG_SOC_IMX6Q +const struct imx_imx_i2c_data imx6q_imx_i2c_data[] __initconst = { +#define imx6q_imx_i2c_data_entry(_id, _hwid) \ + imx_imx_i2c_data_entry(MX6Q, _id, _hwid, SZ_4K) + imx6q_imx_i2c_data_entry(0, 1), + imx6q_imx_i2c_data_entry(1, 2), + imx6q_imx_i2c_data_entry(2, 3), +}; +#endif /* ifdef CONFIG_SOC_IMX6Q */ + +struct platform_device *__init imx_add_imx_i2c( + const struct imx_imx_i2c_data *data, + const struct imxi2c_platform_data *pdata) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + data->iosize - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + + return imx_add_platform_device("imx-i2c", data->id, + res, ARRAY_SIZE(res), + pdata, sizeof(*pdata)); +} diff --git a/arch/arm/plat-mxc/devices/platform-imx-iim.c b/arch/arm/plat-mxc/devices/platform-imx-iim.c new file mode 100755 index 00000000..74043ded --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx-iim.c @@ -0,0 +1,59 @@ +/* + * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx5_iim_data_entry_single(soc) \ + { \ + .iobase = soc ## _IIM_BASE_ADDR, \ + .irq = soc ## _INT_IIM, \ + } + +#ifdef CONFIG_SOC_IMX51 +const struct imx_iim_data imx51_imx_iim_data __initconst = + imx5_iim_data_entry_single(MX51); +#endif /* ifdef CONFIG_SOC_IMX51 */ + +#ifdef CONFIG_SOC_IMX53 +const struct imx_iim_data imx53_imx_iim_data __initconst = + imx5_iim_data_entry_single(MX53); +#endif /* ifdef CONFIG_SOC_IMX53 */ + +struct platform_device *__init imx_add_iim( + const struct imx_iim_data *data, + const struct mxc_iim_platform_data *pdata) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + SZ_16 - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + + return imx_add_platform_device("mxc_iim", 0, + res, ARRAY_SIZE(res), pdata, sizeof(*pdata)); +} + diff --git a/arch/arm/plat-mxc/devices/platform-imx-keypad.c b/arch/arm/plat-mxc/devices/platform-imx-keypad.c new file mode 100644 index 00000000..1a120218 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx-keypad.c @@ -0,0 +1,72 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx_imx_keypad_data_entry_single(soc, _size) \ + { \ + .iobase = soc ## _KPP_BASE_ADDR, \ + .iosize = _size, \ + .irq = soc ## _INT_KPP, \ + } + +#ifdef CONFIG_SOC_IMX21 +const struct imx_imx_keypad_data imx21_imx_keypad_data __initconst = + imx_imx_keypad_data_entry_single(MX21, SZ_16); +#endif /* ifdef CONFIG_SOC_IMX21 */ + +#ifdef CONFIG_SOC_IMX25 +const struct imx_imx_keypad_data imx25_imx_keypad_data __initconst = + imx_imx_keypad_data_entry_single(MX25, SZ_16K); +#endif /* ifdef CONFIG_SOC_IMX25 */ + +#ifdef CONFIG_SOC_IMX27 +const struct imx_imx_keypad_data imx27_imx_keypad_data __initconst = + imx_imx_keypad_data_entry_single(MX27, SZ_16); +#endif /* ifdef CONFIG_SOC_IMX27 */ + +#ifdef CONFIG_SOC_IMX31 +const struct imx_imx_keypad_data imx31_imx_keypad_data __initconst = + imx_imx_keypad_data_entry_single(MX31, SZ_16); +#endif /* ifdef CONFIG_SOC_IMX31 */ + +#ifdef CONFIG_SOC_IMX35 +const struct imx_imx_keypad_data imx35_imx_keypad_data __initconst = + imx_imx_keypad_data_entry_single(MX35, SZ_16); +#endif /* ifdef CONFIG_SOC_IMX35 */ + +#ifdef CONFIG_SOC_IMX51 +const struct imx_imx_keypad_data imx51_imx_keypad_data __initconst = + imx_imx_keypad_data_entry_single(MX51, SZ_16); +#endif /* ifdef CONFIG_SOC_IMX51 */ + +#ifdef CONFIG_SOC_IMX6SL +const struct imx_imx_keypad_data imx6sl_imx_keypad_data __initconst = + imx_imx_keypad_data_entry_single(MX6SL, SZ_16); +#endif /* ifdef CONFIG_SOC_IMX6SL */ + +struct platform_device *__init imx_add_imx_keypad( + const struct imx_imx_keypad_data *data, + const struct matrix_keymap_data *pdata) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + data->iosize - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + + return imx_add_platform_device("imx-keypad", -1, + res, ARRAY_SIZE(res), pdata, sizeof(*pdata)); +} diff --git a/arch/arm/plat-mxc/devices/platform-imx-mipi_csi2.c b/arch/arm/plat-mxc/devices/platform-imx-mipi_csi2.c new file mode 100644 index 00000000..ed8a2fbd --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx-mipi_csi2.c @@ -0,0 +1,49 @@ +/* + * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx_mipi_csi2_data_entry_single(soc, _id, size) \ +{ \ + .id = _id, \ + .iobase = soc ## _MIPI_CSI2_BASE_ADDR, \ + .iosize = size, \ +} + +#ifdef CONFIG_SOC_IMX6Q +const struct imx_mipi_csi2_data imx6q_mipi_csi2_data __initconst = + imx_mipi_csi2_data_entry_single(MX6Q, 0, SZ_4K); +#endif + +struct platform_device *__init imx_add_mipi_csi2( + const struct imx_mipi_csi2_data *data, + const struct mipi_csi2_platform_data *pdata) { + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + data->iosize - 1, + .flags = IORESOURCE_MEM, + }, + }; + + return imx_add_platform_device("mxc_mipi_csi2", -1, + res, ARRAY_SIZE(res), pdata, sizeof(*pdata)); +} diff --git a/arch/arm/plat-mxc/devices/platform-imx-mipi_dsi.c b/arch/arm/plat-mxc/devices/platform-imx-mipi_dsi.c new file mode 100644 index 00000000..136a8fcc --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx-mipi_dsi.c @@ -0,0 +1,63 @@ +/* + * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx_mipi_dsi_data_entry_single(soc, _id, _hwid, size) \ + { \ + .id = _id, \ + .iobase = soc ## _MIPI_DSI ## _hwid ## _BASE_ADDR, \ + .iosize = size, \ + .irq = soc ## _INT_DSI ## _hwid, \ + } + +#define imx_mipi_dsi_data_entry(soc, _id, _hwid, _size) \ + [_id] = imx_mipi_dsi_data_entry_single(soc, _id, _hwid, _size) + +#ifdef CONFIG_SOC_IMX6Q +#define SOC_IOMUXC_BASE_ADDR MX6Q_IOMUXC_BASE_ADDR +const struct imx_mipi_dsi_data imx6q_mipi_dsi_data __initconst = + imx_mipi_dsi_data_entry_single(MX6Q, 0, , SZ_4K); +#endif + +struct platform_device *__init imx_add_mipi_dsi( + const struct imx_mipi_dsi_data *data, + const struct mipi_dsi_platform_data *pdata) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + data->iosize - 1, + .flags = IORESOURCE_MEM, + }, { + .start = SOC_IOMUXC_BASE_ADDR, + .end = SOC_IOMUXC_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + + return imx_add_platform_device("mxc_mipi_dsi", -1, + res, ARRAY_SIZE(res), pdata, sizeof(*pdata)); +} diff --git a/arch/arm/plat-mxc/devices/platform-imx-ocotp.c b/arch/arm/plat-mxc/devices/platform-imx-ocotp.c new file mode 100755 index 00000000..055fe337 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx-ocotp.c @@ -0,0 +1,103 @@ +/* + * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <mach/hardware.h> +#include <mach/devices-common.h> +#include <linux/fsl_devices.h> + +#ifdef CONFIG_SOC_IMX50 +#define BANK(a, b, c, d, e, f, g, h) \ + {\ + ("HW_OCOTP_"#a), ("HW_OCOTP_"#b), ("HW_OCOTP_"#c), ("HW_OCOTP_"#d), \ + ("HW_OCOTP_"#e), ("HW_OCOTP_"#f), ("HW_OCOTP_"#g), ("HW_OCOTP_"#h) \ + } + +#define BANKS (5) +#define BANK_ITEMS (8) +static const char *bank_reg_desc[BANKS][BANK_ITEMS] = { + BANK(LOCK, CFG0, CFG1, CFG2, CFG3, CFG4, CFG5, CFG6), + BANK(MEM0, MEM1, MEM2, MEM3, MEM4, MEM5, GP0, GP1), + BANK(SCC0, SCC1, SCC2, SCC3, SCC4, SCC5, SCC6, SCC7), + BANK(SRK0, SRK1, SRK2, SRK3, SRK4, SRK5, SRK6, SRK7), + BANK(SJC0, SJC1, MAC0, MAC1, HWCAP0, HWCAP1, HWCAP2, SWCAP), +}; + +static const struct mxc_otp_platform_data imx50_otp_platform_data = { + .fuse_name = (char **)bank_reg_desc, + .clock_name = "ocotp_ctrl_ahb_clk", + .fuse_num = BANKS * BANK_ITEMS, +}; + +const struct imx_otp_data imx50_otp_data = { + .iobase = MX50_OCOTP_CTRL_BASE_ADDR, + .pdata = &imx50_otp_platform_data, +}; +#undef BANK +#undef BANKS +#undef BANK_ITEMS +#endif /* ifdef CONFIG_SOC_IMX50 */ + +#ifdef CONFIG_SOC_IMX6Q +#define BANK(a, b, c, d, e, f, g, h) \ + {\ + ("HW_OCOTP_"#a), ("HW_OCOTP_"#b), ("HW_OCOTP_"#c), ("HW_OCOTP_"#d), \ + ("HW_OCOTP_"#e), ("HW_OCOTP_"#f), ("HW_OCOTP_"#g), ("HW_OCOTP_"#h) \ + } + +#define BANKS (16) +#define BANK_ITEMS (8) +static const char *bank_reg_desc[BANKS][BANK_ITEMS] = { + BANK(LOCK, CFG0, CFG1, CFG2, CFG3, CFG4, CFG5, CFG6), + BANK(MEM0, MEM1, MEM2, MEM3, MEM4, ANA0, ANA1, ANA2), + BANK(OTPMK0, OTPMK1, OTPMK2, OTPMK3, OTPMK4, OTPMK5, OTPMK6, OTPMK7), + BANK(SRK0, SRK1, SRK2, SRK3, SRK4, SRK5, SRK6, SRK7), + BANK(RESP0, HSJC_RESP1, MAC0, MAC1, HDCP_KSV0, HDCP_KSV1, GP1, GP2), + BANK(DTCP_KEY0, DTCP_KEY1, DTCP_KEY2, DTCP_KEY3, DTCP_KEY4, MISC_CONF, FIELD_RETURN, SRK_REVOKE), + BANK(HDCP_KEY0, HDCP_KEY1, HDCP_KEY2, HDCP_KEY3, HDCP_KEY4, HDCP_KEY5, HDCP_KEY6, HDCP_KEY7), + BANK(HDCP_KEY8, HDCP_KEY9, HDCP_KEY10, HDCP_KEY11, HDCP_KEY12, HDCP_KEY13, HDCP_KEY14, HDCP_KEY15), + BANK(HDCP_KEY16, HDCP_KEY17, HDCP_KEY18, HDCP_KEY19, HDCP_KEY20, HDCP_KEY21, HDCP_KEY22, HDCP_KEY23), + BANK(HDCP_KEY24, HDCP_KEY25, HDCP_KEY26, HDCP_KEY27, HDCP_KEY28, HDCP_KEY29, HDCP_KEY30, HDCP_KEY31), + BANK(HDCP_KEY32, HDCP_KEY33, HDCP_KEY34, HDCP_KEY35, HDCP_KEY36, HDCP_KEY37, HDCP_KEY38, HDCP_KEY39), + BANK(HDCP_KEY40, HDCP_KEY41, HDCP_KEY42, HDCP_KEY43, HDCP_KEY44, HDCP_KEY45, HDCP_KEY46, HDCP_KEY47), + BANK(HDCP_KEY48, HDCP_KEY49, HDCP_KEY50, HDCP_KEY51, HDCP_KEY52, HDCP_KEY53, HDCP_KEY54, HDCP_KEY55), + BANK(HDCP_KEY56, HDCP_KEY57, HDCP_KEY58, HDCP_KEY59, HDCP_KEY60, HDCP_KEY61, HDCP_KEY62, HDCP_KEY63), + BANK(HDCP_KEY64, HDCP_KEY65, HDCP_KEY66, HDCP_KEY67, HDCP_KEY68, HDCP_KEY69, HDCP_KEY70, HDCP_KEY71), + BANK(CRC0, CRC1, CRC2, CRC3, CRC4, CRC5, CRC6, CRC7), +}; + +static const struct mxc_otp_platform_data imx6q_otp_platform_data = { + .fuse_name = (char **)bank_reg_desc, + .clock_name = "iim_clk", + .fuse_num = BANKS * BANK_ITEMS, +}; + +const struct imx_otp_data imx6q_otp_data = { + .iobase = OCOTP_BASE_ADDR, + .pdata = (struct mxc_otp_platform_data *)&imx6q_otp_platform_data, +}; +#undef BANK +#undef BANKS +#undef BANK_ITEMS +#endif /* ifdef CONFIG_SOC_IMX6Q */ + + +struct platform_device *__init imx_add_otp( + const struct imx_otp_data *data) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + SZ_16 - 1, + .flags = IORESOURCE_MEM, + } + }; + + return imx_add_platform_device("imx-ocotp", 0, + res, ARRAY_SIZE(res), data->pdata, + sizeof(struct mxc_otp_platform_data)); +} + diff --git a/arch/arm/plat-mxc/devices/platform-imx-pcie.c b/arch/arm/plat-mxc/devices/platform-imx-pcie.c new file mode 100644 index 00000000..7e0d630f --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx-pcie.c @@ -0,0 +1,64 @@ +/* + * Copyright (C) 2012-2013 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx_pcie_data_entry_single(soc, _id, _hwid, size) \ + { \ + .id = _id, \ + .iobase = soc ## _PCIE ## _hwid ## _BASE_ADDR, \ + .iosize = size, \ + .irq = soc ## _INT_PCIE ## _hwid, \ + } + +#define imx_pcie_data_entry(soc, _id, _hwid, _size) \ + [_id] = imx_pcie_data_entry_single(soc, _id, _hwid, _size) + +#ifdef CONFIG_SOC_IMX6Q +#define MX6Q_PCIE_BASE_ADDR (PCIE_ARB_END_ADDR - SZ_16K + 1) +#define MX6Q_INT_PCIE MXC_INT_PCIE_3 +const struct imx_pcie_data imx6q_pcie_data __initconst = + imx_pcie_data_entry_single(MX6Q, 0, , SZ_16K); +#endif + +struct platform_device *__init imx_add_pcie( + const struct imx_pcie_data *data, + const struct imx_pcie_platform_data *pdata) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + data->iosize - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + + if (!fuse_dev_is_available(MXC_DEV_PCIE)) + return ERR_PTR(-ENODEV); + + return imx_add_platform_device("imx-pcie", -1, + res, ARRAY_SIZE(res), + pdata, sizeof(*pdata)); +} diff --git a/arch/arm/plat-mxc/devices/platform-imx-perfmon.c b/arch/arm/plat-mxc/devices/platform-imx-perfmon.c new file mode 100644 index 00000000..56e262b3 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx-perfmon.c @@ -0,0 +1,158 @@ +/* + * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <mach/hardware.h> +#include <mach/devices-common.h> +#include <linux/fsl_devices.h> +#include <mach/iomux-v3.h> + +#ifdef CONFIG_SOC_IMX50 +static struct mxs_perfmon_bit_config +mx50_perfmon_bit_config[] = { + {.field = (1 << 0), .name = "MID0-CORE" }, + {.field = (1 << 1), .name = "MID1-DCP" }, + {.field = (1 << 2), .name = "MID2-PXP" }, + {.field = (1 << 3), .name = "MID3-USB" }, + {.field = (1 << 4), .name = "MID4-GPU2D" }, + {.field = (1 << 5), .name = "MID5-BCH" }, + {.field = (1 << 6), .name = "MID6-AHB" }, + {.field = (1 << 7), .name = "MID7-EPDC" }, + {.field = (1 << 8), .name = "MID8-LCDIF" }, + {.field = (1 << 9), .name = "MID9-SDMA" }, + {.field = (1 << 10), .name = "MID10-FEC" }, + {.field = (1 << 11), .name = "MID11-MSHC" } +}; + +struct mxs_platform_perfmon_data mxc_perfmon_data = { + .bit_config_tab = mx50_perfmon_bit_config, + .bit_config_cnt = ARRAY_SIZE(mx50_perfmon_bit_config), +}; + + +const struct imx_perfmon_data imx50_perfmon_data = { + .iobase = MX50_PERFMON_BASE_ADDR, + .pdata = &mxc_perfmon_data, +}; +#endif + +#ifdef CONFIG_SOC_IMX6Q +static struct mxs_perfmon_bit_config +mx6q_perfmon1_bit_config[] = { + {.field = (1 << 0), .name = "MID0-GPU_3D" }, + {.field = (1 << 1), .name = "MID1-GPU_2D" }, + {.field = (1 << 2), .name = "MID2-VDOA" }, + {.field = (1 << 3), .name = "MID3-Unused" }, + {.field = (1 << 4), .name = "MID4-OPENVG" } +}; + +static struct mxs_perfmon_bit_config +mx6q_perfmon2_bit_config[] = { + {.field = (1 << 0), .name = "MID0-IPU1.ld00" }, + {.field = (1 << 1), .name = "MID1-IPU1.ld01" }, + {.field = (1 << 2), .name = "MID2-IPU1.ld10" }, + {.field = (1 << 3), .name = "MID3-IPU1.ld11" } +}; + +static struct mxs_perfmon_bit_config +mx6q_perfmon3_bit_config[] = { + {.field = (1 << 0), .name = "MID0-CORES" }, + {.field = (1 << 1), .name = "MID1-L2-BUF" }, + {.field = (1 << 2), .name = "MID2-Unused" }, + {.field = (1 << 3), .name = "MID3-L2-EVIC" }, + {.field = (1 << 4), .name = "MID4-Unused" } +}; + +static int init; + +static void platform_perfmon_init(void) +{ + if (init) + return; + + if (mx6q_revision() == IMX_CHIP_REVISION_1_0 || cpu_is_mx6dl()) + /* GPR11 bit[16] must be set for TO1.0(6q & 6dl), it's a bug */ + mxc_iomux_set_gpr_register(11, 16, 1, 1); + + mxc_iomux_set_gpr_register(11, 0, 1, 1); + init = true; +} + +static void platform_perfmon_exit(void) +{ + if (!init) + return; + + mxc_iomux_set_gpr_register(11, 0, 1, 0); + init = false; +} + +struct mxs_platform_perfmon_data mxc_perfmon_data1 = { + .bit_config_tab = mx6q_perfmon1_bit_config, + .bit_config_cnt = ARRAY_SIZE(mx6q_perfmon1_bit_config), + .plt_init = platform_perfmon_init, + .plt_exit = platform_perfmon_exit, +}; + +struct mxs_platform_perfmon_data mxc_perfmon_data2 = { + .bit_config_tab = mx6q_perfmon2_bit_config, + .bit_config_cnt = ARRAY_SIZE(mx6q_perfmon2_bit_config), + .plt_init = platform_perfmon_init, +}; + +struct mxs_platform_perfmon_data mxc_perfmon_data3 = { + .bit_config_tab = mx6q_perfmon3_bit_config, + .bit_config_cnt = ARRAY_SIZE(mx6q_perfmon3_bit_config), + .plt_init = platform_perfmon_init, +}; + +const struct imx_perfmon_data imx6q_perfmon_data[3] = { + { + .iobase = IP2APB_PERFMON1_BASE_ADDR, + .pdata = &mxc_perfmon_data1, + }, + { + .iobase = IP2APB_PERFMON2_BASE_ADDR, + .pdata = &mxc_perfmon_data2, + }, + { + .iobase = IP2APB_PERFMON3_BASE_ADDR, + .pdata = &mxc_perfmon_data3, + } +}; +#endif + +struct platform_device *__init imx_add_perfmon( + const struct imx_perfmon_data *data) +{ + static int id; + + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + SZ_4K - 1, + .flags = IORESOURCE_MEM, + } + }; + + return imx_add_platform_device("mxs-perfmon", id++, + res, ARRAY_SIZE(res), data->pdata, + sizeof(struct mxs_platform_perfmon_data)); +} + diff --git a/arch/arm/plat-mxc/devices/platform-imx-pm.c b/arch/arm/plat-mxc/devices/platform-imx-pm.c new file mode 100644 index 00000000..5b865ad4 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx-pm.c @@ -0,0 +1,52 @@ +/* + * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ +#include <asm/sizes.h> +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx_pm_imx_data_entry_single(soc) \ + { \ + } + +#ifdef CONFIG_SOC_IMX6Q +const struct imx_pm_imx_data imx6q_pm_imx_data[] __initconst = + imx_pm_imx_data_entry_single(MX6Q); +#endif + +#ifdef CONFIG_SOC_IMX6SL +const struct imx_pm_imx_data imx6sl_pm_imx_data[] __initconst = + imx_pm_imx_data_entry_single(MX6SL); +#endif + +struct platform_device *__init imx_add_pm_imx( + const struct imx_pm_imx_data *data, + const struct pm_platform_data *pdata) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + }; + + return imx_add_platform_device("imx_pm", 0, + res, ARRAY_SIZE(res), pdata, sizeof(*pdata)); +} diff --git a/arch/arm/plat-mxc/devices/platform-imx-pmu.c b/arch/arm/plat-mxc/devices/platform-imx-pmu.c new file mode 100644 index 00000000..cf29415d --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx-pmu.c @@ -0,0 +1,44 @@ +/* + * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <asm/sizes.h> +#include <mach/hardware.h> +#include <mach/devices-common.h> +#include <asm/pmu.h> + +static struct resource mx6_pmu_resources[] = { + [0] = { + .start = MXC_INT_CHEETAH_PERFORM, + .end = MXC_INT_CHEETAH_PERFORM, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device mx6_pmu_device = { + .name = "arm-pmu", + .id = ARM_PMU_DEVICE_CPU, + .num_resources = ARRAY_SIZE(mx6_pmu_resources), + .resource = mx6_pmu_resources, +}; + +void __init imx_add_imx_armpmu() +{ + platform_device_register(&mx6_pmu_device); +} diff --git a/arch/arm/plat-mxc/devices/platform-imx-pxp.c b/arch/arm/plat-mxc/devices/platform-imx-pxp.c new file mode 100644 index 00000000..fed58d09 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx-pxp.c @@ -0,0 +1,80 @@ +/* + * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <asm/sizes.h> +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx_pxp_data_entry_single(soc, size) \ + { \ + .iobase = soc ## _EPXP_BASE_ADDR, \ + .irq = soc ## _INT_EPXP, \ + .iosize = size, \ + } + +#ifdef CONFIG_SOC_IMX50 +const struct imx_pxp_data imx50_pxp_data __initconst = + imx_pxp_data_entry_single(MX50, SZ_4K); +#endif + +#ifdef CONFIG_SOC_IMX6Q +const struct imx_pxp_data imx6dl_pxp_data __initconst = + imx_pxp_data_entry_single(MX6DL, SZ_16K); +#endif + +struct platform_device *__init imx_add_imx_pxp( + const struct imx_pxp_data *data) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + data->iosize - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + + if (!fuse_dev_is_available(MXC_DEV_PXP)) + return ERR_PTR(-ENODEV); + + return imx_add_platform_device_dmamask("imx-pxp", -1, + res, ARRAY_SIZE(res), NULL, 0, DMA_BIT_MASK(32)); +} + +struct platform_device *__init imx_add_imx_pxp_client() +{ + if (!fuse_dev_is_available(MXC_DEV_PXP)) + return ERR_PTR(-ENODEV); + + return imx_add_platform_device("imx-pxp-client", -1, + NULL, 0, NULL, 0); +} + +struct platform_device *__init imx_add_imx_pxp_v4l2() +{ + if (!fuse_dev_is_available(MXC_DEV_PXP)) + return ERR_PTR(-ENODEV); + + return imx_add_platform_device_dmamask("pxp-v4l2", -1, + NULL, 0, NULL, 0, DMA_BIT_MASK(32)); +} diff --git a/arch/arm/plat-mxc/devices/platform-imx-rngb.c b/arch/arm/plat-mxc/devices/platform-imx-rngb.c new file mode 100755 index 00000000..9a0a652d --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx-rngb.c @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <asm/sizes.h> +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx_rngb_data_entry_single(soc) \ +{ \ + .iobase = soc ## _RNGB_BASE_ADDR, \ + .irq = soc ## _INT_RNGB, \ +} + +#ifdef CONFIG_SOC_IMX50 +const struct imx_rngb_data imx50_rngb_data __initconst = + imx_rngb_data_entry_single(MX50); +#endif /* ifdef CONFIG_SOC_IMX50 */ + +#ifdef CONFIG_SOC_IMX6SL +const struct imx_rngb_data imx6sl_rngb_data __initconst = + imx_rngb_data_entry_single(MX6SL); +#endif /* ifdef CONFIG_SOC_IMX6SL */ + +struct platform_device *__init imx_add_rngb( + const struct imx_rngb_data *data) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + + return imx_add_platform_device("fsl_rngc", 0, + res, ARRAY_SIZE(res), NULL, 0); +} diff --git a/arch/arm/plat-mxc/devices/platform-imx-scc2.c b/arch/arm/plat-mxc/devices/platform-imx-scc2.c new file mode 100644 index 00000000..10e03b66 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx-scc2.c @@ -0,0 +1,284 @@ +/* + * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <asm/sizes.h> +#include <mach/hardware.h> +#include <mach/devices-common.h> +#include <linux/mxc_scc2_driver.h> +#include <linux/delay.h> + +#define imx_scc2_data_entry_single(soc) \ +{ \ + .iobase = soc ## _SCC_BASE_ADDR, \ + .ram_start = soc ## _SCC_RAM_BASE_ADDR, \ + .irq_smn = soc ## _INT_SCC_SMN, \ + .irq_scm = soc ## _INT_SCC_SCM, \ +} + +#ifdef CONFIG_SOC_IMX51 +const struct imx_mxc_scc2_data imx51_mxc_scc2_data __initconst = + imx_scc2_data_entry_single(MX51); +#endif /* ifdef CONFIG_SOC_IMX51 */ + +#ifdef CONFIG_SOC_IMX53 +const struct imx_mxc_scc2_data imx53_mxc_scc2_data __initconst = + imx_scc2_data_entry_single(MX53); +#endif /* ifdef CONFIG_SOC_IMX53 */ + +#define SCM_RD_DELAY 1000000 /* in nanoseconds */ +#define SEC_TO_NANOSEC 1000000000 /*Second to nanoseconds */ +static __init void mxc_init_scc_iram(struct resource res[]) +{ + uint32_t reg_value; + uint32_t reg_mask = 0; + uint8_t *UMID_base; + uint32_t *MAP_base; + uint8_t i; + uint32_t partition_no; + uint32_t scc_partno; + void *scm_ram_base; + void *scc_base; + uint32_t ram_partitions, ram_partition_size, ram_size; + uint32_t scm_version_register; + struct timespec stime; + struct timespec curtime; + long scm_rd_timeout = 0; + long cur_ns = 0; + long start_ns = 0; + + scc_base = ioremap((uint32_t) res[0].start, 0x140); + if (scc_base == NULL) { + printk(KERN_ERR "FAILED TO MAP SCC REGS\n"); + return; + } + + scm_version_register = __raw_readl(scc_base + SCM_VERSION_REG); + ram_partitions = 1 + ((scm_version_register & SCM_VER_NP_MASK) + >> SCM_VER_NP_SHIFT); + ram_partition_size = (uint32_t) (1 << + ((scm_version_register & SCM_VER_BPP_MASK) + >> SCM_VER_BPP_SHIFT)); + + ram_size = (uint32_t)(ram_partitions * ram_partition_size); + + scm_ram_base = ioremap((uint32_t) res[1].start, ram_size); + + if (scm_ram_base == NULL) { + printk(KERN_ERR "FAILED TO MAP SCC RAM\n"); + return; + } + + /* Wait for any running SCC operations to finish or fail */ + getnstimeofday(&stime); + do { + reg_value = __raw_readl(scc_base + SCM_STATUS_REG); + getnstimeofday(&curtime); + if (curtime.tv_nsec > stime.tv_nsec) + scm_rd_timeout = curtime.tv_nsec - stime.tv_nsec; + else{ + /*Converted second to nanosecond and add to + nsec when current nanosec is less than + start time nanosec.*/ + cur_ns = (curtime.tv_sec * SEC_TO_NANOSEC) + + curtime.tv_nsec; + start_ns = (stime.tv_sec * SEC_TO_NANOSEC) + + stime.tv_nsec; + scm_rd_timeout = cur_ns - start_ns; + } + } while (((reg_value & SCM_STATUS_SRS_MASK) != SCM_STATUS_SRS_READY) + && ((reg_value & SCM_STATUS_SRS_MASK) != SCM_STATUS_SRS_FAIL)); + + /* Check for failures */ + if ((reg_value & SCM_STATUS_SRS_MASK) != SCM_STATUS_SRS_READY) { + /* Special message for bad secret key fuses */ + if (reg_value & SCM_STATUS_KST_BAD_KEY) + printk(KERN_ERR "INVALID SCC KEY FUSE PATTERN\n"); + else + printk(KERN_ERR "SECURE RAM FAILURE\n"); + + iounmap(scm_ram_base); + iounmap(scc_base); + return; + } + + scm_rd_timeout = 0; + +#ifdef CONFIG_ARCH_MX5 + /* Release all partitions for SCC2 driver on MX53*/ + if (cpu_is_mx53()) + scc_partno = 0; + /* Release final two partitions for SCC2 driver on MX51 */ + else + scc_partno = ram_partitions - + (MX51_SCC_RAM_SIZE / ram_partition_size); +#else + scc_partno = 0; +#endif + + + for (partition_no = scc_partno; partition_no < ram_partitions; + partition_no++) { + reg_value = (((partition_no << SCM_ZCMD_PART_SHIFT) & + SCM_ZCMD_PART_MASK) | ((0x03 << SCM_ZCMD_CCMD_SHIFT) & + SCM_ZCMD_CCMD_MASK)); + __raw_writel(reg_value, scc_base + SCM_ZCMD_REG); + udelay(1); + /* Wait for zeroization to complete */ + getnstimeofday(&stime); + do { + reg_value = __raw_readl(scc_base + SCM_STATUS_REG); + getnstimeofday(&curtime); + if (curtime.tv_nsec > stime.tv_nsec) + scm_rd_timeout = curtime.tv_nsec - + stime.tv_nsec; + else { + /*Converted second to nanosecond and add to + nsec when current nanosec is less than + start time nanosec.*/ + cur_ns = (curtime.tv_sec * SEC_TO_NANOSEC) + + curtime.tv_nsec; + start_ns = (stime.tv_sec * SEC_TO_NANOSEC) + + stime.tv_nsec; + scm_rd_timeout = cur_ns - start_ns; + } + } while (((reg_value & SCM_STATUS_SRS_MASK) != + SCM_STATUS_SRS_READY) && ((reg_value & SCM_STATUS_SRS_MASK) != + SCM_STATUS_SRS_FAIL) && (scm_rd_timeout <= SCM_RD_DELAY)); + + if (scm_rd_timeout > SCM_RD_DELAY) + printk(KERN_ERR "SCM Status Register Read timeout" + "for Partition No:%d", partition_no); + + if ((reg_value & SCM_STATUS_SRS_MASK) != SCM_STATUS_SRS_READY) + break; + } + + /* 4 partitions on MX53 */ + if (cpu_is_mx53()) + reg_mask = 0xFF; + + /*Check all expected partitions released */ + reg_value = __raw_readl(scc_base + SCM_PART_OWNERS_REG); + if ((reg_value & reg_mask) != 0) { + printk(KERN_ERR "FAILED TO RELEASE IRAM PARTITION\n"); + iounmap(scm_ram_base); + iounmap(scc_base); + return; + } + + /* we are done if this is MX53, since no sharing of IRAM and SCC_RAM */ + if (cpu_is_mx53()) + goto exit; + + reg_mask = 0; + scm_rd_timeout = 0; + /* Allocate remaining partitions for general use */ + for (partition_no = 0; partition_no < scc_partno; partition_no++) { + /* Supervisor mode claims a partition for it's own use + by writing zero to SMID register.*/ + __raw_writel(0, scc_base + (SCM_SMID0_REG + 8 * partition_no)); + + /* Wait for any zeroization to complete */ + getnstimeofday(&stime); + do { + reg_value = __raw_readl(scc_base + SCM_STATUS_REG); + getnstimeofday(&curtime); + if (curtime.tv_nsec > stime.tv_nsec) + scm_rd_timeout = curtime.tv_nsec - + stime.tv_nsec; + else{ + /*Converted second to nanosecond and add to + nsec when current nanosec is less than + start time nanosec.*/ + cur_ns = (curtime.tv_sec * SEC_TO_NANOSEC) + + curtime.tv_nsec; + start_ns = (stime.tv_sec * SEC_TO_NANOSEC) + + stime.tv_nsec; + scm_rd_timeout = cur_ns - start_ns; + } + } while (((reg_value & SCM_STATUS_SRS_MASK) != + SCM_STATUS_SRS_READY) && ((reg_value & SCM_STATUS_SRS_MASK) != + SCM_STATUS_SRS_FAIL) && (scm_rd_timeout <= SCM_RD_DELAY)); + + if (scm_rd_timeout > SCM_RD_DELAY) + printk(KERN_ERR "SCM Status Register Read timeout" + "for Partition No:%d", partition_no); + + if ((reg_value & SCM_STATUS_SRS_MASK) != SCM_STATUS_SRS_READY) + break; + /* Set UMID=0 and permissions for universal data + read/write access */ + MAP_base = scm_ram_base + + (uint32_t) (partition_no * ram_partition_size); + UMID_base = (uint8_t *) MAP_base + 0x10; + for (i = 0; i < 16; i++) + UMID_base[i] = 0; + + MAP_base[0] = (SCM_PERM_NO_ZEROIZE | SCM_PERM_HD_SUP_DISABLE | + SCM_PERM_HD_READ | SCM_PERM_HD_WRITE | + SCM_PERM_HD_EXECUTE | SCM_PERM_TH_READ | + SCM_PERM_TH_WRITE); + reg_mask |= (3 << (2 * (partition_no))); + } + + /* Check all expected partitions allocated */ + reg_value = __raw_readl(scc_base + SCM_PART_OWNERS_REG); + if ((reg_value & reg_mask) != reg_mask) { + printk(KERN_ERR "FAILED TO ACQUIRE IRAM PARTITION\n"); + iounmap(scm_ram_base); + iounmap(scc_base); + return; + } + +exit: + iounmap(scm_ram_base); + iounmap(scc_base); + printk(KERN_INFO "IRAM READY\n"); +} + + +struct platform_device *__init imx_add_mxc_scc2( + const struct imx_mxc_scc2_data *data) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->ram_start, + .end = data->ram_start + SZ_128K - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq_smn, + .end = data->irq_smn, + .flags = IORESOURCE_IRQ, + }, { + .start = data->irq_scm, + .end = data->irq_scm, + .flags = IORESOURCE_IRQ, + }, + }; + + mxc_init_scc_iram(res); + + return imx_add_platform_device("mxc_scc", 0, + res, ARRAY_SIZE(res), NULL, 0); +} diff --git a/arch/arm/plat-mxc/devices/platform-imx-spdc-fb.c b/arch/arm/plat-mxc/devices/platform-imx-spdc-fb.c new file mode 100644 index 00000000..72010e29 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx-spdc-fb.c @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <asm/sizes.h> +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx_spdc_data_entry_single(soc, size) \ + { \ + .iobase = soc ## _SIPIX_BASE_ADDR, \ + .irq = soc ## _INT_SPDC, \ + .iosize = size, \ + } + +#ifdef CONFIG_SOC_IMX6SL +const struct imx_epdc_data imx6sl_spdc_data __initconst = + imx_spdc_data_entry_single(MX6SL, SZ_16K); +#endif + +struct platform_device *__init imx_add_imx_spdc( + const struct imx_epdc_data *data, + const struct imx_spdc_fb_platform_data *pdata) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + data->iosize - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + + return imx_add_platform_device_dmamask("imx_spdc_fb", -1, + res, ARRAY_SIZE(res), pdata, sizeof(*pdata), DMA_BIT_MASK(32)); +} + diff --git a/arch/arm/plat-mxc/devices/platform-imx-spdif-audio.c b/arch/arm/plat-mxc/devices/platform-imx-spdif-audio.c new file mode 100644 index 00000000..4a0cb7bf --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx-spdif-audio.c @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <mach/hardware.h> +#include <mach/devices-common.h> + +struct platform_device *__init imx_add_spdif_audio_device(void) +{ + return imx_add_platform_device("imx-spdif-audio-device", 0, + NULL, 0, NULL, 0); +} + diff --git a/arch/arm/plat-mxc/devices/platform-imx-spdif-dai.c b/arch/arm/plat-mxc/devices/platform-imx-spdif-dai.c new file mode 100644 index 00000000..7e0a97b1 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx-spdif-dai.c @@ -0,0 +1,70 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * Copyright (C) 2011 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define MXC_SPDIF_TX_REG 0x2C +#define MXC_SPDIF_RX_REG 0x14 + +#define imx_spdif_dai_data_entry(soc) \ + { \ + .iobase = soc ## _SPDIF_BASE_ADDR, \ + .dmatx = soc ## _DMA_REQ_SPDIF_TX, \ + .dmarx = soc ## _DMA_REQ_SPDIF_RX, \ + } + +#ifdef CONFIG_SOC_IMX51 +const struct imx_spdif_dai_data imx51_spdif_dai_data __initconst = { + .iobase = MX51_SPDIF_BASE_ADDR, + .dmatx = MX51_DMA_REQ_SPDIF, + }; +#endif /* ifdef CONFIG_SOC_IMX51 */ + +#ifdef CONFIG_SOC_IMX53 +const struct imx_spdif_dai_data imx53_spdif_dai_data __initconst = + imx_spdif_dai_data_entry(MX53); +#endif /* ifdef CONFIG_SOC_IMX53 */ + +#ifdef CONFIG_SOC_IMX6Q +const struct imx_spdif_dai_data imx6q_spdif_dai_data __initconst = + imx_spdif_dai_data_entry(MX6Q); +#endif /* #ifdef CONFIG_SOC_IMX6Q */ + +struct platform_device *__init imx_add_spdif_dai( + const struct imx_spdif_dai_data *data) +{ + struct resource res[] = { + { + .name = "tx_reg", + .start = data->iobase + MXC_SPDIF_TX_REG, + .end = data->iobase + MXC_SPDIF_TX_REG, + .flags = IORESOURCE_DMA, + }, { + .name = "rx_reg", + .start = data->iobase + MXC_SPDIF_RX_REG, + .end = data->iobase + MXC_SPDIF_RX_REG, + .flags = IORESOURCE_DMA, + }, { + .name = "tx", + .start = data->dmatx, + .end = data->dmatx, + .flags = IORESOURCE_DMA, + }, { + .name = "rx", + .start = data->dmarx, + .end = data->dmarx, + .flags = IORESOURCE_DMA, + }, + }; + + return imx_add_platform_device("imx-spdif-dai", 0, + res, ARRAY_SIZE(res), NULL, 0); +} diff --git a/arch/arm/plat-mxc/devices/platform-imx-spdif.c b/arch/arm/plat-mxc/devices/platform-imx-spdif.c new file mode 100644 index 00000000..90a58899 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx-spdif.c @@ -0,0 +1,69 @@ +/* + * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx5_spdif_data_entry_single(soc) \ + { \ + .iobase = soc ## _SPDIF_BASE_ADDR, \ + .irq = soc ## _INT_SPDIF, \ + } + +#ifdef CONFIG_SOC_IMX50 +const struct imx_spdif_data imx50_imx_spdif_data __initconst = + imx5_spdif_data_entry_single(MX53); +#endif /* ifdef CONFIG_SOC_IMX50 */ + +#ifdef CONFIG_SOC_IMX51 +const struct imx_spdif_data imx51_imx_spdif_data __initconst = + imx5_spdif_data_entry_single(MX51); +#endif /* ifdef CONFIG_SOC_IMX51 */ + +#ifdef CONFIG_SOC_IMX53 +const struct imx_spdif_data imx53_imx_spdif_data __initconst = + imx5_spdif_data_entry_single(MX53); +#endif /* ifdef CONFIG_SOC_IMX53 */ + +#ifdef CONFIG_SOC_IMX6Q +const struct imx_spdif_data imx6q_imx_spdif_data __initconst = + imx5_spdif_data_entry_single(MX6Q); +#endif /* ifdef CONFIG_SOC_IMX6Q */ + +struct platform_device *__init imx_add_spdif( + const struct imx_spdif_data *data, + const struct mxc_spdif_platform_data *pdata) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + 0x50, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + + return imx_add_platform_device("mxc_spdif", 0, + res, ARRAY_SIZE(res), pdata, sizeof(*pdata)); +} + diff --git a/arch/arm/plat-mxc/devices/platform-imx-ssi.c b/arch/arm/plat-mxc/devices/platform-imx-ssi.c new file mode 100755 index 00000000..6e62967c --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx-ssi.c @@ -0,0 +1,128 @@ +/* + * Copyright (C) 2010-2012 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx_imx_ssi_data_entry(soc, _id, _hwid, _size) \ + [_id] = { \ + .id = _id, \ + .iobase = soc ## _SSI ## _hwid ## _BASE_ADDR, \ + .iosize = _size, \ + .irq = soc ## _INT_SSI ## _hwid, \ + .dmatx0 = soc ## _DMA_REQ_SSI ## _hwid ## _TX0, \ + .dmarx0 = soc ## _DMA_REQ_SSI ## _hwid ## _RX0, \ + .dmatx1 = soc ## _DMA_REQ_SSI ## _hwid ## _TX1, \ + .dmarx1 = soc ## _DMA_REQ_SSI ## _hwid ## _RX1, \ + } + +#ifdef CONFIG_SOC_IMX21 +const struct imx_imx_ssi_data imx21_imx_ssi_data[] __initconst = { +#define imx21_imx_ssi_data_entry(_id, _hwid) \ + imx_imx_ssi_data_entry(MX21, _id, _hwid, SZ_4K) + imx21_imx_ssi_data_entry(0, 1), + imx21_imx_ssi_data_entry(1, 2), +}; +#endif /* ifdef CONFIG_SOC_IMX21 */ + +#ifdef CONFIG_SOC_IMX25 +const struct imx_imx_ssi_data imx25_imx_ssi_data[] __initconst = { +#define imx25_imx_ssi_data_entry(_id, _hwid) \ + imx_imx_ssi_data_entry(MX25, _id, _hwid, SZ_4K) + imx25_imx_ssi_data_entry(0, 1), + imx25_imx_ssi_data_entry(1, 2), +}; +#endif /* ifdef CONFIG_SOC_IMX25 */ + +#ifdef CONFIG_SOC_IMX27 +const struct imx_imx_ssi_data imx27_imx_ssi_data[] __initconst = { +#define imx27_imx_ssi_data_entry(_id, _hwid) \ + imx_imx_ssi_data_entry(MX27, _id, _hwid, SZ_4K) + imx27_imx_ssi_data_entry(0, 1), + imx27_imx_ssi_data_entry(1, 2), +}; +#endif /* ifdef CONFIG_SOC_IMX27 */ + +#ifdef CONFIG_SOC_IMX31 +const struct imx_imx_ssi_data imx31_imx_ssi_data[] __initconst = { +#define imx31_imx_ssi_data_entry(_id, _hwid) \ + imx_imx_ssi_data_entry(MX31, _id, _hwid, SZ_4K) + imx31_imx_ssi_data_entry(0, 1), + imx31_imx_ssi_data_entry(1, 2), +}; +#endif /* ifdef CONFIG_SOC_IMX31 */ + +#ifdef CONFIG_SOC_IMX35 +const struct imx_imx_ssi_data imx35_imx_ssi_data[] __initconst = { +#define imx35_imx_ssi_data_entry(_id, _hwid) \ + imx_imx_ssi_data_entry(MX35, _id, _hwid, SZ_4K) + imx35_imx_ssi_data_entry(0, 1), + imx35_imx_ssi_data_entry(1, 2), +}; +#endif /* ifdef CONFIG_SOC_IMX35 */ + +#ifdef CONFIG_SOC_IMX51 +const struct imx_imx_ssi_data imx51_imx_ssi_data[] __initconst = { +#define imx51_imx_ssi_data_entry(_id, _hwid) \ + imx_imx_ssi_data_entry(MX51, _id, _hwid, SZ_4K) + imx51_imx_ssi_data_entry(0, 1), + imx51_imx_ssi_data_entry(1, 2), + imx51_imx_ssi_data_entry(2, 3), +}; +#endif /* ifdef CONFIG_SOC_IMX51 */ + +#ifdef CONFIG_SOC_IMX53 +const struct imx_imx_ssi_data imx53_imx_ssi_data[] __initconst = { +#define imx53_imx_ssi_data_entry(_id, _hwid) \ + imx_imx_ssi_data_entry(MX53, _id, _hwid, SZ_4K) + imx53_imx_ssi_data_entry(0, 1), + imx53_imx_ssi_data_entry(1, 2), + imx53_imx_ssi_data_entry(2, 3), +}; +#endif /* ifdef CONFIG_SOC_IMX53 */ + +#ifdef CONFIG_SOC_IMX6Q +const struct imx_imx_ssi_data imx6_imx_ssi_data[] __initconst = { +#define imx6q_imx_ssi_data_entry(_id, _hwid) \ + imx_imx_ssi_data_entry(MX6Q, _id, _hwid, SZ_4K) + imx6q_imx_ssi_data_entry(0, 1), + imx6q_imx_ssi_data_entry(1, 2), + imx6q_imx_ssi_data_entry(2, 3), +}; +#endif /* ifdef CONFIG_SOC_IMX6Q */ + +struct platform_device *__init imx_add_imx_ssi( + const struct imx_imx_ssi_data *data, + const struct imx_ssi_platform_data *pdata) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + data->iosize - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, +#define DMARES(_name) { \ + .name = #_name, \ + .start = data->dma ## _name, \ + .end = data->dma ## _name, \ + .flags = IORESOURCE_DMA, \ +} + DMARES(tx0), + DMARES(rx0), + DMARES(tx1), + DMARES(rx1), + }; + + return imx_add_platform_device("imx-ssi", data->id, + res, ARRAY_SIZE(res), + pdata, sizeof(*pdata)); +} diff --git a/arch/arm/plat-mxc/devices/platform-imx-uart.c b/arch/arm/plat-mxc/devices/platform-imx-uart.c new file mode 100644 index 00000000..e76b026b --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx-uart.c @@ -0,0 +1,199 @@ +/* + * Copyright (C) 2009-2012 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx_imx_uart_3irq_data_entry(soc, _id, _hwid, _size) \ + [_id] = { \ + .id = _id, \ + .iobase = soc ## _UART ## _hwid ## _BASE_ADDR, \ + .iosize = _size, \ + .irqrx = soc ## _INT_UART ## _hwid ## RX, \ + .irqtx = soc ## _INT_UART ## _hwid ## TX, \ + .irqrts = soc ## _INT_UART ## _hwid ## RTS, \ + } + +#define imx_imx_uart_1irq_data_entry(soc, _id, _hwid, _size) \ + [_id] = { \ + .id = _id, \ + .iobase = soc ## _UART ## _hwid ## _BASE_ADDR, \ + .iosize = _size, \ + .irq = soc ## _INT_UART ## _hwid, \ + } + +#ifdef CONFIG_SOC_IMX1 +const struct imx_imx_uart_3irq_data imx1_imx_uart_data[] __initconst = { +#define imx1_imx_uart_data_entry(_id, _hwid) \ + imx_imx_uart_3irq_data_entry(MX1, _id, _hwid, 0xd0) + imx1_imx_uart_data_entry(0, 1), + imx1_imx_uart_data_entry(1, 2), +}; +#endif /* ifdef CONFIG_SOC_IMX1 */ + +#ifdef CONFIG_SOC_IMX21 +const struct imx_imx_uart_1irq_data imx21_imx_uart_data[] __initconst = { +#define imx21_imx_uart_data_entry(_id, _hwid) \ + imx_imx_uart_1irq_data_entry(MX21, _id, _hwid, SZ_4K) + imx21_imx_uart_data_entry(0, 1), + imx21_imx_uart_data_entry(1, 2), + imx21_imx_uart_data_entry(2, 3), + imx21_imx_uart_data_entry(3, 4), +}; +#endif + +#ifdef CONFIG_SOC_IMX25 +const struct imx_imx_uart_1irq_data imx25_imx_uart_data[] __initconst = { +#define imx25_imx_uart_data_entry(_id, _hwid) \ + imx_imx_uart_1irq_data_entry(MX25, _id, _hwid, SZ_16K) + imx25_imx_uart_data_entry(0, 1), + imx25_imx_uart_data_entry(1, 2), + imx25_imx_uart_data_entry(2, 3), + imx25_imx_uart_data_entry(3, 4), + imx25_imx_uart_data_entry(4, 5), +}; +#endif /* ifdef CONFIG_SOC_IMX25 */ + +#ifdef CONFIG_SOC_IMX27 +const struct imx_imx_uart_1irq_data imx27_imx_uart_data[] __initconst = { +#define imx27_imx_uart_data_entry(_id, _hwid) \ + imx_imx_uart_1irq_data_entry(MX27, _id, _hwid, SZ_4K) + imx27_imx_uart_data_entry(0, 1), + imx27_imx_uart_data_entry(1, 2), + imx27_imx_uart_data_entry(2, 3), + imx27_imx_uart_data_entry(3, 4), + imx27_imx_uart_data_entry(4, 5), + imx27_imx_uart_data_entry(5, 6), +}; +#endif /* ifdef CONFIG_SOC_IMX27 */ + +#ifdef CONFIG_SOC_IMX31 +const struct imx_imx_uart_1irq_data imx31_imx_uart_data[] __initconst = { +#define imx31_imx_uart_data_entry(_id, _hwid) \ + imx_imx_uart_1irq_data_entry(MX31, _id, _hwid, SZ_4K) + imx31_imx_uart_data_entry(0, 1), + imx31_imx_uart_data_entry(1, 2), + imx31_imx_uart_data_entry(2, 3), + imx31_imx_uart_data_entry(3, 4), + imx31_imx_uart_data_entry(4, 5), +}; +#endif /* ifdef CONFIG_SOC_IMX31 */ + +#ifdef CONFIG_SOC_IMX35 +const struct imx_imx_uart_1irq_data imx35_imx_uart_data[] __initconst = { +#define imx35_imx_uart_data_entry(_id, _hwid) \ + imx_imx_uart_1irq_data_entry(MX31, _id, _hwid, SZ_16K) + imx35_imx_uart_data_entry(0, 1), + imx35_imx_uart_data_entry(1, 2), + imx35_imx_uart_data_entry(2, 3), +}; +#endif /* ifdef CONFIG_SOC_IMX35 */ + +#ifdef CONFIG_SOC_IMX50 +const struct imx_imx_uart_1irq_data imx50_imx_uart_data[] __initconst = { +#define imx50_imx_uart_data_entry(_id, _hwid) \ + imx_imx_uart_1irq_data_entry(MX50, _id, _hwid, SZ_4K) + imx50_imx_uart_data_entry(0, 1), + imx50_imx_uart_data_entry(1, 2), + imx50_imx_uart_data_entry(2, 3), + imx50_imx_uart_data_entry(3, 4), + imx50_imx_uart_data_entry(4, 5), +}; +#endif /* ifdef CONFIG_SOC_IMX50 */ + +#ifdef CONFIG_SOC_IMX51 +const struct imx_imx_uart_1irq_data imx51_imx_uart_data[] __initconst = { +#define imx51_imx_uart_data_entry(_id, _hwid) \ + imx_imx_uart_1irq_data_entry(MX51, _id, _hwid, SZ_4K) + imx51_imx_uart_data_entry(0, 1), + imx51_imx_uart_data_entry(1, 2), + imx51_imx_uart_data_entry(2, 3), +}; +#endif /* ifdef CONFIG_SOC_IMX51 */ + +#ifdef CONFIG_SOC_IMX53 +const struct imx_imx_uart_1irq_data imx53_imx_uart_data[] __initconst = { +#define imx53_imx_uart_data_entry(_id, _hwid) \ + imx_imx_uart_1irq_data_entry(MX53, _id, _hwid, SZ_4K) + imx53_imx_uart_data_entry(0, 1), + imx53_imx_uart_data_entry(1, 2), + imx53_imx_uart_data_entry(2, 3), +}; +#endif /* ifdef CONFIG_SOC_IMX53 */ + +#ifdef CONFIG_SOC_IMX6Q +const struct imx_imx_uart_1irq_data imx6q_imx_uart_data[] __initconst = { +#define imx6q_imx_uart_data_entry(_id, _hwid) \ + imx_imx_uart_1irq_data_entry(MX6Q, _id, _hwid, SZ_4K) + imx6q_imx_uart_data_entry(0, 1), + imx6q_imx_uart_data_entry(1, 2), + imx6q_imx_uart_data_entry(2, 3), + imx6q_imx_uart_data_entry(3, 4), + imx6q_imx_uart_data_entry(4, 5), +}; +#endif /* ifdef CONFIG_SOC_IMX6Q */ + +#ifdef CONFIG_SOC_IMX6SL +const struct imx_imx_uart_1irq_data imx6sl_imx_uart_data[] __initconst = { +#define imx6sl_imx_uart_data_entry(_id, _hwid) \ + imx_imx_uart_1irq_data_entry(MX6SL, _id, _hwid, SZ_4K) + imx6sl_imx_uart_data_entry(0, 1), + imx6sl_imx_uart_data_entry(1, 2), + imx6sl_imx_uart_data_entry(2, 3), + imx6sl_imx_uart_data_entry(3, 4), + imx6sl_imx_uart_data_entry(4, 5), +}; +#endif /* ifdef CONFIG_SOC_IMX6SL */ + +struct platform_device *__init imx_add_imx_uart_3irq( + const struct imx_imx_uart_3irq_data *data, + const struct imxuart_platform_data *pdata) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + data->iosize - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irqrx, + .end = data->irqrx, + .flags = IORESOURCE_IRQ, + }, { + .start = data->irqtx, + .end = data->irqtx, + .flags = IORESOURCE_IRQ, + }, { + .start = data->irqrts, + .end = data->irqrx, + .flags = IORESOURCE_IRQ, + }, + }; + + return imx_add_platform_device("imx-uart", data->id, res, + ARRAY_SIZE(res), pdata, sizeof(*pdata)); +} + +struct platform_device *__init imx_add_imx_uart_1irq( + const struct imx_imx_uart_1irq_data *data, + const struct imxuart_platform_data *pdata) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + data->iosize - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + + return imx_add_platform_device("imx-uart", data->id, res, ARRAY_SIZE(res), + pdata, sizeof(*pdata)); +} diff --git a/arch/arm/plat-mxc/devices/platform-imx-vdoa.c b/arch/arm/plat-mxc/devices/platform-imx-vdoa.c new file mode 100644 index 00000000..057fda6b --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx-vdoa.c @@ -0,0 +1,60 @@ +/* + * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx_vdoa_data_entry_single(soc, _id, _hwid, size) \ + { \ + .id = _id, \ + .iobase = soc ## _VDOA ## _hwid ## _BASE_ADDR, \ + .iosize = size, \ + .irq = soc ## _INT_VDOA ## _hwid, \ + } + +#define imx_vdoa_data_entry(soc, _id, _hwid, _size) \ + [_id] = imx_vdoa_data_entry_single(soc, _id, _hwid, _size) + +#ifdef CONFIG_SOC_IMX6Q +#define MX6Q_VDOA_BASE_ADDR VDOA_BASE_ADDR +#define SOC_VDOA_BASE_ADDR MX6Q_VDOA_BASE_ADDR +#define MX6Q_INT_VDOA MXC_INT_VDOA +const struct imx_vdoa_data imx6q_vdoa_data __initconst = + imx_vdoa_data_entry_single(MX6Q, 0, , SZ_4K); +#endif + +struct platform_device *__init imx_add_vdoa( + const struct imx_vdoa_data *data) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + data->iosize - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + + return imx_add_platform_device("mxc_vdoa", -1, + res, ARRAY_SIZE(res), NULL, 0); +} diff --git a/arch/arm/plat-mxc/devices/platform-imx-viim.c b/arch/arm/plat-mxc/devices/platform-imx-viim.c new file mode 100644 index 00000000..89c611d5 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx-viim.c @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <mach/hardware.h> +#include <mach/devices-common.h> +#include <linux/fsl_devices.h> + +#ifdef CONFIG_SOC_IMX51 +#define GPT_REG_BASE_ADDR (MX50_GPT1_BASE_ADDR) +const struct imx_viim_data imx50_viim_data = { + .iobase = MX50_OCOTP_CTRL_BASE_ADDR, +}; +#endif + +#ifdef CONFIG_SOC_IMX6Q +#define GPT_REG_BASE_ADDR (GPT_BASE_ADDR) +const struct imx_viim_data imx6q_viim_data = { + .iobase = OCOTP_BASE_ADDR, +}; +#endif + +struct platform_device *__init imx_add_viim( + const struct imx_viim_data *data) +{ + struct resource res[] = { + [0] = { + .start = GPT_REG_BASE_ADDR, + .end = GPT_REG_BASE_ADDR + PAGE_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = data->iobase, + .end = data->iobase + PAGE_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + }; + + return imx_add_platform_device("mxs_viim", 0, + res, ARRAY_SIZE(res), NULL, 0); +} + diff --git a/arch/arm/plat-mxc/devices/platform-imx2-wdt.c b/arch/arm/plat-mxc/devices/platform-imx2-wdt.c new file mode 100644 index 00000000..53cfb8dd --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx2-wdt.c @@ -0,0 +1,91 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <asm/sizes.h> +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx_imx2_wdt_data_entry_single(soc, _id, _hwid, _size) \ + { \ + .id = _id, \ + .iobase = soc ## _WDOG ## _hwid ## _BASE_ADDR, \ + .iosize = _size, \ + .irq = soc ## _INT_WDOG ## _hwid, \ + } +#define imx_imx2_wdt_data_entry(soc, _id, _hwid, _size) \ + [_id] = imx_imx2_wdt_data_entry_single(soc, _id, _hwid, _size) + +#ifdef CONFIG_SOC_IMX21 +const struct imx_imx2_wdt_data imx21_imx2_wdt_data __initconst = + imx_imx2_wdt_data_entry_single(MX21, 0, , SZ_4K); +#endif /* ifdef CONFIG_SOC_IMX21 */ + +#ifdef CONFIG_SOC_IMX25 +const struct imx_imx2_wdt_data imx25_imx2_wdt_data __initconst = + imx_imx2_wdt_data_entry_single(MX25, 0, , SZ_16K); +#endif /* ifdef CONFIG_SOC_IMX25 */ + +#ifdef CONFIG_SOC_IMX27 +const struct imx_imx2_wdt_data imx27_imx2_wdt_data __initconst = + imx_imx2_wdt_data_entry_single(MX27, 0, , SZ_4K); +#endif /* ifdef CONFIG_SOC_IMX27 */ + +#ifdef CONFIG_SOC_IMX31 +const struct imx_imx2_wdt_data imx31_imx2_wdt_data __initconst = + imx_imx2_wdt_data_entry_single(MX31, 0, , SZ_16K); +#endif /* ifdef CONFIG_SOC_IMX31 */ + +#ifdef CONFIG_SOC_IMX35 +const struct imx_imx2_wdt_data imx35_imx2_wdt_data __initconst = + imx_imx2_wdt_data_entry_single(MX35, 0, , SZ_16K); +#endif /* ifdef CONFIG_SOC_IMX35 */ + +#ifdef CONFIG_SOC_IMX51 +const struct imx_imx2_wdt_data imx51_imx2_wdt_data[] __initconst = { +#define imx51_imx2_wdt_data_entry(_id, _hwid) \ + imx_imx2_wdt_data_entry(MX51, _id, _hwid, SZ_16K) + imx51_imx2_wdt_data_entry(0, 1), + imx51_imx2_wdt_data_entry(1, 2), +}; +#endif /* ifdef CONFIG_SOC_IMX51 */ + +#ifdef CONFIG_SOC_IMX53 +const struct imx_imx2_wdt_data imx53_imx2_wdt_data[] __initconst = { +#define imx53_imx2_wdt_data_entry(_id, _hwid) \ + imx_imx2_wdt_data_entry(MX53, _id, _hwid, SZ_16K) + imx53_imx2_wdt_data_entry(0, 1), + imx53_imx2_wdt_data_entry(1, 2), +}; +#endif /* ifdef CONFIG_SOC_IMX53 */ + +#ifdef CONFIG_SOC_IMX6Q +const struct imx_imx2_wdt_data imx6q_imx2_wdt_data[] __initconst = { +#define imx6q_imx2_wdt_data_entry(_id, _hwid) \ + imx_imx2_wdt_data_entry(MX6Q, _id, _hwid, SZ_16K) + imx6q_imx2_wdt_data_entry(0, 1), + imx6q_imx2_wdt_data_entry(1, 2), +}; +#endif + +struct platform_device *__init imx_add_imx2_wdt( + const struct imx_imx2_wdt_data *data) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + data->iosize - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + return imx_add_platform_device("imx2-wdt", data->id, + res, ARRAY_SIZE(res), NULL, 0); +} diff --git a/arch/arm/plat-mxc/devices/platform-imx21-hcd.c b/arch/arm/plat-mxc/devices/platform-imx21-hcd.c new file mode 100644 index 00000000..5770a42f --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx21-hcd.c @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx_imx21_hcd_data_entry_single(soc) \ + { \ + .iobase = soc ## _USBOTG_BASE_ADDR, \ + .irq = soc ## _INT_USBHOST, \ + } + +#ifdef CONFIG_SOC_IMX21 +const struct imx_imx21_hcd_data imx21_imx21_hcd_data __initconst = + imx_imx21_hcd_data_entry_single(MX21); +#endif /* ifdef CONFIG_SOC_IMX21 */ + +struct platform_device *__init imx_add_imx21_hcd( + const struct imx_imx21_hcd_data *data, + const struct mx21_usbh_platform_data *pdata) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + SZ_8K - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + return imx_add_platform_device_dmamask("imx21-hcd", 0, + res, ARRAY_SIZE(res), + pdata, sizeof(*pdata), DMA_BIT_MASK(32)); +} diff --git a/arch/arm/plat-mxc/devices/platform-imx_dvfs.c b/arch/arm/plat-mxc/devices/platform-imx_dvfs.c new file mode 100755 index 00000000..ae62ff9b --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx_dvfs.c @@ -0,0 +1,63 @@ +/* + * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. + * Jason Chen <jason.chen@freescale.com> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx_dvfs_core_data_entry_single(soc) \ + { \ + .iobase = soc ## _DVFSCORE_BASE_ADDR, \ + .irq = soc ## _INT_GPC1, \ + } + +#ifdef CONFIG_SOC_IMX50 +const struct imx_dvfs_core_data imx50_dvfs_core_data __initconst = + imx_dvfs_core_data_entry_single(MX50); +#endif /* ifdef CONFIG_SOC_IMX50 */ + +#ifdef CONFIG_SOC_IMX51 +const struct imx_dvfs_core_data imx51_dvfs_core_data __initconst = + imx_dvfs_core_data_entry_single(MX51); +#endif /* ifdef CONFIG_SOC_IMX51 */ + +#ifdef CONFIG_SOC_IMX53 +const struct imx_dvfs_core_data imx53_dvfs_core_data __initconst = + imx_dvfs_core_data_entry_single(MX53); +#endif /* ifdef CONFIG_SOC_IMX53 */ + +#ifdef CONFIG_SOC_IMX6Q +const struct imx_dvfs_core_data imx6q_dvfs_core_data __initconst = + imx_dvfs_core_data_entry_single(MX6Q); +#endif /* ifdef CONFIG_SOC_IMX6Q */ + +struct platform_device *__init imx_add_dvfs_core( + const struct imx_dvfs_core_data *data, + const struct mxc_dvfs_platform_data *pdata) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + 4 * SZ_16 - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + + return imx_add_platform_device("imx_dvfscore", 0, + res, ARRAY_SIZE(res), pdata, sizeof(*pdata)); +} + +struct platform_device *__init imx_add_busfreq() +{ + return imx_add_platform_device("imx_busfreq", 0, + NULL, 0, NULL, 0); +} + diff --git a/arch/arm/plat-mxc/devices/platform-imx_ipuv3.c b/arch/arm/plat-mxc/devices/platform-imx_ipuv3.c new file mode 100755 index 00000000..c5b4d992 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx_ipuv3.c @@ -0,0 +1,239 @@ +/* + * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <mach/hardware.h> +#include <mach/devices-common.h> +#include <linux/clk.h> + +#define imx5_ipuv3_data_entry_single(soc, size, ipu_init, ipu_pg) \ + { \ + .iobase = soc ## _IPU_CTRL_BASE_ADDR, \ + .irq_err = soc ## _INT_IPU_ERR, \ + .irq = soc ## _INT_IPU_SYN, \ + .irq_start = MXC_IPU_IRQ_START, \ + .iosize = size, \ + .init = ipu_init, \ + .pg = ipu_pg, \ + } + +#define imx6_ipuv3_data_entry_single(soc, id, size, ipu_init, ipu_pg) \ + { \ + .iobase = soc ## _IPU ## id ## _ARB_BASE_ADDR, \ + .irq_err = soc ## _INT_IPU ## id ## _ERR, \ + .irq = soc ## _INT_IPU ## id ## _SYN, \ + .irq_start = MXC_IPU_IRQ_START, \ + .iosize = size, \ + .init = ipu_init, \ + .pg = ipu_pg, \ + } + +#ifdef CONFIG_SOC_IMX51 +/* + * The MIPI HSC unit has been removed from the i.MX51 Reference Manual by + * the Freescale marketing division. However this did not remove the + * hardware from the chip which still needs to be configured... + */ +static int __init ipu_mipi_setup(void) +{ + struct clk *hsc_clk; + void __iomem *hsc_addr; + int ret = 0; + + hsc_addr = ioremap(MX51_MIPI_HSC_BASE_ADDR, PAGE_SIZE); + if (!hsc_addr) + return -ENOMEM; + + hsc_clk = clk_get_sys(NULL, "mipi_hsp"); + if (IS_ERR(hsc_clk)) { + ret = PTR_ERR(hsc_clk); + goto unmap; + } + clk_enable(hsc_clk); + + /* setup MIPI module to legacy mode */ + writel(0xF00, hsc_addr); + + /* CSI mode: reserved; DI control mode: legacy (from Freescale BSP) */ + writel(readl(hsc_addr + 0x800) | 0x30ff, + hsc_addr + 0x800); + + clk_disable(hsc_clk); + clk_put(hsc_clk); +unmap: + iounmap(hsc_addr); + + return ret; +} + +int __init mx51_ipuv3_init(int id) +{ + int ret = 0; + u32 val; + + ret = ipu_mipi_setup(); + + /* hard reset the IPU */ + val = readl(MX51_IO_ADDRESS(MX51_SRC_BASE_ADDR)); + val |= 1 << 3; + writel(val, MX51_IO_ADDRESS(MX51_SRC_BASE_ADDR)); + + return ret; +} + +void mx51_ipuv3_pg(int enable) +{ + if (enable) { + writel(MXC_PGCR_PCR, MX51_PGC_IPU_PGCR); + writel(MXC_PGSR_PSR, MX51_PGC_IPU_PGSR); + } else { + writel(0x0, MX51_PGC_IPU_PGCR); + if (readl(MX51_PGC_IPU_PGSR) & MXC_PGSR_PSR) + printk(KERN_DEBUG "power gating successful\n"); + writel(MXC_PGSR_PSR, MX51_PGC_IPU_PGSR); + } +} + +const struct imx_ipuv3_data imx51_ipuv3_data __initconst = + imx5_ipuv3_data_entry_single(MX51, SZ_512M, + mx51_ipuv3_init, mx51_ipuv3_pg); +#endif + +#ifdef CONFIG_SOC_IMX53 +int __init mx53_ipuv3_init(int id) +{ + int ret = 0; + u32 val; + + /* hard reset the IPU */ + val = readl(MX53_IO_ADDRESS(MX53_SRC_BASE_ADDR)); + val |= 1 << 3; + writel(val, MX53_IO_ADDRESS(MX53_SRC_BASE_ADDR)); + + return ret; +} + +void mx53_ipuv3_pg(int enable) +{ + if (enable) { + writel(MXC_PGCR_PCR, MX53_PGC_IPU_PGCR); + writel(MXC_PGSR_PSR, MX53_PGC_IPU_PGSR); + } else { + writel(0x0, MX53_PGC_IPU_PGCR); + if (readl(MX53_PGC_IPU_PGSR) & MXC_PGSR_PSR) + printk(KERN_DEBUG "power gating successful\n"); + writel(MXC_PGSR_PSR, MX53_PGC_IPU_PGSR); + } +} + +const struct imx_ipuv3_data imx53_ipuv3_data __initconst = + imx5_ipuv3_data_entry_single(MX53, SZ_128M, + mx53_ipuv3_init, mx53_ipuv3_pg); +#endif + +#ifdef CONFIG_SOC_IMX6Q +int __init mx6q_ipuv3_init(int id) +{ + int ret = 0; + u32 val; + + /* hard reset the IPU */ + val = readl(MX6_IO_ADDRESS(SRC_BASE_ADDR)); + if (id == 0) + val |= 1 << 3; + else + val |= 1 << 12; + writel(val, MX6_IO_ADDRESS(SRC_BASE_ADDR)); + + return ret; +} + +void mx6q_ipuv3_pg(int enable) +{ + /*TODO*/ +} + +const struct imx_ipuv3_data imx6q_ipuv3_data[] __initconst = { + imx6_ipuv3_data_entry_single(MX6Q, 1, SZ_4M, + mx6q_ipuv3_init, mx6q_ipuv3_pg), + imx6_ipuv3_data_entry_single(MX6Q, 2, SZ_4M, + mx6q_ipuv3_init, mx6q_ipuv3_pg), +}; +#endif + +struct platform_device *__init imx_add_ipuv3( + const int id, + const struct imx_ipuv3_data *data, + struct imx_ipuv3_platform_data *pdata) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + data->iosize - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq_err, + .end = data->irq_err, + .flags = IORESOURCE_IRQ, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + + pdata->init = data->init; + pdata->pg = data->pg; + + return imx_add_platform_device_dmamask("imx-ipuv3", id, + res, ARRAY_SIZE(res), pdata, sizeof(*pdata), + DMA_BIT_MASK(32)); +} + +struct platform_device *__init imx_add_ipuv3_fb( + const int id, + const struct ipuv3_fb_platform_data *pdata) +{ + if (pdata->res_size[0] > 0) { + struct resource res[] = { + { + .start = pdata->res_base[0], + .end = pdata->res_base[0] + pdata->res_size[0] - 1, + .flags = IORESOURCE_MEM, + }, { + .start = 0, + .end = 0, + .flags = IORESOURCE_MEM, + }, + }; + + if (pdata->res_size[1] > 0) { + res[1].start = pdata->res_base[1]; + res[1].end = pdata->res_base[1] + + pdata->res_size[1] - 1; + } + + return imx_add_platform_device_dmamask("mxc_sdc_fb", + id, res, ARRAY_SIZE(res), pdata, + sizeof(*pdata), DMA_BIT_MASK(32)); + } else + return imx_add_platform_device_dmamask("mxc_sdc_fb", id, + NULL, 0, pdata, sizeof(*pdata), + DMA_BIT_MASK(32)); +} diff --git a/arch/arm/plat-mxc/devices/platform-imx_ldb.c b/arch/arm/plat-mxc/devices/platform-imx_ldb.c new file mode 100644 index 00000000..a0919a7b --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx_ldb.c @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <mach/hardware.h> +#include <mach/devices-common.h> +#include <linux/clk.h> + +#define imx_ldb_data_entry_single(soc, size) \ + { \ + .iobase = soc ## _IOMUXC_BASE_ADDR, \ + .iosize = size, \ + } + +#ifdef CONFIG_SOC_IMX53 +const struct imx_ldb_data imx53_ldb_data __initconst = + imx_ldb_data_entry_single(MX53, SZ_4K); +#endif + +#ifdef CONFIG_SOC_IMX6Q +const struct imx_ldb_data imx6q_ldb_data __initconst = + imx_ldb_data_entry_single(MX6Q, SZ_4K); +#endif + +struct platform_device *__init imx_add_ldb( + const struct imx_ldb_data *data, + struct fsl_mxc_ldb_platform_data *pdata) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + data->iosize - 1, + .flags = IORESOURCE_MEM, + }, + }; + + return imx_add_platform_device("mxc_ldb", -1, + res, ARRAY_SIZE(res), pdata, sizeof(*pdata)); +} + diff --git a/arch/arm/plat-mxc/devices/platform-imx_snvs_rtc.c b/arch/arm/plat-mxc/devices/platform-imx_snvs_rtc.c new file mode 100644 index 00000000..031a0741 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx_snvs_rtc.c @@ -0,0 +1,53 @@ +/* + * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <asm/sizes.h> +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx_snvs_rtc_data_entry_single(soc) \ + { \ + .iobase = soc ## _SNVS_BASE_ADDR, \ + .irq = soc ## _INT_SNVS, \ + } + +#ifdef CONFIG_SOC_IMX6Q +const struct imx_snvs_rtc_data imx6q_imx_snvs_rtc_data __initconst = + imx_snvs_rtc_data_entry_single(MX6Q); +#endif /* ifdef CONFIG_SOC_IMX6Q */ + +struct platform_device *__init imx_add_snvs_rtc( + const struct imx_snvs_rtc_data *data) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + + return imx_add_platform_device("snvs_rtc", 0, + res, ARRAY_SIZE(res), NULL, 0); +} diff --git a/arch/arm/plat-mxc/devices/platform-imx_srtc.c b/arch/arm/plat-mxc/devices/platform-imx_srtc.c new file mode 100755 index 00000000..9e4191ec --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx_srtc.c @@ -0,0 +1,63 @@ +/* + * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <asm/sizes.h> +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx_imx_srtc_data_entry_single(soc) \ + { \ + .iobase = soc ## _SRTC_BASE_ADDR, \ + .irq = soc ## _INT_SRTC_NTZ, \ + } + +#ifdef CONFIG_SOC_IMX50 +const struct imx_srtc_data imx50_imx_srtc_data __initconst = + imx_imx_srtc_data_entry_single(MX50); +#endif /* ifdef CONFIG_SOC_IMX50 */ + +#ifdef CONFIG_SOC_IMX51 +const struct imx_srtc_data imx51_imx_srtc_data __initconst = + imx_imx_srtc_data_entry_single(MX51); +#endif /* ifdef CONFIG_SOC_IMX51 */ + +#ifdef CONFIG_SOC_IMX53 +const struct imx_srtc_data imx53_imx_srtc_data __initconst = + imx_imx_srtc_data_entry_single(MX53); +#endif /* ifdef CONFIG_SOC_IMX53 */ + +struct platform_device *__init imx_add_srtc( + const struct imx_srtc_data *data) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + + return imx_add_platform_device("mxc_rtc", 0, + res, ARRAY_SIZE(res), NULL, 0); +} diff --git a/arch/arm/plat-mxc/devices/platform-imx_tve.c b/arch/arm/plat-mxc/devices/platform-imx_tve.c new file mode 100755 index 00000000..6dc23d53 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx_tve.c @@ -0,0 +1,47 @@ +/* + * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. + * Jason Chen <jason.chen@freescale.com> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx5_tve_data_entry_single(soc) \ + { \ + .iobase = soc ## _TVE_BASE_ADDR, \ + .irq = soc ## _INT_TVE, \ + } + +#ifdef CONFIG_SOC_IMX51 +const struct imx_tve_data imx51_tve_data __initconst = + imx5_tve_data_entry_single(MX51); +#endif /* ifdef CONFIG_SOC_IMX51 */ + +#ifdef CONFIG_SOC_IMX53 +const struct imx_tve_data imx53_tve_data __initconst = + imx5_tve_data_entry_single(MX53); +#endif /* ifdef CONFIG_SOC_IMX53 */ + +struct platform_device *__init imx_add_tve( + const struct imx_tve_data *data, + const struct fsl_mxc_tve_platform_data *pdata) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + + return imx_add_platform_device("mxc_tve", -1, + res, ARRAY_SIZE(res), pdata, sizeof(*pdata)); +} + diff --git a/arch/arm/plat-mxc/devices/platform-imx_udc.c b/arch/arm/plat-mxc/devices/platform-imx_udc.c new file mode 100644 index 00000000..6fd675df --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx_udc.c @@ -0,0 +1,75 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx_imx_udc_data_entry_single(soc, _size) \ + { \ + .iobase = soc ## _USBD_BASE_ADDR, \ + .iosize = _size, \ + .irq0 = soc ## _INT_USBD0, \ + .irq1 = soc ## _INT_USBD1, \ + .irq2 = soc ## _INT_USBD2, \ + .irq3 = soc ## _INT_USBD3, \ + .irq4 = soc ## _INT_USBD4, \ + .irq5 = soc ## _INT_USBD5, \ + .irq6 = soc ## _INT_USBD6, \ + } + +#define imx_imx_udc_data_entry(soc, _size) \ + [_id] = imx_imx_udc_data_entry_single(soc, _size) + +#ifdef CONFIG_SOC_IMX1 +const struct imx_imx_udc_data imx1_imx_udc_data __initconst = + imx_imx_udc_data_entry_single(MX1, SZ_4K); +#endif /* ifdef CONFIG_SOC_IMX1 */ + +struct platform_device *__init imx_add_imx_udc( + const struct imx_imx_udc_data *data, + const struct imxusb_platform_data *pdata) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + data->iosize - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq0, + .end = data->irq0, + .flags = IORESOURCE_IRQ, + }, { + .start = data->irq1, + .end = data->irq1, + .flags = IORESOURCE_IRQ, + }, { + .start = data->irq2, + .end = data->irq2, + .flags = IORESOURCE_IRQ, + }, { + .start = data->irq3, + .end = data->irq3, + .flags = IORESOURCE_IRQ, + }, { + .start = data->irq4, + .end = data->irq4, + .flags = IORESOURCE_IRQ, + }, { + .start = data->irq5, + .end = data->irq5, + .flags = IORESOURCE_IRQ, + }, { + .start = data->irq6, + .end = data->irq6, + .flags = IORESOURCE_IRQ, + }, + }; + + return imx_add_platform_device("imx_udc", 0, + res, ARRAY_SIZE(res), pdata, sizeof(*pdata)); +} diff --git a/arch/arm/plat-mxc/devices/platform-imx_vpu.c b/arch/arm/plat-mxc/devices/platform-imx_vpu.c new file mode 100755 index 00000000..f0295ad1 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx_vpu.c @@ -0,0 +1,179 @@ +/* + * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved. + * Jason Chen <jason.chen@freescale.com> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx5_vpu_data_entry_single(soc, flag, size, vpu_reset, vpu_pg) \ + { \ + .iobase = soc ## _VPU_BASE_ADDR, \ + .irq_ipi = soc ## _INT_VPU, \ + .iram_enable = flag, \ + .iram_size = size, \ + .reset = vpu_reset, \ + .pg = vpu_pg, \ + } + +#define imx6_vpu_data_entry_single(soc, flag, size, vpu_reset, vpu_pg) \ + { \ + .iobase = soc ## _VPU_BASE_ADDR, \ + .irq_ipi = soc ## _INT_VPU_IPI, \ + .irq_jpg = soc ## _INT_VPU_JPG, \ + .iram_enable = flag, \ + .iram_size = size, \ + .reset = vpu_reset, \ + .pg = vpu_pg, \ + } + +#ifdef CONFIG_SOC_IMX51 +void mx51_vpu_reset(void) +{ + u32 reg; + void __iomem *src_base; + + src_base = ioremap(MX51_SRC_BASE_ADDR, PAGE_SIZE); + + /* mask interrupt due to vpu passed reset */ + reg = __raw_readl(src_base + 0x18); + reg |= 0x02; + __raw_writel(reg, src_base + 0x18); + + reg = __raw_readl(src_base); + reg |= 0x5; /* warm reset vpu */ + __raw_writel(reg, src_base); + while (__raw_readl(src_base) & 0x04) + ; + + iounmap(src_base); +} + +void mx51_vpu_pg(int enable) +{ + if (enable) { + __raw_writel(MXC_PGCR_PCR, MX51_PGC_VPU_PGCR); + __raw_writel(MXC_PGSR_PSR, MX51_PGC_VPU_PGSR); + } else { + __raw_writel(0x0, MX51_PGC_VPU_PGCR); + if (__raw_readl(MX51_PGC_VPU_PGSR) & MXC_PGSR_PSR) + printk(KERN_DEBUG "power gating successful\n"); + __raw_writel(MXC_PGSR_PSR, MX51_PGC_VPU_PGSR); + } +} +const struct imx_vpu_data imx51_vpu_data __initconst = + imx5_vpu_data_entry_single(MX51, + false, 0x14000, mx51_vpu_reset, mx51_vpu_pg); +#endif + +#ifdef CONFIG_SOC_IMX53 +void mx53_vpu_reset(void) +{ + u32 reg; + void __iomem *src_base; + + src_base = ioremap(MX53_SRC_BASE_ADDR, PAGE_SIZE); + + /* mask interrupt due to vpu passed reset */ + reg = __raw_readl(src_base + 0x18); + reg |= 0x02; + __raw_writel(reg, src_base + 0x18); + + reg = __raw_readl(src_base); + reg |= 0x5; /* warm reset vpu */ + __raw_writel(reg, src_base); + while (__raw_readl(src_base) & 0x04) + ; + + iounmap(src_base); +} + +void mx53_vpu_pg(int enable) +{ + if (enable) { + __raw_writel(MXC_PGCR_PCR, MX53_PGC_VPU_PGCR); + __raw_writel(MXC_PGSR_PSR, MX53_PGC_VPU_PGSR); + } else { + __raw_writel(0x0, MX53_PGC_VPU_PGCR); + if (__raw_readl(MX53_PGC_VPU_PGSR) & MXC_PGSR_PSR) + printk(KERN_DEBUG "power gating successful\n"); + __raw_writel(MXC_PGSR_PSR, MX53_PGC_VPU_PGSR); + } +} + +const struct imx_vpu_data imx53_vpu_data __initconst = + imx5_vpu_data_entry_single(MX53, + true, 0x14000, mx53_vpu_reset, mx53_vpu_pg); +#endif + +#ifdef CONFIG_SOC_IMX6Q +void mx6q_vpu_reset(void) +{ + u32 reg; + void __iomem *src_base; + + src_base = ioremap(SRC_BASE_ADDR, PAGE_SIZE); + + /* mask interrupt due to vpu passed reset */ + reg = __raw_readl(src_base + 0x18); + reg |= 0x02; + __raw_writel(reg, src_base + 0x18); + + reg = __raw_readl(src_base); + reg |= 0x4; /* warm reset vpu */ + __raw_writel(reg, src_base); + while (__raw_readl(src_base) & 0x04) + ; + + iounmap(src_base); +} + +const struct imx_vpu_data imx6q_vpu_data __initconst = + imx6_vpu_data_entry_single(MX6Q, + true, 0x21000, mx6q_vpu_reset, NULL); +#endif + +struct platform_device *__init imx_add_vpu( + const struct imx_vpu_data *data) +{ + struct mxc_vpu_platform_data pdata; + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + SZ_16K - 1, + .name = "vpu_regs", + .flags = IORESOURCE_MEM, + }, { + .start = data->irq_ipi, + .end = data->irq_ipi, + .name = "vpu_ipi_irq", + .flags = IORESOURCE_IRQ, + }, +#ifdef CONFIG_SOC_IMX6Q + { + .start = data->irq_jpg, + .end = data->irq_jpg, + .name = "vpu_jpu_irq", + .flags = IORESOURCE_IRQ, + }, +#endif + }; + + pdata.reset = data->reset; + pdata.pg = data->pg; + pdata.iram_enable = data->iram_enable; + pdata.iram_size = data->iram_size; + + if (!fuse_dev_is_available(MXC_DEV_VPU)) + return ERR_PTR(-ENODEV); + + if (cpu_is_mx6dl()) + pdata.iram_enable = false; + + return imx_add_platform_device("mxc_vpu", -1, + res, ARRAY_SIZE(res), &pdata, sizeof(pdata)); +} + diff --git a/arch/arm/plat-mxc/devices/platform-imxdi_rtc.c b/arch/arm/plat-mxc/devices/platform-imxdi_rtc.c new file mode 100644 index 00000000..805336fd --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imxdi_rtc.c @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <asm/sizes.h> +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx_imxdi_rtc_data_entry_single(soc) \ + { \ + .iobase = soc ## _DRYICE_BASE_ADDR, \ + .irq = soc ## _INT_DRYICE, \ + } + +#ifdef CONFIG_SOC_IMX25 +const struct imx_imxdi_rtc_data imx25_imxdi_rtc_data __initconst = + imx_imxdi_rtc_data_entry_single(MX25); +#endif /* ifdef CONFIG_SOC_IMX25 */ + +struct platform_device *__init imx_add_imxdi_rtc( + const struct imx_imxdi_rtc_data *data) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + + return imx_add_platform_device("imxdi_rtc", 0, + res, ARRAY_SIZE(res), NULL, 0); +} diff --git a/arch/arm/plat-mxc/devices/platform-ipu-core.c b/arch/arm/plat-mxc/devices/platform-ipu-core.c new file mode 100644 index 00000000..79d340ae --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-ipu-core.c @@ -0,0 +1,130 @@ +/* + * Copyright (C) 2011 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <linux/dma-mapping.h> +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx_ipu_core_entry_single(soc) \ +{ \ + .iobase = soc ## _IPU_CTRL_BASE_ADDR, \ + .synirq = soc ## _INT_IPU_SYN, \ + .errirq = soc ## _INT_IPU_ERR, \ +} + +#ifdef CONFIG_SOC_IMX31 +const struct imx_ipu_core_data imx31_ipu_core_data __initconst = + imx_ipu_core_entry_single(MX31); +#endif + +#ifdef CONFIG_SOC_IMX35 +const struct imx_ipu_core_data imx35_ipu_core_data __initconst = + imx_ipu_core_entry_single(MX35); +#endif + +static struct platform_device *imx_ipu_coredev __initdata; + +struct platform_device *__init imx_add_ipu_core( + const struct imx_ipu_core_data *data, + const struct ipu_platform_data *pdata) +{ + /* The resource order is important! */ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + 0x5f, + .flags = IORESOURCE_MEM, + }, { + .start = data->iobase + 0x88, + .end = data->iobase + 0xb3, + .flags = IORESOURCE_MEM, + }, { + .start = data->synirq, + .end = data->synirq, + .flags = IORESOURCE_IRQ, + }, { + .start = data->errirq, + .end = data->errirq, + .flags = IORESOURCE_IRQ, + }, + }; + + return imx_ipu_coredev = imx_add_platform_device("ipu-core", -1, + res, ARRAY_SIZE(res), pdata, sizeof(*pdata)); +} + +struct platform_device *__init imx_alloc_mx3_camera( + const struct imx_ipu_core_data *data, + const struct mx3_camera_pdata *pdata) +{ + struct resource res[] = { + { + .start = data->iobase + 0x60, + .end = data->iobase + 0x87, + .flags = IORESOURCE_MEM, + }, + }; + int ret = -ENOMEM; + struct platform_device *pdev; + + if (IS_ERR_OR_NULL(imx_ipu_coredev)) + return ERR_PTR(-ENODEV); + + pdev = platform_device_alloc("mx3-camera", 0); + if (!pdev) + goto err; + + pdev->dev.dma_mask = kmalloc(sizeof(*pdev->dev.dma_mask), GFP_KERNEL); + if (!pdev->dev.dma_mask) + goto err; + + *pdev->dev.dma_mask = DMA_BIT_MASK(32); + pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32); + + ret = platform_device_add_resources(pdev, res, ARRAY_SIZE(res)); + if (ret) + goto err; + + if (pdata) { + struct mx3_camera_pdata *copied_pdata; + + ret = platform_device_add_data(pdev, pdata, sizeof(*pdata)); + if (ret) { +err: + kfree(pdev->dev.dma_mask); + platform_device_put(pdev); + return ERR_PTR(-ENODEV); + } + copied_pdata = dev_get_platdata(&pdev->dev); + copied_pdata->dma_dev = &imx_ipu_coredev->dev; + } + + return pdev; +} + +struct platform_device *__init imx_add_mx3_sdc_fb( + const struct imx_ipu_core_data *data, + struct mx3fb_platform_data *pdata) +{ + struct resource res[] = { + { + .start = data->iobase + 0xb4, + .end = data->iobase + 0x1bf, + .flags = IORESOURCE_MEM, + }, + }; + + if (IS_ERR_OR_NULL(imx_ipu_coredev)) + return ERR_PTR(-ENODEV); + + pdata->dma_dev = &imx_ipu_coredev->dev; + + return imx_add_platform_device_dmamask("mx3_sdc_fb", -1, + res, ARRAY_SIZE(res), pdata, sizeof(*pdata), + DMA_BIT_MASK(32)); +} diff --git a/arch/arm/plat-mxc/devices/platform-mx1-camera.c b/arch/arm/plat-mxc/devices/platform-mx1-camera.c new file mode 100644 index 00000000..edcc581a --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-mx1-camera.c @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx_mx1_camera_data_entry_single(soc, _size) \ + { \ + .iobase = soc ## _CSI ## _BASE_ADDR, \ + .iosize = _size, \ + .irq = soc ## _INT_CSI, \ + } + +#ifdef CONFIG_SOC_IMX1 +const struct imx_mx1_camera_data imx1_mx1_camera_data __initconst = + imx_mx1_camera_data_entry_single(MX1, 10); +#endif /* ifdef CONFIG_SOC_IMX1 */ + +struct platform_device *__init imx_add_mx1_camera( + const struct imx_mx1_camera_data *data, + const struct mx1_camera_pdata *pdata) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + data->iosize - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + return imx_add_platform_device_dmamask("mx1-camera", 0, + res, ARRAY_SIZE(res), + pdata, sizeof(*pdata), DMA_BIT_MASK(32)); +} diff --git a/arch/arm/plat-mxc/devices/platform-mx2-camera.c b/arch/arm/plat-mxc/devices/platform-mx2-camera.c new file mode 100644 index 00000000..b3f4828d --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-mx2-camera.c @@ -0,0 +1,64 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx_mx2_camera_data_entry_single(soc) \ + { \ + .iobasecsi = soc ## _CSI_BASE_ADDR, \ + .iosizecsi = SZ_4K, \ + .irqcsi = soc ## _INT_CSI, \ + } +#define imx_mx2_camera_data_entry_single_emma(soc) \ + { \ + .iobasecsi = soc ## _CSI_BASE_ADDR, \ + .iosizecsi = SZ_32, \ + .irqcsi = soc ## _INT_CSI, \ + .iobaseemmaprp = soc ## _EMMAPRP_BASE_ADDR, \ + .iosizeemmaprp = SZ_32, \ + .irqemmaprp = soc ## _INT_EMMAPRP, \ + } + +#ifdef CONFIG_SOC_IMX25 +const struct imx_mx2_camera_data imx25_mx2_camera_data __initconst = + imx_mx2_camera_data_entry_single(MX25); +#endif /* ifdef CONFIG_SOC_IMX25 */ + +#ifdef CONFIG_SOC_IMX27 +const struct imx_mx2_camera_data imx27_mx2_camera_data __initconst = + imx_mx2_camera_data_entry_single_emma(MX27); +#endif /* ifdef CONFIG_SOC_IMX27 */ + +struct platform_device *__init imx_add_mx2_camera( + const struct imx_mx2_camera_data *data, + const struct mx2_camera_platform_data *pdata) +{ + struct resource res[] = { + { + .start = data->iobasecsi, + .end = data->iobasecsi + data->iosizecsi - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irqcsi, + .end = data->irqcsi, + .flags = IORESOURCE_IRQ, + }, { + .start = data->iobaseemmaprp, + .end = data->iobaseemmaprp + data->iosizeemmaprp - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irqemmaprp, + .end = data->irqemmaprp, + .flags = IORESOURCE_IRQ, + }, + }; + return imx_add_platform_device_dmamask("mx2-camera", 0, + res, data->iobaseemmaprp ? 4 : 2, + pdata, sizeof(*pdata), DMA_BIT_MASK(32)); +} diff --git a/arch/arm/plat-mxc/devices/platform-mxc-ehci.c b/arch/arm/plat-mxc/devices/platform-mxc-ehci.c new file mode 100644 index 00000000..984fa296 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-mxc-ehci.c @@ -0,0 +1,152 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <linux/dma-mapping.h> +#include <mach/hardware.h> +#include <mach/devices-common.h> +#define imx_mxc_ehci_data_entry_single(soc, _id, hs) \ + { \ + .id = _id, \ + .iobase = soc ## _USB_ ## hs ## _BASE_ADDR, \ + .irq = soc ## _INT_USB_ ## hs, \ + } + +#ifdef CONFIG_SOC_IMX25 +const struct imx_mxc_ehci_data imx25_mxc_ehci_otg_data __initconst = + imx_mxc_ehci_data_entry_single(MX25, 0, OTG); +const struct imx_mxc_ehci_data imx25_mxc_ehci_hs_data __initconst = + imx_mxc_ehci_data_entry_single(MX25, 1, HS); +#endif /* ifdef CONFIG_SOC_IMX25 */ + +#ifdef CONFIG_SOC_IMX27 +const struct imx_mxc_ehci_data imx27_mxc_ehci_otg_data __initconst = + imx_mxc_ehci_data_entry_single(MX27, 0, OTG); +const struct imx_mxc_ehci_data imx27_mxc_ehci_hs_data[] __initconst = { + imx_mxc_ehci_data_entry_single(MX27, 1, HS1), + imx_mxc_ehci_data_entry_single(MX27, 2, HS2), +}; +#endif /* ifdef CONFIG_SOC_IMX27 */ + +#ifdef CONFIG_SOC_IMX31 +const struct imx_mxc_ehci_data imx31_mxc_ehci_otg_data __initconst = + imx_mxc_ehci_data_entry_single(MX31, 0, OTG); +const struct imx_mxc_ehci_data imx31_mxc_ehci_hs_data[] __initconst = { + imx_mxc_ehci_data_entry_single(MX31, 1, HS1), + imx_mxc_ehci_data_entry_single(MX31, 2, HS2), +}; +#endif /* ifdef CONFIG_SOC_IMX31 */ + +#ifdef CONFIG_SOC_IMX35 +const struct imx_mxc_ehci_data imx35_mxc_ehci_otg_data __initconst = + imx_mxc_ehci_data_entry_single(MX35, 0, OTG); +const struct imx_mxc_ehci_data imx35_mxc_ehci_hs_data __initconst = + imx_mxc_ehci_data_entry_single(MX35, 1, HS); +#endif /* ifdef CONFIG_SOC_IMX35 */ + +#ifdef CONFIG_SOC_IMX6Q +const struct imx_mxc_ehci_data imx6q_mxc_ehci_otg_data __initconst = + imx_mxc_ehci_data_entry_single(MX6Q, 0, OTG); +const struct imx_mxc_ehci_data imx6q_mxc_ehci_hs_data[] __initconst = { + imx_mxc_ehci_data_entry_single(MX6Q, 1, HS1), + imx_mxc_ehci_data_entry_single(MX6Q, 2, HS2), + imx_mxc_ehci_data_entry_single(MX6Q, 3, HS3), +}; + +const struct imx_mxc_ehci_data imx6sl_mxc_ehci_hs_data[] __initconst = { + imx_mxc_ehci_data_entry_single(MX6SL, 1, HS1), + imx_mxc_ehci_data_entry_single(MX6SL, 2, HS2), + imx_mxc_ehci_data_entry_single(MX6SL, 3, HS3), +}; +#endif /* ifdef CONFIG_SOC_IMX6Q */ + +struct platform_device *__init imx_add_mxc_ehci( + const struct imx_mxc_ehci_data *data, + const struct mxc_usbh_platform_data *pdata) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + SZ_512 - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + return imx_add_platform_device_dmamask("mxc-ehci", data->id, + res, ARRAY_SIZE(res), + pdata, sizeof(*pdata), DMA_BIT_MASK(32)); +} +EXPORT_SYMBOL(imx_add_mxc_ehci); + +/* FSL internal non-upstream code */ +struct platform_device *__init imx_add_fsl_ehci( + const struct imx_mxc_ehci_data *data, + const struct fsl_usb2_platform_data *pdata) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + SZ_512 - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + int ret = -ENOMEM; + const char *name = "fsl-ehci"; + int id = data->id; + unsigned int num_resources = ARRAY_SIZE(res); + size_t size_data = sizeof(*pdata); + u64 dmamask = DMA_BIT_MASK(32); + struct platform_device *pdev; + + pdev = platform_device_alloc(name, id); + if (!pdev) + goto err; + + if (dmamask) { + /* + * This memory isn't freed when the device is put, + * I don't have a nice idea for that though. Conceptually + * dma_mask in struct device should not be a pointer. + * See http://thread.gmane.org/gmane.linux.kernel.pci/9081 + */ + pdev->dev.dma_mask = + kmalloc(sizeof(*pdev->dev.dma_mask), GFP_KERNEL); + if (!pdev->dev.dma_mask) + /* ret is still -ENOMEM; */ + goto err; + + *pdev->dev.dma_mask = dmamask; + pdev->dev.coherent_dma_mask = dmamask; + } + + ret = platform_device_add_resources(pdev, res, num_resources); + if (ret) + goto err; + + if (data) { + ret = platform_device_add_data(pdev, pdata, size_data); + if (ret) + goto err; + } + + return pdev; + +err: + if (dmamask) + kfree(pdev->dev.dma_mask); + platform_device_put(pdev); + return ERR_PTR(ret); + +} +EXPORT_SYMBOL(imx_add_fsl_ehci); diff --git a/arch/arm/plat-mxc/devices/platform-mxc-hdmi-core.c b/arch/arm/plat-mxc/devices/platform-mxc-hdmi-core.c new file mode 100644 index 00000000..2c9a32a9 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-mxc-hdmi-core.c @@ -0,0 +1,53 @@ +/* + * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <asm/sizes.h> +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx6_mxc_hdmi_core_data_entry_single(soc, size) \ + { \ + .iobase = soc ## _HDMI_ARB_BASE_ADDR, \ + .iosize = size, \ + } + +#ifdef CONFIG_SOC_IMX6Q +const struct imx_mxc_hdmi_core_data imx6q_mxc_hdmi_core_data __initconst = + imx6_mxc_hdmi_core_data_entry_single(MX6Q, SZ_32K + SZ_4K); +#endif + +struct platform_device *__init imx_add_mxc_hdmi_core( + const struct imx_mxc_hdmi_core_data *data, + const struct fsl_mxc_hdmi_core_platform_data *pdata) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + data->iosize - 1, + .flags = IORESOURCE_MEM, + }, + }; + + if (!fuse_dev_is_available(MXC_DEV_HDMI)) + return ERR_PTR(-ENODEV); + + return imx_add_platform_device_dmamask("mxc_hdmi_core", -1, + res, ARRAY_SIZE(res), pdata, sizeof(*pdata), DMA_BIT_MASK(32)); +} diff --git a/arch/arm/plat-mxc/devices/platform-mxc-mmc.c b/arch/arm/plat-mxc/devices/platform-mxc-mmc.c new file mode 100644 index 00000000..540d3a7d --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-mxc-mmc.c @@ -0,0 +1,73 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <linux/dma-mapping.h> +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx_mxc_mmc_data_entry_single(soc, _id, _hwid, _size) \ + { \ + .id = _id, \ + .iobase = soc ## _SDHC ## _hwid ## _BASE_ADDR, \ + .iosize = _size, \ + .irq = soc ## _INT_SDHC ## _hwid, \ + .dmareq = soc ## _DMA_REQ_SDHC ## _hwid, \ + } +#define imx_mxc_mmc_data_entry(soc, _id, _hwid, _size) \ + [_id] = imx_mxc_mmc_data_entry_single(soc, _id, _hwid, _size) + +#ifdef CONFIG_SOC_IMX21 +const struct imx_mxc_mmc_data imx21_mxc_mmc_data[] __initconst = { +#define imx21_mxc_mmc_data_entry(_id, _hwid) \ + imx_mxc_mmc_data_entry(MX21, _id, _hwid, SZ_4K) + imx21_mxc_mmc_data_entry(0, 1), + imx21_mxc_mmc_data_entry(1, 2), +}; +#endif /* ifdef CONFIG_SOC_IMX21 */ + +#ifdef CONFIG_SOC_IMX27 +const struct imx_mxc_mmc_data imx27_mxc_mmc_data[] __initconst = { +#define imx27_mxc_mmc_data_entry(_id, _hwid) \ + imx_mxc_mmc_data_entry(MX27, _id, _hwid, SZ_4K) + imx27_mxc_mmc_data_entry(0, 1), + imx27_mxc_mmc_data_entry(1, 2), +}; +#endif /* ifdef CONFIG_SOC_IMX27 */ + +#ifdef CONFIG_SOC_IMX31 +const struct imx_mxc_mmc_data imx31_mxc_mmc_data[] __initconst = { +#define imx31_mxc_mmc_data_entry(_id, _hwid) \ + imx_mxc_mmc_data_entry(MX31, _id, _hwid, SZ_16K) + imx31_mxc_mmc_data_entry(0, 1), + imx31_mxc_mmc_data_entry(1, 2), +}; +#endif /* ifdef CONFIG_SOC_IMX31 */ + +struct platform_device *__init imx_add_mxc_mmc( + const struct imx_mxc_mmc_data *data, + const struct imxmmc_platform_data *pdata) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, { + .start = data->dmareq, + .end = data->dmareq, + .flags = IORESOURCE_DMA, + }, + }; + return imx_add_platform_device_dmamask("mxc-mmc", data->id, + res, ARRAY_SIZE(res), + pdata, sizeof(*pdata), DMA_BIT_MASK(32)); +} diff --git a/arch/arm/plat-mxc/devices/platform-mxc_gpu.c b/arch/arm/plat-mxc/devices/platform-mxc_gpu.c new file mode 100755 index 00000000..06ac1560 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-mxc_gpu.c @@ -0,0 +1,101 @@ +/* + * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <asm/sizes.h> +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx_mxc_gpu_entry_3d_2d(soc) \ + { \ + .irq_3d = soc ## _INT_GPU, \ + .irq_2d = soc ## _INT_GPU2_IRQ, \ + .iobase_3d = soc ## _GPU_BASE_ADDR, \ + .iobase_2d = soc ## _GPU2D_BASE_ADDR, \ + .gmem_base = soc ## _GPU_GMEM_BASE_ADDR, \ + .gmem_size = soc ## _GPU_GMEM_SIZE, \ + } + +#define imx_mxc_gpu_entry_2d(soc) \ + { \ + .irq_2d = soc ## _INT_GPU2_IRQ, \ + .iobase_2d = soc ## _GPU2D_BASE_ADDR, \ + } + +#ifdef CONFIG_SOC_IMX35 +const struct imx_mxc_gpu_data imx35_gpu_data __initconst = + imx_mxc_gpu_entry_2d(MX35); +#endif + +#ifdef CONFIG_SOC_IMX50 +const struct imx_mxc_gpu_data imx50_gpu_data __initconst = + imx_mxc_gpu_entry_2d(MX50); +#endif + +#ifdef CONFIG_SOC_IMX51 +const struct imx_mxc_gpu_data imx51_gpu_data __initconst = + imx_mxc_gpu_entry_3d_2d(MX51); +#endif + +#ifdef CONFIG_SOC_IMX53 +const struct imx_mxc_gpu_data imx53_gpu_data __initconst = + imx_mxc_gpu_entry_3d_2d(MX53); +#endif + +struct platform_device *__init imx_add_mxc_gpu( + const struct imx_mxc_gpu_data *data, + const struct mxc_gpu_platform_data *pdata) +{ + struct resource res[] = { + { + .start = data->irq_2d, + .end = data->irq_2d, + .name = "gpu_2d_irq", + .flags = IORESOURCE_IRQ, + }, + { + .start = data->irq_3d, + .end = data->irq_3d, + .name = "gpu_3d_irq", + .flags = IORESOURCE_IRQ, + }, + { + .start = data->iobase_2d, + .end = data->iobase_2d + SZ_4K - 1, + .name = "gpu_2d_registers", + .flags = IORESOURCE_MEM, + }, + { + .start = data->iobase_3d, + .end = data->iobase_3d + SZ_128K - 1, + .name = "gpu_3d_registers", + .flags = IORESOURCE_MEM, + }, + { + .start = data->gmem_base, + .end = data->gmem_base + data->gmem_size - 1, + .name = "gpu_graphics_mem", + .flags = IORESOURCE_MEM, + }, + }; + + return imx_add_platform_device_dmamask("mxc_gpu", 0, + res, ARRAY_SIZE(res), + pdata, sizeof(*pdata), DMA_BIT_MASK(32)); +} diff --git a/arch/arm/plat-mxc/devices/platform-mxc_hdmi.c b/arch/arm/plat-mxc/devices/platform-mxc_hdmi.c new file mode 100644 index 00000000..cdbdae49 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-mxc_hdmi.c @@ -0,0 +1,55 @@ +/* + * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <asm/sizes.h> +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx6_mxc_hdmi_data_entry_single(soc) \ + { \ + .irq = soc ## _INT_HDMI_TX, \ + } + +#ifdef CONFIG_SOC_IMX6Q +const struct imx_mxc_hdmi_data imx6q_mxc_hdmi_data __initconst = + imx6_mxc_hdmi_data_entry_single(MX6Q); +#endif + +struct platform_device *__init imx_add_mxc_hdmi( + const struct imx_mxc_hdmi_data *data, + const struct fsl_mxc_hdmi_platform_data *pdata) +{ + struct resource res[] = { + { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + + if (!fuse_dev_is_available(MXC_DEV_HDMI)) + return ERR_PTR(-ENODEV); + + imx_add_platform_device("mxc_hdmi_cec", 0, + res, ARRAY_SIZE(res), NULL, 0); + return imx_add_platform_device_dmamask("mxc_hdmi", -1, + res, ARRAY_SIZE(res), pdata, sizeof(*pdata), DMA_BIT_MASK(32)); +} + diff --git a/arch/arm/plat-mxc/devices/platform-mxc_mlb.c b/arch/arm/plat-mxc/devices/platform-mxc_mlb.c new file mode 100644 index 00000000..8925f3ee --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-mxc_mlb.c @@ -0,0 +1,76 @@ +/* + * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#ifdef CONFIG_SOC_IMX53 +struct platform_device *__init imx_add_mlb( + const struct mxc_mlb_platform_data *pdata) +{ + struct resource res[] = { + { + .start = MX53_MLB_BASE_ADDR, + .end = MX53_MLB_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = MX53_INT_MLB, + .end = MX53_INT_MLB, + .flags = IORESOURCE_IRQ, + }, + }; + return imx_add_platform_device("mxc_mlb", 0, + res, ARRAY_SIZE(res), pdata, sizeof(*pdata)); +} +#endif /* ifdef CONFIG_SOC_IMX53 */ + +#ifdef CONFIG_SOC_IMX6Q + +struct platform_device *__init imx_add_mlb( + const struct mxc_mlb_platform_data *pdata) +{ + struct resource res[] = { + { + .start = MLB_BASE_ADDR, + .end = MLB_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = MXC_INT_MLB, + .end = MXC_INT_MLB, + .flags = IORESOURCE_IRQ, + }, + { + .start = MXC_INT_MLB_AHB0, + .end = MXC_INT_MLB_AHB0, + .flags = IORESOURCE_IRQ, + }, + { + .start = MXC_INT_MLB_AHB1, + .end = MXC_INT_MLB_AHB1, + .flags = IORESOURCE_IRQ, + }, + }; + + if (!fuse_dev_is_available(MXC_DEV_MLB)) + return ERR_PTR(-ENODEV); + + return imx_add_platform_device("mxc_mlb150", 0, + res, ARRAY_SIZE(res), pdata, sizeof(*pdata)); +} +#endif diff --git a/arch/arm/plat-mxc/devices/platform-mxc_nand.c b/arch/arm/plat-mxc/devices/platform-mxc_nand.c new file mode 100644 index 00000000..1568f39f --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-mxc_nand.c @@ -0,0 +1,83 @@ +/* + * Copyright (C) 2009-2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <asm/sizes.h> +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx_mxc_nand_data_entry_single(soc, _size) \ + { \ + .iobase = soc ## _NFC_BASE_ADDR, \ + .iosize = _size, \ + .irq = soc ## _INT_NFC \ + } + +#define imx_mxc_nandv3_data_entry_single(soc, _size) \ + { \ + .id = -1, \ + .iobase = soc ## _NFC_BASE_ADDR, \ + .iosize = _size, \ + .axibase = soc ## _NFC_AXI_BASE_ADDR, \ + .irq = soc ## _INT_NFC \ + } + +#ifdef CONFIG_SOC_IMX21 +const struct imx_mxc_nand_data imx21_mxc_nand_data __initconst = + imx_mxc_nand_data_entry_single(MX21, SZ_4K); +#endif /* ifdef CONFIG_SOC_IMX21 */ + +#ifdef CONFIG_SOC_IMX25 +const struct imx_mxc_nand_data imx25_mxc_nand_data __initconst = + imx_mxc_nand_data_entry_single(MX25, SZ_8K); +#endif /* ifdef CONFIG_SOC_IMX25 */ + +#ifdef CONFIG_SOC_IMX27 +const struct imx_mxc_nand_data imx27_mxc_nand_data __initconst = + imx_mxc_nand_data_entry_single(MX27, SZ_4K); +#endif /* ifdef CONFIG_SOC_IMX27 */ + +#ifdef CONFIG_SOC_IMX31 +const struct imx_mxc_nand_data imx31_mxc_nand_data __initconst = + imx_mxc_nand_data_entry_single(MX31, SZ_4K); +#endif + +#ifdef CONFIG_SOC_IMX35 +const struct imx_mxc_nand_data imx35_mxc_nand_data __initconst = + imx_mxc_nand_data_entry_single(MX35, SZ_8K); +#endif + +#ifdef CONFIG_SOC_IMX51 +const struct imx_mxc_nand_data imx51_mxc_nand_data __initconst = + imx_mxc_nandv3_data_entry_single(MX51, SZ_16K); +#endif + +struct platform_device *__init imx_add_mxc_nand( + const struct imx_mxc_nand_data *data, + const struct mxc_nand_platform_data *pdata) +{ + /* AXI has to come first, that's how the mxc_nand driver expect it */ + struct resource res[] = { + { + .start = data->axibase, + .end = data->axibase + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->iobase, + .end = data->iobase + data->iosize - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + return imx_add_platform_device("mxc_nand", data->id, + res + !data->axibase, + ARRAY_SIZE(res) - !data->axibase, + pdata, sizeof(*pdata)); +} diff --git a/arch/arm/plat-mxc/devices/platform-mxc_pwm.c b/arch/arm/plat-mxc/devices/platform-mxc_pwm.c new file mode 100755 index 00000000..a8521b97 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-mxc_pwm.c @@ -0,0 +1,89 @@ +/* + * Copyright (C) 2009-2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx_mxc_pwm_data_entry_single(soc, _id, _hwid, _size) \ + { \ + .id = _id, \ + .iobase = soc ## _PWM ## _hwid ## _BASE_ADDR, \ + .iosize = _size, \ + .irq = soc ## _INT_PWM ## _hwid, \ + } +#define imx_mxc_pwm_data_entry(soc, _id, _hwid, _size) \ + [_id] = imx_mxc_pwm_data_entry_single(soc, _id, _hwid, _size) + +#ifdef CONFIG_SOC_IMX21 +const struct imx_mxc_pwm_data imx21_mxc_pwm_data __initconst = + imx_mxc_pwm_data_entry_single(MX21, 0, , SZ_4K); +#endif /* ifdef CONFIG_SOC_IMX21 */ + +#ifdef CONFIG_SOC_IMX25 +const struct imx_mxc_pwm_data imx25_mxc_pwm_data[] __initconst = { +#define imx25_mxc_pwm_data_entry(_id, _hwid) \ + imx_mxc_pwm_data_entry(MX25, _id, _hwid, SZ_16K) + imx25_mxc_pwm_data_entry(0, 1), + imx25_mxc_pwm_data_entry(1, 2), + imx25_mxc_pwm_data_entry(2, 3), + imx25_mxc_pwm_data_entry(3, 4), +}; +#endif /* ifdef CONFIG_SOC_IMX25 */ + +#ifdef CONFIG_SOC_IMX27 +const struct imx_mxc_pwm_data imx27_mxc_pwm_data __initconst = + imx_mxc_pwm_data_entry_single(MX27, 0, , SZ_4K); +#endif /* ifdef CONFIG_SOC_IMX27 */ + +#ifdef CONFIG_SOC_IMX51 +const struct imx_mxc_pwm_data imx51_mxc_pwm_data[] __initconst = { +#define imx51_mxc_pwm_data_entry(_id, _hwid) \ + imx_mxc_pwm_data_entry(MX51, _id, _hwid, SZ_16K) + imx51_mxc_pwm_data_entry(0, 1), + imx51_mxc_pwm_data_entry(1, 2), +}; +#endif /* ifdef CONFIG_SOC_IMX51 */ + +#ifdef CONFIG_SOC_IMX53 +const struct imx_mxc_pwm_data imx53_mxc_pwm_data[] __initconst = { +#define imx53_mxc_pwm_data_entry(_id, _hwid) \ + imx_mxc_pwm_data_entry(MX53, _id, _hwid, SZ_16K) + imx53_mxc_pwm_data_entry(0, 1), + imx53_mxc_pwm_data_entry(1, 2), +}; +#endif /* ifdef CONFIG_SOC_IMX53 */ + +#ifdef CONFIG_SOC_IMX6Q +const struct imx_mxc_pwm_data imx6q_mxc_pwm_data[] __initconst = { +#define imx6q_mxc_pwm_data_entry(_id, _hwid) \ + imx_mxc_pwm_data_entry(MX6Q, _id, _hwid, SZ_16K) + imx6q_mxc_pwm_data_entry(0, 1), + imx6q_mxc_pwm_data_entry(1, 2), + imx6q_mxc_pwm_data_entry(2, 3), + imx6q_mxc_pwm_data_entry(3, 4), +}; +#endif /* ifdef CONFIG_SOC_IMX6Q */ + +struct platform_device *__init imx_add_mxc_pwm( + const struct imx_mxc_pwm_data *data) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + data->iosize - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + + return imx_add_platform_device("mxc_pwm", data->id, + res, ARRAY_SIZE(res), NULL, 0); +} diff --git a/arch/arm/plat-mxc/devices/platform-mxc_rnga.c b/arch/arm/plat-mxc/devices/platform-mxc_rnga.c new file mode 100644 index 00000000..b4b7612b --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-mxc_rnga.c @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <mach/hardware.h> +#include <mach/devices-common.h> + +struct imx_mxc_rnga_data { + resource_size_t iobase; +}; + +#define imx_mxc_rnga_data_entry_single(soc) \ + { \ + .iobase = soc ## _RNGA_BASE_ADDR, \ + } + +#ifdef CONFIG_SOC_IMX31 +static const struct imx_mxc_rnga_data imx31_mxc_rnga_data __initconst = + imx_mxc_rnga_data_entry_single(MX31); +#endif /* ifdef CONFIG_SOC_IMX31 */ + +static struct platform_device *__init imx_add_mxc_rnga( + const struct imx_mxc_rnga_data *data) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + }; + return imx_add_platform_device("mxc_rnga", -1, + res, ARRAY_SIZE(res), NULL, 0); +} + +static int __init imxXX_add_mxc_rnga(void) +{ + struct platform_device *ret; + +#if defined(CONFIG_SOC_IMX31) + if (cpu_is_mx31()) + ret = imx_add_mxc_rnga(&imx31_mxc_rnga_data); + else +#endif /* if defined(CONFIG_SOC_IMX31) */ + ret = ERR_PTR(-ENODEV); + + if (IS_ERR(ret)) + return PTR_ERR(ret); + + return 0; +} +arch_initcall(imxXX_add_mxc_rnga); diff --git a/arch/arm/plat-mxc/devices/platform-mxc_rtc.c b/arch/arm/plat-mxc/devices/platform-mxc_rtc.c new file mode 100644 index 00000000..16d0ec4d --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-mxc_rtc.c @@ -0,0 +1,40 @@ +/* + * Copyright (C) 2010-2011 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx_mxc_rtc_data_entry_single(soc) \ + { \ + .iobase = soc ## _RTC_BASE_ADDR, \ + .irq = soc ## _INT_RTC, \ + } + +#ifdef CONFIG_SOC_IMX31 +const struct imx_mxc_rtc_data imx31_mxc_rtc_data __initconst = + imx_mxc_rtc_data_entry_single(MX31); +#endif /* ifdef CONFIG_SOC_IMX31 */ + +struct platform_device *__init imx_add_mxc_rtc( + const struct imx_mxc_rtc_data *data) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + + return imx_add_platform_device("mxc_rtc", -1, + res, ARRAY_SIZE(res), NULL, 0); +} diff --git a/arch/arm/plat-mxc/devices/platform-mxc_w1.c b/arch/arm/plat-mxc/devices/platform-mxc_w1.c new file mode 100644 index 00000000..96fa5ea9 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-mxc_w1.c @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx_mxc_w1_data_entry_single(soc) \ + { \ + .iobase = soc ## _OWIRE_BASE_ADDR, \ + } + +#ifdef CONFIG_SOC_IMX21 +const struct imx_mxc_w1_data imx21_mxc_w1_data __initconst = + imx_mxc_w1_data_entry_single(MX21); +#endif /* ifdef CONFIG_SOC_IMX21 */ + +#ifdef CONFIG_SOC_IMX27 +const struct imx_mxc_w1_data imx27_mxc_w1_data __initconst = + imx_mxc_w1_data_entry_single(MX27); +#endif /* ifdef CONFIG_SOC_IMX27 */ + +#ifdef CONFIG_SOC_IMX31 +const struct imx_mxc_w1_data imx31_mxc_w1_data __initconst = + imx_mxc_w1_data_entry_single(MX31); +#endif /* ifdef CONFIG_SOC_IMX31 */ + +#ifdef CONFIG_SOC_IMX35 +const struct imx_mxc_w1_data imx35_mxc_w1_data __initconst = + imx_mxc_w1_data_entry_single(MX35); +#endif /* ifdef CONFIG_SOC_IMX35 */ + +struct platform_device *__init imx_add_mxc_w1( + const struct imx_mxc_w1_data *data) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + }; + + return imx_add_platform_device("mxc_w1", 0, + res, ARRAY_SIZE(res), NULL, 0); +} diff --git a/arch/arm/plat-mxc/devices/platform-sdhci-esdhc-imx.c b/arch/arm/plat-mxc/devices/platform-sdhci-esdhc-imx.c new file mode 100755 index 00000000..4aaaecc2 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-sdhci-esdhc-imx.c @@ -0,0 +1,120 @@ +/* + * Copyright (C) 2010 Pengutronix, Wolfram Sang <w.sang@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ + +#include <mach/hardware.h> +#include <mach/devices-common.h> +#include <mach/esdhc.h> + +#define imx_sdhci_esdhc_imx_data_entry_single(soc, _id, hwid) \ + { \ + .id = _id, \ + .iobase = soc ## _ESDHC ## hwid ## _BASE_ADDR, \ + .irq = soc ## _INT_ESDHC ## hwid, \ + } + +#define imx_sdhci_usdhc_imx_data_entry_single(soc, _id, hwid) \ + { \ + .id = _id, \ + .iobase = soc ## _USDHC ## hwid ## _BASE_ADDR, \ + .irq = soc ## _INT_USDHC ## hwid, \ + } + +#define imx_sdhci_esdhc_imx_data_entry(soc, id, hwid) \ + [id] = imx_sdhci_esdhc_imx_data_entry_single(soc, id, hwid) + +#define imx_sdhci_usdhc_imx_data_entry(soc, id, hwid) \ + [id] = imx_sdhci_usdhc_imx_data_entry_single(soc, id, hwid) + +#ifdef CONFIG_SOC_IMX25 +const struct imx_sdhci_esdhc_imx_data +imx25_sdhci_esdhc_imx_data[] __initconst = { +#define imx25_sdhci_esdhc_imx_data_entry(_id, _hwid) \ + imx_sdhci_esdhc_imx_data_entry(MX25, _id, _hwid) + imx25_sdhci_esdhc_imx_data_entry(0, 1), + imx25_sdhci_esdhc_imx_data_entry(1, 2), +}; +#endif /* ifdef CONFIG_SOC_IMX25 */ + +#ifdef CONFIG_SOC_IMX35 +const struct imx_sdhci_esdhc_imx_data +imx35_sdhci_esdhc_imx_data[] __initconst = { +#define imx35_sdhci_esdhc_imx_data_entry(_id, _hwid) \ + imx_sdhci_esdhc_imx_data_entry(MX35, _id, _hwid) + imx35_sdhci_esdhc_imx_data_entry(0, 1), + imx35_sdhci_esdhc_imx_data_entry(1, 2), + imx35_sdhci_esdhc_imx_data_entry(2, 3), +}; +#endif /* ifdef CONFIG_SOC_IMX35 */ + +#ifdef CONFIG_SOC_IMX50 +const struct imx_sdhci_esdhc_imx_data +imx50_sdhci_esdhc_imx_data[] __initconst = { +#define imx50_sdhci_esdhc_imx_data_entry(_id, _hwid) \ + imx_sdhci_esdhc_imx_data_entry(MX50, _id, _hwid) + imx50_sdhci_esdhc_imx_data_entry(0, 1), + imx50_sdhci_esdhc_imx_data_entry(1, 2), + imx50_sdhci_esdhc_imx_data_entry(2, 3), + imx50_sdhci_esdhc_imx_data_entry(3, 4), +}; +#endif /* ifdef CONFIG_SOC_IMX50 */ + +#ifdef CONFIG_SOC_IMX51 +const struct imx_sdhci_esdhc_imx_data +imx51_sdhci_esdhc_imx_data[] __initconst = { +#define imx51_sdhci_esdhc_imx_data_entry(_id, _hwid) \ + imx_sdhci_esdhc_imx_data_entry(MX51, _id, _hwid) + imx51_sdhci_esdhc_imx_data_entry(0, 1), + imx51_sdhci_esdhc_imx_data_entry(1, 2), + imx51_sdhci_esdhc_imx_data_entry(2, 3), + imx51_sdhci_esdhc_imx_data_entry(3, 4), +}; +#endif /* ifdef CONFIG_SOC_IMX51 */ + +#ifdef CONFIG_SOC_IMX53 +const struct imx_sdhci_esdhc_imx_data +imx53_sdhci_esdhc_imx_data[] __initconst = { +#define imx53_sdhci_esdhc_imx_data_entry(_id, _hwid) \ + imx_sdhci_esdhc_imx_data_entry(MX53, _id, _hwid) + imx53_sdhci_esdhc_imx_data_entry(0, 1), + imx53_sdhci_esdhc_imx_data_entry(1, 2), + imx53_sdhci_esdhc_imx_data_entry(2, 3), + imx53_sdhci_esdhc_imx_data_entry(3, 4), +}; +#endif /* ifdef CONFIG_SOC_IMX53 */ + +#ifdef CONFIG_SOC_IMX6Q +const struct imx_sdhci_esdhc_imx_data +imx6q_sdhci_usdhc_imx_data[] __initconst = { +#define imx6q_sdhci_usdhc_imx_data_entry(_id, _hwid) \ + imx_sdhci_usdhc_imx_data_entry(MX6Q, _id, _hwid) + imx6q_sdhci_usdhc_imx_data_entry(0, 1), + imx6q_sdhci_usdhc_imx_data_entry(1, 2), + imx6q_sdhci_usdhc_imx_data_entry(2, 3), + imx6q_sdhci_usdhc_imx_data_entry(3, 4), +}; +#endif /* ifdef CONFIG_SOC_IMX6Q */ + +struct platform_device *__init imx_add_sdhci_esdhc_imx( + const struct imx_sdhci_esdhc_imx_data *data, + const struct esdhc_platform_data *pdata) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + + return imx_add_platform_device_dmamask("sdhci-esdhc-imx", data->id, res, + ARRAY_SIZE(res), pdata, sizeof(*pdata), DMA_BIT_MASK(32)); +} diff --git a/arch/arm/plat-mxc/devices/platform-spi_imx.c b/arch/arm/plat-mxc/devices/platform-spi_imx.c new file mode 100644 index 00000000..bbe66e1a --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-spi_imx.c @@ -0,0 +1,144 @@ +/* + * Copyright (C) 2009-2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx_spi_imx_data_entry_single(soc, type, _devid, _id, hwid, _size) \ + { \ + .devid = _devid, \ + .id = _id, \ + .iobase = soc ## _ ## type ## hwid ## _BASE_ADDR, \ + .iosize = _size, \ + .irq = soc ## _INT_ ## type ## hwid, \ + } + +#define imx_spi_imx_data_entry(soc, type, devid, id, hwid, size) \ + [id] = imx_spi_imx_data_entry_single(soc, type, devid, id, hwid, size) + +#ifdef CONFIG_SOC_IMX1 +const struct imx_spi_imx_data imx1_cspi_data[] __initconst = { +#define imx1_cspi_data_entry(_id, _hwid) \ + imx_spi_imx_data_entry(MX1, CSPI, "imx1-cspi", _id, _hwid, SZ_4K) + imx1_cspi_data_entry(0, 1), + imx1_cspi_data_entry(1, 2), +}; +#endif + +#ifdef CONFIG_SOC_IMX21 +const struct imx_spi_imx_data imx21_cspi_data[] __initconst = { +#define imx21_cspi_data_entry(_id, _hwid) \ + imx_spi_imx_data_entry(MX21, CSPI, "imx21-cspi", _id, _hwid, SZ_4K) + imx21_cspi_data_entry(0, 1), + imx21_cspi_data_entry(1, 2), +}; +#endif + +#ifdef CONFIG_SOC_IMX25 +const struct imx_spi_imx_data imx25_cspi_data[] __initconst = { +#define imx25_cspi_data_entry(_id, _hwid) \ + imx_spi_imx_data_entry(MX25, CSPI, "imx25-cspi", _id, _hwid, SZ_16K) + imx25_cspi_data_entry(0, 1), + imx25_cspi_data_entry(1, 2), + imx25_cspi_data_entry(2, 3), +}; +#endif /* ifdef CONFIG_SOC_IMX25 */ + +#ifdef CONFIG_SOC_IMX27 +const struct imx_spi_imx_data imx27_cspi_data[] __initconst = { +#define imx27_cspi_data_entry(_id, _hwid) \ + imx_spi_imx_data_entry(MX27, CSPI, "imx27-cspi", _id, _hwid, SZ_4K) + imx27_cspi_data_entry(0, 1), + imx27_cspi_data_entry(1, 2), + imx27_cspi_data_entry(2, 3), +}; +#endif /* ifdef CONFIG_SOC_IMX27 */ + +#ifdef CONFIG_SOC_IMX31 +const struct imx_spi_imx_data imx31_cspi_data[] __initconst = { +#define imx31_cspi_data_entry(_id, _hwid) \ + imx_spi_imx_data_entry(MX31, CSPI, "imx31-cspi", _id, _hwid, SZ_4K) + imx31_cspi_data_entry(0, 1), + imx31_cspi_data_entry(1, 2), + imx31_cspi_data_entry(2, 3), +}; +#endif /* ifdef CONFIG_SOC_IMX31 */ + +#ifdef CONFIG_SOC_IMX35 +const struct imx_spi_imx_data imx35_cspi_data[] __initconst = { +#define imx35_cspi_data_entry(_id, _hwid) \ + imx_spi_imx_data_entry(MX35, CSPI, "imx35-cspi", _id, _hwid, SZ_4K) + imx35_cspi_data_entry(0, 1), + imx35_cspi_data_entry(1, 2), +}; +#endif /* ifdef CONFIG_SOC_IMX35 */ + +#ifdef CONFIG_SOC_IMX50 +const struct imx_spi_imx_data imx50_cspi_data[] __initconst = { +#define imx50_cspi_data_entry(_id, _hwid) \ + imx_spi_imx_data_entry(MX50, CSPI, "imx50-cspi", _id, _hwid, SZ_4K) + imx50_cspi_data_entry(1, 1), + imx50_cspi_data_entry(2, 2), + imx50_cspi_data_entry(3, 3), +}; +#endif /* ifdef CONFIG_SOC_IMX50 */ + +#ifdef CONFIG_SOC_IMX51 +const struct imx_spi_imx_data imx51_cspi_data __initconst = + imx_spi_imx_data_entry_single(MX51, CSPI, "imx51-cspi", 2, , SZ_4K); + +const struct imx_spi_imx_data imx51_ecspi_data[] __initconst = { +#define imx51_ecspi_data_entry(_id, _hwid) \ + imx_spi_imx_data_entry(MX51, ECSPI, "imx51-ecspi", _id, _hwid, SZ_4K) + imx51_ecspi_data_entry(0, 1), + imx51_ecspi_data_entry(1, 2), +}; +#endif /* ifdef CONFIG_SOC_IMX51 */ + +#ifdef CONFIG_SOC_IMX53 +const struct imx_spi_imx_data imx53_cspi_data __initconst = + imx_spi_imx_data_entry_single(MX53, CSPI, "imx53-cspi", 0, , SZ_4K); + +const struct imx_spi_imx_data imx53_ecspi_data[] __initconst = { +#define imx53_ecspi_data_entry(_id, _hwid) \ + imx_spi_imx_data_entry(MX53, ECSPI, "imx53-ecspi", _id, _hwid, SZ_4K) + imx53_ecspi_data_entry(0, 1), + imx53_ecspi_data_entry(1, 2), +}; +#endif /* ifdef CONFIG_SOC_IMX53 */ + +#ifdef CONFIG_SOC_IMX6Q +const struct imx_spi_imx_data imx6q_ecspi_data[] __initconst = { +#define imx6q_ecspi_data_entry(_id, _hwid) \ + imx_spi_imx_data_entry(MX6Q, ECSPI, "imx6q-ecspi", _id, _hwid, SZ_4K) + imx6q_ecspi_data_entry(0, 1), + imx6q_ecspi_data_entry(1, 2), + imx6q_ecspi_data_entry(2, 3), + imx6q_ecspi_data_entry(3, 4), + imx6q_ecspi_data_entry(4, 5), +}; +#endif /* ifdef CONFIG_SOC_IMX6Q */ + +struct platform_device *__init imx_add_spi_imx( + const struct imx_spi_imx_data *data, + const struct spi_imx_master *pdata) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + data->iosize - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + return imx_add_platform_device(data->devid, data->id, + res, ARRAY_SIZE(res), pdata, sizeof(*pdata)); +} diff --git a/arch/arm/plat-mxc/devices/platform-viv_gpu.c b/arch/arm/plat-mxc/devices/platform-viv_gpu.c new file mode 100644 index 00000000..52c9b082 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-viv_gpu.c @@ -0,0 +1,127 @@ +/* + * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#ifdef CONFIG_ARCH_MX6 +#ifdef CONFIG_SOC_IMX6SL +const struct imx_viv_gpu_data imx6_gpu_data __initconst = { + .phys_baseaddr = MX6SL_MMDC0_ARB_BASE_ADDR, + .iobase_3d = 0, + .irq_3d = -1, + .iobase_2d = MX6SL_GPU_2D_ARB_BASE_ADDR, + .irq_2d = MXC_INT_GPU2D_IRQ, + .iobase_vg = OPENVG_ARB_BASE_ADDR, + .irq_vg = MXC_INT_OPENVG_XAQ2, +}; +#else +const struct imx_viv_gpu_data imx6_gpu_data __initconst = { + .phys_baseaddr = 0, + .iobase_3d = GPU_3D_ARB_BASE_ADDR, + .irq_3d = MXC_INT_GPU3D_IRQ, + .iobase_2d = GPU_2D_ARB_BASE_ADDR, + .irq_2d = MXC_INT_GPU2D_IRQ, + .iobase_vg = OPENVG_ARB_BASE_ADDR, + .irq_vg = MXC_INT_OPENVG_XAQ2, +}; +#endif +#endif + +struct platform_device *__init imx_add_viv_gpu( + const struct imx_viv_gpu_data *data, + const struct viv_gpu_platform_data *pdata) +{ + u32 res_count = 0; + struct resource res[] = { + { + .name = "phys_baseaddr", + .start = data->phys_baseaddr, + .end = data->phys_baseaddr, + .flags = IORESOURCE_MEM, + }, { + + .name = "iobase_3d", + .start = data->iobase_3d, + .end = data->iobase_3d + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, { + .name = "irq_3d", + .start = data->irq_3d, + .end = data->irq_3d, + .flags = IORESOURCE_IRQ, + }, { + .name = "iobase_2d", + .start = data->iobase_2d, + .end = data->iobase_2d + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, { + .name = "irq_2d", + .start = data->irq_2d, + .end = data->irq_2d, + .flags = IORESOURCE_IRQ, + }, { + .name = "iobase_vg", + .start = data->iobase_vg, + .end = data->iobase_vg + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, { + .name = "irq_vg", + .start = data->irq_vg, + .end = data->irq_vg, + .flags = IORESOURCE_IRQ, + }, + }; + + res_count = ARRAY_SIZE(res); + BUG_ON(!res_count); + + if (!fuse_dev_is_available(MXC_DEV_3D)) { + res[1].start = 0; + res[1].end = 0; + res[2].start = -1; + res[2].end = -1; + } + + if (!fuse_dev_is_available(MXC_DEV_2D)) { + res[3].start = 0; + res[3].end = 0; + res[4].start = -1; + res[4].end = -1; + } + + if (!fuse_dev_is_available(MXC_DEV_OVG)) { + res[5].start = 0; + res[5].end = 0; + res[6].start = -1; + res[6].end = -1; + } + + /* None GPU core exists */ + if ((res[2].start == -1) && + (res[4].start == -1) && + (res[6].start == -1)) + return ERR_PTR(-ENODEV); + + return imx_add_platform_device_dmamask("galcore", 0, + res, res_count, + pdata, sizeof(*pdata), + DMA_BIT_MASK(32)); +} diff --git a/arch/arm/plat-mxc/dvfs_core.c b/arch/arm/plat-mxc/dvfs_core.c new file mode 100755 index 00000000..f2760dd0 --- /dev/null +++ b/arch/arm/plat-mxc/dvfs_core.c @@ -0,0 +1,1132 @@ +/* + * Copyright 2008-2012 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file dvfs_core.c + * + * @brief A simplied driver for the Freescale Semiconductor MXC DVFS module. + * + * Upon initialization, the DVFS driver initializes the DVFS hardware + * sets up driver nodes attaches to the DVFS interrupt and initializes internal + * data structures. When the DVFS interrupt occurs the driver checks the cause + * of the interrupt (lower frequency, increase frequency or emergency) and + * changes the CPU voltage according to translation table that is loaded into + * the driver. + * + * @ingroup PM + */ + +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/fs.h> +#include <linux/interrupt.h> +#include <linux/jiffies.h> +#include <linux/device.h> +#include <linux/sysdev.h> +#include <linux/delay.h> +#include <linux/clk.h> +#include <linux/regulator/consumer.h> +#include <linux/input.h> +#include <linux/platform_device.h> +#if defined(CONFIG_CPU_FREQ) +#include <linux/cpufreq.h> +#endif +#include <asm/cpu.h> + +#include <mach/hardware.h> +#include <mach/mxc_dvfs.h> + +#define MXC_DVFSTHRS_UPTHR_MASK 0x0FC00000 +#define MXC_DVFSTHRS_UPTHR_OFFSET 22 +#define MXC_DVFSTHRS_DNTHR_MASK 0x003F0000 +#define MXC_DVFSTHRS_DNTHR_OFFSET 16 +#define MXC_DVFSTHRS_PNCTHR_MASK 0x0000003F +#define MXC_DVFSTHRS_PNCTHR_OFFSET 0 + +#define MXC_DVFSCOUN_DNCNT_MASK 0x00FF0000 +#define MXC_DVFSCOUN_DNCNT_OFFSET 16 +#define MXC_DVFSCOUN_UPCNT_MASK 0x000000FF +#define MXC_DVFSCOUN_UPCNT_OFFSET 0 + +#define MXC_DVFSEMAC_EMAC_MASK 0x000001FF +#define MXC_DVFSEMAC_EMAC_OFFSET 0 + +#define MXC_DVFSCNTR_DVFEV 0x10000000 +#define MXC_DVFSCNTR_LBMI 0x08000000 +#define MXC_DVFSCNTR_LBFL 0x06000000 +#define MXC_DVFSCNTR_DVFIS 0x01000000 +#define MXC_DVFSCNTR_FSVAIM 0x00400000 +#define MXC_DVFSCNTR_FSVAI_MASK 0x00300000 +#define MXC_DVFSCNTR_FSVAI_OFFSET 20 +#define MXC_DVFSCNTR_WFIM 0x00080000 +#define MXC_DVFSCNTR_WFIM_OFFSET 19 +#define MXC_DVFSCNTR_MAXF_MASK 0x00040000 +#define MXC_DVFSCNTR_MAXF_OFFSET 18 +#define MXC_DVFSCNTR_MINF_MASK 0x00020000 +#define MXC_DVFSCNTR_MINF_OFFSET 17 +#define MXC_DVFSCNTR_LTBRSR_MASK 0x00000018 +#define MXC_DVFSCNTR_LTBRSR_OFFSET 3 +#define MXC_DVFSCNTR_DVFEN 0x00000001 + +#define CCM_CDCR_SW_DVFS_EN 0x20 +#define CCM_CDCR_ARM_FREQ_SHIFT_DIVIDER 0x4 +#define CCM_CDHIPR_ARM_PODF_BUSY 0x10000 + +int cpufreq_trig_needed; +int dvfs_core_is_active; +static struct mxc_dvfs_platform_data *dvfs_data; +static struct device *dvfs_dev; +static struct cpu_op *cpu_op_tbl; +static int dvfs_core_resume; +static int curr_op; +static int old_op; +static int dvfs_core_op; +static int dvfs_config_setpoint; + +static int maxf; +static int minf; + +extern void setup_pll(void); +extern struct regulator *cpu_regulator; + +struct timeval core_prev_intr; + +void dump_dvfs_core_regs(void); +void stop_dvfs(void); +struct dvfs_op *(*get_dvfs_core_op)(int *op); + +static struct delayed_work dvfs_core_handler; + +/* + * Clock structures + */ +static struct clk *pll1_sw_clk; +static struct clk *cpu_clk; +static struct clk *dvfs_clk; + +static int cpu_op_nr; +extern struct cpu_op *(*get_cpu_op)(int *op); + +static inline unsigned long dvfs_cpu_jiffies(unsigned long old, u_int div, u_int mult) +{ +#if BITS_PER_LONG == 32 + + u64 result = ((u64) old) * ((u64) mult); + do_div(result, div); + return (unsigned long) result; + +#elif BITS_PER_LONG == 64 + + unsigned long result = old * ((u64) mult); + result /= div; + return result; + +#endif +} + +enum { + FSVAI_FREQ_NOCHANGE = 0x0, + FSVAI_FREQ_INCREASE, + FSVAI_FREQ_DECREASE, + FSVAI_FREQ_EMERG, +}; + +/* + * Load tracking buffer source: 1 for ld_add; 0 for pre_ld_add; 2 for after EMA + */ +#define DVFS_LTBRSR (2 << MXC_DVFSCNTR_LTBRSR_OFFSET) + +static struct dvfs_op *dvfs_core_setpoint; +extern int low_bus_freq_mode; +extern int high_bus_freq_mode; +extern int set_low_bus_freq(void); +extern int set_high_bus_freq(int high_bus_speed); +extern int low_freq_bus_used(void); +extern struct mutex bus_freq_mutex; + +DEFINE_SPINLOCK(mxc_dvfs_core_lock); + +static void dvfs_load_config(int set_point) +{ + u32 reg; + reg = 0; + + reg |= dvfs_core_setpoint[set_point].upthr << MXC_DVFSTHRS_UPTHR_OFFSET; + reg |= dvfs_core_setpoint[set_point].downthr << + MXC_DVFSTHRS_DNTHR_OFFSET; + reg |= dvfs_core_setpoint[set_point].panicthr; + __raw_writel(reg, dvfs_data->membase + MXC_DVFSCORE_THRS); + + reg = 0; + reg |= dvfs_core_setpoint[set_point].downcnt << + MXC_DVFSCOUN_DNCNT_OFFSET; + reg |= dvfs_core_setpoint[set_point].upcnt << MXC_DVFSCOUN_UPCNT_OFFSET; + __raw_writel(reg, dvfs_data->membase + MXC_DVFSCORE_COUN); + + /* Set EMAC value */ + reg = __raw_readl(dvfs_data->membase + MXC_DVFSCORE_EMAC); + reg &= ~MXC_DVFSEMAC_EMAC_MASK; + reg |= dvfs_core_setpoint[set_point].emac << MXC_DVFSEMAC_EMAC_OFFSET; + __raw_writel(reg, dvfs_data->membase + MXC_DVFSCORE_EMAC); + + dvfs_config_setpoint = set_point; +} + +static int mx5_set_cpu_freq(int op) +{ + int arm_podf; + int podf; + int vinc = 0; + int ret = 0; + int org_cpu_rate; + unsigned long rate = 0; + int gp_volt = 0; + u32 reg; + u32 reg1; + u32 en_sw_dvfs = 0; + unsigned long flags; + + if (cpu_op_tbl[op].pll_rate != cpu_op_tbl[old_op].pll_rate) { + org_cpu_rate = clk_get_rate(cpu_clk); + rate = cpu_op_tbl[op].cpu_rate; + + if (org_cpu_rate == rate) + return ret; + + gp_volt = cpu_op_tbl[op].cpu_voltage; + if (gp_volt == 0) + return ret; + + /*Set the voltage for the GP domain. */ + if ((!IS_ERR(cpu_regulator)) && (rate > org_cpu_rate)) { + ret = regulator_set_voltage(cpu_regulator, gp_volt, + gp_volt); + if (ret < 0) { + printk(KERN_DEBUG "COULD NOT SET GP VOLTAGE\n"); + return ret; + } + udelay(dvfs_data->delay_time); + } + spin_lock_irqsave(&mxc_dvfs_core_lock, flags); + /* PLL_RELOCK, set ARM_FREQ_SHIFT_DIVIDER */ + reg = __raw_readl(ccm_base + dvfs_data->ccm_cdcr_offset); + /* Check if software_dvfs_en bit set */ + if ((reg & CCM_CDCR_SW_DVFS_EN) != 0) + en_sw_dvfs = CCM_CDCR_SW_DVFS_EN; + else + en_sw_dvfs = 0x0; + reg &= ~(CCM_CDCR_SW_DVFS_EN); + reg &= 0xFFFFFFFB; + __raw_writel(reg, ccm_base + dvfs_data->ccm_cdcr_offset); + + setup_pll(); + /* START the GPC main control FSM */ + /* set VINC */ + reg = __raw_readl(gpc_base + dvfs_data->gpc_vcr_offset); + reg &= ~(MXC_GPCVCR_VINC_MASK | MXC_GPCVCR_VCNTU_MASK | + MXC_GPCVCR_VCNT_MASK); + + if (rate > org_cpu_rate) + reg |= 1 << MXC_GPCVCR_VINC_OFFSET; + + reg |= (1 << MXC_GPCVCR_VCNTU_OFFSET) | + (1 << MXC_GPCVCR_VCNT_OFFSET); + __raw_writel(reg, gpc_base + dvfs_data->gpc_vcr_offset); + + reg = __raw_readl(gpc_base + dvfs_data->gpc_cntr_offset); + reg &= ~(MXC_GPCCNTR_ADU_MASK | MXC_GPCCNTR_FUPD_MASK); + reg |= MXC_GPCCNTR_FUPD; + reg |= MXC_GPCCNTR_ADU; + __raw_writel(reg, gpc_base + dvfs_data->gpc_cntr_offset); + + reg |= MXC_GPCCNTR_STRT; + __raw_writel(reg, gpc_base + dvfs_data->gpc_cntr_offset); + while (__raw_readl(gpc_base + dvfs_data->gpc_cntr_offset) + & 0x4000) + udelay(10); + spin_unlock_irqrestore(&mxc_dvfs_core_lock, flags); + + if ((!IS_ERR(cpu_regulator)) && (rate < org_cpu_rate)) { + ret = regulator_set_voltage(cpu_regulator, gp_volt, + gp_volt); + if (ret < 0) { + printk(KERN_DEBUG + "COULD NOT SET GP VOLTAGE!!!!\n"); + return ret; + } + udelay(dvfs_data->delay_time); + } + /* set software_dvfs_en bit back to original setting*/ + reg = __raw_readl(ccm_base + dvfs_data->ccm_cdcr_offset); + reg &= ~(CCM_CDCR_SW_DVFS_EN); + reg |= en_sw_dvfs; + clk_set_rate(cpu_clk, rate); + } else { + podf = cpu_op_tbl[op].cpu_podf; + gp_volt = cpu_op_tbl[op].cpu_voltage; + + /* Change arm_podf only */ + /* set ARM_FREQ_SHIFT_DIVIDER */ + reg = __raw_readl(ccm_base + dvfs_data->ccm_cdcr_offset); + + /* Check if software_dvfs_en bit set */ + if ((reg & CCM_CDCR_SW_DVFS_EN) != 0) + en_sw_dvfs = CCM_CDCR_SW_DVFS_EN; + else + en_sw_dvfs = 0x0; + + reg &= ~(CCM_CDCR_SW_DVFS_EN | CCM_CDCR_ARM_FREQ_SHIFT_DIVIDER); + reg |= CCM_CDCR_ARM_FREQ_SHIFT_DIVIDER; + __raw_writel(reg, ccm_base + dvfs_data->ccm_cdcr_offset); + + /* Get ARM_PODF */ + reg = __raw_readl(ccm_base + dvfs_data->ccm_cacrr_offset); + arm_podf = reg & 0x07; + if (podf == arm_podf) { + printk(KERN_DEBUG + "No need to change freq and voltage!!!!\n"); + return 0; + } + /* Check if FSVAI indicate freq up */ + if ((!IS_ERR(cpu_regulator)) && (podf < arm_podf)) { + ret = regulator_set_voltage(cpu_regulator, gp_volt, + gp_volt); + if (ret < 0) { + printk(KERN_DEBUG + "COULD NOT SET GP VOLTAGE!!!!\n"); + return 0; + } + udelay(dvfs_data->delay_time); + vinc = 1; + } else { + vinc = 0; + } + + arm_podf = podf; + /* Set ARM_PODF */ + reg &= 0xFFFFFFF8; + reg |= arm_podf; + spin_lock_irqsave(&mxc_dvfs_core_lock, flags); + + reg1 = __raw_readl(ccm_base + dvfs_data->ccm_cdhipr_offset); + while (1) { + if ((reg1 & CCM_CDHIPR_ARM_PODF_BUSY) == 0) { + __raw_writel(reg, + ccm_base + dvfs_data->ccm_cacrr_offset); + break; + } else { + reg1 = __raw_readl( + ccm_base + dvfs_data->ccm_cdhipr_offset); + printk(KERN_DEBUG "ARM_PODF still in busy!!!!\n"); + } + } + /* set VINC */ + reg = __raw_readl(gpc_base + dvfs_data->gpc_vcr_offset); + reg &= + ~(MXC_GPCVCR_VINC_MASK | MXC_GPCVCR_VCNTU_MASK | + MXC_GPCVCR_VCNT_MASK); + reg |= (1 << MXC_GPCVCR_VCNTU_OFFSET) | + (100 << MXC_GPCVCR_VCNT_OFFSET) | + (vinc << MXC_GPCVCR_VINC_OFFSET); + __raw_writel(reg, gpc_base + dvfs_data->gpc_vcr_offset); + + reg = __raw_readl(gpc_base + dvfs_data->gpc_cntr_offset); + reg &= (~(MXC_GPCCNTR_ADU | MXC_GPCCNTR_FUPD + | MXC_GPCCNTR_STRT)); + __raw_writel(reg, gpc_base + dvfs_data->gpc_cntr_offset); + reg = __raw_readl(gpc_base + dvfs_data->gpc_cntr_offset); + reg |= MXC_GPCCNTR_ADU | MXC_GPCCNTR_FUPD; + __raw_writel(reg, gpc_base + dvfs_data->gpc_cntr_offset); + reg = __raw_readl(gpc_base + dvfs_data->gpc_cntr_offset); + reg |= MXC_GPCCNTR_STRT; + __raw_writel(reg, gpc_base + dvfs_data->gpc_cntr_offset); + + /* Wait for arm podf Enable */ + while ((__raw_readl(gpc_base + dvfs_data->gpc_cntr_offset) & + MXC_GPCCNTR_STRT) == MXC_GPCCNTR_STRT) { + printk(KERN_DEBUG "Waiting arm_podf enabled!\n"); + udelay(10); + } + spin_unlock_irqrestore(&mxc_dvfs_core_lock, flags); + + if ((!IS_ERR(cpu_regulator)) && (vinc == 0)) { + ret = regulator_set_voltage(cpu_regulator, gp_volt, + gp_volt); + if (ret < 0) { + printk(KERN_DEBUG + "COULD NOT SET GP VOLTAGE\n!!!"); + return ret; + } + udelay(dvfs_data->delay_time); + } + + /* Clear the ARM_FREQ_SHIFT_DIVIDER and */ + /* set software_dvfs_en bit back to original setting*/ + reg = __raw_readl(ccm_base + dvfs_data->ccm_cdcr_offset); + reg &= ~(CCM_CDCR_SW_DVFS_EN | CCM_CDCR_ARM_FREQ_SHIFT_DIVIDER); + reg |= en_sw_dvfs; + __raw_writel(reg, ccm_base + dvfs_data->ccm_cdcr_offset); + } + return ret; +} + +static int mx6_set_cpu_freq(int op) +{ + int ret = 0; + int org_cpu_rate; + unsigned long rate = 0; + int gp_volt = cpu_op_tbl[op].cpu_voltage; + + org_cpu_rate = clk_get_rate(cpu_clk); + rate = cpu_op_tbl[op].cpu_rate; + + if (rate == org_cpu_rate) + return ret; + + if ((!IS_ERR(cpu_regulator)) && (rate > org_cpu_rate)) { + /* Increase voltage first. */ + ret = regulator_set_voltage(cpu_regulator, gp_volt, + gp_volt); + if (ret < 0) { + printk(KERN_DEBUG "COULD NOT INCREASE GP VOLTAGE!!!!\n"); + return ret; + } + udelay(dvfs_data->delay_time); + } + ret = clk_set_rate(cpu_clk, rate); + if (ret != 0) { + printk(KERN_DEBUG "cannot set CPU clock rate\n"); + return ret; + } + + if ((!IS_ERR(cpu_regulator)) && (rate < org_cpu_rate)) { + /* Increase voltage first. */ + ret = regulator_set_voltage(cpu_regulator, gp_volt, + gp_volt); + if (ret < 0) { + printk(KERN_DEBUG "COULD NOT INCREASE GP VOLTAGE!!!!\n"); + return ret; + } + } + return ret; +} + + +static int set_cpu_freq(int op) +{ + int ret = 0; + + if (cpu_is_mx6()) + ret = mx6_set_cpu_freq(op); + else + ret = mx5_set_cpu_freq(op); + + cpufreq_trig_needed = 1; + old_op = op; + return ret; +} + +static int start_dvfs(void) +{ + u32 reg, cpu_rate; + unsigned long flags; + + if (dvfs_core_is_active) + return 0; + + spin_lock_irqsave(&mxc_dvfs_core_lock, flags); + + clk_enable(dvfs_clk); + + /* get current working point */ + cpu_rate = clk_get_rate(cpu_clk); + curr_op = cpu_op_nr - 1; + do { + if (cpu_rate <= cpu_op_tbl[curr_op].cpu_rate) + break; + } while (--curr_op >= 0); + old_op = curr_op; + + dvfs_load_config(curr_op); + + if (curr_op == 0) + maxf = 1; + else + maxf = 0; + if (curr_op == (cpu_op_nr - 1)) + minf = 1; + else + minf = 0; + + /* config reg GPC_CNTR */ + reg = __raw_readl(gpc_base + dvfs_data->gpc_cntr_offset); + + reg &= ~MXC_GPCCNTR_GPCIRQM; + /* GPCIRQ=1, select ARM IRQ */ + reg |= MXC_GPCCNTR_GPCIRQ_ARM; + /* ADU=1, select ARM domain */ + if (!cpu_is_mx6()) + reg |= MXC_GPCCNTR_ADU; + __raw_writel(reg, gpc_base + dvfs_data->gpc_cntr_offset); + + /* Set PREDIV bits */ + reg = __raw_readl(dvfs_data->membase + MXC_DVFSCORE_CNTR); + reg = (reg & ~(dvfs_data->prediv_mask)); + reg |= (dvfs_data->prediv_val) << (dvfs_data->prediv_offset); + __raw_writel(reg, dvfs_data->membase + MXC_DVFSCORE_CNTR); + + /* Enable DVFS interrupt */ + reg = __raw_readl(dvfs_data->membase + MXC_DVFSCORE_CNTR); + /* FSVAIM=0 */ + reg = (reg & ~MXC_DVFSCNTR_FSVAIM); + + /* Set MAXF, MINF */ + reg = (reg & ~(MXC_DVFSCNTR_MAXF_MASK + | MXC_DVFSCNTR_MINF_MASK)); + reg |= 1 << MXC_DVFSCNTR_MAXF_OFFSET; + + /* Select ARM domain */ + reg |= MXC_DVFSCNTR_DVFIS; + /* Enable DVFS frequency adjustment interrupt */ + reg = (reg & ~MXC_DVFSCNTR_FSVAIM); + /* Set load tracking buffer register source */ + reg = (reg & ~MXC_DVFSCNTR_LTBRSR_MASK); + reg |= DVFS_LTBRSR; + /* Set DIV3CK */ + reg = (reg & ~(dvfs_data->div3ck_mask)); + reg |= (dvfs_data->div3ck_val) << (dvfs_data->div3ck_offset); + __raw_writel(reg, dvfs_data->membase + MXC_DVFSCORE_CNTR); + + /* Enable DVFS */ + if (cpu_is_mx6()) { + unsigned long cpu_wfi = 0; + int num_cpus = num_possible_cpus(); + reg = __raw_readl(dvfs_data->membase + MXC_DVFSCORE_EMAC); + /* Need to enable DVFS tracking for each core that is active */ + do { + if (cpu_active(num_cpus)) + set_bit(num_cpus, &cpu_wfi); + } while (num_cpus--); + reg |= cpu_wfi << 9; + __raw_writel(reg, dvfs_data->membase + MXC_DVFSCORE_EMAC); + } else { + reg = __raw_readl(dvfs_data->membase + MXC_DVFSCORE_CNTR); + reg |= MXC_DVFSCNTR_DVFEN; + __raw_writel(reg, dvfs_data->membase + MXC_DVFSCORE_CNTR); + } + + dvfs_core_is_active = 1; + + spin_unlock_irqrestore(&mxc_dvfs_core_lock, flags); + + printk(KERN_DEBUG "DVFS is started\n"); + return 0; +} + +/*! + * This function is called for module initialization. + * It sets up the DVFS hardware. + * It sets default values for DVFS thresholds and counters. The default + * values was chosen from a set of different reasonable values. They was tested + * and the default values in the driver gave the best results. + * More work should be done to find optimal values. + * + * @return 0 if successful; non-zero otherwise. + * + */ +static int init_dvfs_controller(void) +{ + /* DVFS loading config */ + dvfs_load_config(0); + + return 0; +} + +static irqreturn_t dvfs_irq(int irq, void *dev_id) +{ + u32 reg; + + /* Check if DVFS0 (ARM) id requesting for freqency/voltage update */ + if ((__raw_readl(gpc_base + dvfs_data->gpc_cntr_offset) + & MXC_GPCCNTR_DVFS0CR) == 0) + return IRQ_NONE; + + /* Mask DVFS irq */ + reg = __raw_readl(dvfs_data->membase + MXC_DVFSCORE_CNTR); + /* FSVAIM=1 */ + reg |= MXC_DVFSCNTR_FSVAIM; + __raw_writel(reg, dvfs_data->membase + MXC_DVFSCORE_CNTR); + + /* Mask GPC1 irq */ + reg = __raw_readl(gpc_base + dvfs_data->gpc_cntr_offset); + reg |= MXC_GPCCNTR_GPCIRQM | 0x1000000; + __raw_writel(reg, gpc_base + dvfs_data->gpc_cntr_offset); + + schedule_delayed_work(&dvfs_core_handler, 0); + return IRQ_HANDLED; +} + +static void dvfs_core_work_handler(struct work_struct *work) +{ + u32 fsvai; + u32 reg; + u32 curr_cpu = 0; + int ret = 0; + int low_freq_bus_ready = 0; + int bus_incr = 0, cpu_dcr = 0; + int cpu; + + low_freq_bus_ready = low_freq_bus_used(); + + /* Check DVFS frequency adjustment interrupt status */ + reg = __raw_readl(dvfs_data->membase + MXC_DVFSCORE_CNTR); + fsvai = (reg & MXC_DVFSCNTR_FSVAI_MASK) >> MXC_DVFSCNTR_FSVAI_OFFSET; + /* Check FSVAI, FSVAI=0 is error */ + if (fsvai == FSVAI_FREQ_NOCHANGE) { + /* Do nothing. Freq change is not required */ + goto END; + } + curr_cpu = clk_get_rate(cpu_clk); + /* If FSVAI indicate freq down, + check arm-clk is not in lowest frequency*/ + if (fsvai == FSVAI_FREQ_DECREASE) { + if (curr_cpu <= cpu_op_tbl[cpu_op_nr - 1].cpu_rate) { + minf = 1; + mutex_lock(&bus_freq_mutex); + if (low_bus_freq_mode) { + mutex_unlock(&bus_freq_mutex); + goto END; + } else + mutex_unlock(&bus_freq_mutex); + } else { + /* freq down */ + curr_op++; + maxf = 0; + if (curr_op >= cpu_op_nr) { + curr_op = cpu_op_nr - 1; + goto END; + } + cpu_dcr = 1; + dvfs_load_config(curr_op); + } + } else { + if (curr_cpu == cpu_op_tbl[0].cpu_rate) { + maxf = 1; + goto END; + } else { + mutex_lock(&bus_freq_mutex); + if (!high_bus_freq_mode && + dvfs_config_setpoint == (cpu_op_nr + 1)) { + /* bump up LP freq first. */ + bus_incr = 1; + dvfs_load_config(cpu_op_nr); + } else { + /* freq up */ + curr_op = 0; + maxf = 1; + minf = 0; + dvfs_load_config(0); + } + mutex_unlock(&bus_freq_mutex); + } + } + + low_freq_bus_ready = low_freq_bus_used(); + mutex_lock(&bus_freq_mutex); + if ((curr_op == cpu_op_nr - 1) && (!low_bus_freq_mode) + && (low_freq_bus_ready) && !bus_incr) { + if (!minf) + set_cpu_freq(curr_op); + /* If dvfs_core_op is greater than cpu_op_nr, it implies + * we support LPAPM mode for this platform. + */ + if (dvfs_core_op > cpu_op_nr) { + set_low_bus_freq(); + dvfs_load_config(cpu_op_nr + 1); + } + mutex_unlock(&bus_freq_mutex); + } else { + if (!high_bus_freq_mode) { + mutex_unlock(&bus_freq_mutex); + set_high_bus_freq(1); + } else + mutex_unlock(&bus_freq_mutex); + if (!bus_incr) + ret = set_cpu_freq(curr_op); + bus_incr = 0; + } + +END: + if (cpufreq_trig_needed == 1) { + /*Fix loops-per-jiffy */ +#ifdef CONFIG_SMP + for_each_online_cpu(cpu) + per_cpu(cpu_data, cpu).loops_per_jiffy = + dvfs_cpu_jiffies(per_cpu(cpu_data, cpu).loops_per_jiffy, + curr_cpu / 1000, clk_get_rate(cpu_clk) / 1000); +#else + u32 old_loops_per_jiffy = loops_per_jiffy; + + loops_per_jiffy = + dvfs_cpu_jiffies(old_loops_per_jiffy, + curr_cpu/1000, clk_get_rate(cpu_clk) / 1000); +#endif +#if defined (CONFIG_CPU_FREQ) + /* Fix CPU frequency for CPUFREQ. */ + for (cpu = 0; cpu < num_online_cpus(); cpu++) + cpufreq_get(cpu); +#endif + cpufreq_trig_needed = 0; + } + + /* Set MAXF, MINF */ + reg = __raw_readl(dvfs_data->membase + MXC_DVFSCORE_CNTR); + reg = (reg & ~(MXC_DVFSCNTR_MAXF_MASK | MXC_DVFSCNTR_MINF_MASK)); + reg |= maxf << MXC_DVFSCNTR_MAXF_OFFSET; + reg |= minf << MXC_DVFSCNTR_MINF_OFFSET; + + /* Enable DVFS interrupt */ + /* FSVAIM=0 */ + reg = (reg & ~MXC_DVFSCNTR_FSVAIM); + reg |= FSVAI_FREQ_NOCHANGE; + /* LBFL=1 */ + reg = (reg & ~MXC_DVFSCNTR_LBFL); + reg |= MXC_DVFSCNTR_LBFL; + __raw_writel(reg, dvfs_data->membase + MXC_DVFSCORE_CNTR); + /*Unmask GPC1 IRQ */ + reg = __raw_readl(gpc_base + dvfs_data->gpc_cntr_offset); + reg &= ~MXC_GPCCNTR_GPCIRQM; + __raw_writel(reg, gpc_base + dvfs_data->gpc_cntr_offset); + +} + + +/*! + * This function disables the DVFS module. + */ +void stop_dvfs(void) +{ + u32 reg = 0; + unsigned long flags; + u32 curr_cpu; + int cpu; +#ifndef CONFIG_SMP + unsigned long old_loops_per_jiffy; +#endif + + if (dvfs_core_is_active) { + + /* Mask dvfs irq, disable DVFS */ + reg = __raw_readl(dvfs_data->membase + + MXC_DVFSCORE_CNTR); + /* FSVAIM=1 */ + reg |= MXC_DVFSCNTR_FSVAIM; + __raw_writel(reg, dvfs_data->membase + + MXC_DVFSCORE_CNTR); + + curr_op = 0; + mutex_lock(&bus_freq_mutex); + if (!high_bus_freq_mode) { + mutex_unlock(&bus_freq_mutex); + set_high_bus_freq(1); + } else + mutex_unlock(&bus_freq_mutex); + + curr_cpu = clk_get_rate(cpu_clk); + if (curr_cpu != cpu_op_tbl[curr_op].cpu_rate) { + set_cpu_freq(curr_op); + + /*Fix loops-per-jiffy */ +#ifdef CONFIG_SMP + for_each_online_cpu(cpu) + per_cpu(cpu_data, cpu).loops_per_jiffy = + dvfs_cpu_jiffies(per_cpu(cpu_data, cpu).loops_per_jiffy, + curr_cpu/1000, clk_get_rate(cpu_clk) / 1000); +#else + old_loops_per_jiffy = loops_per_jiffy; + + loops_per_jiffy = + dvfs_cpu_jiffies(old_loops_per_jiffy, + curr_cpu/1000, clk_get_rate(cpu_clk) / 1000); +#endif + +#if defined (CONFIG_CPU_FREQ) + /* Fix CPU frequency for CPUFREQ. */ + for (cpu = 0; cpu < num_online_cpus(); cpu++) + cpufreq_get(cpu); +#endif + } + spin_lock_irqsave(&mxc_dvfs_core_lock, flags); + + reg = __raw_readl(dvfs_data->membase + + MXC_DVFSCORE_CNTR); + reg = (reg & ~MXC_DVFSCNTR_DVFEN); + __raw_writel(reg, dvfs_data->membase + + MXC_DVFSCORE_CNTR); + + spin_unlock_irqrestore(&mxc_dvfs_core_lock, flags); + + dvfs_core_is_active = 0; + + clk_disable(dvfs_clk); + } + + printk(KERN_DEBUG "DVFS is stopped\n"); +} + +void dump_dvfs_core_regs() +{ + struct timeval cur; + u32 diff = 0; + if (core_prev_intr.tv_sec == 0) + do_gettimeofday(&core_prev_intr); + else { + do_gettimeofday(&cur); + diff = (cur.tv_sec - core_prev_intr.tv_sec)*1000000 + + (cur.tv_usec - core_prev_intr.tv_usec); + core_prev_intr = cur; + } + if (diff < 90000) + printk(KERN_DEBUG "diff = %d\n", diff); + + printk(KERN_INFO "THRS = 0x%08x\n", + __raw_readl(dvfs_data->membase + + MXC_DVFSCORE_THRS)); + printk(KERN_INFO "COUNT = 0x%08x\n", + __raw_readl(dvfs_data->membase + + MXC_DVFSCORE_THRS + 0x04)); + printk(KERN_INFO "SIG1 = 0x%08x\n", + __raw_readl(dvfs_data->membase + + MXC_DVFSCORE_THRS + 0x08)); + printk(KERN_INFO "SIG0 = 0x%08x\n", + __raw_readl(dvfs_data->membase + + MXC_DVFSCORE_THRS + 0x0c)); + printk(KERN_INFO "GPC0 = 0x%08x\n", + __raw_readl(dvfs_data->membase + + MXC_DVFSCORE_THRS + 0x10)); + printk(KERN_INFO "GPC1 = 0x%08x\n", + __raw_readl(dvfs_data->membase + + MXC_DVFSCORE_THRS + 0x14)); + printk(KERN_INFO "GPBT = 0x%08x\n", + __raw_readl(dvfs_data->membase + + MXC_DVFSCORE_THRS + 0x18)); + printk(KERN_INFO "EMAC = 0x%08x\n", + __raw_readl(dvfs_data->membase + + MXC_DVFSCORE_THRS + 0x1c)); + printk(KERN_INFO "CNTR = 0x%08x\n", + __raw_readl(dvfs_data->membase + + MXC_DVFSCORE_THRS + 0x20)); + printk(KERN_INFO "LTR0_0 = 0x%08x\n", + __raw_readl(dvfs_data->membase + + MXC_DVFSCORE_THRS + 0x24)); + printk(KERN_INFO "LTR0_1 = 0x%08x\n", + __raw_readl(dvfs_data->membase + + MXC_DVFSCORE_THRS + 0x28)); + printk(KERN_INFO "LTR1_0 = 0x%08x\n", + __raw_readl(dvfs_data->membase + + MXC_DVFSCORE_THRS + 0x2c)); + printk(KERN_DEBUG "LTR1_1 = 0x%08x\n", + __raw_readl(dvfs_data->membase + + MXC_DVFSCORE_THRS + 0x30)); + printk(KERN_INFO "PT0 = 0x%08x\n", + __raw_readl(dvfs_data->membase + + MXC_DVFSCORE_THRS + 0x34)); + printk(KERN_INFO "PT1 = 0x%08x\n", + __raw_readl(dvfs_data->membase + + MXC_DVFSCORE_THRS + 0x38)); + printk(KERN_INFO "PT2 = 0x%08x\n", + __raw_readl(dvfs_data->membase + + MXC_DVFSCORE_THRS + 0x3c)); + printk(KERN_INFO "PT3 = 0x%08x\n", + __raw_readl(dvfs_data->membase + + MXC_DVFSCORE_THRS + 0x40)); +} +#if 0 +static ssize_t downthreshold_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%u\n", dvfs_core_setpoint[0].downthr); +} + +static ssize_t downthreshold_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + int ret = 0; + int val; + ret = sscanf(buf, "%u", &val); + dvfs_core_setpoint[0].downthr = val; + + return size; +} + +static ssize_t downcount_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%u\n", dvfs_core_setpoint[0].downcnt); +} + +static ssize_t downcount_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + int ret = 0; + int val; + ret = sscanf(buf, "%u", &val); + dvfs_core_setpoint[0].downcnt = val; + + return size; +} +#endif + +static ssize_t dvfs_enable_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + if (dvfs_core_is_active) + return sprintf(buf, "DVFS is enabled\n"); + else + return sprintf(buf, "DVFS is disabled\n"); +} + +static ssize_t dvfs_enable_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + if (strstr(buf, "1") != NULL) { + if (start_dvfs() != 0) + printk(KERN_ERR "Failed to start DVFS\n"); + } else if (strstr(buf, "0") != NULL) + stop_dvfs(); + + return size; +} + +static ssize_t dvfs_regs_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + if (dvfs_core_is_active) + dump_dvfs_core_regs(); + return 0; +} + +static ssize_t dvfs_regs_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + if (dvfs_core_is_active) + dump_dvfs_core_regs(); + return 0; + + return size; +} + +static DEVICE_ATTR(enable, S_IRUGO | S_IWUSR, + dvfs_enable_show, dvfs_enable_store); +static DEVICE_ATTR(show_regs, S_IRUGO, dvfs_regs_show, + dvfs_regs_store); + +/*! + * This is the probe routine for the DVFS driver. + * + * @param pdev The platform device structure + * + * @return The function returns 0 on success + */ +static int __devinit mxc_dvfs_core_probe(struct platform_device *pdev) +{ + int err = 0; + struct resource *res; + + printk(KERN_INFO "mxc_dvfs_core_probe\n"); + dvfs_dev = &pdev->dev; + dvfs_data = pdev->dev.platform_data; + + INIT_DELAYED_WORK(&dvfs_core_handler, dvfs_core_work_handler); + + pll1_sw_clk = clk_get(NULL, "pll1_sw_clk"); + if (IS_ERR(pll1_sw_clk)) { + printk(KERN_INFO "%s: failed to get pll1_sw_clk\n", __func__); + return PTR_ERR(pll1_sw_clk); + } + + cpu_clk = clk_get(NULL, dvfs_data->clk1_id); + if (IS_ERR(cpu_clk)) { + printk(KERN_ERR "%s: failed to get cpu clock\n", __func__); + return PTR_ERR(cpu_clk); + } + if (!cpu_is_mx6()) { + dvfs_clk = clk_get(NULL, dvfs_data->clk2_id); + if (IS_ERR(dvfs_clk)) { + printk(KERN_ERR "%s: failed to get dvfs clock\n", __func__); + return PTR_ERR(dvfs_clk); + } + } + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (res == NULL) { + err = -ENODEV; + goto err1; + } + dvfs_data->membase = ioremap(res->start, res->end - res->start + 1); + /* + * Request the DVFS interrupt + */ + dvfs_data->irq = platform_get_irq(pdev, 0); + if (dvfs_data->irq < 0) { + err = dvfs_data->irq; + goto err2; + } + + /* request the DVFS interrupt */ + err = request_irq(dvfs_data->irq, dvfs_irq, IRQF_SHARED, "dvfs", + dvfs_dev); + if (err) { + printk(KERN_ERR + "DVFS: Unable to attach to DVFS interrupt,err = %d", + err); + goto err2; + } + + dvfs_core_setpoint = get_dvfs_core_op(&dvfs_core_op); + if (dvfs_core_setpoint == NULL) { + printk(KERN_ERR "No dvfs_core working point table defined\n"); + goto err3; + } + + clk_enable(dvfs_clk); + err = init_dvfs_controller(); + if (err) { + printk(KERN_ERR "DVFS: Unable to initialize DVFS"); + return err; + } + clk_disable(dvfs_clk); + + err = sysfs_create_file(&pdev->dev.kobj, &dev_attr_enable.attr); + if (err) { + printk(KERN_ERR + "DVFS: Unable to register sysdev entry for DVFS"); + goto err3; + } + + err = sysfs_create_file(&dvfs_dev->kobj, &dev_attr_show_regs.attr); + if (err) { + printk(KERN_ERR + "DVFS: Unable to register sysdev entry for DVFS"); + goto err3; + } + + /* Set the current working point. */ + cpu_op_tbl = get_cpu_op(&cpu_op_nr); + old_op = 0; + curr_op = 0; + dvfs_core_resume = 0; + cpufreq_trig_needed = 0; + + return err; +err3: + free_irq(dvfs_data->irq, dvfs_dev); +err2: + iounmap(dvfs_data->membase); +err1: + dev_err(&pdev->dev, "Failed to probe DVFS CORE\n"); + return err; +} + +/*! + * This function is called to put DVFS in a low power state. + * + * @param pdev the device structure + * @param state the power state the device is entering + * + * @return The function always returns 0. + */ +static int mxc_dvfs_core_suspend(struct platform_device *pdev, + pm_message_t state) +{ + if (dvfs_core_is_active) { + dvfs_core_resume = 1; + stop_dvfs(); + } + + return 0; +} + +/*! + * This function is called to resume the MU from a low power state. + * + * @param dev the device structure + * @param level the stage in device suspension process that we want the + * device to be put in + * + * @return The function always returns 0. + */ +static int mxc_dvfs_core_resume(struct platform_device *pdev) +{ + if (dvfs_core_resume) { + dvfs_core_resume = 0; + start_dvfs(); + } + + return 0; +} + +static struct platform_driver mxc_dvfs_core_driver = { + .driver = { + .name = "imx_dvfscore", + }, + .probe = mxc_dvfs_core_probe, + .suspend = mxc_dvfs_core_suspend, + .resume = mxc_dvfs_core_resume, +}; + +static int __init dvfs_init(void) +{ + if (platform_driver_register(&mxc_dvfs_core_driver) != 0) { + printk(KERN_ERR "mxc_dvfs_core_driver register failed\n"); + return -ENODEV; + } + + dvfs_core_is_active = 0; + printk(KERN_INFO "DVFS driver module loaded\n"); + + return 0; +} + +static void __exit dvfs_cleanup(void) +{ + stop_dvfs(); + + /* release the DVFS interrupt */ + free_irq(dvfs_data->irq, dvfs_dev); + + sysfs_remove_file(&dvfs_dev->kobj, &dev_attr_enable.attr); + /* Unregister the device structure */ + platform_driver_unregister(&mxc_dvfs_core_driver); + + iounmap(ccm_base); + iounmap(dvfs_data->membase); + clk_put(cpu_clk); + clk_put(dvfs_clk); + + dvfs_core_is_active = 0; + printk(KERN_INFO "DVFS driver module unloaded\n"); + +} + +late_initcall(dvfs_init); +module_exit(dvfs_cleanup); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("DVFS driver"); +MODULE_LICENSE("GPL"); diff --git a/arch/arm/plat-mxc/dvfs_per.c b/arch/arm/plat-mxc/dvfs_per.c new file mode 100755 index 00000000..74b10144 --- /dev/null +++ b/arch/arm/plat-mxc/dvfs_per.c @@ -0,0 +1,936 @@ +/* + * Copyright (C) 2009-2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file dvfs_per.c + * + * @brief A simplied driver for the Freescale Semiconductor MXC DVFS module. + * + * Upon initialization, the DVFS driver initializes the DVFS hardware + * sets up driver nodes attaches to the DVFS interrupt and initializes internal + * data structures. When the DVFS interrupt occurs the driver checks the cause + * of the interrupt (lower frequency, increase frequency or emergency) and + * changes the CPU voltage according to translation table that is loaded into + * the driver. + * + * @ingroup PM + */ + +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/fs.h> +#include <linux/interrupt.h> +#include <linux/jiffies.h> +#include <linux/device.h> +#include <linux/sysdev.h> +#include <linux/delay.h> +#include <linux/clk.h> +#include <linux/regulator/consumer.h> +#include <linux/clk.h> +#include <linux/platform_device.h> +#include <linux/workqueue.h> +#include <linux/io.h> +#include <linux/slab.h> + +#include <mach/hardware.h> +#include <mach/mxc_dvfs.h> +#include <mach/sdram_autogating.h> +#include <mach/clock.h> +#if defined(CONFIG_ARCH_MX37) +#include <mach/mxc_dptc.h> +#endif + +/* DVFS PER */ +#define MXC_DVFS_PER_LTR0 0x00 +#define MXC_DVFS_PER_LTR1 0x04 +#define MXC_DVFS_PER_LTR2 0x08 +#define MXC_DVFS_PER_LTR3 0x0C +#define MXC_DVFS_PER_LTBR0 0x10 +#define MXC_DVFS_PER_LTBR1 0x14 +#define MXC_DVFS_PER_PMCR0 0x18 +#define MXC_DVFS_PER_PMCR1 0x1C + +#define DRIVER_NAME "DVFSPER" +#define DVFS_PER_DEBUG 0 + +static int dvfs_per_stop; +static int dvfs_per_low_freq; +static int dvfs_per_suspended; +static volatile int freq_increased; +static int cur_setpoint; +static struct delayed_work dvfs_per_work; +static struct clk *dvfs_clk; +static struct clk *main_bus_clk; +static struct clk *pll2; +static struct clk *lpapm; +static struct clk *cpu_clk; +static struct clk *axi_b_clk; +static struct clk *ahb_clk; +static struct clk *ddr_hf_clk; +static struct regulator *lp_regulator; + +/* Flag used to indicate if dvfs_per is active. */ +static int dvfs_per_is_active; +static int dvfs_per_is_paused; +static int ipu_freq_scaled; + +struct dvfsper_device *dvfsper_device_data; +/* DVFS platform data pointer */ +struct mxc_dvfsper_data *dvfsper_plt_data; +struct timeval prev_intr; + +int start_dvfs_per(void); +void stop_dvfs_per(void); +int dvfs_per_active(void); +int dvfs_per_divider_active(void); +int dvfs_per_pixel_clk_limit(void); + +extern int low_bus_freq_mode; +extern int bus_freq_scaling_is_active; + + +/*! + * In case the MXC device has multiple DVFS modules, this structure is used to + * store information specific to each DVFS module. + */ +struct dvfsper_device { + /* DVFS delayed work */ + struct delayed_work dvfs_work; + /* DVFS regulator */ + struct regulator *dvfs_reg; + /* DVFS clock */ + struct clk *dvfs_clk; + /* The interrupt number used by the DVFS device */ + int irq; +}; +struct dvfs_wp dvfs_per_setpoint[] = {{33, 7, 33, 20, 40, 0x10}, + {18, 0, 33, 25, 10, 0x10}, + /* When LP is at 24MHz */ + {8, 0, 10, 5, 5, 0x2E},}; + +enum { + FSVAI_FREQ_NOCHANGE = 0x0, + FSVAI_FREQ_INCREASE, + FSVAI_FREQ_DECREASE, + FSVAI_FREQ_EMERG, +}; + +#define LOW_BUS_FREQ 24000000 + +DEFINE_SPINLOCK(mxc_dvfs_per_lock); + +static void dvfs_per_load_config(void) +{ + u32 reg; + + reg = __raw_readl(dvfsper_plt_data->membase + MXC_DVFS_PER_LTR0); + reg &= ~MXC_DVFSLTR0_UPTHR_MASK; + reg &= ~MXC_DVFSLTR0_DNTHR_MASK; + reg |= dvfs_per_setpoint[cur_setpoint].upthr << + MXC_DVFSLTR0_UPTHR_OFFSET; + reg |= dvfs_per_setpoint[cur_setpoint].downthr << + MXC_DVFSLTR0_DNTHR_OFFSET; + __raw_writel(reg, dvfsper_plt_data->membase + MXC_DVFS_PER_LTR0); + + reg = __raw_readl(dvfsper_plt_data->membase + MXC_DVFS_PER_LTR1); + reg &= ~MXC_DVFSLTR1_PNCTHR_MASK; + reg &= ~MXC_DVFSLTR1_DNCNT_MASK; + reg &= ~MXC_DVFSLTR1_UPCNT_MASK; + reg |= dvfs_per_setpoint[cur_setpoint].downcnt << + MXC_DVFSLTR1_DNCNT_OFFSET; + reg |= dvfs_per_setpoint[cur_setpoint].upcnt << + MXC_DVFSLTR1_UPCNT_OFFSET; + reg |= dvfs_per_setpoint[cur_setpoint].panicthr << + MXC_DVFSLTR1_PNCTHR_OFFSET; + __raw_writel(reg, dvfsper_plt_data->membase + MXC_DVFS_PER_LTR1); + + reg = dvfs_per_setpoint[cur_setpoint].emac << + MXC_DVFSLTR2_EMAC_OFFSET; + __raw_writel(reg, dvfsper_plt_data->membase + MXC_DVFS_PER_LTR2); +} + +/*! + * This function is called for module initialization. + * It sets up the DVFS hardware. + * It sets default values for DVFS thresholds and counters. The default + * values was chosen from a set of different reasonable values. They was tested + * and the default values in the driver gave the best results. + * More work should be done to find optimal values. + * + * @return 0 if successful; non-zero otherwise. + * + */ +static int init_dvfs_per_controller(void) +{ + u32 reg; + + reg = __raw_readl(dvfsper_plt_data->membase + MXC_DVFS_PER_LTR0); + /* DIV3CLK */ + reg &= ~dvfsper_plt_data->div3_mask; + reg |= (dvfsper_plt_data->div3_div << + dvfsper_plt_data->div3_offset); + __raw_writel(reg, dvfsper_plt_data->membase + MXC_DVFS_PER_LTR0); + + reg = __raw_readl(dvfsper_plt_data->membase + MXC_DVFS_PER_LTR1); + /* Set load tracking buffer register source */ + reg &= ~MXC_DVFSLTR1_LTBRSR; + reg |= MXC_DVFSLTR1_LTBRSR; + reg &= ~MXC_DVFSLTR1_LTBRSH; + __raw_writel(reg, dvfsper_plt_data->membase + MXC_DVFS_PER_LTR1); + + /* Enable all the peripheral signals, but VPU and IPU panic*/ + __raw_writel(0x30000, dvfsper_plt_data->membase + MXC_DVFS_PER_PMCR1); + /* Disable weighted load tracking signals */ + __raw_writel(0, dvfsper_plt_data->membase + MXC_DVFS_PER_LTR3); + + reg = __raw_readl(dvfsper_plt_data->membase + MXC_DVFS_PER_PMCR0); + reg &= ~MXC_DVFSPMCR0_DVFEV; + reg |= MXC_DVFSPMCR0_LBMI; + __raw_writel(reg, dvfsper_plt_data->membase + MXC_DVFS_PER_PMCR0); + + /* DVFS loading config */ + dvfs_per_load_config(); + return 0; +} + +#if DVFS_PER_DEBUG +static void dump_dvfs_per_regs(void) +{ + struct timeval cur; + u32 diff = 0; + if (prev_intr.tv_sec == 0) + do_gettimeofday(&prev_intr); + else { + do_gettimeofday(&cur); + diff = (cur.tv_sec - prev_intr.tv_sec)*1000000 + + (cur.tv_usec - prev_intr.tv_usec); + prev_intr = cur; + } + if (diff < 90000) + printk(KERN_INFO "diff = %d\n", diff); + + printk(KERN_INFO "LTRO = 0x%08x\n", + __raw_readl(dvfsper_plt_data->membase + MXC_DVFS_PER_LTR0)); + printk(KERN_INFO "LTR1 = 0x%08x\n", + __raw_readl(dvfsper_plt_data->membase + MXC_DVFS_PER_LTR1)); + printk(KERN_INFO "LTR2 = 0x%08x\n", + __raw_readl(dvfsper_plt_data->membase + MXC_DVFS_PER_LTR2)); + printk(KERN_INFO "LTR3 = 0x%08x\n", + __raw_readl(dvfsper_plt_data->membase + MXC_DVFS_PER_LTR3)); + printk(KERN_INFO "LBTR0 = 0x%08x\n", + __raw_readl(dvfsper_plt_data->membase + MXC_DVFS_PER_LTBR0)); + printk(KERN_INFO "LBTR1 = 0x%08x\n", + __raw_readl(dvfsper_plt_data->membase + MXC_DVFS_PER_LTBR1)); + printk(KERN_INFO "PMCR0 = 0x%08x\n", + __raw_readl(dvfsper_plt_data->membase + MXC_DVFS_PER_PMCR0)); + printk(KERN_INFO "PMCR1 = 0x%08x\n", + __raw_readl(dvfsper_plt_data->membase + MXC_DVFS_PER_PMCR1)); +} +#endif + +static irqreturn_t dvfs_per_irq(int irq, void *dev_id) +{ + u32 reg; + + /* Check if DVFS1 (PER) id requesting for freqency/voltage update */ + if ((__raw_readl(dvfsper_plt_data->gpc_cntr_reg_addr) & + MXC_GPCCNTR_DVFS1CR) == 0) + return IRQ_NONE; + /* Mask DVFS irq */ + reg = __raw_readl(dvfsper_plt_data->membase + MXC_DVFS_PER_PMCR0); + /* FSVAIM=1 */ + reg |= MXC_DVFSPMCR0_FSVAIM; + __raw_writel(reg, dvfsper_plt_data->membase + MXC_DVFS_PER_PMCR0); + /* Mask GPC1 irq */ + reg = __raw_readl(dvfsper_plt_data->gpc_cntr_reg_addr); + reg |= MXC_GPCCNTR_GPCIRQM | 0x1000000; + __raw_writel(reg, dvfsper_plt_data->gpc_cntr_reg_addr); + + reg = __raw_readl(dvfsper_plt_data->membase + MXC_DVFS_PER_PMCR0); + if (reg & MXC_DVFSPMCR0_LBFL) { + /* clear LBFL */ + reg = (reg & ~MXC_DVFSPMCR0_LBFL); + reg |= MXC_DVFSPMCR0_LBFL; + __raw_writel(reg, dvfsper_plt_data->membase + + MXC_DVFS_PER_PMCR0); + } + schedule_delayed_work(&dvfs_per_work, 0); + return IRQ_HANDLED; +} + +static void dvfs_per_handler(struct work_struct *work) +{ + u32 fsvai; + u32 reg; + u32 ret; + unsigned long flags; + int retry = 20; + + /* Check DVFS frequency adjustment interrupt status */ + reg = __raw_readl(dvfsper_plt_data->membase + MXC_DVFS_PER_PMCR0); + fsvai = (reg & MXC_DVFSPMCR0_FSVAI_MASK) >> MXC_DVFSPMCR0_FSVAI_OFFSET; + /* Check FSVAI, FSVAI=0 is error */ + if (fsvai == FSVAI_FREQ_NOCHANGE) { + /* Do nothing. Freq change is not required */ + goto END; + } + +#if DVFS_PER_DEBUG + dump_dvfs_per_regs(); +#endif + /* If FSVAI indicate freq down. */ + if (fsvai == FSVAI_FREQ_DECREASE) { + if (cpu_is_mx51()) { + /*Change the DDR freq to 133Mhz. */ + clk_set_rate(ddr_hf_clk, + clk_round_rate(ddr_hf_clk, 133000000)); + } + +#ifndef DVFS_SW_WORKAROUND + spin_lock_irqsave(&mxc_dvfs_per_lock, flags); + reg = __raw_readl(dvfsper_plt_data->membase + + MXC_DVFS_PER_PMCR0); + reg &= ~MXC_DVFSPMCR0_UDCS; + __raw_writel(reg, dvfsper_plt_data->membase + + MXC_DVFS_PER_PMCR0); + + /* Set the peripheral divider */ + reg = __raw_readl(dvfsper_plt_data->gpc_cntr_reg_addr); + reg &= ~(MXC_GPCCNTR_ADU_MASK | MXC_GPCCNTR_FUPD_MASK); + reg |= MXC_GPCCNTR_FUPD; + __raw_writel(reg, dvfsper_plt_data->gpc_cntr_reg_addr); + + reg = __raw_readl(dvfsper_plt_data->gpc_vcr_reg_addr); + reg &= ~(MXC_GPCVCR_VINC_MASK | MXC_GPCVCR_VCNTU_MASK | + MXC_GPCVCR_VCNT_MASK); + reg |= (1 << MXC_GPCVCR_VCNTU_OFFSET) | + (1 << MXC_GPCVCR_VCNT_OFFSET); + __raw_writel(reg, dvfsper_plt_data->gpc_vcr_reg_addr); + + reg = __raw_readl(dvfsper_plt_data->gpc_cntr_reg_addr); + reg |= MXC_GPCCNTR_STRT; + __raw_writel(reg, dvfsper_plt_data->gpc_cntr_reg_addr); + + retry = 10; + while ((__raw_readl( + dvfsper_plt_data->gpc_cntr_reg_addr) & 0x4000) + && retry > 0) { + udelay(10); + retry--; + } + spin_unlock_irqrestore(&mxc_dvfs_per_lock, flags); +#else + /*Set the frequencies manually */ + rate = clk_get_rate(axi_b_clk); + clk_set_rate(axi_b_clk, clk_round_rate(axi_b_clk, rate/2)); + + rate = clk_get_rate(ahb_clk); + clk_set_rate(ahb_clk, clk_round_rate(ahb_clk, rate/2)); +#endif + dvfs_per_low_freq = 1; + if (clk_get_rate(main_bus_clk) == LOW_BUS_FREQ) { + cur_setpoint = 2; + } else { +#if defined(CONFIG_ARCH_MX37) + dptc_suspend(DPTC_LP_ID); +#endif + cur_setpoint = 1; +#ifndef DVFS_SW_WORKAROUND + clk_set_parent(main_bus_clk, clk_get(NULL, "pll2")); +#endif + } +#ifndef DVFS_SW_WORKAROUND + /* Drop the LP domain voltage */ + ret = regulator_set_voltage(lp_regulator, + dvfsper_plt_data->lp_low, + dvfsper_plt_data->lp_low); + if (ret < 0) { + printk(KERN_DEBUG "COULD NOT SET LP VOLTAGE\n"); + return; + } + udelay(100); +#endif + dvfs_per_load_config(); + } else if ((fsvai == FSVAI_FREQ_INCREASE) || + (fsvai == FSVAI_FREQ_EMERG)) { +#ifndef DVFS_SW_WORKAROUND + /* Increase the LP domain voltage first. */ + ret = regulator_set_voltage(lp_regulator, + dvfsper_plt_data->lp_high, + dvfsper_plt_data->lp_high); + if (ret < 0) { + printk(KERN_DEBUG "COULD NOT SET LP VOLTAGE\n"); + return; + } + udelay(100); +#endif + +#ifndef DVFS_SW_WORKAROUND + spin_lock_irqsave(&mxc_dvfs_per_lock, flags); + reg = __raw_readl(dvfsper_plt_data->membase + + MXC_DVFS_PER_PMCR0); + reg |= MXC_DVFSPMCR0_UDCS; + __raw_writel(reg, dvfsper_plt_data->membase + + MXC_DVFS_PER_PMCR0); + + reg = __raw_readl(dvfsper_plt_data->gpc_cntr_reg_addr); + reg &= ~(MXC_GPCCNTR_ADU_MASK | MXC_GPCCNTR_FUPD_MASK); + reg |= MXC_GPCCNTR_FUPD; + __raw_writel(reg, dvfsper_plt_data->gpc_cntr_reg_addr); + + reg = __raw_readl(dvfsper_plt_data->gpc_vcr_reg_addr); + reg &= ~(MXC_GPCVCR_VINC_MASK | MXC_GPCVCR_VCNTU_MASK | + MXC_GPCVCR_VCNT_MASK); + reg |= (1 << MXC_GPCVCR_VINC_OFFSET | + 1 << MXC_GPCVCR_VCNTU_OFFSET | + 1 << MXC_GPCVCR_VCNT_OFFSET); + __raw_writel(reg, dvfsper_plt_data->gpc_vcr_reg_addr); + + reg = __raw_readl(dvfsper_plt_data->gpc_cntr_reg_addr); + reg &= ~MXC_GPCCNTR_ADU; + reg |= MXC_GPCCNTR_STRT; + __raw_writel(reg, dvfsper_plt_data->gpc_cntr_reg_addr); + retry = 10; + while ((__raw_readl( + dvfsper_plt_data->gpc_cntr_reg_addr) & 0x4000) + && retry > 0) { + udelay(10); + retry--; + } + spin_unlock_irqrestore(&mxc_dvfs_per_lock, flags); + + if (retry < 0) + printk(KERN_ERR "****ERROR- DVFS\n"); +#else + /*Set the frequencies manually */ + rate = clk_get_rate(axi_b_clk); + clk_set_rate(axi_b_clk, clk_round_rate(axi_b_clk, 130000000)); + rate = clk_get_rate(ahb_clk); + clk_set_rate(ahb_clk, clk_round_rate(ahb_clk, 130000000)); +#endif + if (cpu_is_mx51()) { + /*Change the DDR freq to 200Mhz. */ + clk_set_rate(ddr_hf_clk, clk_round_rate(ddr_hf_clk, + 200000000)); + } + dvfs_per_low_freq = 0; + if (clk_get_rate(main_bus_clk) == LOW_BUS_FREQ) { + cur_setpoint = 2; + } else { + cur_setpoint = 0; +#if defined(CONFIG_ARCH_MX37) + dptc_resume(DPTC_LP_ID); +#endif +#ifndef DVFS_SW_WORKAROUND + clk_set_parent(main_bus_clk, clk_get(NULL, "pll2")); +#endif + } + dvfs_per_load_config(); + freq_increased = 1; + } + +END: +#if DVFS_PER_DEBUG + dump_dvfs_per_regs(void)(); +#endif + if (dvfs_per_is_active) { + reg = __raw_readl(dvfsper_plt_data->membase + + MXC_DVFS_PER_PMCR0); + /* Enable dVFS interrupt */ + /* FSVAIM=0 */ + reg &= ~MXC_DVFSPMCR0_FSVAI_MASK; + reg |= FSVAI_FREQ_NOCHANGE; + reg = (reg & ~MXC_DVFSPMCR0_FSVAIM); + __raw_writel(reg, dvfsper_plt_data->membase + + MXC_DVFS_PER_PMCR0); + /*Unmask GPC1 IRQ */ + reg = __raw_readl(dvfsper_plt_data->gpc_cntr_reg_addr); + reg &= ~MXC_GPCCNTR_GPCIRQM; + __raw_writel(reg, dvfsper_plt_data->gpc_cntr_reg_addr); + } +} + +static void force_freq_change(void) +{ + u32 reg; + int retry = 50; + + freq_increased = 0; + + reg = __raw_readl(dvfsper_plt_data->membase + MXC_DVFS_PER_PMCR0); + reg |= MXC_DVFSPMCR0_UDCS; + __raw_writel(reg, dvfsper_plt_data->membase + MXC_DVFS_PER_PMCR0); + + if (cpu_is_mx51()) { + /*Change the DDR freq to 133Mhz. */ + clk_set_rate(ddr_hf_clk, clk_round_rate(ddr_hf_clk, 200000000)); + } + +#ifndef DVFS_SW_WORKAROUND + reg = __raw_readl(dvfsper_plt_data->gpc_cntr_reg_addr); + reg |= MXC_GPCCNTR_FUPD; + __raw_writel(reg, dvfsper_plt_data->gpc_cntr_reg_addr); + reg = __raw_readl(dvfsper_plt_data->gpc_vcr_reg_addr); + reg &= ~(MXC_GPCVCR_VINC_MASK | MXC_GPCVCR_VCNTU_MASK | + MXC_GPCVCR_VCNT_MASK); + reg |= (1 << MXC_GPCVCR_VINC_OFFSET | + 1 << MXC_GPCVCR_VCNTU_OFFSET | + 20 << MXC_GPCVCR_VCNT_OFFSET); + __raw_writel(reg, dvfsper_plt_data->gpc_vcr_reg_addr); + reg = __raw_readl(dvfsper_plt_data->gpc_cntr_reg_addr); + reg &= ~MXC_GPCCNTR_ADU; + reg |= MXC_GPCCNTR_STRT; + __raw_writel(reg, dvfsper_plt_data->gpc_cntr_reg_addr); + while ((__raw_readl( + dvfsper_plt_data->gpc_cntr_reg_addr) & 0x4000) + && retry > 0) { + udelay(30); + retry--; + } + freq_increased = 1; + if (retry <= 0) + printk(KERN_ERR "Cannot stop DVFS-PER\n"); +#else + /* Set the frequencies manually */ + rate = clk_get_rate(axi_b_clk); + clk_set_rate(axi_b_clk, clk_round_rate(axi_b_clk, 130000000)); + rate = clk_get_rate(ahb_clk); + clk_set_rate(ahb_clk, clk_round_rate(ahb_clk, 130000000)); +#endif + dvfs_per_low_freq = 0; + +#ifndef DVFS_SW_WORKAROUND + clk_set_parent(main_bus_clk, pll2); +#endif +} + +static int start(void) +{ + u32 reg; + unsigned long flags; + + if (dvfs_per_is_active || dvfs_per_stop) + return 0; + + if (low_bus_freq_mode) + return 0; + + if (bus_freq_scaling_is_active) { + dvfs_per_is_paused = 1; + printk(KERN_INFO "Cannot start DVFS-PER since bus_freq_scaling\ + is active\n"); + return 0; + } + + if (!dvfs_per_pixel_clk_limit()) { + dvfs_per_is_paused = 1; + printk(KERN_INFO "Cannot start DVFS-PER since pixel clock is\ + above 60MHz or divider is not even\n"); + return 0; + } + + stop_sdram_autogating(); + + spin_lock_irqsave(&mxc_dvfs_per_lock, flags); + + clk_enable(dvfs_clk); + + cur_setpoint = 0; + init_dvfs_per_controller(); + + /* config reg GPC_CNTR */ + reg = __raw_readl(dvfsper_plt_data->gpc_cntr_reg_addr); + /* ADU=0, select PER domain */ + reg &= ~MXC_GPCCNTR_ADU; + __raw_writel(reg, dvfsper_plt_data->gpc_cntr_reg_addr); + + reg = __raw_readl(dvfsper_plt_data->membase + MXC_DVFS_PER_PMCR0); + /* Select ARM domain */ + reg |= MXC_DVFSPMCR0_DVFIS; + /* Set the UDCS bit */ + reg |= MXC_DVFSPMCR0_UDCS; + /* Enable DVFS interrupt */ + /* FSVAIM=0 */ + reg &= ~MXC_DVFSPMCR0_FSVAIM; + /*Set the FSVAI to no_freq_change */ + reg &= ~MXC_DVFSPMCR0_FSVAI_MASK; + reg |= FSVAI_FREQ_NOCHANGE << MXC_DVFSPMCR0_FSVAI_OFFSET; + __raw_writel(reg, dvfsper_plt_data->membase + MXC_DVFS_PER_PMCR0); + + /* config reg GPC_CNTR */ + reg = __raw_readl(dvfsper_plt_data->gpc_cntr_reg_addr); + /* GPCIRQ=1, select ARM IRQ */ + reg |= MXC_GPCCNTR_GPCIRQ_ARM; + reg &= ~MXC_GPCCNTR_GPCIRQM; + __raw_writel(reg, dvfsper_plt_data->gpc_cntr_reg_addr); + + /* Enable DVFS */ + reg = __raw_readl(dvfsper_plt_data->membase + MXC_DVFS_PER_PMCR0); + reg |= MXC_DVFSPMCR0_DVFEN; + __raw_writel(reg, dvfsper_plt_data->membase + MXC_DVFS_PER_PMCR0); + + dvfs_per_is_active = 1; + spin_unlock_irqrestore(&mxc_dvfs_per_lock, flags); + + printk(KERN_DEBUG "DVFS PER is started\n"); + + return 0; +} + +/*! + * This function disables the DVFS module. + */ +static void stop(void) +{ + u32 reg = 0; + unsigned long flags; + u32 ret = 0; + + if (dvfs_per_is_active) { + dvfs_per_is_active = 0; +#ifndef DVFS_SW_WORKAROUND + /* Increase the LP domain voltage first. */ + ret = regulator_set_voltage( + lp_regulator, dvfsper_plt_data->lp_high, + dvfsper_plt_data->lp_high); + if (ret < 0) { + printk(KERN_DEBUG "COULD NOT SET LP VOLTAGE\n"); + return; + } + udelay(100); +#endif + + spin_lock_irqsave(&mxc_dvfs_per_lock, flags); + + /* Mask dvfs irq, disable DVFS */ + reg = __raw_readl(dvfsper_plt_data->membase + + MXC_DVFS_PER_PMCR0); + /* FSVAIM=1 */ + reg |= MXC_DVFSPMCR0_FSVAIM; + __raw_writel(reg, dvfsper_plt_data->membase + + MXC_DVFS_PER_PMCR0); + + if (cur_setpoint != 0) + force_freq_change(); + + reg = __raw_readl(dvfsper_plt_data->membase + + MXC_DVFS_PER_PMCR0); + reg = (reg & ~MXC_DVFSPMCR0_DVFEN); + __raw_writel(reg, dvfsper_plt_data->membase + + MXC_DVFS_PER_PMCR0); + + spin_unlock_irqrestore(&mxc_dvfs_per_lock, flags); + clk_disable(dvfs_clk); + + start_sdram_autogating(); + } +} + + +int dvfs_per_active() +{ + return dvfs_per_is_active; +} + +int dvfs_per_divider_active() +{ + return dvfs_per_low_freq; +} + +int dvfs_per_pixel_clk_limit() +{ + struct clk *disp0_pixel_clk; + struct clk *disp1_pixel_clk; + int disp0_rate = 0; + int disp1_rate = 0; + int div1 = 0; + int div2 = 0; + int even_div1 = 1; + int even_div2 = 1; + + disp0_pixel_clk = clk_get(NULL, "pixel_clk.0"); + disp1_pixel_clk = clk_get(NULL, "pixel_clk.1"); + + if (disp0_pixel_clk != NULL) + disp0_rate = clk_get_rate(disp0_pixel_clk); + + if (disp1_pixel_clk != NULL) + disp1_rate = clk_get_rate(disp1_pixel_clk); + + /* DVFS-PER will not work if pixel clock divider is odd */ + if (disp0_rate != 0) + div1 = (clk_get_rate( + clk_get_parent(disp0_pixel_clk)) * 10) / disp0_rate; + + if ((div1 % 2) || ((div1 / 10) % 2)) + even_div1 = 0; + + if ((div2 % 2) || ((div2 / 10) % 2)) + even_div2 = 0; + + if (disp1_rate != 0) + div2 = (clk_get_rate( + clk_get_parent(disp1_pixel_clk)) * 10) / disp1_rate; + + if (((disp0_rate < DVFS_MAX_PIX_CLK && even_div1) || + !clk_get_usecount(disp0_pixel_clk)) && + ((disp1_rate < DVFS_MAX_PIX_CLK && even_div2) || + !clk_get_usecount(disp1_pixel_clk))) + ipu_freq_scaled = 1; + else + ipu_freq_scaled = 0; + + clk_put(disp0_pixel_clk); + clk_put(disp1_pixel_clk); + + return ipu_freq_scaled; +} + +int start_dvfs_per(void) +{ + if (dvfs_per_is_paused) { + dvfs_per_is_paused = 0; + return start(); + } + return 0; +} + +void stop_dvfs_per(void) +{ + if (dvfs_per_is_active) { + dvfs_per_is_paused = 1; + stop(); + } +} + +/*! + * Enable DVFS Peripheral + * + */ +int dvfs_enable(struct device *dev) +{ + if (dvfs_per_is_active) + return 0; + return start(); +} + +static ssize_t dvfsper_enable_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + if (strstr(buf, "1") != NULL) { + dvfs_per_stop = 0; + if (dvfs_enable(dev) != 0) + printk(KERN_ERR "Failed to start DVFS\n"); + } else if (strstr(buf, "0") != NULL) { + dvfs_per_stop = 1; + stop(); + } + return size; +} + +static ssize_t dvfsper_status_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + int size = 0; + + if (dvfs_per_is_active) + size = sprintf(buf, "DVFS PER is enabled\n"); + else + size = sprintf(buf, "DVFS PEr is disabled\n"); + + return size; +} + +static DEVICE_ATTR(enable, 0644, dvfsper_status_show, dvfsper_enable_store); + +/*! + * This is the probe routine for the DVFS PER driver. + * + * @param pdev The platform device structure + * + * @return The function returns 0 on success + * + */ +static int __devinit mxc_dvfsper_probe(struct platform_device *pdev) +{ + int ret = 0; + struct resource *res; + struct mxc_dvfsper_data *dvfsper_data = pdev->dev.platform_data; + + if (dvfsper_data == NULL) { + printk(KERN_ERR "DVFS: Pointer to DVFS data is NULL\ + not started\n"); + return -1; + } + + /* Set driver data */ + platform_set_drvdata(pdev, dvfsper_device_data); + + dvfsper_plt_data = pdev->dev.platform_data; + dvfsper_device_data = kzalloc(sizeof(struct dvfsper_device), + GFP_KERNEL); + if (!dvfsper_device_data) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (res == NULL) { + ret = -ENODEV; + goto err1; + } + dvfsper_plt_data->membase = ioremap(res->start, + res->end - res->start + 1); + + /* + * Request the DVFSPER interrupt + */ + dvfsper_device_data->irq = platform_get_irq(pdev, 0); + if (dvfsper_device_data->irq < 0) { + ret = dvfsper_device_data->irq; + goto err1; + } + + ret = + request_irq(dvfsper_device_data->irq, dvfs_per_irq, IRQF_SHARED, + pdev->name, &pdev->dev); + if (ret) { + printk(KERN_ERR "DVFS: Unable to attach to DVFS interrupt\n"); + goto err1; + } + + lp_regulator = regulator_get(NULL, dvfsper_data->reg_id); + if (IS_ERR(lp_regulator)) { + printk(KERN_ERR "%s: failed to get lp regulator\n", __func__); + return PTR_ERR(lp_regulator); + } + + INIT_DELAYED_WORK(&dvfs_per_work, dvfs_per_handler); + + main_bus_clk = clk_get(NULL, "main_bus_clk"); + pll2 = clk_get(NULL, "pll2"); + lpapm = clk_get(NULL, "lp_apm"); + cpu_clk = clk_get(NULL, "cpu_clk"); + ahb_clk = clk_get(NULL, "ahb_clk"); + axi_b_clk = clk_get(NULL, "axi_b_clk"); + + if (cpu_is_mx51()) + ddr_hf_clk = clk_get(NULL, "ddr_hf_clk"); + + dvfsper_device_data->dvfs_clk = clk_get(NULL, dvfsper_data->clk_id); + dvfs_clk = dvfsper_device_data->dvfs_clk; + + ret = sysfs_create_file(&pdev->dev.kobj, &dev_attr_enable.attr); + + if (ret) { + printk(KERN_ERR + "DVFS: Unable to register sysdev entry for dvfs"); + goto err1; + } + + return 0; +err1: + dev_err(&pdev->dev, "Failed to probe DVFS\n"); + kfree(dvfsper_device_data); + + return ret; +} + +/*! + * This function is called to put DVFS in a low power state. + * + * @param pdev the device structure + * @param state the power state the device is entering + * + * @return The function always returns 0. + */ +static int mxc_dvfs_suspend(struct platform_device *pdev, + pm_message_t state) +{ + if (dvfs_per_is_active) { + stop_dvfs_per(); + dvfs_per_suspended = 1; + } + return 0; +} + +/*! + * This function is called to resume the DVFS from a low power state. + * + * @param dev the device structure + * @param level the stage in device suspension process that we want the + * device to be put in + * + * @return The function always returns 0. + */ +static int mxc_dvfs_resume(struct platform_device *pdev) +{ + if (dvfs_per_suspended) { + dvfs_per_suspended = 0; + return start_dvfs_per(); + } + + return 0; +} + +static struct platform_driver mxc_dvfsper_driver = { + .driver = { + .name = "mxc_dvfsper", + .owner = THIS_MODULE, + }, + .probe = mxc_dvfsper_probe, + .suspend = mxc_dvfs_suspend, + .resume = mxc_dvfs_resume, +}; + +static int __init dvfs_per_init(void) +{ + int err = 0; + + if (platform_driver_register(&mxc_dvfsper_driver) != 0) { + printk(KERN_ERR "mxc_dvfsper_driver register failed\n"); + return -ENODEV; + } + printk(KERN_INFO "DVFS PER driver module loaded\n"); + + return err; +} + +static void __exit dvfs_per_cleanup(void) +{ + stop_dvfs_per(); + + /* release the DVFS interrupt */ + free_irq(dvfsper_device_data->irq, NULL); + + clk_put(dvfs_clk); + clk_put(main_bus_clk); + clk_put(pll2); + clk_put(lpapm); + clk_put(cpu_clk); + clk_put(ahb_clk); + clk_put(axi_b_clk); + if (cpu_is_mx51()) + clk_put(ddr_hf_clk); + + /* Unregister the device structure */ + platform_driver_unregister(&mxc_dvfsper_driver); +} + +module_init(dvfs_per_init); +module_exit(dvfs_per_cleanup); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("DVFS PERIPHERAL driver"); +MODULE_LICENSE("GPL"); diff --git a/arch/arm/plat-mxc/epit.c b/arch/arm/plat-mxc/epit.c new file mode 100644 index 00000000..d3467f81 --- /dev/null +++ b/arch/arm/plat-mxc/epit.c @@ -0,0 +1,225 @@ +/* + * linux/arch/arm/plat-mxc/epit.c + * + * Copyright (C) 2010 Sascha Hauer <s.hauer@pengutronix.de> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#define EPITCR 0x00 +#define EPITSR 0x04 +#define EPITLR 0x08 +#define EPITCMPR 0x0c +#define EPITCNR 0x10 + +#define EPITCR_EN (1 << 0) +#define EPITCR_ENMOD (1 << 1) +#define EPITCR_OCIEN (1 << 2) +#define EPITCR_RLD (1 << 3) +#define EPITCR_PRESC(x) (((x) & 0xfff) << 4) +#define EPITCR_SWR (1 << 16) +#define EPITCR_IOVW (1 << 17) +#define EPITCR_DBGEN (1 << 18) +#define EPITCR_WAITEN (1 << 19) +#define EPITCR_RES (1 << 20) +#define EPITCR_STOPEN (1 << 21) +#define EPITCR_OM_DISCON (0 << 22) +#define EPITCR_OM_TOGGLE (1 << 22) +#define EPITCR_OM_CLEAR (2 << 22) +#define EPITCR_OM_SET (3 << 22) +#define EPITCR_CLKSRC_OFF (0 << 24) +#define EPITCR_CLKSRC_PERIPHERAL (1 << 24) +#define EPITCR_CLKSRC_REF_HIGH (1 << 24) +#define EPITCR_CLKSRC_REF_LOW (3 << 24) + +#define EPITSR_OCIF (1 << 0) + +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/clockchips.h> +#include <linux/clk.h> + +#include <mach/hardware.h> +#include <asm/mach/time.h> +#include <mach/common.h> + +static struct clock_event_device clockevent_epit; +static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED; + +static void __iomem *timer_base; + +static inline void epit_irq_disable(void) +{ + u32 val; + + val = __raw_readl(timer_base + EPITCR); + val &= ~EPITCR_OCIEN; + __raw_writel(val, timer_base + EPITCR); +} + +static inline void epit_irq_enable(void) +{ + u32 val; + + val = __raw_readl(timer_base + EPITCR); + val |= EPITCR_OCIEN; + __raw_writel(val, timer_base + EPITCR); +} + +static void epit_irq_acknowledge(void) +{ + __raw_writel(EPITSR_OCIF, timer_base + EPITSR); +} + +static int __init epit_clocksource_init(struct clk *timer_clk) +{ + unsigned int c = clk_get_rate(timer_clk); + + return clocksource_mmio_init(timer_base + EPITCNR, "epit", c, 200, 32, + clocksource_mmio_readl_down); +} + +/* clock event */ + +static int epit_set_next_event(unsigned long evt, + struct clock_event_device *unused) +{ + unsigned long tcmp; + + tcmp = __raw_readl(timer_base + EPITCNR); + + __raw_writel(tcmp - evt, timer_base + EPITCMPR); + + return 0; +} + +static void epit_set_mode(enum clock_event_mode mode, + struct clock_event_device *evt) +{ + unsigned long flags; + + /* + * The timer interrupt generation is disabled at least + * for enough time to call epit_set_next_event() + */ + local_irq_save(flags); + + /* Disable interrupt in GPT module */ + epit_irq_disable(); + + if (mode != clockevent_mode) { + /* Set event time into far-far future */ + + /* Clear pending interrupt */ + epit_irq_acknowledge(); + } + + /* Remember timer mode */ + clockevent_mode = mode; + local_irq_restore(flags); + + switch (mode) { + case CLOCK_EVT_MODE_PERIODIC: + printk(KERN_ERR "epit_set_mode: Periodic mode is not " + "supported for i.MX EPIT\n"); + break; + case CLOCK_EVT_MODE_ONESHOT: + /* + * Do not put overhead of interrupt enable/disable into + * epit_set_next_event(), the core has about 4 minutes + * to call epit_set_next_event() or shutdown clock after + * mode switching + */ + local_irq_save(flags); + epit_irq_enable(); + local_irq_restore(flags); + break; + case CLOCK_EVT_MODE_SHUTDOWN: + case CLOCK_EVT_MODE_UNUSED: + case CLOCK_EVT_MODE_RESUME: + /* Left event sources disabled, no more interrupts appear */ + break; + } +} + +/* + * IRQ handler for the timer + */ +static irqreturn_t epit_timer_interrupt(int irq, void *dev_id) +{ + struct clock_event_device *evt = &clockevent_epit; + + epit_irq_acknowledge(); + + evt->event_handler(evt); + + return IRQ_HANDLED; +} + +static struct irqaction epit_timer_irq = { + .name = "i.MX EPIT Timer Tick", + .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, + .handler = epit_timer_interrupt, +}; + +static struct clock_event_device clockevent_epit = { + .name = "epit", + .features = CLOCK_EVT_FEAT_ONESHOT, + .shift = 32, + .set_mode = epit_set_mode, + .set_next_event = epit_set_next_event, + .rating = 200, +}; + +static int __init epit_clockevent_init(struct clk *timer_clk) +{ + unsigned int c = clk_get_rate(timer_clk); + + clockevent_epit.mult = div_sc(c, NSEC_PER_SEC, + clockevent_epit.shift); + clockevent_epit.max_delta_ns = + clockevent_delta2ns(0xfffffffe, &clockevent_epit); + clockevent_epit.min_delta_ns = + clockevent_delta2ns(0x800, &clockevent_epit); + + clockevent_epit.cpumask = cpumask_of(0); + + clockevents_register_device(&clockevent_epit); + + return 0; +} + +void __init epit_timer_init(struct clk *timer_clk, void __iomem *base, int irq) +{ + clk_enable(timer_clk); + + timer_base = base; + + /* + * Initialise to a known state (all timers off, and timing reset) + */ + __raw_writel(0x0, timer_base + EPITCR); + + __raw_writel(0xffffffff, timer_base + EPITLR); + __raw_writel(EPITCR_EN | EPITCR_CLKSRC_REF_HIGH | EPITCR_WAITEN, + timer_base + EPITCR); + + /* init and register the timer to the framework */ + epit_clocksource_init(timer_clk); + epit_clockevent_init(timer_clk); + + /* Make irqs happen */ + setup_irq(irq, &epit_timer_irq); +} diff --git a/arch/arm/plat-mxc/fuse.c b/arch/arm/plat-mxc/fuse.c new file mode 100644 index 00000000..1238e76b --- /dev/null +++ b/arch/arm/plat-mxc/fuse.c @@ -0,0 +1,165 @@ +/* + * Copyright (C) 2013 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <linux/io.h> +#include <linux/kernel.h> +#include <mach/hardware.h> + +#define HW_OCOTP_CFGn(n) (0x00000410 + (n) * 0x10) + +/* Note: the names oder is the same as device enum order defined in mxc.h */ +static char *names[] = { + "pxp", "ovg", "dsi_csi2", "enet", "mlb", + "epdc", "hdmi", "pcie", "sata", "dtcp", + "2d", "3d", "vpu", "divx3", "rv", + "sorensen", +}; + +int fuse_dev_is_available(enum mxc_dev_type dev) +{ + u32 uninitialized_var(reg); + u32 uninitialized_var(mask); + int ret; + + if (!cpu_is_mx6()) + return 1; + + /* mx6sl is still not supported */ + if (cpu_is_mx6sl()) + return 1; + + switch (dev) { + case MXC_DEV_PXP: + if (cpu_is_mx6q()) + return 0; + + if (cpu_is_mx6dl()) { + reg = HW_OCOTP_CFGn(2); + mask = 0x80000000; + } + break; + case MXC_DEV_OVG: + if (cpu_is_mx6dl()) + return 0; + + if (cpu_is_mx6q()) { + reg = HW_OCOTP_CFGn(2); + mask = 0x40000000; + } + break; + case MXC_DEV_DSI_CSI2: + if (cpu_is_mx6dl() || cpu_is_mx6q()) { + reg = HW_OCOTP_CFGn(2); + mask = 0x10000000; + } + break; + case MXC_DEV_ENET: + if (cpu_is_mx6dl() || cpu_is_mx6q()) { + reg = HW_OCOTP_CFGn(2); + mask = 0x08000000; + } + break; + case MXC_DEV_MLB: + if (cpu_is_mx6dl() || cpu_is_mx6q()) { + reg = HW_OCOTP_CFGn(2); + mask = 0x04000000; + } + break; + case MXC_DEV_EPDC: + if (cpu_is_mx6q()) + return 0; + + if (cpu_is_mx6dl()) { + reg = HW_OCOTP_CFGn(2); + mask = 0x02000000; + } + break; + case MXC_DEV_HDMI: + if (cpu_is_mx6dl() || cpu_is_mx6q()) { + reg = HW_OCOTP_CFGn(3); + mask = 0x00000080; + } + break; + case MXC_DEV_PCIE: + if (cpu_is_mx6dl() || cpu_is_mx6q()) { + reg = HW_OCOTP_CFGn(3); + mask = 0x00000040; + } + break; + case MXC_DEV_SATA: + if (cpu_is_mx6dl()) + return 0; + + if (cpu_is_mx6q()) { + reg = HW_OCOTP_CFGn(3); + mask = 0x00000020; + } + break; + case MXC_DEV_DTCP: + if (cpu_is_mx6dl() || cpu_is_mx6q()) { + reg = HW_OCOTP_CFGn(3); + mask = 0x00000010; + } + break; + case MXC_DEV_2D: + if (cpu_is_mx6dl() || cpu_is_mx6q()) { + reg = HW_OCOTP_CFGn(3); + mask = 0x00000008; + } + break; + case MXC_DEV_3D: + if (cpu_is_mx6dl() || cpu_is_mx6q()) { + reg = HW_OCOTP_CFGn(3); + mask = 0x00000004; + } + break; + case MXC_DEV_VPU: + if (cpu_is_mx6dl() || cpu_is_mx6q()) { + reg = HW_OCOTP_CFGn(3); + mask = 0x00008000; + } + break; + case MXC_DEV_DIVX3: + if (cpu_is_mx6dl() || cpu_is_mx6q()) { + reg = HW_OCOTP_CFGn(3); + mask = 0x00000400; + } + break; + case MXC_DEV_RV: + if (cpu_is_mx6dl() || cpu_is_mx6q()) { + reg = HW_OCOTP_CFGn(3); + mask = 0x00000200; + } + break; + case MXC_DEV_SORENSEN: + if (cpu_is_mx6dl() || cpu_is_mx6q()) { + reg = HW_OCOTP_CFGn(3); + mask = 0x00000100; + } + break; + default: + /* we treat the unkown device is avaiable by default */ + return 1; + } + + ret = readl(MX6_IO_ADDRESS(OCOTP_BASE_ADDR) + reg) & mask; + pr_debug("fuse_check: %s is %s\n", names[dev], ret ? + "unavailable" : "available"); + + return !ret; +} diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c new file mode 100755 index 00000000..0af29c0c --- /dev/null +++ b/arch/arm/plat-mxc/gpio.c @@ -0,0 +1,377 @@ +/* + * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de> + * Copyright 2008 Juergen Beisert, kernel@pengutronix.de + * + * Based on code from Freescale, + * Copyright (C) 2004-2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/io.h> +#include <linux/irq.h> +#include <linux/gpio.h> +#include <mach/hardware.h> +#include <asm-generic/bug.h> +#include <asm/mach/irq.h> + +static struct mxc_gpio_port *mxc_gpio_ports; +static int gpio_table_size; + +#define cpu_is_mx1_mx2() (cpu_is_mx1() || cpu_is_mx2()) + +#define GPIO_DR (cpu_is_mx1_mx2() ? 0x1c : 0x00) +#define GPIO_GDIR (cpu_is_mx1_mx2() ? 0x00 : 0x04) +#define GPIO_PSR (cpu_is_mx1_mx2() ? 0x24 : 0x08) +#define GPIO_ICR1 (cpu_is_mx1_mx2() ? 0x28 : 0x0C) +#define GPIO_ICR2 (cpu_is_mx1_mx2() ? 0x2C : 0x10) +#define GPIO_IMR (cpu_is_mx1_mx2() ? 0x30 : 0x14) +#define GPIO_ISR (cpu_is_mx1_mx2() ? 0x34 : 0x18) + +#define GPIO_INT_LOW_LEV (cpu_is_mx1_mx2() ? 0x3 : 0x0) +#define GPIO_INT_HIGH_LEV (cpu_is_mx1_mx2() ? 0x2 : 0x1) +#define GPIO_INT_RISE_EDGE (cpu_is_mx1_mx2() ? 0x0 : 0x2) +#define GPIO_INT_FALL_EDGE (cpu_is_mx1_mx2() ? 0x1 : 0x3) +#define GPIO_INT_NONE 0x4 + +/* Note: This driver assumes 32 GPIOs are handled in one register */ + +static void _clear_gpio_irqstatus(struct mxc_gpio_port *port, u32 index) +{ + __raw_writel(1 << index, port->base + GPIO_ISR); +} + +static void _set_gpio_irqenable(struct mxc_gpio_port *port, u32 index, + int enable) +{ + u32 l; + + l = __raw_readl(port->base + GPIO_IMR); + l = (l & (~(1 << index))) | (!!enable << index); + __raw_writel(l, port->base + GPIO_IMR); +} + +static void gpio_ack_irq(struct irq_data *d) +{ + u32 gpio = irq_to_gpio(d->irq); + _clear_gpio_irqstatus(&mxc_gpio_ports[gpio / 32], gpio & 0x1f); +} + +static void gpio_mask_irq(struct irq_data *d) +{ + u32 gpio = irq_to_gpio(d->irq); + _set_gpio_irqenable(&mxc_gpio_ports[gpio / 32], gpio & 0x1f, 0); +} + +static void gpio_unmask_irq(struct irq_data *d) +{ + u32 gpio = irq_to_gpio(d->irq); + _set_gpio_irqenable(&mxc_gpio_ports[gpio / 32], gpio & 0x1f, 1); +} + +static int mxc_gpio_get(struct gpio_chip *chip, unsigned offset); + +static int gpio_set_irq_type(struct irq_data *d, u32 type) +{ + u32 gpio = irq_to_gpio(d->irq); + struct mxc_gpio_port *port = &mxc_gpio_ports[gpio / 32]; + u32 bit, val; + int edge; + void __iomem *reg = port->base; + + port->both_edges &= ~(1 << (gpio & 31)); + switch (type) { + case IRQ_TYPE_EDGE_RISING: + edge = GPIO_INT_RISE_EDGE; + break; + case IRQ_TYPE_EDGE_FALLING: + edge = GPIO_INT_FALL_EDGE; + break; + case IRQ_TYPE_EDGE_BOTH: + val = mxc_gpio_get(&port->chip, gpio & 31); + if (val) { + edge = GPIO_INT_LOW_LEV; + pr_debug("mxc: set GPIO %d to low trigger\n", gpio); + } else { + edge = GPIO_INT_HIGH_LEV; + pr_debug("mxc: set GPIO %d to high trigger\n", gpio); + } + port->both_edges |= 1 << (gpio & 31); + break; + case IRQ_TYPE_LEVEL_LOW: + edge = GPIO_INT_LOW_LEV; + break; + case IRQ_TYPE_LEVEL_HIGH: + edge = GPIO_INT_HIGH_LEV; + break; + default: + return -EINVAL; + } + + reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */ + bit = gpio & 0xf; + val = __raw_readl(reg) & ~(0x3 << (bit << 1)); + __raw_writel(val | (edge << (bit << 1)), reg); + _clear_gpio_irqstatus(port, gpio & 0x1f); + + return 0; +} + +static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio) +{ + void __iomem *reg = port->base; + u32 bit, val; + int edge; + + reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */ + bit = gpio & 0xf; + val = __raw_readl(reg); + edge = (val >> (bit << 1)) & 3; + val &= ~(0x3 << (bit << 1)); + if (edge == GPIO_INT_HIGH_LEV) { + edge = GPIO_INT_LOW_LEV; + pr_debug("mxc: switch GPIO %d to low trigger\n", gpio); + } else if (edge == GPIO_INT_LOW_LEV) { + edge = GPIO_INT_HIGH_LEV; + pr_debug("mxc: switch GPIO %d to high trigger\n", gpio); + } else { + pr_err("mxc: invalid configuration for GPIO %d: %x\n", + gpio, edge); + return; + } + __raw_writel(val | (edge << (bit << 1)), reg); +} + +/* handle 32 interrupts in one status register */ +static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat) +{ + u32 gpio_irq_no_base = port->virtual_irq_start; + + while (irq_stat != 0) { + int irqoffset = fls(irq_stat) - 1; + + if (port->both_edges & (1 << irqoffset)) + mxc_flip_edge(port, irqoffset); + + generic_handle_irq(gpio_irq_no_base + irqoffset); + + irq_stat &= ~(1 << irqoffset); + } +} + +/* MX1 and MX3 has one interrupt *per* gpio port */ +static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc) +{ + u32 irq_stat; + struct mxc_gpio_port *port = irq_get_handler_data(irq); + struct irq_chip *chip = irq_get_chip(irq); + + chained_irq_enter(chip, desc); + + irq_stat = __raw_readl(port->base + GPIO_ISR) & + __raw_readl(port->base + GPIO_IMR); + + mxc_gpio_irq_handler(port, irq_stat); + + chained_irq_exit(chip, desc); +} + +/* MX2 has one interrupt *for all* gpio ports */ +static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc) +{ + int i; + u32 irq_msk, irq_stat; + struct mxc_gpio_port *port = irq_get_handler_data(irq); + + /* walk through all interrupt status registers */ + for (i = 0; i < gpio_table_size; i++) { + irq_msk = __raw_readl(port[i].base + GPIO_IMR); + if (!irq_msk) + continue; + + irq_stat = __raw_readl(port[i].base + GPIO_ISR) & irq_msk; + if (irq_stat) + mxc_gpio_irq_handler(&port[i], irq_stat); + } +} + +/* + * Set interrupt number "irq" in the GPIO as a wake-up source. + * While system is running, all registered GPIO interrupts need to have + * wake-up enabled. When system is suspended, only selected GPIO interrupts + * need to have wake-up enabled. + * @param irq interrupt source number + * @param enable enable as wake-up if equal to non-zero + * @return This function returns 0 on success. + */ +static int gpio_set_wake_irq(struct irq_data *d, u32 enable) +{ + u32 gpio = irq_to_gpio(d->irq); + u32 gpio_idx = gpio & 0x1F; + struct mxc_gpio_port *port = &mxc_gpio_ports[gpio / 32]; + + if (enable) { + if (port->irq_high && (gpio_idx >= 16)) + enable_irq_wake(port->irq_high); + else + enable_irq_wake(port->irq); + } else { + if (port->irq_high && (gpio_idx >= 16)) + disable_irq_wake(port->irq_high); + else + disable_irq_wake(port->irq); + } + + return 0; +} + +static struct irq_chip gpio_irq_chip = { + .name = "GPIO", + .irq_ack = gpio_ack_irq, + .irq_mask = gpio_mask_irq, + .irq_unmask = gpio_unmask_irq, + .irq_set_type = gpio_set_irq_type, + .irq_set_wake = gpio_set_wake_irq, +}; + +static void _set_gpio_direction(struct gpio_chip *chip, unsigned offset, + int dir) +{ + struct mxc_gpio_port *port = + container_of(chip, struct mxc_gpio_port, chip); + unsigned long flags; + + spin_lock_irqsave(&port->lock, flags); + port->dir = __raw_readl(port->base + GPIO_GDIR); + if (dir) + port->dir |= (1 << offset); + else + port->dir &= (~(1 << offset)); + __raw_writel(port->dir, port->base + GPIO_GDIR); + spin_unlock_irqrestore(&port->lock, flags); +} + +static void mxc_gpio_set(struct gpio_chip *chip, unsigned offset, int value) +{ + struct mxc_gpio_port *port = + container_of(chip, struct mxc_gpio_port, chip); + void __iomem *reg = port->base + GPIO_DR; + u32 l; + unsigned long flags; + + spin_lock_irqsave(&port->lock, flags); + l = (__raw_readl(reg) & (~(1 << offset))) | (!!value << offset); + __raw_writel(l, reg); + spin_unlock_irqrestore(&port->lock, flags); +} + +static int mxc_gpio_get(struct gpio_chip *chip, unsigned offset) +{ + struct mxc_gpio_port *port = + container_of(chip, struct mxc_gpio_port, chip); + u32 gpio_direction; + + gpio_direction = __raw_readl(port->base + GPIO_GDIR); + if (((gpio_direction >> offset) & 1)) /* output mode */ + return (__raw_readl(port->base + GPIO_DR) >> offset) & 1; + else /* input mode */ + return (__raw_readl(port->base + GPIO_PSR) >> offset) & 1; + +} + +static int mxc_gpio_direction_input(struct gpio_chip *chip, unsigned offset) +{ + _set_gpio_direction(chip, offset, 0); + return 0; +} + +static int mxc_gpio_direction_output(struct gpio_chip *chip, + unsigned offset, int value) +{ + mxc_gpio_set(chip, offset, value); + _set_gpio_direction(chip, offset, 1); + return 0; +} + +/* + * This lock class tells lockdep that GPIO irqs are in a different + * category than their parents, so it won't report false recursion. + */ +static struct lock_class_key gpio_lock_class; + +int mxc_gpio_init(struct mxc_gpio_port *port, int cnt) +{ + int i, j; + static bool initialed; + + /* save for local usage */ + mxc_gpio_ports = port; + gpio_table_size = cnt; + + printk(KERN_INFO "MXC GPIO hardware\n"); + + for (i = 0; i < cnt; i++) { + /* disable the interrupt and clear the status */ + __raw_writel(0, port[i].base + GPIO_IMR); + __raw_writel(~0, port[i].base + GPIO_ISR); + for (j = port[i].virtual_irq_start; + j < port[i].virtual_irq_start + 32; j++) { + irq_set_lockdep_class(j, &gpio_lock_class); + irq_set_chip_and_handler(j, &gpio_irq_chip, + handle_level_irq); + set_irq_flags(j, IRQF_VALID); + } + + /* register gpio chip */ + port[i].chip.direction_input = mxc_gpio_direction_input; + port[i].chip.direction_output = mxc_gpio_direction_output; + port[i].chip.get = mxc_gpio_get; + port[i].chip.set = mxc_gpio_set; + port[i].chip.base = i * 32; + port[i].chip.ngpio = 32; + port[i].dir = 0; + + spin_lock_init(&port[i].lock); + + if (!initialed) + /* its a serious configuration bug when it fails */ + BUG_ON(gpiochip_add(&port[i].chip) < 0); + + if (cpu_is_mx1() || cpu_is_mx3() || cpu_is_mx25() || + cpu_is_mx51() || cpu_is_mx53() || cpu_is_mx6q() || + cpu_is_mx6dl() || cpu_is_mx6sl()) { + /* setup one handler for each entry */ + irq_set_chained_handler(port[i].irq, + mx3_gpio_irq_handler); + irq_set_handler_data(port[i].irq, &port[i]); + if (port[i].irq_high) { + /* setup handler for GPIO 16 to 31 */ + irq_set_chained_handler(port[i].irq_high, + mx3_gpio_irq_handler); + irq_set_handler_data(port[i].irq_high, + &port[i]); + } + } + } + initialed = true; + if (cpu_is_mx2()) { + /* setup one handler for all GPIO interrupts */ + irq_set_chained_handler(port[0].irq, mx2_gpio_irq_handler); + irq_set_handler_data(port[0].irq, port); + } + + return 0; +} diff --git a/arch/arm/plat-mxc/include/mach/3ds_debugboard.h b/arch/arm/plat-mxc/include/mach/3ds_debugboard.h new file mode 100644 index 00000000..a384fdd4 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/3ds_debugboard.h @@ -0,0 +1,18 @@ +/* + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __ASM_ARCH_MXC_3DS_DB_H__ +#define __ASM_ARCH_MXC_3DS_DB_H__ + +extern int __init mxc_expio_init(u32 base, u32 p_irq); + +#endif /* __ASM_ARCH_MXC_3DS_DB_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/ahci_sata.h b/arch/arm/plat-mxc/include/mach/ahci_sata.h new file mode 100755 index 00000000..48b93e55 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/ahci_sata.h @@ -0,0 +1,62 @@ +/* + * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software Foundation, + * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __PLAT_MXC_AHCI_SATA_H__ +#define __PLAT_MXC_AHCI_SATA_H__ + +enum { + HOST_CAP = 0x00, + HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */ + HOST_CTL = 0x04, /* global host control */ + HOST_RESET = (1 << 0), /* reset controller; self-clear */ + HOST_PORTS_IMPL = 0x0c, + HOST_TIMER1MS = 0xe0, /* Timer 1-ms */ + HOST_VERSIONR = 0xfc, /* host version register*/ + + /* Offest used to control the MPLL input clk */ + PHY_CR_CLOCK_FREQ_OVRD = 0x12, + /* Port0 SATA Status */ + PORT_SATA_SR = 0x128, + /* Port0 PHY Control */ + PORT_PHY_CTL = 0x178, + /* PORT_PHY_CTL bits */ + PORT_PHY_CTL_CAP_ADR_LOC = 0x10000, + PORT_PHY_CTL_CAP_DAT_LOC = 0x20000, + PORT_PHY_CTL_WRITE_LOC = 0x40000, + PORT_PHY_CTL_READ_LOC = 0x80000, + PORT_PHY_CTL_PDDQ_LOC = 0x100000, + /* Port0 PHY Status */ + PORT_PHY_SR = 0x17c, + /* PORT_PHY_SR */ + PORT_PHY_STAT_DATA_LOC = 0, + PORT_PHY_STAT_ACK_LOC = 18, + /* SATA PHY Register */ + SATA_PHY_CR_CLOCK_CRCMP_LT_LIMIT = 0x0001, + SATA_PHY_CR_CLOCK_DAC_CTL = 0x0008, + SATA_PHY_CR_CLOCK_RTUNE_CTL = 0x0009, + SATA_PHY_CR_CLOCK_ADC_OUT = 0x000A, + SATA_PHY_CR_CLOCK_MPLL_TST = 0x0017, +}; + +extern int write_phy_ctl_ack_polling(u32 data, void __iomem *mmio, + int max_iterations, u32 exp_val); +extern int sata_phy_cr_addr(u32 addr, void __iomem *mmio); +extern int sata_phy_cr_write(u32 data, void __iomem *mmio); +extern int sata_phy_cr_read(u32 *data, void __iomem *mmio); +extern int sata_init(void __iomem *addr, unsigned long timer1ms); +#endif /* __PLAT_MXC_AHCI_SATA_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/anatop_thermal.h b/arch/arm/plat-mxc/include/mach/anatop_thermal.h new file mode 100644 index 00000000..7549bc59 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/anatop_thermal.h @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ +#ifndef __ASM_ARCH_IMX_ANATOP_THERMAL_H +#define __ASM_ARCH_IMX_ANATOP_THERMAL_H + +/** + * struct anatop_thermal_platform_data - optional platform data for thermal on i.MX + * + */ + +struct anatop_thermal_platform_data { + char *name; +}; +#endif /* __ASM_ARCH_IMX_ANATOP_THERMAL_H */ diff --git a/arch/arm/plat-mxc/include/mach/arc_otg.h b/arch/arm/plat-mxc/include/mach/arc_otg.h new file mode 100755 index 00000000..fdd84503 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/arc_otg.h @@ -0,0 +1,348 @@ +/* + * Copyright (C) 2005-2013 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ASM_ARCH_MXC_ARC_OTG_H__ +#define __ASM_ARCH_MXC_ARC_OTG_H__ + +#ifdef CONFIG_ARCH_MX3 +extern volatile u32 *mx3_usb_otg_addr; +#define OTG_BASE_ADDR mx3_usb_otg_addr +#else +extern void __iomem *imx_otg_base; +#define OTG_BASE_ADDR imx_otg_base +#endif + +#define USB_OTGREGS_BASE (OTG_BASE_ADDR + 0x000) +#define USB_H1REGS_BASE (OTG_BASE_ADDR + 0x200) +#define USB_H2REGS_BASE (OTG_BASE_ADDR + 0x400) +#if (defined CONFIG_ARCH_MX5 | defined CONFIG_ARCH_MX6) +#define USB_H3REGS_BASE (OTG_BASE_ADDR + 0x600) +#define USB_OTHERREGS_BASE (OTG_BASE_ADDR + 0x800) +#else +#define USB_OTHERREGS_BASE (OTG_BASE_ADDR + 0x600) +#endif + +#define USBOTG_REG32(offset) (*((volatile u32 __force *)(USB_OTGREGS_BASE + (offset)))) +#define USBOTG_REG16(offset) (*((volatile u16 __force *)(USB_OTGREGS_BASE + (offset)))) + +#define USBH1_REG32(offset) (*((volatile u32 __force *)(USB_H1REGS_BASE + (offset)))) +#define USBH1_REG16(offset) (*((volatile u16 __force *)(USB_H1REGS_BASE + (offset)))) + +#define USBH2_REG32(offset) (*((volatile u32 __force *)(USB_H2REGS_BASE + (offset)))) +#define USBH2_REG16(offset) (*((volatile u16 __force *)(USB_H2REGS_BASE + (offset)))) + +#define USBH3_REG32(offset) (*((volatile u32 __force *)(USB_H3REGS_BASE + (offset)))) +#define USBH3_REG16(offset) (*((volatile u16 __force *)(USB_H3REGS_BASE + (offset)))) + +#define USBOTHER_REG(offset) (*((volatile u32 __force *)(USB_OTHERREGS_BASE + (offset)))) + +/* + * OTG registers + */ +#define UOG_ID USBOTG_REG32(0x00) /* Host ID */ +#define UOG_HWGENERAL USBOTG_REG32(0x04) /* Host General */ +#define UOG_HWHOST USBOTG_REG32(0x08) /* Host h/w params */ +#define UOG_HWTXBUF USBOTG_REG32(0x10) /* TX buffer h/w params */ +#define UOG_HWRXBUF USBOTG_REG32(0x14) /* RX buffer h/w params */ +#define UOG_CAPLENGTH USBOTG_REG16(0x100) /* Capability register length */ +#define UOG_HCIVERSION USBOTG_REG16(0x102) /* Host Interface version */ +#define UOG_HCSPARAMS USBOTG_REG32(0x104) /* Host control structural params */ +#define UOG_HCCPARAMS USBOTG_REG32(0x108) /* control capability params */ +#define UOG_DCIVERSION USBOTG_REG32(0x120) /* device interface version */ +/* start EHCI registers: */ +#define UOG_USBCMD USBOTG_REG32(0x140) /* USB command register */ +#define UOG_USBSTS USBOTG_REG32(0x144) /* USB status register */ +#define UOG_USBINTR USBOTG_REG32(0x148) /* interrupt enable register */ +#define UOG_FRINDEX USBOTG_REG32(0x14c) /* USB frame index */ +/* segment (0x150) addr bits 63:32 if needed */ +#define UOG_PERIODICLISTBASE USBOTG_REG32(0x154) /* host crtlr frame list base addr */ +#define UOG_DEVICEADDR USBOTG_REG32(0x154) /* device crtlr device address */ +#define UOG_ASYNCLISTADDR USBOTG_REG32(0x158) /* host ctrlr next async addr */ +#define UOG_EPLISTADDR USBOTG_REG32(0x158) /* device ctrlr endpoint list addr */ +#define UOG_BURSTSIZE USBOTG_REG32(0x160) /* host ctrlr embedded TT async buf status */ +#define UOG_TXFILLTUNING USBOTG_REG32(0x164) /* TX FIFO fill tuning */ +#define UOG_ULPIVIEW USBOTG_REG32(0x170) /* ULPI viewport */ +#define UOG_CFGFLAG USBOTG_REG32(0x180) /* configflag (supports HS) */ +#define UOG_PORTSC1 USBOTG_REG32(0x184) /* port status and control */ +/* end EHCI registers: */ +#define UOG_OTGSC USBOTG_REG32(0x1a4) /* OTG status and control */ +#define UOG_USBMODE USBOTG_REG32(0x1a8) /* USB device mode */ +#define UOG_ENDPTSETUPSTAT USBOTG_REG32(0x1ac) /* endpoint setup status */ +#define UOG_ENDPTPRIME USBOTG_REG32(0x1b0) /* endpoint initialization */ +#define UOG_ENDPTFLUSH USBOTG_REG32(0x1b4) /* endpoint de-initialize */ +#define UOG_ENDPTSTAT USBOTG_REG32(0x1b8) /* endpoint status */ +#define UOG_ENDPTCOMPLETE USBOTG_REG32(0x1bc) /* endpoint complete */ +#define UOG_EPCTRL0 USBOTG_REG32(0x1c0) /* endpoint control0 */ +#define UOG_EPCTRL1 USBOTG_REG32(0x1c4) /* endpoint control1 */ +#define UOG_EPCTRL2 USBOTG_REG32(0x1c8) /* endpoint control2 */ +#define UOG_EPCTRL3 USBOTG_REG32(0x1cc) /* endpoint control3 */ +#define UOG_EPCTRL4 USBOTG_REG32(0x1d0) /* endpoint control4 */ +#define UOG_EPCTRL5 USBOTG_REG32(0x1d4) /* endpoint control5 */ +#define UOG_EPCTRL6 USBOTG_REG32(0x1d8) /* endpoint control6 */ +#define UOG_EPCTRL7 USBOTG_REG32(0x1dc) /* endpoint control7 */ + +/* + * Host 1 registers + */ +#define UH1_ID USBH1_REG32(0x00) /* Host ID */ +#define UH1_HWGENERAL USBH1_REG32(0x04) /* Host General */ +#define UH1_HWHOST USBH1_REG32(0x08) /* Host h/w params */ +#define UH1_HWTXBUF USBH1_REG32(0x10) /* TX buffer h/w params */ +#define UH1_HWRXBUF USBH1_REG32(0x14) /* RX buffer h/w params */ +#define UH1_CAPLENGTH USBH1_REG16(0x100) /* Capability register length */ +#define UH1_HCIVERSION USBH1_REG16(0x102) /* Host Interface version */ +#define UH1_HCSPARAMS USBH1_REG32(0x104) /* Host control structural params */ +#define UH1_HCCPARAMS USBH1_REG32(0x108) /* control capability params */ +/* start EHCI registers: */ +#define UH1_USBCMD USBH1_REG32(0x140) /* USB command register */ +#define UH1_USBSTS USBH1_REG32(0x144) /* USB status register */ +#define UH1_USBINTR USBH1_REG32(0x148) /* interrupt enable register */ +#define UH1_FRINDEX USBH1_REG32(0x14c) /* USB frame index */ +/* segment (0x150) addr bits 63:32 if needed */ +#define UH1_PERIODICLISTBASE USBH1_REG32(0x154) /* host crtlr frame list base addr */ +#define UH1_ASYNCLISTADDR USBH1_REG32(0x158) /* host ctrlr nest async addr */ +#define UH1_BURSTSIZE USBH1_REG32(0x160) /* host ctrlr embedded TT async buf status */ +#define UH1_TXFILLTUNING USBH1_REG32(0x164) /* TX FIFO fill tuning */ +/* configured_flag (0x180) configflag (supports HS) */ +#define UH1_PORTSC1 USBH1_REG32(0x184) /* port status and control */ +/* end EHCI registers: */ +#define UH1_OTGSC USBH1_REG32(0x1a4) /* OTG status and control */ +#define UH1_USBMODE USBH1_REG32(0x1a8) /* USB device mode */ + +/* + * Host 2 registers + */ +#define UH2_ID USBH2_REG32(0x00) /* Host ID */ +#define UH2_HWGENERAL USBH2_REG32(0x04) /* Host General */ +#define UH2_HWHOST USBH2_REG32(0x08) /* Host h/w params */ +#define UH2_HWTXBUF USBH2_REG32(0x10) /* TX buffer h/w params */ +#define UH2_HWRXBUF USBH2_REG32(0x14) /* RX buffer h/w params */ +#define UH2_CAPLENGTH USBH2_REG16(0x100) /* Capability register length */ +#define UH2_HCIVERSION USBH2_REG16(0x102) /* Host Interface version */ +#define UH2_HCSPARAMS USBH2_REG32(0x104) /* Host control structural params */ +#define UH2_HCCPARAMS USBH2_REG32(0x108) /* control capability params */ +/* start EHCI registers: */ +#define UH2_USBCMD USBH2_REG32(0x140) /* USB command register */ +#define UH2_USBSTS USBH2_REG32(0x144) /* USB status register */ +#define UH2_USBINTR USBH2_REG32(0x148) /* interrupt enable register */ +#define UH2_FRINDEX USBH2_REG32(0x14c) /* USB frame index */ +/* segment (0x150) addr bits 63:32 if needed */ +#define UH2_PERIODICLISTBASE USBH2_REG32(0x154) /* host crtlr frame list base addr */ +#define UH2_ASYNCLISTADDR USBH2_REG32(0x158) /* host ctrlr nest async addr */ +#define UH2_BURSTSIZE USBH2_REG32(0x160) /* host ctrlr embedded TT async buf status */ +#define UH2_TXFILLTUNING USBH2_REG32(0x164) /* TX FIFO fill tuning */ +#define UH2_ULPIVIEW USBH2_REG32(0x170) /* ULPI viewport */ +/* configured_flag (0x180) configflag (supports HS) */ +#define UH2_PORTSC1 USBH2_REG32(0x184) /* port status and control */ +/* end EHCI registers */ +#define UH2_USBMODE USBH2_REG32(0x1a8) /* USB device mode */ +/* + * Host 2 registers + */ +#define UH2_ID USBH2_REG32(0x00) /* Host ID */ +#define UH2_HWGENERAL USBH2_REG32(0x04) /* Host General */ +#define UH2_HWHOST USBH2_REG32(0x08) /* Host h/w params */ +#define UH2_HWTXBUF USBH2_REG32(0x10) /* TX buffer h/w params */ +#define UH2_HWRXBUF USBH2_REG32(0x14) /* RX buffer h/w params */ +#define UH2_CAPLENGTH USBH2_REG16(0x100) /* Capability register length */ +#define UH2_HCIVERSION USBH2_REG16(0x102) /* Host Interface version */ +#define UH2_HCSPARAMS USBH2_REG32(0x104) /* Host control structural params */ +#define UH2_HCCPARAMS USBH2_REG32(0x108) /* control capability params */ +/* start EHCI registers: */ +#define UH2_USBCMD USBH2_REG32(0x140) /* USB command register */ +#define UH2_USBSTS USBH2_REG32(0x144) /* USB status register */ +#define UH2_USBINTR USBH2_REG32(0x148) /* interrupt enable register */ +#define UH2_FRINDEX USBH2_REG32(0x14c) /* USB frame index */ +/* segment (0x150) addr bits 63:32 if needed */ +#define UH2_PERIODICLISTBASE USBH2_REG32(0x154) /* host crtlr frame list base addr */ +#define UH2_ASYNCLISTADDR USBH2_REG32(0x158) /* host ctrlr nest async addr */ +#define UH2_BURSTSIZE USBH2_REG32(0x160) /* host ctrlr embedded TT async buf status */ +#define UH2_TXFILLTUNING USBH2_REG32(0x164) /* TX FIFO fill tuning */ +#define UH2_ULPIVIEW USBH2_REG32(0x170) /* ULPI viewport */ +/* configured_flag (0x180) configflag (supports HS) */ +#define UH2_PORTSC1 USBH2_REG32(0x184) /* port status and control */ +/* end EHCI registers */ +#define UH2_USBMODE USBH2_REG32(0x1a8) /* USB device mode */ +/* + * Host 2 registers + */ +#define UH3_ID USBH3_REG32(0x00) /* Host ID */ +#define UH3_HWGENERAL USBH3_REG32(0x04) /* Host General */ +#define UH3_HWHOST USBH3_REG32(0x08) /* Host h/w params */ +#define UH3_HWTXBUF USBH3_REG32(0x10) /* TX buffer h/w params */ +#define UH3_HWRXBUF USBH3_REG32(0x14) /* RX buffer h/w params */ +#define UH3_CAPLENGTH USBH3_REG16(0x100) /* Capability register length */ +#define UH3_HCIVERSION USBH3_REG16(0x102) /* Host Interface version */ +#define UH3_HCSPARAMS USBH3_REG32(0x104) /* Host control structural params */ +#define UH3_HCCPARAMS USBH3_REG32(0x108) /* control capability params */ +/* start EHCI registers: */ +#define UH3_USBCMD USBH3_REG32(0x140) /* USB command register */ +#define UH3_USBSTS USBH3_REG32(0x144) /* USB status register */ +#define UH3_USBINTR USBH3_REG32(0x148) /* interrupt enable register */ +#define UH3_FRINDEX USBH3_REG32(0x14c) /* USB frame index */ +/* segment (0x150) addr bits 63:32 if needed */ +#define UH3_PERIODICLISTBASE USBH3_REG32(0x154) /* host crtlr frame list base addr */ +#define UH3_ASYNCLISTADDR USBH3_REG32(0x158) /* host ctrlr nest async addr */ +#define UH3_BURSTSIZE USBH3_REG32(0x160) /* host ctrlr embedded TT async buf status */ +#define UH3_TXFILLTUNING USBH3_REG32(0x164) /* TX FIFO fill tuning */ +#define UH3_ULPIVIEW USBH3_REG32(0x170) /* ULPI viewport */ +/* configured_flag (0x180) configflag (supports HS) */ +#define UH3_PORTSC1 USBH3_REG32(0x184) /* port status and control */ +/* end EHCI registers */ +#define UH3_USBMODE USBH3_REG32(0x1a8) /* USB device mode */ + +/* + * other regs (not part of ARC core) + */ +#define USBCTRL USBOTHER_REG(0x00) /* USB Control register */ +#define USB_OTG_MIRROR USBOTHER_REG(0x04) /* USB OTG mirror register */ +#define USB_PHY_CTR_FUNC USBOTHER_REG(0x08) /* OTG UTMI PHY Function Control register */ +#define USB_PHY_CTR_FUNC2 USBOTHER_REG(0x0c) /* OTG UTMI PHY Function Control register */ +#define USB_CTRL_1 USBOTHER_REG(0x10) /* USB Cotrol Register 1*/ +#define USBCTRL_HOST2 USBOTHER_REG(0x14) /* USB Cotrol Register 1*/ +#define USBCTRL_HOST3 USBOTHER_REG(0x18) /* USB Cotrol Register 1*/ +#define USBH1_PHY_CTRL0 USBOTHER_REG(0x1c) /* USB Cotrol Register 1*/ +#define USBH1_PHY_CTRL1 USBOTHER_REG(0x20) /* USB Cotrol Register 1*/ +#define USB_CLKONOFF_CTRL USBOTHER_REG(0x24) /* USB Clock on/off Control Register */ + +/* mx6x other regs */ +#define USB_OTG_CTRL USBOTHER_REG(0x00) /* USB OTG Control register */ +#define USB_H1_CTRL USBOTHER_REG(0x04) /* USB H1 Control register */ +#define USB_H2_CTRL USBOTHER_REG(0x08) /* USB H2 Control register */ +#define USB_H3_CTRL USBOTHER_REG(0x0c) /* USB H3 Control register */ +#define USB_UH2_HSIC_CTRL USBOTHER_REG(0x10) /* USB Host2 HSIC Control Register */ +#define USB_UH3_HSIC_CTRL USBOTHER_REG(0x14) /* USB Host3 HSIC Control Register */ +#define USB_OTG_PHY_CTRL_0 USBOTHER_REG(0x18) /* OTG UTMI PHY Control 0 Register */ +#define USB_H1_PHY_CTRL_0 USBOTHER_REG(0x1c) /* OTG UTMI PHY Control 1 Register */ +#define USB_UH2_HSIC_DLL_CFG1 USBOTHER_REG(0x20) /* USB Host2 HSIC DLL Configuration Register 1 */ +#define USB_UH2_HSIC_DLL_CFG2 USBOTHER_REG(0x24) /* USB Host2 HSIC DLL Configuration Register 2 */ +#define USB_UH2_HSIC_DLL_CFG3 USBOTHER_REG(0x28) /* USB Host2 HSIC DLL Configuration Register 3 */ +#define USB_UH3_HSIC_DLL_CFG1 USBOTHER_REG(0x30) /* USB Host3 HSIC DLL Configuration Register 1 */ +#define USB_UH3_HSIC_DLL_CFG2 USBOTHER_REG(0x34) /* USB Host3 HSIC DLL Configuration Register 2 */ +#define USB_UH3_HSIC_DLL_CFG3 USBOTHER_REG(0x38) /* USB Host3 HSIC DLL Configuration Register 3 */ +/* + * register bits + */ + +/* x_PORTSCx */ +#define PORTSC_PTS_MASK (3 << 30) /* parallel xcvr select mask */ +#define PORTSC_PTS_UTMI (0 << 30) /* UTMI/UTMI+ */ +#define PORTSC_PTS_PHILIPS (1 << 30) /* Philips classic */ +#define PORTSC_PTS_ULPI (2 << 30) /* ULPI */ +#define PORTSC_PTS_SERIAL (3 << 30) /* serial */ +#define PORTSC_STS (1 << 29) /* serial xcvr select */ +#define PORTSC_PTW (1 << 28) /* UTMI width */ +#define PORTSC_PORT_SPEED_FULL (0x0<<26) +#define PORTSC_PORT_SPEED_LOW (0x1<<26) +#define PORTSC_PORT_SPEED_HIGH (0x2<<26) +#define PORTSC_PORT_SPEED_UNDEF (0x3<<26) +#define PORTSC_PORT_SPEED_MASK (0x3<<26) +#define PORTSC_HSIC_MODE (1 << 25) /* Only for HSIC */ +#define PORTSC_PHCD (1 << 23) /* Low Power Suspend */ +#define PORTSC_WKDC (1 << 21) /* wakeup on discnt*/ +#define PORTSC_WKCN (1 << 20) /* wakeup on connect*/ +#define PORTSC_PORT_POWER (1 << 12) /* port power */ +#define PORTSC_LS_MASK (3 << 10) /* Line State mask */ +#define PORTSC_LS_SE0 (0 << 10) /* SE0 */ +#define PORTSC_LS_K_STATE (1 << 10) /* K-state */ +#define PORTSC_LS_J_STATE (2 << 10) /* J-state */ +#define PORTSC_PORT_RESET (1 << 8) /* Port reset */ +#define PORTSC_PORT_SUSPEND (1 << 7) /* Suspend */ +#define PORTSC_PORT_FORCE_RESUME (1 << 6) /* Force port resume */ +#define PORTSC_OVER_CURRENT_CHG (1 << 5) /* over current change */ +#define PORTSC_OVER_CURRENT_ACT (1 << 4) /* over currrent active */ +#define PORTSC_PORT_EN_DIS_CHANGE (1 << 3) /* port {en,dis}able change */ +#define PORTSC_PORT_ENABLE (1 << 2) /* port enabled */ +#define PORTSC_CONNECT_STATUS_CHANGE (1 << 1) /* connect status change */ +#define PORTSC_CURRENT_CONNECT_STATUS (1 << 0) /* current connect status */ + +#define PORTSC_W1C_BITS \ + (PORTSC_CONNECT_STATUS_CHANGE | \ + PORTSC_PORT_EN_DIS_CHANGE | \ + PORTSC_OVER_CURRENT_CHG) + +/* UOG_OTGSC Register Bits */ +/* control bits: */ +#define OTGSC_CTRL_VBUS_DISCHARGE (1 << 0) +#define OTGSC_CTRL_VBUS_CHARGE (1 << 1) +#define OTGSC_CTRL_OTG_TERM (1 << 3) /* controls DM pulldown */ +#define OTGSC_CTRL_DATA_PULSING (1 << 4) +#define OTGSC_CTRL_USB_ID_PU (1 << 5) /* enable ID pullup */ +/* current status: (R/O) */ +#define OTGSC_STS_USB_ID (1 << 8) /* 0=A-device 1=B-device */ +#define OTGSC_STS_A_VBUS_VALID (1 << 9) +#define OTGSC_STS_A_SESSION_VALID (1 << 10) +#define OTGSC_STS_B_SESSION_VALID (1 << 11) +#define OTGSC_STS_B_SESSION_END (1 << 12) +#define OTGSC_STS_1ms_TIMER (1 << 13) +#define OTGSC_STS_DATA_PULSE (1 << 14) +/* interrupt status: (write to clear) */ +#define OTGSC_IS_MASK (0x7f << 16) +#define OTGSC_IS_USB_ID (1 << 16) +#define OTGSC_IS_A_VBUS_VALID (1 << 17) +#define OTGSC_IS_A_SESSION_VALID (1 << 18) +#define OTGSC_IS_B_SESSION_VALID (1 << 19) +#define OTGSC_IS_B_SESSION_END (1 << 20) +#define OTGSC_IS_1ms_TIMER (1 << 21) +#define OTGSC_IS_DATA_PULSE (1 << 22) +/* interrupt enables: */ +#define OTGSC_IE_MASK (0x7f << 24) +#define OTGSC_IE_USB_ID (1 << 24) +#define OTGSC_IE_A_VBUS_VALID (1 << 25) +#define OTGSC_IE_A_SESSION_VALID (1 << 26) +#define OTGSC_IE_B_SESSION_VALID (1 << 27) +#define OTGSC_IE_B_SESSION_END (1 << 28) +#define OTGSC_IE_1ms_TIMER (1 << 29) +#define OTGSC_IE_DATA_PULSE (1 << 30) + +/* UOG_USBSTS bits */ +#define USBSTS_PCI (1 << 2) /* Port Change Detect */ +#define USBSTS_URI (1 << 6) /* USB Reset Received */ + +/* USBCMD */ +#define UCMD_RUN_STOP (1 << 0) /* controller run/stop */ +#define UCMD_RESET (1 << 1) /* controller reset */ +#define UCMD_ITC_NO_THRESHOLD (~(0xff << 16)) /* Interrupt Threshold Control */ + +#if 1 /* FIXME these here for compatibility between my names and Leo's */ +/* OTG interrupt enable bit masks */ +#define OTGSC_INTERRUPT_ENABLE_BITS_MASK OTGSC_IE_MASK +#define OTGSC_INTSTS_MASK OTGSC_IS_MASK + +/* OTG interrupt status bit masks */ +#define OTGSC_INTERRUPT_STATUS_BITS_MASK OTGSC_IS_MASK +#endif + +/* x_USBMODE */ +#define USBMODE_SLOM (1 << 3) /* setup lockout mode */ +#define USBMODE_ES (1 << 2) /* (big) endian select */ +#define USBMODE_CM_MASK (3 << 0) /* controller mode mask */ +#define USBMODE_CM_HOST (3 << 0) /* host */ +#define USBMODE_CM_DEVICE (2 << 0) /* device */ +#define USBMODE_CM_reserved (1 << 0) /* reserved */ + +#define HCSPARAMS_PPC (0x1<<4) /* Port Power Control */ +extern enum fsl_usb2_modes get_usb_mode(struct fsl_usb2_platform_data *pdata); +#ifdef CONFIG_ARCH_MX6 +#include "regs-usbphy-mx6.h" +#else +#include "regs-usbphy-others.h" +#endif + +#endif /* __ASM_ARCH_MXC_ARC_OTG_H__ */ + diff --git a/arch/arm/plat-mxc/include/mach/audmux.h b/arch/arm/plat-mxc/include/mach/audmux.h new file mode 100644 index 00000000..6fda788e --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/audmux.h @@ -0,0 +1,60 @@ +#ifndef __MACH_AUDMUX_H +#define __MACH_AUDMUX_H + +#define MX27_AUDMUX_HPCR1_SSI0 0 +#define MX27_AUDMUX_HPCR2_SSI1 1 +#define MX27_AUDMUX_HPCR3_SSI_PINS_4 2 +#define MX27_AUDMUX_PPCR1_SSI_PINS_1 3 +#define MX27_AUDMUX_PPCR2_SSI_PINS_2 4 +#define MX27_AUDMUX_PPCR3_SSI_PINS_3 5 + +#define MX31_AUDMUX_PORT1_SSI0 0 +#define MX31_AUDMUX_PORT2_SSI1 1 +#define MX31_AUDMUX_PORT3_SSI_PINS_3 2 +#define MX31_AUDMUX_PORT4_SSI_PINS_4 3 +#define MX31_AUDMUX_PORT5_SSI_PINS_5 4 +#define MX31_AUDMUX_PORT6_SSI_PINS_6 5 + +#define MX51_AUDMUX_PORT1_SSI0 0 +#define MX51_AUDMUX_PORT2_SSI1 1 +#define MX51_AUDMUX_PORT3 2 +#define MX51_AUDMUX_PORT4 3 +#define MX51_AUDMUX_PORT5 4 +#define MX51_AUDMUX_PORT6 5 +#define MX51_AUDMUX_PORT7 6 + +/* Register definitions for the i.MX21/27 Digital Audio Multiplexer */ +#define MXC_AUDMUX_V1_PCR_INMMASK(x) ((x) & 0xff) +#define MXC_AUDMUX_V1_PCR_INMEN (1 << 8) +#define MXC_AUDMUX_V1_PCR_TXRXEN (1 << 10) +#define MXC_AUDMUX_V1_PCR_SYN (1 << 12) +#define MXC_AUDMUX_V1_PCR_RXDSEL(x) (((x) & 0x7) << 13) +#define MXC_AUDMUX_V1_PCR_RFCSEL(x) (((x) & 0xf) << 20) +#define MXC_AUDMUX_V1_PCR_RCLKDIR (1 << 24) +#define MXC_AUDMUX_V1_PCR_RFSDIR (1 << 25) +#define MXC_AUDMUX_V1_PCR_TFCSEL(x) (((x) & 0xf) << 26) +#define MXC_AUDMUX_V1_PCR_TCLKDIR (1 << 30) +#define MXC_AUDMUX_V1_PCR_TFSDIR (1 << 31) + +/* Register definitions for the i.MX25/31/35/51 Digital Audio Multiplexer */ +#define MXC_AUDMUX_V2_PTCR_TFSDIR (1 << 31) +#define MXC_AUDMUX_V2_PTCR_TFSEL(x) (((x) & 0xf) << 27) +#define MXC_AUDMUX_V2_PTCR_TCLKDIR (1 << 26) +#define MXC_AUDMUX_V2_PTCR_TCSEL(x) (((x) & 0xf) << 22) +#define MXC_AUDMUX_V2_PTCR_RFSDIR (1 << 21) +#define MXC_AUDMUX_V2_PTCR_RFSEL(x) (((x) & 0xf) << 17) +#define MXC_AUDMUX_V2_PTCR_RCLKDIR (1 << 16) +#define MXC_AUDMUX_V2_PTCR_RCSEL(x) (((x) & 0xf) << 12) +#define MXC_AUDMUX_V2_PTCR_SYN (1 << 11) + +#define MXC_AUDMUX_V2_PDCR_RXDSEL(x) (((x) & 0x7) << 13) +#define MXC_AUDMUX_V2_PDCR_TXRXEN (1 << 12) +#define MXC_AUDMUX_V2_PDCR_MODE(x) (((x) & 0x3) << 8) +#define MXC_AUDMUX_V2_PDCR_INMMASK(x) ((x) & 0xff) + +int mxc_audmux_v1_configure_port(unsigned int port, unsigned int pcr); + +int mxc_audmux_v2_configure_port(unsigned int port, unsigned int ptcr, + unsigned int pdcr); + +#endif /* __MACH_AUDMUX_H */ diff --git a/arch/arm/plat-mxc/include/mach/board-mx31ads.h b/arch/arm/plat-mxc/include/mach/board-mx31ads.h new file mode 100644 index 00000000..94b60dd4 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/board-mx31ads.h @@ -0,0 +1,33 @@ +/* + * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_MXC_BOARD_MX31ADS_H__ +#define __ASM_ARCH_MXC_BOARD_MX31ADS_H__ + +#include <mach/hardware.h> + +/* + * These symbols are used by drivers/net/cs89x0.c. + * This is ugly as hell, but we have to provide them until + * someone fixed the driver. + */ + +/* Base address of PBC controller */ +#define PBC_BASE_ADDRESS MX31_CS4_BASE_ADDR_VIRT +/* Offsets for the PBC Controller register */ + +/* Ethernet Controller IO base address */ +#define PBC_CS8900A_IOBASE 0x020000 + +#define MXC_EXP_IO_BASE (MXC_BOARD_IRQ_START) + +#define EXPIO_INT_ENET_INT (MXC_EXP_IO_BASE + 8) + +#endif /* __ASM_ARCH_MXC_BOARD_MX31ADS_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/board-mx31lilly.h b/arch/arm/plat-mxc/include/mach/board-mx31lilly.h new file mode 100644 index 00000000..0df71bfe --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/board-mx31lilly.h @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2009 Daniel Mack <daniel@caiaq.de> + * + * Based on code for mobots boards, + * Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#ifndef __ASM_ARCH_MXC_BOARD_MX31LILLY_H__ +#define __ASM_ARCH_MXC_BOARD_MX31LILLY_H__ + +#ifndef __ASSEMBLY__ + +enum mx31lilly_boards { + MX31LILLY_NOBOARD = 0, + MX31LILLY_DB = 1, +}; + +/* + * This CPU module needs a baseboard to work. After basic initializing + * its own devices, it calls the baseboard's init function. + */ + +extern void mx31lilly_db_init(void); + +#endif + +#endif /* __ASM_ARCH_MXC_BOARD_MX31LILLY_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/board-mx31lite.h b/arch/arm/plat-mxc/include/mach/board-mx31lite.h new file mode 100644 index 00000000..c1ad0ae8 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/board-mx31lite.h @@ -0,0 +1,42 @@ +/* + * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2009 Daniel Mack <daniel@caiaq.de> + * + * Based on code for mobots boards, + * Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#ifndef __ASM_ARCH_MXC_BOARD_MX31LITE_H__ +#define __ASM_ARCH_MXC_BOARD_MX31LITE_H__ + +#ifndef __ASSEMBLY__ + +enum mx31lite_boards { + MX31LITE_NOBOARD = 0, + MX31LITE_DB = 1, +}; + +/* + * This CPU module needs a baseboard to work. After basic initializing + * its own devices, it calls the baseboard's init function. + */ + +extern void mx31lite_db_init(void); + +#endif + +#endif /* __ASM_ARCH_MXC_BOARD_MX31LITE_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/board-mx31moboard.h b/arch/arm/plat-mxc/include/mach/board-mx31moboard.h new file mode 100644 index 00000000..de145438 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/board-mx31moboard.h @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#ifndef __ASM_ARCH_MXC_BOARD_MX31MOBOARD_H__ +#define __ASM_ARCH_MXC_BOARD_MX31MOBOARD_H__ + +#ifndef __ASSEMBLY__ + +enum mx31moboard_boards { + MX31NOBOARD = 0, + MX31DEVBOARD = 1, + MX31MARXBOT = 2, + MX31SMARTBOT = 3, + MX31EYEBOT = 4, +}; + +/* + * This CPU module needs a baseboard to work. After basic initializing + * its own devices, it calls the baseboard's init function. + */ + +extern void mx31moboard_devboard_init(void); +extern void mx31moboard_marxbot_init(void); +extern void mx31moboard_smartbot_init(int board); + +#endif + +#endif /* __ASM_ARCH_MXC_BOARD_MX31MOBOARD_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/board-pcm038.h b/arch/arm/plat-mxc/include/mach/board-pcm038.h new file mode 100644 index 00000000..6f371e35 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/board-pcm038.h @@ -0,0 +1,36 @@ +/* + * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#ifndef __ASM_ARCH_MXC_BOARD_PCM038_H__ +#define __ASM_ARCH_MXC_BOARD_PCM038_H__ + +#ifndef __ASSEMBLY__ +/* + * This CPU module needs a baseboard to work. After basic initializing + * its own devices, it calls the baseboard's init function. + * TODO: Add your own baseboard init function and call it from + * inside pcm038_init(). + * + * This example here is for the development board. Refer pcm970-baseboard.c + */ + +extern void pcm970_baseboard_init(void); + +#endif + +#endif /* __ASM_ARCH_MXC_BOARD_PCM038_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/clkdev.h b/arch/arm/plat-mxc/include/mach/clkdev.h new file mode 100644 index 00000000..04b37a89 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/clkdev.h @@ -0,0 +1,7 @@ +#ifndef __ASM_MACH_CLKDEV_H +#define __ASM_MACH_CLKDEV_H + +#define __clk_get(clk) ({ 1; }) +#define __clk_put(clk) do { } while (0) + +#endif diff --git a/arch/arm/plat-mxc/include/mach/clock.h b/arch/arm/plat-mxc/include/mach/clock.h new file mode 100755 index 00000000..e150579e --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/clock.h @@ -0,0 +1,85 @@ +/* + * Copyright 2005-2012 Freescale Semiconductor, Inc. + * Copyright 2008 Juergen Beisert, kernel@pengutronix.de + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#ifndef __ASM_ARCH_MXC_CLOCK_H__ +#define __ASM_ARCH_MXC_CLOCK_H__ + +#ifndef __ASSEMBLY__ +#include <linux/list.h> + +#define CLK_NAME_LEN 32 +struct module; + +struct clk { +#ifdef CONFIG_CLK_DEBUG + char name[CLK_NAME_LEN]; + struct dentry *dentry; +#endif + int id; + /* Source clock this clk depends on */ + struct clk *parent; + /* Secondary clock to enable/disable with this clock */ + struct clk *secondary; + /* Reference count of clock enable/disable */ + __s8 usecount; + /* Register bit position for clock's enable/disable control. */ + u8 enable_shift; + /* Register address for clock's enable/disable control. */ + void __iomem *enable_reg; + u32 flags; + /* get the current clock rate (always a fresh value) */ + unsigned long (*get_rate) (struct clk *); + /* Function ptr to set the clock to a new rate. The rate must match a + supported rate returned from round_rate. Leave blank if clock is not + programmable */ + int (*set_rate) (struct clk *, unsigned long); + /* Function ptr to round the requested clock rate to the nearest + supported rate that is less than or equal to the requested rate. */ + unsigned long (*round_rate) (struct clk *, unsigned long); + /* Function ptr to enable the clock. Leave blank if clock can not + be gated. */ + int (*enable) (struct clk *); + /* Function ptr to disable the clock. Leave blank if clock can not + be gated. */ + void (*disable) (struct clk *); + /* Function ptr to set the parent clock of the clock. */ + int (*set_parent) (struct clk *, struct clk *); +}; + +int clk_get_usecount(struct clk *clk); + +/* Clock flags */ +#define RATE_PROPAGATES (1 << 0) /* Program children too */ +#define ALWAYS_ENABLED (1 << 1) /* Clock cannot be disabled */ +#define RATE_FIXED (1 << 2) /* Fixed clock rate */ +#define CPU_FREQ_TRIG_UPDATE (1 << 3) /* CPUFREQ trig update */ +#define AHB_HIGH_SET_POINT (1 << 4) /* Requires max AHB clock */ +#define AHB_MED_SET_POINT (1 << 5) /* Requires med AHB clock */ +#define AHB_AUDIO_SET_POINT (1 << 6) /* Requires LOW AHB, but higher DDR clock */ + +unsigned long mxc_decode_pll(unsigned int pll, u32 f_ref); + +#ifdef CONFIG_CLK_DEBUG +void clk_debug_register(struct clk *clk); +#else +static inline void clk_debug_register(struct clk *clk) {} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ASM_ARCH_MXC_CLOCK_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h new file mode 100755 index 00000000..3dfc6646 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/common.h @@ -0,0 +1,98 @@ +/* + * Copyright (C) 2004-2012 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ASM_ARCH_MXC_COMMON_H__ +#define __ASM_ARCH_MXC_COMMON_H__ + +struct fec_platform_data; +struct platform_device; +struct clk; + +extern char *gp_reg_id; +extern void mx1_map_io(void); +extern void mx21_map_io(void); +extern void mx25_map_io(void); +extern void mx27_map_io(void); +extern void mx31_map_io(void); +extern void mx35_map_io(void); +extern void mx50_map_io(void); +extern void mx51_map_io(void); +extern void mx53_map_io(void); +extern void mx6_map_io(void); +extern void mxc91231_map_io(void); +extern void imx1_init_early(void); +extern void imx21_init_early(void); +extern void imx25_init_early(void); +extern void imx27_init_early(void); +extern void imx31_init_early(void); +extern void imx35_init_early(void); +extern void imx50_init_early(void); +extern void imx51_init_early(void); +extern void imx53_init_early(void); +extern void mxc91231_init_early(void); +extern void mxc_init_irq(void __iomem *); +extern void tzic_init_irq(void __iomem *); +extern void mx1_init_irq(void); +extern void mx21_init_irq(void); +extern void mx25_init_irq(void); +extern void mx27_init_irq(void); +extern void mx31_init_irq(void); +extern void mx35_init_irq(void); +extern void mx50_init_irq(void); +extern void mx51_init_irq(void); +extern void mx53_init_irq(void); +extern void mx6_init_irq(void); +extern void mxc91231_init_irq(void); +extern void epit_timer_init(struct clk *timer_clk, void __iomem *base, int irq); +extern void mxc_timer_init(struct clk *timer_clk, void __iomem *, int); +extern int mx1_clocks_init(unsigned long fref); +extern int mx21_clocks_init(unsigned long lref, unsigned long fref); +extern int mx25_clocks_init(void); +extern int mx27_clocks_init(unsigned long fref); +extern int mx31_clocks_init(unsigned long fref); +extern int mx35_clocks_init(void); +extern int mx51_clocks_init(unsigned long ckil, unsigned long osc, + unsigned long ckih1, unsigned long ckih2); +extern int mx53_clocks_init(unsigned long ckil, unsigned long osc, + unsigned long ckih1, unsigned long ckih2); +extern int mx50_clocks_init(unsigned long ckil, unsigned long osc, + unsigned long ckih1); +extern int mx6_clocks_init(unsigned long ckil, unsigned long osc, + unsigned long ckih1, unsigned long ckih2); +extern int mx6sl_clocks_init(unsigned long ckil, unsigned long osc, + unsigned long ckih1, unsigned long ckih2); +extern void imx6_init_fec(struct fec_platform_data fec_data); +extern int mxc91231_clocks_init(unsigned long fref); +extern int mxc_register_gpios(void); +extern int mxc_register_device(struct platform_device *pdev, void *data); +extern void mxc_set_cpu_type(unsigned int type); +extern void mxc_arch_reset_init(void __iomem *); +extern void mxc91231_power_off(void); +extern void mxc91231_arch_reset(int, const char *); +extern void mxc91231_prepare_idle(void); +extern void mx51_efikamx_reset(void); +extern int mx53_revision(void); +extern int mx50_revision(void); +extern int mx53_display_revision(void); +extern int mxs_reset_block(void __iomem *); +extern void early_console_setup(unsigned long base, struct clk *clk); +extern void mx6_cpu_regulator_init(void); +extern int mx6q_sabreauto_init_pfuze100(u32 int_gpio); +extern int mx6q_sabresd_init_pfuze100(u32 int_gpio); +extern void imx_print_silicon_rev(const char *cpu, int srev); +#endif diff --git a/arch/arm/plat-mxc/include/mach/debug-macro.S b/arch/arm/plat-mxc/include/mach/debug-macro.S new file mode 100644 index 00000000..e19086cc --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/debug-macro.S @@ -0,0 +1,72 @@ +/* arch/arm/mach-imx/include/mach/debug-macro.S + * + * Debugging macro include header + * + * Copyright (C) 1994-1999 Russell King + * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ +#include <mach/hardware.h> + +#ifdef CONFIG_ARCH_MX1 +#define UART_PADDR MX1_UART1_BASE_ADDR +#endif + +#ifdef CONFIG_ARCH_MX25 +#ifdef UART_PADDR +#error "CONFIG_DEBUG_LL is incompatible with multiple archs" +#endif +#define UART_PADDR MX25_UART1_BASE_ADDR +#endif + +#ifdef CONFIG_ARCH_MX2 +#ifdef UART_PADDR +#error "CONFIG_DEBUG_LL is incompatible with multiple archs" +#endif +#define UART_PADDR MX2x_UART1_BASE_ADDR +#endif + +#ifdef CONFIG_ARCH_MX3 +#ifdef UART_PADDR +#error "CONFIG_DEBUG_LL is incompatible with multiple archs" +#endif +#define UART_PADDR MX3x_UART1_BASE_ADDR +#endif + +#ifdef CONFIG_ARCH_MX5 +#ifdef UART_PADDR +#error "CONFIG_DEBUG_LL is incompatible with multiple archs" +#endif +#define UART_PADDR MX51_UART1_BASE_ADDR +#endif + +#ifdef CONFIG_ARCH_MX6Q +#ifdef UART_PADDR +#error "CONFIG_DEBUG_LL is incompatible with multiple archs" +#endif +#define UART_PADDR MX6Q_UART4_BASE_ADDR +#endif + +#define UART_VADDR IMX_IO_ADDRESS(UART_PADDR) + + .macro addruart, rp, rv + ldr \rp, =UART_PADDR @ physical + ldr \rv, =UART_VADDR @ virtual + .endm + + .macro senduart,rd,rx + str \rd, [\rx, #0x40] @ TXDATA + .endm + + .macro waituart,rd,rx + .endm + + .macro busyuart,rd,rx +1002: ldr \rd, [\rx, #0x98] @ SR2 + tst \rd, #1 << 3 @ TXDC + beq 1002b @ wait until transmit done + .endm diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h new file mode 100755 index 00000000..f6d616d0 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/devices-common.h @@ -0,0 +1,702 @@ +/* + * Copyright (C) 2009-2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <linux/kernel.h> +#include <linux/platform_device.h> +#include <linux/init.h> +#include <linux/dma-mapping.h> + +struct platform_device *imx_add_platform_device_dmamask( + const char *name, int id, + const struct resource *res, unsigned int num_resources, + const void *data, size_t size_data, u64 dmamask); + +static inline struct platform_device *imx_add_platform_device( + const char *name, int id, + const struct resource *res, unsigned int num_resources, + const void *data, size_t size_data) +{ + return imx_add_platform_device_dmamask( + name, id, res, num_resources, data, size_data, 0); +} + +struct imx_dma_res_data { + resource_size_t iobase; +}; +struct platform_device *__init imx_add_dma(const struct imx_dma_res_data *data); + +#include <linux/fec.h> +struct imx_fec_data { + resource_size_t iobase; + resource_size_t irq; + const char *devid; +}; +struct platform_device *__init imx_add_fec( + const struct imx_fec_data *data, + const struct fec_platform_data *pdata); + +#include <linux/can/platform/flexcan.h> +struct imx_flexcan_data { + const char *devid; + int id; + resource_size_t iobase; + resource_size_t iosize; + resource_size_t irq; +}; +struct platform_device *__init imx_add_flexcan( + const struct imx_flexcan_data *data, + const struct flexcan_platform_data *pdata); + +#include <linux/fsl_devices.h> +struct platform_device *__init imx_add_mlb( + const struct mxc_mlb_platform_data *pdata); +struct imx_fsl_usb2_udc_data { + resource_size_t iobase; + resource_size_t irq; +}; +struct platform_device *__init imx_add_fsl_usb2_udc( + const struct imx_fsl_usb2_udc_data *data, + const struct fsl_usb2_platform_data *pdata); + +#include <linux/gpio_keys.h> +struct platform_device *__init imx_add_gpio_keys( + const struct gpio_keys_platform_data *pdata); + +#include <mach/mx21-usbhost.h> +struct imx_imx21_hcd_data { + resource_size_t iobase; + resource_size_t irq; +}; +struct platform_device *__init imx_add_imx21_hcd( + const struct imx_imx21_hcd_data *data, + const struct mx21_usbh_platform_data *pdata); + +struct imx_imx2_wdt_data { + int id; + resource_size_t iobase; + resource_size_t iosize; + resource_size_t irq; +}; +struct platform_device *__init imx_add_imx2_wdt( + const struct imx_imx2_wdt_data *data); + +struct imx_imxdi_rtc_data { + resource_size_t iobase; + resource_size_t irq; +}; +struct platform_device *__init imx_add_imxdi_rtc( + const struct imx_imxdi_rtc_data *data); + +struct imx_srtc_data { + resource_size_t iobase; + resource_size_t irq; +}; +struct platform_device *__init imx_add_srtc( + const struct imx_srtc_data *data); + +struct imx_snvs_rtc_data { + resource_size_t iobase; + resource_size_t irq; +}; +struct platform_device *__init imx_add_snvs_rtc( + const struct imx_snvs_rtc_data *data); + +struct imx_caam_jr_data { + resource_size_t offset_jr; + resource_size_t irq_jr; +}; + +struct imx_caam_data { + resource_size_t iobase_caam; /* entirety of CAAM register map */ + resource_size_t iobase_caam_sm; /* base of secure memory */ + resource_size_t iobase_snvs; /* base of SNVS */ + resource_size_t irq_sec_vio; /* SNVS security violation */ + resource_size_t irq_snvs; /* SNVS consolidated (incl. RTC) */ + struct imx_caam_jr_data jr[4]; /* offset+IRQ for each possible ring */ +}; + +struct platform_device *__init imx_add_caam( + const struct imx_caam_data *data); + +#include <mach/imxfb.h> +struct imx_imx_fb_data { + resource_size_t iobase; + resource_size_t iosize; + resource_size_t irq; +}; +struct platform_device *__init imx_add_imx_fb( + const struct imx_imx_fb_data *data, + const struct imx_fb_platform_data *pdata); + +#include <mach/i2c.h> +struct imx_imx_i2c_data { + int id; + resource_size_t iobase; + resource_size_t iosize; + resource_size_t irq; +}; +struct platform_device *__init imx_add_imx_i2c( + const struct imx_imx_i2c_data *data, + const struct imxi2c_platform_data *pdata); + +#include <linux/input/matrix_keypad.h> +struct imx_imx_keypad_data { + resource_size_t iobase; + resource_size_t iosize; + resource_size_t irq; +}; +struct platform_device *__init imx_add_imx_keypad( + const struct imx_imx_keypad_data *data, + const struct matrix_keymap_data *pdata); + +#include <mach/ssi.h> +struct imx_imx_ssi_data { + int id; + resource_size_t iobase; + resource_size_t iosize; + resource_size_t irq; + resource_size_t dmatx0; + resource_size_t dmarx0; + resource_size_t dmatx1; + resource_size_t dmarx1; +}; +struct platform_device *__init imx_add_imx_ssi( + const struct imx_imx_ssi_data *data, + const struct imx_ssi_platform_data *pdata); + +#include <mach/esai.h> +struct imx_imx_esai_data { + int id; + resource_size_t iobase; + resource_size_t iosize; + resource_size_t irq; + resource_size_t dmatx; + resource_size_t dmarx; +}; +struct platform_device *__init imx_add_imx_esai( + const struct imx_imx_esai_data *data, + const struct imx_esai_platform_data *pdata); + +#include <mach/imx-uart.h> +struct imx_imx_uart_3irq_data { + int id; + resource_size_t iobase; + resource_size_t iosize; + resource_size_t irqrx; + resource_size_t irqtx; + resource_size_t irqrts; +}; +struct platform_device *__init imx_add_imx_uart_3irq( + const struct imx_imx_uart_3irq_data *data, + const struct imxuart_platform_data *pdata); + +struct imx_imx_uart_1irq_data { + int id; + resource_size_t iobase; + resource_size_t iosize; + resource_size_t irq; +}; +struct platform_device *__init imx_add_imx_uart_1irq( + const struct imx_imx_uart_1irq_data *data, + const struct imxuart_platform_data *pdata); + +#include <mach/usb.h> +struct imx_imx_udc_data { + resource_size_t iobase; + resource_size_t iosize; + resource_size_t irq0; + resource_size_t irq1; + resource_size_t irq2; + resource_size_t irq3; + resource_size_t irq4; + resource_size_t irq5; + resource_size_t irq6; +}; +struct platform_device *__init imx_add_imx_udc( + const struct imx_imx_udc_data *data, + const struct imxusb_platform_data *pdata); +#if 0 +#include <mach/ipu.h> +#include <mach/mx3fb.h> +#include <mach/mx3_camera.h> +struct imx_ipu_core_data { + resource_size_t iobase; + resource_size_t synirq; + resource_size_t errirq; +}; +struct platform_device *__init imx_add_ipu_core( + const struct imx_ipu_core_data *data, + const struct ipu_platform_data *pdata); +struct platform_device *__init imx_alloc_mx3_camera( + const struct imx_ipu_core_data *data, + const struct mx3_camera_pdata *pdata); +struct platform_device *__init imx_add_mx3_sdc_fb( + const struct imx_ipu_core_data *data, + struct mx3fb_platform_data *pdata); +#endif +#include <mach/mx1_camera.h> +struct imx_mx1_camera_data { + resource_size_t iobase; + resource_size_t iosize; + resource_size_t irq; +}; +struct platform_device *__init imx_add_mx1_camera( + const struct imx_mx1_camera_data *data, + const struct mx1_camera_pdata *pdata); + +#include <mach/mx2_cam.h> +struct imx_mx2_camera_data { + resource_size_t iobasecsi; + resource_size_t iosizecsi; + resource_size_t irqcsi; + resource_size_t iobaseemmaprp; + resource_size_t iosizeemmaprp; + resource_size_t irqemmaprp; +}; +struct platform_device *__init imx_add_mx2_camera( + const struct imx_mx2_camera_data *data, + const struct mx2_camera_platform_data *pdata); + +#include <mach/mxc_ehci.h> +struct imx_mxc_ehci_data { + int id; + resource_size_t iobase; + resource_size_t irq; +}; +struct platform_device *__init imx_add_mxc_ehci( + const struct imx_mxc_ehci_data *data, + const struct mxc_usbh_platform_data *pdata); + +struct platform_device *__init imx_add_fsl_ehci( + const struct imx_mxc_ehci_data *data, + const struct fsl_usb2_platform_data *pdata); + +#include <mach/mmc.h> +struct imx_mxc_mmc_data { + int id; + resource_size_t iobase; + resource_size_t iosize; + resource_size_t irq; + resource_size_t dmareq; +}; +struct platform_device *__init imx_add_mxc_mmc( + const struct imx_mxc_mmc_data *data, + const struct imxmmc_platform_data *pdata); + +#include <mach/mxc_nand.h> +struct imx_mxc_nand_data { + /* + * id is traditionally 0, but -1 is more appropriate. We use -1 for new + * machines but don't change existing devices as the nand device usually + * appears in the kernel command line to pass its partitioning. + */ + int id; + resource_size_t iobase; + resource_size_t iosize; + resource_size_t axibase; + resource_size_t irq; +}; +struct platform_device *__init imx_add_mxc_nand( + const struct imx_mxc_nand_data *data, + const struct mxc_nand_platform_data *pdata); + +struct imx_mxc_pwm_data { + int id; + resource_size_t iobase; + resource_size_t iosize; + resource_size_t irq; +}; +struct platform_device *__init imx_add_mxc_pwm( + const struct imx_mxc_pwm_data *data); + +/* mxc_rtc */ +struct imx_mxc_rtc_data { + resource_size_t iobase; + resource_size_t irq; +}; +struct platform_device *__init imx_add_mxc_rtc( + const struct imx_mxc_rtc_data *data); + +/* mxc_w1 */ +struct imx_mxc_w1_data { + resource_size_t iobase; +}; +struct platform_device *__init imx_add_mxc_w1( + const struct imx_mxc_w1_data *data); + +#include <mach/esdhc.h> +struct imx_sdhci_esdhc_imx_data { + int id; + resource_size_t iobase; + resource_size_t irq; +}; +struct platform_device *__init imx_add_sdhci_esdhc_imx( + const struct imx_sdhci_esdhc_imx_data *data, + const struct esdhc_platform_data *pdata); + +#include <mach/spi.h> +struct imx_spi_imx_data { + const char *devid; + int id; + resource_size_t iobase; + resource_size_t iosize; + int irq; +}; +struct platform_device *__init imx_add_spi_imx( + const struct imx_spi_imx_data *data, + const struct spi_imx_master *pdata); + +#include <mach/ipu-v3.h> +struct imx_ipuv3_data { + resource_size_t iobase; + resource_size_t iosize; + resource_size_t irq_err; + resource_size_t irq; + unsigned int irq_start; + int (*init) (int); + void (*pg) (int); +}; +struct platform_device *__init imx_add_ipuv3( + const int id, + const struct imx_ipuv3_data *data, + struct imx_ipuv3_platform_data *pdata); + +struct platform_device *__init imx_add_ipuv3_fb( + const int id, + const struct ipuv3_fb_platform_data *pdata); + +#include <mach/mxc_vpu.h> +struct imx_vpu_data { + resource_size_t iobase; + resource_size_t irq_ipi; + resource_size_t irq_jpg; + bool iram_enable; + int iram_size; + void (*reset) (void); + void (*pg) (int); +}; +struct platform_device *__init imx_add_vpu( + const struct imx_vpu_data *data); + +#include <mach/mxc_dvfs.h> +struct imx_dvfs_core_data { + resource_size_t iobase; + resource_size_t irq; +}; +struct platform_device *__init imx_add_dvfs_core( + const struct imx_dvfs_core_data *data, + const struct mxc_dvfs_platform_data *pdata); + +struct platform_device *__init imx_add_busfreq(void); + +#include <linux/fsl_devices.h> +struct imx_tve_data { + resource_size_t iobase; + resource_size_t irq; +}; +struct platform_device *__init imx_add_tve( + const struct imx_tve_data *data, + const struct fsl_mxc_tve_platform_data *pdata); + +#include <linux/ahci_platform.h> +struct imx_ahci_data { + int id; + resource_size_t iobase; + resource_size_t irq; +}; +struct platform_device *__init imx_add_ahci( + const struct imx_ahci_data *data, + const struct ahci_platform_data *pdata); + +struct imx_iim_data { + resource_size_t iobase; + resource_size_t irq; +}; +struct platform_device *__init imx_add_iim( + const struct imx_iim_data *data, + const struct mxc_iim_platform_data *pdata); + +#include <mach/mxc_gpu.h> +struct imx_mxc_gpu_data { + resource_size_t irq_2d; + resource_size_t irq_3d; + resource_size_t iobase_2d; + resource_size_t iobase_3d; + resource_size_t gmem_base; + resource_size_t gmem_size; +}; + +struct platform_device *__init imx_add_mxc_gpu( + const struct imx_mxc_gpu_data *data, + const struct mxc_gpu_platform_data *pdata); + +struct imx_perfmon_data { + resource_size_t iobase; + struct mxs_platform_perfmon_data *pdata; +}; + +struct platform_device *__init imx_add_perfmon( + const struct imx_perfmon_data *data); + +struct imx_ldb_data { + resource_size_t iobase; + resource_size_t iosize; +}; + +struct platform_device *__init imx_add_ldb( + const struct imx_ldb_data *data, + struct fsl_mxc_ldb_platform_data *pdata); + +struct imx_mxc_scc2_data { + resource_size_t iobase; + resource_size_t ram_start; + resource_size_t irq_smn; + resource_size_t irq_scm; +}; + +struct platform_device *__init imx_add_mxc_scc2( + const struct imx_mxc_scc2_data *data); + +struct imx_pxp_data { + resource_size_t iobase; + resource_size_t iosize; + resource_size_t irq; +}; +struct platform_device *__init imx_add_imx_pxp( + const struct imx_pxp_data *data); +struct platform_device *__init imx_add_imx_pxp_client(void); +struct platform_device *__init imx_add_imx_pxp_v4l2(void); + +#include <linux/fsl_devices.h> +struct imx_elcdif_data { + resource_size_t iobase; + resource_size_t iosize; + resource_size_t irq; +}; + +struct platform_device *__init imx_add_imx_elcdif( + const struct imx_elcdif_data *data, + const struct mxc_fb_platform_data *pdata); + +#include <mach/epdc.h> +struct imx_epdc_data { + resource_size_t iobase; + resource_size_t iosize; + resource_size_t irq; +}; +struct platform_device *__init imx_add_imx_epdc( + const struct imx_epdc_data *data, + const struct imx_epdc_fb_platform_data *pdata); + +struct platform_device *__init imx_add_imx_spdc( + const struct imx_epdc_data *data, + const struct imx_spdc_fb_platform_data *pdata); + +struct imx_spdif_data { + resource_size_t iobase; + resource_size_t irq; +}; +struct platform_device *__init imx_add_spdif( + const struct imx_spdif_data *data, + const struct mxc_spdif_platform_data *pdata); + +struct imx_spdif_dai_data { + resource_size_t iobase; + resource_size_t dmatx; + resource_size_t dmarx; +}; +struct platform_device *__init imx_add_spdif_dai( + const struct imx_spdif_dai_data *data); + +struct platform_device *__init imx_add_spdif_audio_device(void); + +#include <mach/viv_gpu.h> +struct imx_viv_gpu_data { + resource_size_t phys_baseaddr; + resource_size_t irq_3d; + resource_size_t iobase_3d; + resource_size_t irq_2d; + resource_size_t iobase_2d; + resource_size_t irq_vg; + resource_size_t iobase_vg; +}; +struct platform_device *__init imx_add_viv_gpu( + const struct imx_viv_gpu_data *data, + const struct viv_gpu_platform_data *pdata); + +#include <mach/anatop_thermal.h> +struct imx_anatop_thermal_imx_data { + int id; + resource_size_t iobase; + resource_size_t calibration_addr; + resource_size_t irq; +}; +struct platform_device *__init imx_add_anatop_thermal_imx( + const struct imx_anatop_thermal_imx_data *data, + const struct anatop_thermal_platform_data *pdata); + +struct imx_otp_data { + resource_size_t iobase; + struct mxc_otp_platform_data *pdata; +}; + +struct platform_device *__init imx_add_otp( + const struct imx_otp_data *data); + +struct imx_viim_data { + resource_size_t iobase; +}; + +struct platform_device *__init imx_add_viim( + const struct imx_viim_data *data); + +struct imx_dcp_data { + resource_size_t iobase; + resource_size_t irq1; + resource_size_t irq2; +}; + + +#include <mach/imx-pm.h> +struct imx_pm_imx_data { + int id; + resource_size_t iobase; + resource_size_t irq; +}; +struct platform_device *__init imx_add_pm_imx( + const struct imx_pm_imx_data *data, + const struct pm_platform_data *pdata); + +#include <mach/mxc_hdmi.h> +struct imx_mxc_hdmi_data { + resource_size_t irq; + resource_size_t irq_wakeup; +}; + +struct platform_device *__init imx_add_mxc_hdmi( + const struct imx_mxc_hdmi_data *data, + const struct fsl_mxc_hdmi_platform_data *pdata); + +struct imx_mxc_hdmi_core_data { + resource_size_t iobase; + resource_size_t iosize; +}; + +struct platform_device *__init imx_add_mxc_hdmi_core( + const struct imx_mxc_hdmi_core_data *data, + const struct fsl_mxc_hdmi_core_platform_data *pdata); + +#include <mach/mxc_asrc.h> +struct imx_imx_asrc_data { + int id; + resource_size_t iobase; + resource_size_t iosize; + resource_size_t irq; + resource_size_t dmatx1; + resource_size_t dmarx1; + resource_size_t dmatx2; + resource_size_t dmarx2; + resource_size_t dmatx3; + resource_size_t dmarx3; +}; +struct platform_device *__init imx_add_imx_asrc( + const struct imx_imx_asrc_data *data, + const struct imx_asrc_platform_data *pdata); + +struct imx_hdmi_soc_data { + resource_size_t irq; +}; +struct platform_device *__init imx_add_hdmi_soc(void); + +struct platform_device *__init imx_add_hdmi_soc_dai( + const struct imx_hdmi_soc_data *data); + +#include <mach/mipi_dsi.h> +struct imx_mipi_dsi_data { + int id; + resource_size_t iobase; + resource_size_t iosize; + resource_size_t irq; +}; +struct platform_device *__init imx_add_mipi_dsi( + const struct imx_mipi_dsi_data *data, + const struct mipi_dsi_platform_data *pdata); + +#include <mach/mipi_csi2.h> +struct imx_mipi_csi2_data { + int id; + resource_size_t iobase; + resource_size_t iosize; +}; +struct platform_device *__init imx_add_mipi_csi2( + const struct imx_mipi_csi2_data *data, + const struct mipi_csi2_platform_data *pdata); + +struct platform_device *__init imx_add_dcp( + const struct imx_dcp_data *data); + +struct imx_fsl_usb2_otg_data { + resource_size_t iobase; + resource_size_t irq; +}; +struct platform_device *__init imx_add_fsl_usb2_otg( + const struct imx_fsl_usb2_otg_data *data, + const struct fsl_usb2_platform_data *pdata); + +struct imx_fsl_usb2_wakeup_data { + int id; + resource_size_t irq_phy; + resource_size_t irq_core; +}; +struct platform_device *__init imx_add_fsl_usb2_wakeup( + const struct imx_fsl_usb2_wakeup_data *data, + const struct fsl_usb2_wakeup_platform_data *pdata); + +/* gpmi-nand*/ +#include <linux/mtd/gpmi-nand.h> +struct platform_device *__init imx_add_gpmi( + const struct gpmi_nand_platform_data *data); + +struct imx_rngb_data { + resource_size_t iobase; + resource_size_t irq; +}; + +struct platform_device *__init imx_add_rngb( + const struct imx_rngb_data *data); + +struct imx_vdoa_data { + int id; + resource_size_t iobase; + resource_size_t iosize; + resource_size_t irq; +}; +struct platform_device *__init imx_add_vdoa( + const struct imx_vdoa_data *data); + +#include <mach/pcie.h> +struct imx_pcie_data { + int id; + resource_size_t iobase; + resource_size_t iosize; + resource_size_t irq; +}; + +struct platform_device *__init imx_add_pcie( + const struct imx_pcie_data *data, + const struct imx_pcie_platform_data *pdata); + +void __init imx_add_imx_armpmu(void); + +struct imx_fsl_csi_data { + resource_size_t iobase; + resource_size_t iosize; + resource_size_t irq; +}; +struct platform_device *__init imx_add_fsl_csi( + const struct imx_fsl_csi_data *data); diff --git a/arch/arm/plat-mxc/include/mach/dma.h b/arch/arm/plat-mxc/include/mach/dma.h new file mode 100644 index 00000000..af2edb84 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/dma.h @@ -0,0 +1,106 @@ +/* + * Copyright (C) 2004-2012 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_MXC_DMA_H__ +#define __ASM_ARCH_MXC_DMA_H__ + +#include <linux/scatterlist.h> +#include <linux/device.h> +#include <linux/dmaengine.h> + +#define MXC_DMA_DYNAMIC_CHANNEL 255 + +#define MXC_DMA_DONE 0x0 +#define MXC_DMA_REQUEST_TIMEOUT 0x1 +#define MXC_DMA_TRANSFER_ERROR 0x2 + +/* + * This enumerates peripheral types. Used for SDMA. + */ +enum sdma_peripheral_type { + IMX_DMATYPE_SSI, /* MCU domain SSI */ + IMX_DMATYPE_SSI_SP, /* Shared SSI */ + IMX_DMATYPE_MMC, /* MMC */ + IMX_DMATYPE_SDHC, /* SDHC */ + IMX_DMATYPE_UART, /* MCU domain UART */ + IMX_DMATYPE_UART_SP, /* Shared UART */ + IMX_DMATYPE_FIRI, /* FIRI */ + IMX_DMATYPE_CSPI, /* MCU domain CSPI */ + IMX_DMATYPE_CSPI_SP, /* Shared CSPI */ + IMX_DMATYPE_SIM, /* SIM */ + IMX_DMATYPE_ATA, /* ATA */ + IMX_DMATYPE_CCM, /* CCM */ + IMX_DMATYPE_EXT, /* External peripheral */ + IMX_DMATYPE_MSHC, /* Memory Stick Host Controller */ + IMX_DMATYPE_MSHC_SP, /* Shared Memory Stick Host Controller */ + IMX_DMATYPE_DSP, /* DSP */ + IMX_DMATYPE_MEMORY, /* Memory */ + IMX_DMATYPE_FIFO_MEMORY,/* FIFO type Memory */ + IMX_DMATYPE_SPDIF, /* SPDIF */ + IMX_DMATYPE_IPU_MEMORY, /* IPU Memory */ + IMX_DMATYPE_ASRC, /* ASRC */ + IMX_DMATYPE_ESAI, /* ESAI */ + IMX_DMATYPE_HDMI, +}; + +enum imx_dma_prio { + DMA_PRIO_HIGH = 0, + DMA_PRIO_MEDIUM = 1, + DMA_PRIO_LOW = 2 +}; + +struct imx_dma_data { + int dma_request; /* DMA request line */ + int dma_request_p2p; + enum sdma_peripheral_type peripheral_type; + int priority; + void *private; +}; + +struct imx_pcm_dma_params { + enum sdma_peripheral_type peripheral_type; + int dma; + unsigned long dma_addr; + int burstsize; +}; + +static inline int imx_dma_is_ipu(struct dma_chan *chan) +{ + return !strcmp(dev_name(chan->device->dev), "ipu-core"); +} + +static inline int imx_dma_is_pxp(struct dma_chan *chan) +{ + return !strcmp(dev_name(chan->device->dev), "imx-pxp"); +} + +static inline int imx_dma_is_general_purpose(struct dma_chan *chan) +{ + return !strcmp(dev_name(chan->device->dev), "imx-sdma") || + !strcmp(dev_name(chan->device->dev), "imx-dma"); +} + +struct mxs_dma_data { + int chan_irq; +}; + +#define MXS_DMA_F_APPEND (1 << 0) +#define MXS_DMA_F_WAIT4END (1 << 1) +static inline int mxs_dma_is_apbh(struct dma_chan *chan) +{ + return !strcmp(dev_name(chan->device->dev), "mxs-dma-apbh"); +} + +static inline int mxs_dma_is_apbx(struct dma_chan *chan) +{ + return !strcmp(dev_name(chan->device->dev), "mxs-dma-apbx"); +} + +void sdma_set_event_pending(struct dma_chan *chan); + +#endif diff --git a/arch/arm/plat-mxc/include/mach/dvfs_dptc_struct.h b/arch/arm/plat-mxc/include/mach/dvfs_dptc_struct.h new file mode 100755 index 00000000..560b0564 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/dvfs_dptc_struct.h @@ -0,0 +1,169 @@ +/* + * Copyright 2004-2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file arch-mxc/dvfs_dptc_struct.h + * + * @brief MXC dvfs & dptc structure definitions file. + * + * @ingroup PM_MX27 PM_MX31 PM_MXC91321 PM_MXC91311 + */ +#ifndef __ASM_ARCH_MXC_DVFS_DPTC_STRUCT_H__ +#define __ASM_ARCH_MXC_DVFS_DPTC_STRUCT_H__ + +#include <linux/semaphore.h> +#include <mach/pm_api.h> + +/*! + * Number of entries in the DPTC log buffer + */ +#define LOG_ENTRIES 1024 + +/*! + * Log buffer Structure.\n + * This structure records the DPTC changes. \n + * This structure can be read by the user using the proc file system DPTC read entry. + */ +typedef struct { + /*! + * Index to the head of the log buffer + */ + int head; + + /*! + * Index to the tail of the log buffer + */ + int tail; + + /*! + * Mutex to allow access to the log buffer + */ + struct semaphore mutex; + + /*! + * Array of log buffer entries + */ + dptc_log_entry_s entries[LOG_ENTRIES]; +} dptc_log_s; + +/*! + * DPTC driver data structure.\n + * Holds all driver parameters and data structures. + */ +typedef struct { + /*! + * This variable holds the current frequency index + */ + int current_freq_index; + + /*! + * Boolean variable, if TRUE the DPTC module is enabled + * if FALSE the DPTC module is disabled + */ + int dptc_is_active; + + /*! + * Boolean variable, if TRUE turbo mode enable + * if FALSE turbo mode disabled + */ + int turbo_mode_active; + + /*! + * Boolean variable, if TRUE the DVFS module is enabled + * if FALSE the DPTC module is disabled + */ + int dvfs_is_active; + + /*! + * Boolean variable, if TRUE the DPTC module is suspended + */ + int suspended; + + unsigned char rc_state; + + /*! + * Pointer to the DVFS & DPTC translation table + */ + dvfs_dptc_tables_s *dvfs_dptc_tables_ptr; + + /*! + * The DPTC log buffer + */ + dptc_log_s dptc_log_buffer; + + /*! + * The DVFS log buffer + */ + unsigned char *dvfs_log_buffer; + + /*! + * The DVFS log buffer physical address (for SDMA) + */ + dma_addr_t dvfs_log_buffer_phys; + +#ifdef CONFIG_MXC_DVFS_SDMA + /*! + * SDMA channel number + */ + int sdma_channel; + + /*! + * This holds the previous working point + */ + int prev_wp; + + /*! + * Wait entry for predictive DVFS + */ + wait_queue_head_t dvfs_pred_wait; +#endif + + /*! + * This holds the current DVFS mode + */ + unsigned int dvfs_mode; + + /*! + * Log buffer read pointer + */ + unsigned char *read_ptr; + + /* + * Number of characters in log buffer + */ + int chars_in_buffer; +} dvfs_dptc_params_s; + +/*! + * This struct contains the array with values of supported frequencies in Hz + */ +typedef struct { + /* + * Number of supported states + */ + unsigned int num_of_states; + /*! + * Array of frequencies + */ + unsigned int *freqs; +} dvfs_states_table; + +/* + * if not defined define TREU and FALSE values. + */ +#ifndef TRUE +#define TRUE 1 +#define FALSE 0 +#endif /* TRUE */ + +#endif diff --git a/arch/arm/plat-mxc/include/mach/entry-macro.S b/arch/arm/plat-mxc/include/mach/entry-macro.S new file mode 100644 index 00000000..927f0d3c --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/entry-macro.S @@ -0,0 +1,97 @@ +/* + * Copyright (C) 2007 Lennert Buytenhek <buytenh@wantstofly.org> + * Copyright (C) 2004-2011 Freescale Semiconductor, Inc. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <mach/hardware.h> + +#if defined(CONFIG_ARM_GIC) +#include <asm/hardware/entry-macro-gic.S> + + .macro disable_fiq + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm + +#else + +#define AVIC_NIMASK 0x04 + + @ this macro disables fast irq (not implemented) + .macro disable_fiq + .endm + + .macro get_irqnr_preamble, base, tmp +#ifndef CONFIG_MXC_TZIC + ldr \base, =avic_base + ldr \base, [\base] +#ifdef CONFIG_MXC_IRQ_PRIOR + ldr r4, [\base, #AVIC_NIMASK] +#endif +#elif defined CONFIG_MXC_TZIC + ldr \base, =tzic_base + ldr \base, [\base] +#endif /* CONFIG_MXC_TZIC */ + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm + + @ this macro checks which interrupt occurred + @ and returns its number in irqnr + @ and returns if an interrupt occurred in irqstat + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp +#ifndef CONFIG_MXC_TZIC + @ Load offset & priority of the highest priority + @ interrupt pending from AVIC_NIVECSR + ldr \irqstat, [\base, #0x40] + @ Shift to get the decoded IRQ number, using ASR so + @ 'no interrupt pending' becomes 0xffffffff + mov \irqnr, \irqstat, asr #16 + @ set zero flag if IRQ + 1 == 0 + adds \tmp, \irqnr, #1 +#ifdef CONFIG_MXC_IRQ_PRIOR + bicne \tmp, \irqstat, #0xFFFFFFE0 + strne \tmp, [\base, #AVIC_NIMASK] + streq r4, [\base, #AVIC_NIMASK] +#endif +#elif defined CONFIG_MXC_TZIC + @ Load offset & priority of the highest priority + @ interrupt pending. + @ 0x080 is INTSEC0 register + @ 0xD80 is HIPND0 register + mov \irqnr, #0 +1000: add \irqstat, \base, \irqnr, lsr #3 + ldr \tmp, [\irqstat, #0xd80] + ldr \irqstat, [\irqstat, #0x080] + ands \tmp, \tmp, \irqstat + bne 1001f + add \irqnr, \irqnr, #32 + cmp \irqnr, #128 + blo 1000b + b 2001f +1001: mov \irqstat, #1 +1002: tst \tmp, \irqstat + bne 2002f + movs \tmp, \tmp, lsr #1 + addne \irqnr, \irqnr, #1 + bne 1002b +2001: + mov \irqnr, #0 +2002: + movs \irqnr, \irqnr +#endif + .endm + + @ irq priority table (not used) + .macro irq_prio_table + .endm +#endif + diff --git a/arch/arm/plat-mxc/include/mach/epdc.h b/arch/arm/plat-mxc/include/mach/epdc.h new file mode 100644 index 00000000..36aac882 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/epdc.h @@ -0,0 +1,68 @@ +/* + * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#ifndef __MACH_EPDC_H_ +#define __MACH_EPDC_H_ + +struct imx_epdc_fb_mode { + struct fb_videomode *vmode; + int vscan_holdoff; + int sdoed_width; + int sdoed_delay; + int sdoez_width; + int sdoez_delay; + int gdclk_hp_offs; + int gdsp_offs; + int gdoe_offs; + int gdclk_offs; + int num_ce; +}; + +struct imx_epdc_fb_platform_data { + struct imx_epdc_fb_mode *epdc_mode; + int num_modes; + int (*get_pins) (void); + void (*put_pins) (void); + void (*enable_pins) (void); + void (*disable_pins) (void); +}; + +struct imx_spdc_panel_init_set { + bool yoe_pol; + bool dual_gate; + u8 resolution; + bool ud; + bool rl; + bool data_filter_n; + bool power_ready; + bool rgbw_mode_enable; + bool hburst_len_en; +}; + +struct imx_spdc_fb_mode { + struct fb_videomode *vmode; + struct imx_spdc_panel_init_set *init_set; + const char *wave_timing; +}; + +struct imx_spdc_fb_platform_data { + struct imx_spdc_fb_mode *spdc_mode; + int num_modes; + int (*get_pins) (void); + void (*put_pins) (void); + void (*enable_pins) (void); + void (*disable_pins) (void); +}; + +#endif /* __MACH_EPDC_H_ */ diff --git a/arch/arm/plat-mxc/include/mach/esai.h b/arch/arm/plat-mxc/include/mach/esai.h new file mode 100644 index 00000000..d77eb154 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/esai.h @@ -0,0 +1,18 @@ +/* + * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ + +#ifndef __MACH_ESAI_H +#define __MACH_ESAI_H + +struct imx_esai_platform_data { + unsigned int flags; +#define IMX_ESAI_NET (1 << 0) +#define IMX_ESAI_SYN (1 << 1) +}; + +#endif diff --git a/arch/arm/plat-mxc/include/mach/esdhc.h b/arch/arm/plat-mxc/include/mach/esdhc.h new file mode 100644 index 00000000..10df1856 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/esdhc.h @@ -0,0 +1,42 @@ +/* + * Copyright 2011 Wolfram Sang <w.sang@pengutronix.de> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; version 2 + * of the License. + */ + +#ifndef __ASM_ARCH_IMX_ESDHC_H +#define __ASM_ARCH_IMX_ESDHC_H + +enum cd_types { + ESDHC_CD_NONE, /* no CD, neither controller nor gpio */ + ESDHC_CD_CONTROLLER, /* mmc controller internal CD */ + ESDHC_CD_GPIO, /* external gpio pin for CD */ + ESDHC_CD_PERMANENT, /* no CD, card permanently wired to host */ + ESDHC_CD_WIFI_PWR, /* wifi host, use wifi pwr pin as CD */ +}; + +/** + * struct esdhc_platform_data - optional platform data for esdhc on i.MX + * + * strongly recommended for i.MX25/35, not needed for other variants + * + * @wp_gpio: gpio for write_protect (-EINVAL if unused) + * @cd_gpio: gpio for card_detect interrupt (-EINVAL if unused) + */ + +struct esdhc_platform_data { + unsigned int wp_gpio; + unsigned int cd_gpio; + enum cd_types cd_type; + unsigned int always_present; + unsigned int support_18v; + unsigned int support_8bit; + unsigned int keep_power_at_suspend; + unsigned int delay_line; + bool runtime_pm; + int (*platform_pad_change)(unsigned int index, int clock); +}; +#endif /* __ASM_ARCH_IMX_ESDHC_H */ diff --git a/arch/arm/plat-mxc/include/mach/eukrea-baseboards.h b/arch/arm/plat-mxc/include/mach/eukrea-baseboards.h new file mode 100644 index 00000000..a21d3313 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/eukrea-baseboards.h @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2010 Eric Benard - eric@eukrea.com + * + * Based on board-pcm038.h which is : + * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#ifndef __MACH_EUKREA_BASEBOARDS_H__ +#define __MACH_EUKREA_BASEBOARDS_H__ + +#ifndef __ASSEMBLY__ +/* + * This CPU module needs a baseboard to work. After basic initializing + * its own devices, it calls baseboard's init function. + * TODO: Add your own baseboard init function and call it from + * inside eukrea_cpuimx25_init() eukrea_cpuimx27_init() + * eukrea_cpuimx35_init() eukrea_cpuimx51_init() + * or eukrea_cpuimx51sd_init(). + * + * This example here is for the development board. Refer + * mach-mx25/eukrea_mbimxsd-baseboard.c for cpuimx25 + * mach-imx/eukrea_mbimx27-baseboard.c for cpuimx27 + * mach-mx3/eukrea_mbimxsd-baseboard.c for cpuimx35 + * mach-mx5/eukrea_mbimx51-baseboard.c for cpuimx51 + * mach-mx5/eukrea_mbimxsd-baseboard.c for cpuimx51sd + */ + +extern void eukrea_mbimxsd25_baseboard_init(void); +extern void eukrea_mbimx27_baseboard_init(void); +extern void eukrea_mbimxsd35_baseboard_init(void); +extern void eukrea_mbimx51_baseboard_init(void); +extern void eukrea_mbimxsd51_baseboard_init(void); + +#endif + +#endif /* __MACH_EUKREA_BASEBOARDS_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/fsl_usb.h b/arch/arm/plat-mxc/include/mach/fsl_usb.h new file mode 100755 index 00000000..0b47a7d5 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/fsl_usb.h @@ -0,0 +1,107 @@ +/* + * Copyright 2005-2012 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/* + * USB Host side, platform-specific functionality. + */ + +#include <linux/usb/fsl_xcvr.h> +#include <mach/arc_otg.h> + +static void fsl_setup_phy(struct ehci_hcd *ehci, + enum fsl_usb2_phy_modes phy_mode, + int port_offset); + +static inline void fsl_platform_usb_setup(struct ehci_hcd *ehci) +{ + struct fsl_usb2_platform_data *pdata; + + pdata = ehci_to_hcd(ehci)->self.controller->platform_data; + fsl_setup_phy(ehci, pdata->phy_mode, 0); +} + +static inline void fsl_platform_set_host_mode(struct usb_hcd *hcd) +{ + unsigned int temp; + struct fsl_usb2_platform_data *pdata; + + pdata = hcd->self.controller->platform_data; + + if (pdata->xcvr_ops && pdata->xcvr_ops->set_host) + pdata->xcvr_ops->set_host(); + + /* set host mode */ + temp = readl(hcd->regs + 0x1a8); + writel(temp | USBMODE_CM_HOST, hcd->regs + 0x1a8); +} + +/* Needed for enable PP and i2c/serial transceivers */ +static inline void +fsl_platform_set_vbus_power(struct fsl_usb2_platform_data *pdata, int on) +{ + u32 temp; + + /* HCSPARAMS */ + temp = readl(pdata->regs + 0x104); + /* Port Power Control */ + if (temp & HCSPARAMS_PPC) { + temp = readl(pdata->regs + FSL_SOC_USB_PORTSC1); + if (on) + temp |= PORT_POWER; + else + temp &= ~PORT_POWER; + + writel(temp, pdata->regs + FSL_SOC_USB_PORTSC1); + } + + if (pdata->xcvr_ops && pdata->xcvr_ops->set_vbus_power) + pdata->xcvr_ops->set_vbus_power(pdata->xcvr_ops, pdata, on); +} + +/* Set USB AHB burst length for host */ +static inline void fsl_platform_set_ahb_burst(struct usb_hcd *hcd) +{ + struct fsl_usb2_platform_data *pdata; + unsigned int temp; + + pdata = hcd->self.controller->platform_data; + if (pdata->change_ahb_burst) { + temp = readl(hcd->regs + FSL_SOC_USB_SBUSCFG); + writel((temp & (~(0x7))) | pdata->ahb_burst_mode, + hcd->regs + FSL_SOC_USB_SBUSCFG); + } + + /* Increase TX fifo threshold for USB+ATA for i.mx35 2.0 */ + if (cpu_is_mx35() && (imx_cpu_ver() >= IMX_CHIP_REVISION_2_0)) { + temp = readl(hcd->regs + FSL_SOC_USB_TXFILLTUNING); + /* Change TX FIFO threshold to be 0x20 */ + writel((temp & (~(0x3f << 16))) | (0x20 << 16), + hcd->regs + FSL_SOC_USB_TXFILLTUNING); + } + + /* Increase TX fifo threshold for USB+SD in Hostx */ + if (cpu_is_mx53() && (strcmp("DR", pdata->name))) { + temp = readl(hcd->regs + FSL_SOC_USB_TXFILLTUNING); + /* Change TX FIFO threshold to be 0x08 */ + writel((temp & (~(0x3f << 16))) | (0x08 << 16), + hcd->regs + FSL_SOC_USB_TXFILLTUNING); + } + + /* Increase TX fifo threshold for in Hostx */ + if (cpu_is_mx6()) { + temp = readl(hcd->regs + FSL_SOC_USB_TXFILLTUNING); + /* Change TX FIFO threshold to be 0x08 */ + writel((temp & (~(0x3f << 16))) | (0x08 << 16), + hcd->regs + FSL_SOC_USB_TXFILLTUNING); + } +} diff --git a/arch/arm/plat-mxc/include/mach/fsl_usb_gadget.h b/arch/arm/plat-mxc/include/mach/fsl_usb_gadget.h new file mode 100755 index 00000000..53f9b05a --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/fsl_usb_gadget.h @@ -0,0 +1,40 @@ +/* + * Copyright 2005-2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/* + * USB Gadget side, platform-specific functionality. + */ + +#include <linux/usb/fsl_xcvr.h> + +/* Needed for i2c/serial transceivers */ +static inline void +fsl_platform_set_device_mode(struct fsl_usb2_platform_data *pdata) +{ + if (pdata->xcvr_ops && pdata->xcvr_ops->set_device) + pdata->xcvr_ops->set_device(); +} + +static inline void +fsl_platform_pullup_enable(struct fsl_usb2_platform_data *pdata) +{ + if (pdata->xcvr_ops && pdata->xcvr_ops->pullup) + pdata->xcvr_ops->pullup(1); +} + +static inline void +fsl_platform_pullup_disable(struct fsl_usb2_platform_data *pdata) +{ + if (pdata->xcvr_ops && pdata->xcvr_ops->pullup) + pdata->xcvr_ops->pullup(0); +} diff --git a/arch/arm/plat-mxc/include/mach/gpio.h b/arch/arm/plat-mxc/include/mach/gpio.h new file mode 100644 index 00000000..f008e40f --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/gpio.h @@ -0,0 +1,67 @@ +/* + * Copyright 2007-2013 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008 Juergen Beisert, kernel@pengutronix.de + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#ifndef __ASM_ARCH_MXC_GPIO_H__ +#define __ASM_ARCH_MXC_GPIO_H__ + +#include <linux/spinlock.h> +#include <mach/hardware.h> +#include <asm-generic/gpio.h> + + +/* There's a off-by-one betweem the gpio bank number and the gpiochip */ +/* range e.g. GPIO_1_5 is gpio 5 under linux */ +#define IMX_GPIO_NR(bank, nr) (((bank) - 1) * 32 + (nr)) + +/* use gpiolib dispatchers */ +#define gpio_get_value __gpio_get_value +#define gpio_set_value __gpio_set_value +#define gpio_cansleep __gpio_cansleep + +#define gpio_to_irq(gpio) (MXC_GPIO_IRQ_START + (gpio)) +#define irq_to_gpio(irq) ((irq) - MXC_GPIO_IRQ_START) + +struct mxc_gpio_port { + void __iomem *base; + int irq; + int irq_high; + int virtual_irq_start; + struct gpio_chip chip; + u32 both_edges; + spinlock_t lock; + u32 dir; +}; + +#define DEFINE_IMX_GPIO_PORT_IRQ_HIGH(soc, _id, _hwid, _irq, _irq_high) \ + { \ + .chip.label = "gpio-" #_id, \ + .irq = _irq, \ + .irq_high = _irq_high, \ + .base = soc ## _IO_ADDRESS( \ + soc ## _GPIO ## _hwid ## _BASE_ADDR), \ + .virtual_irq_start = MXC_GPIO_IRQ_START + (_id) * 32, \ + } + +#define DEFINE_IMX_GPIO_PORT_IRQ(soc, _id, _hwid, _irq) \ + DEFINE_IMX_GPIO_PORT_IRQ_HIGH(soc, _id, _hwid, _irq, 0) +#define DEFINE_IMX_GPIO_PORT(soc, _id, _hwid) \ + DEFINE_IMX_GPIO_PORT_IRQ(soc, _id, _hwid, 0) + +int mxc_gpio_init(struct mxc_gpio_port*, int); + +#endif diff --git a/arch/arm/plat-mxc/include/mach/gpmi-nfc.h b/arch/arm/plat-mxc/include/mach/gpmi-nfc.h new file mode 100644 index 00000000..25fc6053 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/gpmi-nfc.h @@ -0,0 +1,71 @@ +/* + * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __INCLUDE_GPMI_NFC_H +#define __INCLUDE_GPMI_NFC_H + +/* The size of the resource is fixed. */ +#define RES_SIZE 6 + +/* Resource names for the GPMI NFC driver. */ +#define GPMI_NFC_GPMI_REGS_ADDR_RES_NAME "GPMI NFC GPMI Registers" +#define GPMI_NFC_GPMI_INTERRUPT_RES_NAME "GPMI NFC GPMI Interrupt" +#define GPMI_NFC_BCH_REGS_ADDR_RES_NAME "GPMI NFC BCH Registers" +#define GPMI_NFC_BCH_INTERRUPT_RES_NAME "GPMI NFC BCH Interrupt" +#define GPMI_NFC_DMA_CHANNELS_RES_NAME "GPMI NFC DMA Channels" +#define GPMI_NFC_DMA_INTERRUPT_RES_NAME "GPMI NFC DMA Interrupt" + +/** + * struct gpmi_nfc_platform_data - GPMI NFC driver platform data. + * + * This structure communicates platform-specific information to the GPMI NFC + * driver that can't be expressed as resources. + * + * @platform_init: A pointer to a function the driver will call to + * initialize the platform (e.g., set up the pin mux). + * @platform_exit: A pointer to a function the driver will call to + * exit the platform (e.g., free pins). + * @min_prop_delay_in_ns: Minimum propagation delay of GPMI signals to and + * from the NAND Flash device, in nanoseconds. + * @max_prop_delay_in_ns: Maximum propagation delay of GPMI signals to and + * from the NAND Flash device, in nanoseconds. + * @max_chip_count: The maximum number of chips for which the driver + * should configure the hardware. This value most + * likely reflects the number of pins that are + * connected to a NAND Flash device. If this is + * greater than the SoC hardware can support, the + * driver will print a message and fail to initialize. + * @partitions: An optional pointer to an array of partition + * descriptions. + * @partition_count: The number of elements in the partitions array. + */ +struct gpmi_nfc_platform_data { + /* SoC hardware information. */ + int (*platform_init)(void); + void (*platform_exit)(void); + + /* NAND Flash information. */ + unsigned int min_prop_delay_in_ns; + unsigned int max_prop_delay_in_ns; + unsigned int max_chip_count; + + /* Medium information. */ + struct mtd_partition *partitions; + unsigned partition_count; +}; +#endif diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h new file mode 100755 index 00000000..e1c52344 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/hardware.h @@ -0,0 +1,146 @@ +/* + * Copyright 2004-2012 Freescale Semiconductor, Inc. + * Copyright 2008 Juergen Beisert, kernel@pengutronix.de + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#ifndef __ASM_ARCH_MXC_HARDWARE_H__ +#define __ASM_ARCH_MXC_HARDWARE_H__ + +#include <asm/sizes.h> + +#ifdef __ASSEMBLER__ +#define IOMEM(addr) (addr) +#else +#define IOMEM(addr) ((void __force __iomem *)(addr)) +#endif + +#define IMX_IO_P2V_MODULE(addr, module) \ + (((addr) - module ## _BASE_ADDR) < module ## _SIZE ? \ + (addr) - (module ## _BASE_ADDR) + (module ## _BASE_ADDR_VIRT) : 0) + +/* + * This is rather complicated for humans and ugly to verify, but for a machine + * it's OK. Still more as it is usually only applied to constants. The upsides + * on using this approach are: + * + * - same mapping on all i.MX machines + * - works for assembler, too + * - no need to nurture #defines for virtual addresses + * + * The downside it, it's hard to verify (but I have a script for that). + * + * Obviously this needs to be injective for each SoC. In general it maps the + * whole address space to [0xf4000000, 0xf5ffffff]. So [0xf6000000,0xfeffffff] + * is free for per-machine use (e.g. KZM_ARM11_01 uses 64MiB there). + * + * It applies the following mappings for the different SoCs: + * + * mx1: + * IO 0x00200000+0x100000 -> 0xf4000000+0x100000 + * mx21: + * AIPI 0x10000000+0x100000 -> 0xf4400000+0x100000 + * SAHB1 0x80000000+0x100000 -> 0xf4000000+0x100000 + * X_MEMC 0xdf000000+0x004000 -> 0xf5f00000+0x004000 + * mx25: + * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000 + * AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000 + * AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000 + * mx27: + * AIPI 0x10000000+0x100000 -> 0xf4400000+0x100000 + * SAHB1 0x80000000+0x100000 -> 0xf4000000+0x100000 + * X_MEMC 0xd8000000+0x100000 -> 0xf5c00000+0x100000 + * mx31: + * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000 + * AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000 + * AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000 + * X_MEMC 0xb8000000+0x010000 -> 0xf4c00000+0x010000 + * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000 + * mx35: + * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000 + * AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000 + * AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000 + * X_MEMC 0xb8000000+0x010000 -> 0xf4c00000+0x010000 + * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000 + * mx50: + * TZIC 0x0fffc000+0x004000 -> 0xf4bfc000+0x004000 + * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000 + * AIPS1 0x53f00000+0x100000 -> 0xf5700000+0x100000 + * AIPS2 0x63f00000+0x100000 -> 0xf5300000+0x100000 + * mx51: + * IRAM 0x1ffe0000+0x020000 -> 0xf4fe0000+0x020000 + * DEBUG 0x60000000+0x100000 -> 0xf5000000+0x100000 + * SPBA0 0x70000000+0x100000 -> 0xf5400000+0x100000 + * AIPS1 0x73f00000+0x100000 -> 0xf5700000+0x100000 + * AIPS2 0x83f00000+0x100000 -> 0xf4300000+0x100000 + */ +#define IMX_IO_P2V(x) ( \ + 0xf2000000 + \ + (((x) & 0x50000000) >> 6) + \ + (((x) & 0x0b000000) >> 4) + \ + (((x) & 0x000fffff))) + +#define IMX_IO_ADDRESS(x) IOMEM(IMX_IO_P2V(x)) + +#include <mach/mxc.h> + +#ifdef CONFIG_ARCH_MX5 +#include <mach/mx50.h> +#include <mach/mx51.h> +#include <mach/mx53.h> +#endif + +#ifdef CONFIG_ARCH_MX6 +#include <mach/mx6.h> +#endif + +#ifdef CONFIG_ARCH_MX3 +#include <mach/mx3x.h> +#include <mach/mx31.h> +#include <mach/mx35.h> +#endif + +#ifdef CONFIG_ARCH_MX2 +# include <mach/mx2x.h> +# ifdef CONFIG_MACH_MX21 +# include <mach/mx21.h> +# endif +# ifdef CONFIG_MACH_MX27 +# include <mach/mx27.h> +# endif +#endif + +#ifdef CONFIG_ARCH_MX1 +# include <mach/mx1.h> +#endif + +#ifdef CONFIG_ARCH_MX25 +# include <mach/mx25.h> +#endif + +#define imx_map_entry(soc, name, _type) { \ + .virtual = soc ## _IO_P2V(soc ## _ ## name ## _BASE_ADDR), \ + .pfn = __phys_to_pfn(soc ## _ ## name ## _BASE_ADDR), \ + .length = soc ## _ ## name ## _SIZE, \ + .type = _type, \ +} + +/* macro to get at IO space when running virtually */ +#define PCIBIOS_MIN_IO 0x00000000 +#define PCIBIOS_MIN_MEM 0x00000000 +#define pcibios_assign_all_busses() 0 + +#endif /* __ASM_ARCH_MXC_HARDWARE_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/i2c.h b/arch/arm/plat-mxc/include/mach/i2c.h new file mode 100644 index 00000000..4a5dc5c6 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/i2c.h @@ -0,0 +1,25 @@ +/* + * i2c.h - i.MX I2C driver header file + * + * Copyright (c) 2008, Darius Augulis <augulis.darius@gmail.com> + * + * This file is released under the GPLv2 + */ + +#ifndef __ASM_ARCH_I2C_H_ +#define __ASM_ARCH_I2C_H_ + +/** + * struct imxi2c_platform_data - structure of platform data for MXC I2C driver + * @init: Initialise gpio's and other board specific things + * @exit: Free everything initialised by @init + * @bitrate: Bus speed measured in Hz + * + **/ +struct imxi2c_platform_data { + int (*init)(struct device *dev); + void (*exit)(struct device *dev); + int bitrate; +}; + +#endif /* __ASM_ARCH_I2C_H_ */ diff --git a/arch/arm/plat-mxc/include/mach/iim.h b/arch/arm/plat-mxc/include/mach/iim.h new file mode 100644 index 00000000..315bffad --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/iim.h @@ -0,0 +1,77 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008 Juergen Beisert, kernel@pengutronix.de + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#ifndef __ASM_ARCH_MXC_IIM_H__ +#define __ASM_ARCH_MXC_IIM_H__ + +/* Register offsets */ +#define MXC_IIMSTAT 0x0000 +#define MXC_IIMSTATM 0x0004 +#define MXC_IIMERR 0x0008 +#define MXC_IIMEMASK 0x000C +#define MXC_IIMFCTL 0x0010 +#define MXC_IIMUA 0x0014 +#define MXC_IIMLA 0x0018 +#define MXC_IIMSDAT 0x001C +#define MXC_IIMPREV 0x0020 +#define MXC_IIMSREV 0x0024 +#define MXC_IIMPRG_P 0x0028 +#define MXC_IIMSCS0 0x002C +#define MXC_IIMSCS1 0x0030 +#define MXC_IIMSCS2 0x0034 +#define MXC_IIMSCS3 0x0038 +#define MXC_IIMFBAC0 0x0800 +#define MXC_IIMJAC 0x0804 +#define MXC_IIMHWV1 0x0808 +#define MXC_IIMHWV2 0x080C +#define MXC_IIMHAB0 0x0810 +#define MXC_IIMHAB1 0x0814 +/* Definitions for i.MX27 TO2 */ +#define MXC_IIMMAC 0x0814 +#define MXC_IIMPREV_FUSE 0x0818 +#define MXC_IIMSREV_FUSE 0x081C +#define MXC_IIMSJC_CHALL_0 0x0820 +#define MXC_IIMSJC_CHALL_7 0x083C +#define MXC_IIMFB0UC17 0x0840 +#define MXC_IIMFB0UC255 0x0BFC +#define MXC_IIMFBAC1 0x0C00 +/* Definitions for i.MX27 TO2 */ +#define MXC_IIMSUID 0x0C04 +#define MXC_IIMKEY0 0x0C04 +#define MXC_IIMKEY20 0x0C54 +#define MXC_IIMSJC_RESP_0 0x0C58 +#define MXC_IIMSJC_RESP_7 0x0C74 +#define MXC_IIMFB1UC30 0x0C78 +#define MXC_IIMFB1UC255 0x0FFC + +/* Bit definitions */ + +#define MXC_IIMHWV1_WLOCK (0x1 << 7) +#define MXC_IIMHWV1_MCU_ENDIAN (0x1 << 6) +#define MXC_IIMHWV1_DSP_ENDIAN (0x1 << 5) +#define MXC_IIMHWV1_BOOT_INT (0x1 << 4) +#define MXC_IIMHWV1_SCC_DISABLE (0x1 << 3) +#define MXC_IIMHWV1_HANTRO_DISABLE (0x1 << 2) +#define MXC_IIMHWV1_MEMSTICK_DIS (0x1 << 1) + +#define MXC_IIMHWV2_WLOCK (0x1 << 7) +#define MXC_IIMHWV2_BP_SDMA (0x1 << 6) +#define MXC_IIMHWV2_SCM_DCM (0x1 << 5) + +#endif /* __ASM_ARCH_MXC_IIM_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/imx-pm.h b/arch/arm/plat-mxc/include/mach/imx-pm.h new file mode 100644 index 00000000..f6d375a4 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/imx-pm.h @@ -0,0 +1,31 @@ +/* + * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ +#ifndef __ASM_ARCH_IMX_PM_H +#define __ASM_ARCH_IMX_PM_H + +/** + * struct pm_platform_data - optional platform data for pm on i.MX + * + */ + +struct pm_platform_data { + char *name; + void (*suspend_enter) (void); + void (*suspend_exit) (void); +}; +#endif /* __ASM_ARCH_IMX_PM_H */ diff --git a/arch/arm/plat-mxc/include/mach/imx-uart.h b/arch/arm/plat-mxc/include/mach/imx-uart.h new file mode 100644 index 00000000..21dcdaf2 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/imx-uart.h @@ -0,0 +1,39 @@ +/* + * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#ifndef ASMARM_ARCH_UART_H +#define ASMARM_ARCH_UART_H + +#define IMXUART_HAVE_RTSCTS (1<<0) +#define IMXUART_IRDA (1<<1) +#define IMXUART_USE_DCEDTE (1<<2) +#define IMXUART_SDMA (1<<3) + +struct imxuart_platform_data { + int (*init)(struct platform_device *pdev); + void (*exit)(struct platform_device *pdev); + unsigned int flags; + void (*irda_enable)(int enable); + unsigned int irda_inv_rx:1; + unsigned int irda_inv_tx:1; + unsigned short transceiver_delay; + unsigned int dma_req_rx; + unsigned int dma_req_tx; +}; + +#endif diff --git a/arch/arm/plat-mxc/include/mach/imx_rfkill.h b/arch/arm/plat-mxc/include/mach/imx_rfkill.h new file mode 100755 index 00000000..d7263f57 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/imx_rfkill.h @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef IMX_RFKILL_H +#define IMX_RFKILL_H +struct imx_bt_rfkill_platform_data { + int (*power_change) (int status); +}; + +#endif diff --git a/arch/arm/plat-mxc/include/mach/imxfb.h b/arch/arm/plat-mxc/include/mach/imxfb.h new file mode 100644 index 00000000..9de8f062 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/imxfb.h @@ -0,0 +1,84 @@ +/* + * This structure describes the machine which we are running on. + */ +#ifndef __MACH_IMXFB_H__ +#define __MACH_IMXFB_H__ + +#include <linux/fb.h> + +#define PCR_TFT (1 << 31) +#define PCR_COLOR (1 << 30) +#define PCR_PBSIZ_1 (0 << 28) +#define PCR_PBSIZ_2 (1 << 28) +#define PCR_PBSIZ_4 (2 << 28) +#define PCR_PBSIZ_8 (3 << 28) +#define PCR_BPIX_1 (0 << 25) +#define PCR_BPIX_2 (1 << 25) +#define PCR_BPIX_4 (2 << 25) +#define PCR_BPIX_8 (3 << 25) +#define PCR_BPIX_12 (4 << 25) +#define PCR_BPIX_16 (5 << 25) +#define PCR_BPIX_18 (6 << 25) +#define PCR_PIXPOL (1 << 24) +#define PCR_FLMPOL (1 << 23) +#define PCR_LPPOL (1 << 22) +#define PCR_CLKPOL (1 << 21) +#define PCR_OEPOL (1 << 20) +#define PCR_SCLKIDLE (1 << 19) +#define PCR_END_SEL (1 << 18) +#define PCR_END_BYTE_SWAP (1 << 17) +#define PCR_REV_VS (1 << 16) +#define PCR_ACD_SEL (1 << 15) +#define PCR_ACD(x) (((x) & 0x7f) << 8) +#define PCR_SCLK_SEL (1 << 7) +#define PCR_SHARP (1 << 6) +#define PCR_PCD(x) ((x) & 0x3f) + +#define PWMR_CLS(x) (((x) & 0x1ff) << 16) +#define PWMR_LDMSK (1 << 15) +#define PWMR_SCR1 (1 << 10) +#define PWMR_SCR0 (1 << 9) +#define PWMR_CC_EN (1 << 8) +#define PWMR_PW(x) ((x) & 0xff) + +#define LSCR1_PS_RISE_DELAY(x) (((x) & 0x7f) << 26) +#define LSCR1_CLS_RISE_DELAY(x) (((x) & 0x3f) << 16) +#define LSCR1_REV_TOGGLE_DELAY(x) (((x) & 0xf) << 8) +#define LSCR1_GRAY2(x) (((x) & 0xf) << 4) +#define LSCR1_GRAY1(x) (((x) & 0xf)) + +#define DMACR_BURST (1 << 31) +#define DMACR_HM(x) (((x) & 0xf) << 16) +#define DMACR_TM(x) ((x) & 0xf) + +struct imx_fb_videomode { + struct fb_videomode mode; + u32 pcr; + unsigned char bpp; +}; + +struct imx_fb_platform_data { + struct imx_fb_videomode *mode; + int num_modes; + + u_int cmap_greyscale:1, + cmap_inverse:1, + cmap_static:1, + unused:29; + + u_int pwmr; + u_int lscr1; + u_int dmacr; + + u_char * fixed_screen_cpu; + dma_addr_t fixed_screen_dma; + + int (*init)(struct platform_device *); + void (*exit)(struct platform_device *); + + void (*lcd_power)(int); + void (*backlight_power)(int); +}; + +void set_imx_fb_info(struct imx_fb_platform_data *); +#endif /* ifndef __MACH_IMXFB_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/io.h b/arch/arm/plat-mxc/include/mach/io.h new file mode 100644 index 00000000..4347a87d --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/io.h @@ -0,0 +1,49 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_MXC_IO_H__ +#define __ASM_ARCH_MXC_IO_H__ + +/* Allow IO space to be anywhere in the memory */ +#define IO_SPACE_LIMIT 0xffffffff + +#if defined(CONFIG_SOC_IMX31) || defined(CONFIG_SOC_IMX35) +#include <mach/hardware.h> + +#define __arch_ioremap __imx_ioremap +#define __arch_iounmap __iounmap + +#define addr_in_module(addr, mod) \ + ((unsigned long)(addr) - mod ## _BASE_ADDR < mod ## _SIZE) + +static inline void __iomem * +__imx_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype) +{ + if (mtype == MT_DEVICE && (cpu_is_mx31() || cpu_is_mx35())) { + /* + * Access all peripherals below 0x80000000 as nonshared device + * on mx3, but leave l2cc alone. Otherwise cache corruptions + * can occur. + */ + if (phys_addr < 0x80000000 && + !addr_in_module(phys_addr, MX3x_L2CC)) + mtype = MT_DEVICE_NONSHARED; + } + + return __arm_ioremap(phys_addr, size, mtype); +} +#endif + +/* io address mapping macro */ +#define __io(a) __typesafe_io(a) + +#define __mem_pci(a) (a) + +#endif diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx1.h b/arch/arm/plat-mxc/include/mach/iomux-mx1.h new file mode 100644 index 00000000..6b1507cf --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/iomux-mx1.h @@ -0,0 +1,155 @@ +/* + * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ +#ifndef __MACH_IOMUX_MX1_H__ +#define __MACH_IOMUX_MX1_H__ + +#include <mach/iomux-v1.h> + +#define PA0_AIN_SPI2_CLK (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 0) +#define PA0_AF_ETMTRACESYNC (GPIO_PORTA | GPIO_AF | 0) +#define PA1_AOUT_SPI2_RXD (GPIO_PORTA | GPIO_AOUT | GPIO_IN | 1) +#define PA1_PF_TIN (GPIO_PORTA | GPIO_PF | 1) +#define PA2_PF_PWM0 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 2) +#define PA3_PF_CSI_MCLK (GPIO_PORTA | GPIO_PF | 3) +#define PA4_PF_CSI_D0 (GPIO_PORTA | GPIO_PF | 4) +#define PA5_PF_CSI_D1 (GPIO_PORTA | GPIO_PF | 5) +#define PA6_PF_CSI_D2 (GPIO_PORTA | GPIO_PF | 6) +#define PA7_PF_CSI_D3 (GPIO_PORTA | GPIO_PF | 7) +#define PA8_PF_CSI_D4 (GPIO_PORTA | GPIO_PF | 8) +#define PA9_PF_CSI_D5 (GPIO_PORTA | GPIO_PF | 9) +#define PA10_PF_CSI_D6 (GPIO_PORTA | GPIO_PF | 10) +#define PA11_PF_CSI_D7 (GPIO_PORTA | GPIO_PF | 11) +#define PA12_PF_CSI_VSYNC (GPIO_PORTA | GPIO_PF | 12) +#define PA13_PF_CSI_HSYNC (GPIO_PORTA | GPIO_PF | 13) +#define PA14_PF_CSI_PIXCLK (GPIO_PORTA | GPIO_PF | 14) +#define PA15_PF_I2C_SDA (GPIO_PORTA | GPIO_PF | GPIO_OUT | 15) +#define PA16_PF_I2C_SCL (GPIO_PORTA | GPIO_PF | GPIO_OUT | 16) +#define PA17_AF_ETMTRACEPKT4 (GPIO_PORTA | GPIO_AF | 17) +#define PA17_AIN_SPI2_SS (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 17) +#define PA18_AF_ETMTRACEPKT5 (GPIO_PORTA | GPIO_AF | 18) +#define PA19_AF_ETMTRACEPKT6 (GPIO_PORTA | GPIO_AF | 19) +#define PA20_AF_ETMTRACEPKT7 (GPIO_PORTA | GPIO_AF | 20) +#define PA21_PF_A0 (GPIO_PORTA | GPIO_PF | 21) +#define PA22_PF_CS4 (GPIO_PORTA | GPIO_PF | 22) +#define PA23_PF_CS5 (GPIO_PORTA | GPIO_PF | 23) +#define PA24_PF_A16 (GPIO_PORTA | GPIO_PF | 24) +#define PA24_AF_ETMTRACEPKT0 (GPIO_PORTA | GPIO_AF | 24) +#define PA25_PF_A17 (GPIO_PORTA | GPIO_PF | 25) +#define PA25_AF_ETMTRACEPKT1 (GPIO_PORTA | GPIO_AF | 25) +#define PA26_PF_A18 (GPIO_PORTA | GPIO_PF | 26) +#define PA26_AF_ETMTRACEPKT2 (GPIO_PORTA | GPIO_AF | 26) +#define PA27_PF_A19 (GPIO_PORTA | GPIO_PF | 27) +#define PA27_AF_ETMTRACEPKT3 (GPIO_PORTA | GPIO_AF | 27) +#define PA28_PF_A20 (GPIO_PORTA | GPIO_PF | 28) +#define PA28_AF_ETMPIPESTAT0 (GPIO_PORTA | GPIO_AF | 28) +#define PA29_PF_A21 (GPIO_PORTA | GPIO_PF | 29) +#define PA29_AF_ETMPIPESTAT1 (GPIO_PORTA | GPIO_AF | 29) +#define PA30_PF_A22 (GPIO_PORTA | GPIO_PF | 30) +#define PA30_AF_ETMPIPESTAT2 (GPIO_PORTA | GPIO_AF | 30) +#define PA31_PF_A23 (GPIO_PORTA | GPIO_PF | 31) +#define PA31_AF_ETMTRACECLK (GPIO_PORTA | GPIO_AF | 31) +#define PB8_PF_SD_DAT0 (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 8) +#define PB8_AF_MS_PIO (GPIO_PORTB | GPIO_AF | 8) +#define PB9_PF_SD_DAT1 (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 9) +#define PB9_AF_MS_PI1 (GPIO_PORTB | GPIO_AF | 9) +#define PB10_PF_SD_DAT2 (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 10) +#define PB10_AF_MS_SCLKI (GPIO_PORTB | GPIO_AF | 10) +#define PB11_PF_SD_DAT3 (GPIO_PORTB | GPIO_PF | 11) +#define PB11_AF_MS_SDIO (GPIO_PORTB | GPIO_AF | 11) +#define PB12_PF_SD_CLK (GPIO_PORTB | GPIO_PF | 12) +#define PB12_AF_MS_SCLK0 (GPIO_PORTB | GPIO_AF | 12) +#define PB13_PF_SD_CMD (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 13) +#define PB13_AF_MS_BS (GPIO_PORTB | GPIO_AF | 13) +#define PB14_AF_SSI_RXFS (GPIO_PORTB | GPIO_AF | 14) +#define PB15_AF_SSI_RXCLK (GPIO_PORTB | GPIO_AF | 15) +#define PB16_AF_SSI_RXDAT (GPIO_PORTB | GPIO_AF | GPIO_IN | 16) +#define PB17_AF_SSI_TXDAT (GPIO_PORTB | GPIO_AF | GPIO_OUT | 17) +#define PB18_AF_SSI_TXFS (GPIO_PORTB | GPIO_AF | 18) +#define PB19_AF_SSI_TXCLK (GPIO_PORTB | GPIO_AF | 19) +#define PB20_PF_USBD_AFE (GPIO_PORTB | GPIO_PF | 20) +#define PB21_PF_USBD_OE (GPIO_PORTB | GPIO_PF | 21) +#define PB22_PF_USBD_RCV (GPIO_PORTB | GPIO_PF | 22) +#define PB23_PF_USBD_SUSPND (GPIO_PORTB | GPIO_PF | 23) +#define PB24_PF_USBD_VP (GPIO_PORTB | GPIO_PF | 24) +#define PB25_PF_USBD_VM (GPIO_PORTB | GPIO_PF | 25) +#define PB26_PF_USBD_VPO (GPIO_PORTB | GPIO_PF | 26) +#define PB27_PF_USBD_VMO (GPIO_PORTB | GPIO_PF | 27) +#define PB28_PF_UART2_CTS (GPIO_PORTB | GPIO_PF | GPIO_OUT | 28) +#define PB29_PF_UART2_RTS (GPIO_PORTB | GPIO_PF | GPIO_IN | 29) +#define PB30_PF_UART2_TXD (GPIO_PORTB | GPIO_PF | GPIO_OUT | 30) +#define PB31_PF_UART2_RXD (GPIO_PORTB | GPIO_PF | GPIO_IN | 31) +#define PC3_PF_SSI_RXFS (GPIO_PORTC | GPIO_PF | 3) +#define PC4_PF_SSI_RXCLK (GPIO_PORTC | GPIO_PF | 4) +#define PC5_PF_SSI_RXDAT (GPIO_PORTC | GPIO_PF | GPIO_IN | 5) +#define PC6_PF_SSI_TXDAT (GPIO_PORTC | GPIO_PF | GPIO_OUT | 6) +#define PC7_PF_SSI_TXFS (GPIO_PORTC | GPIO_PF | 7) +#define PC8_PF_SSI_TXCLK (GPIO_PORTC | GPIO_PF | 8) +#define PC9_PF_UART1_CTS (GPIO_PORTC | GPIO_PF | GPIO_OUT | 9) +#define PC10_PF_UART1_RTS (GPIO_PORTC | GPIO_PF | GPIO_IN | 10) +#define PC11_PF_UART1_TXD (GPIO_PORTC | GPIO_PF | GPIO_OUT | 11) +#define PC12_PF_UART1_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 12) +#define PC13_PF_SPI1_SPI_RDY (GPIO_PORTC | GPIO_PF | 13) +#define PC14_PF_SPI1_SCLK (GPIO_PORTC | GPIO_PF | 14) +#define PC15_PF_SPI1_SS (GPIO_PORTC | GPIO_PF | 15) +#define PC16_PF_SPI1_MISO (GPIO_PORTC | GPIO_PF | 16) +#define PC17_PF_SPI1_MOSI (GPIO_PORTC | GPIO_PF | 17) +#define PC24_BIN_UART3_RI (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 24) +#define PC25_BIN_UART3_DSR (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 25) +#define PC26_AOUT_UART3_DTR (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 26) +#define PC27_BIN_UART3_DCD (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 27) +#define PC28_BIN_UART3_CTS (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 28) +#define PC29_AOUT_UART3_RTS (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 29) +#define PC30_BIN_UART3_TX (GPIO_PORTC | GPIO_BIN | 30) +#define PC31_AOUT_UART3_RX (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 31) +#define PD6_PF_LSCLK (GPIO_PORTD | GPIO_PF | GPIO_OUT | 6) +#define PD7_PF_REV (GPIO_PORTD | GPIO_PF | 7) +#define PD7_AF_UART2_DTR (GPIO_PORTD | GPIO_AF | GPIO_IN | 7) +#define PD7_AIN_SPI2_SCLK (GPIO_PORTD | GPIO_AIN | 7) +#define PD8_PF_CLS (GPIO_PORTD | GPIO_PF | 8) +#define PD8_AF_UART2_DCD (GPIO_PORTD | GPIO_AF | GPIO_OUT | 8) +#define PD8_AIN_SPI2_SS (GPIO_PORTD | GPIO_AIN | 8) +#define PD9_PF_PS (GPIO_PORTD | GPIO_PF | 9) +#define PD9_AF_UART2_RI (GPIO_PORTD | GPIO_AF | GPIO_OUT | 9) +#define PD9_AOUT_SPI2_RXD (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 9) +#define PD10_PF_SPL_SPR (GPIO_PORTD | GPIO_PF | GPIO_OUT | 10) +#define PD10_AF_UART2_DSR (GPIO_PORTD | GPIO_AF | GPIO_OUT | 10) +#define PD10_AIN_SPI2_TXD (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 10) +#define PD11_PF_CONTRAST (GPIO_PORTD | GPIO_PF | GPIO_OUT | 11) +#define PD12_PF_ACD_OE (GPIO_PORTD | GPIO_PF | GPIO_OUT | 12) +#define PD13_PF_LP_HSYNC (GPIO_PORTD | GPIO_PF | GPIO_OUT | 13) +#define PD14_PF_FLM_VSYNC (GPIO_PORTD | GPIO_PF | GPIO_OUT | 14) +#define PD15_PF_LD0 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 15) +#define PD16_PF_LD1 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 16) +#define PD17_PF_LD2 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 17) +#define PD18_PF_LD3 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 18) +#define PD19_PF_LD4 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 19) +#define PD20_PF_LD5 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 20) +#define PD21_PF_LD6 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 21) +#define PD22_PF_LD7 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 22) +#define PD23_PF_LD8 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 23) +#define PD24_PF_LD9 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 24) +#define PD25_PF_LD10 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 25) +#define PD26_PF_LD11 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 26) +#define PD27_PF_LD12 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 27) +#define PD28_PF_LD13 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 28) +#define PD29_PF_LD14 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 29) +#define PD30_PF_LD15 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 30) +#define PD31_PF_TMR2OUT (GPIO_PORTD | GPIO_PF | 31) +#define PD31_BIN_SPI2_TXD (GPIO_PORTD | GPIO_BIN | 31) + +#endif /* ifndef __MACH_IOMUX_MX1_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx21.h b/arch/arm/plat-mxc/include/mach/iomux-mx21.h new file mode 100644 index 00000000..1495dfda --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/iomux-mx21.h @@ -0,0 +1,122 @@ +/* + * Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ +#ifndef __MACH_IOMUX_MX21_H__ +#define __MACH_IOMUX_MX21_H__ + +#include <mach/iomux-mx2x.h> +#include <mach/iomux-v1.h> + +/* Primary GPIO pin functions */ + +#define PB22_PF_USBH1_BYP (GPIO_PORTB | GPIO_PF | 22) +#define PB25_PF_USBH1_ON (GPIO_PORTB | GPIO_PF | 25) +#define PC5_PF_USBOTG_SDA (GPIO_PORTC | GPIO_PF | 5) +#define PC6_PF_USBOTG_SCL (GPIO_PORTC | GPIO_PF | 6) +#define PC7_PF_USBOTG_ON (GPIO_PORTC | GPIO_PF | 7) +#define PC8_PF_USBOTG_FS (GPIO_PORTC | GPIO_PF | 8) +#define PC9_PF_USBOTG_OE (GPIO_PORTC | GPIO_PF | 9) +#define PC10_PF_USBOTG_TXDM (GPIO_PORTC | GPIO_PF | 10) +#define PC11_PF_USBOTG_TXDP (GPIO_PORTC | GPIO_PF | 11) +#define PC12_PF_USBOTG_RXDM (GPIO_PORTC | GPIO_PF | 12) +#define PC13_PF_USBOTG_RXDP (GPIO_PORTC | GPIO_PF | 13) +#define PC16_PF_SAP_FS (GPIO_PORTC | GPIO_PF | 16) +#define PC17_PF_SAP_RXD (GPIO_PORTC | GPIO_PF | 17) +#define PC18_PF_SAP_TXD (GPIO_PORTC | GPIO_PF | 18) +#define PC19_PF_SAP_CLK (GPIO_PORTC | GPIO_PF | 19) +#define PE0_PF_TEST_WB2 (GPIO_PORTE | GPIO_PF | 0) +#define PE1_PF_TEST_WB1 (GPIO_PORTE | GPIO_PF | 1) +#define PE2_PF_TEST_WB0 (GPIO_PORTE | GPIO_PF | 2) +#define PF1_PF_NFCE (GPIO_PORTF | GPIO_PF | 1) +#define PF3_PF_NFCLE (GPIO_PORTF | GPIO_PF | 3) +#define PF7_PF_NFIO0 (GPIO_PORTF | GPIO_PF | 7) +#define PF8_PF_NFIO1 (GPIO_PORTF | GPIO_PF | 8) +#define PF9_PF_NFIO2 (GPIO_PORTF | GPIO_PF | 9) +#define PF10_PF_NFIO3 (GPIO_PORTF | GPIO_PF | 10) +#define PF11_PF_NFIO4 (GPIO_PORTF | GPIO_PF | 11) +#define PF12_PF_NFIO5 (GPIO_PORTF | GPIO_PF | 12) +#define PF13_PF_NFIO6 (GPIO_PORTF | GPIO_PF | 13) +#define PF14_PF_NFIO7 (GPIO_PORTF | GPIO_PF | 14) +#define PF16_PF_RES (GPIO_PORTF | GPIO_PF | 16) + +/* Alternate GPIO pin functions */ + +#define PA5_AF_BMI_CLK_CS (GPIO_PORTA | GPIO_AF | 5) +#define PA6_AF_BMI_D0 (GPIO_PORTA | GPIO_AF | 6) +#define PA7_AF_BMI_D1 (GPIO_PORTA | GPIO_AF | 7) +#define PA8_AF_BMI_D2 (GPIO_PORTA | GPIO_AF | 8) +#define PA9_AF_BMI_D3 (GPIO_PORTA | GPIO_AF | 9) +#define PA10_AF_BMI_D4 (GPIO_PORTA | GPIO_AF | 10) +#define PA11_AF_BMI_D5 (GPIO_PORTA | GPIO_AF | 11) +#define PA12_AF_BMI_D6 (GPIO_PORTA | GPIO_AF | 12) +#define PA13_AF_BMI_D7 (GPIO_PORTA | GPIO_AF | 13) +#define PA14_AF_BMI_D8 (GPIO_PORTA | GPIO_AF | 14) +#define PA15_AF_BMI_D9 (GPIO_PORTA | GPIO_AF | 15) +#define PA16_AF_BMI_D10 (GPIO_PORTA | GPIO_AF | 16) +#define PA17_AF_BMI_D11 (GPIO_PORTA | GPIO_AF | 17) +#define PA18_AF_BMI_D12 (GPIO_PORTA | GPIO_AF | 18) +#define PA19_AF_BMI_D13 (GPIO_PORTA | GPIO_AF | 19) +#define PA20_AF_BMI_D14 (GPIO_PORTA | GPIO_AF | 20) +#define PA21_AF_BMI_D15 (GPIO_PORTA | GPIO_AF | 21) +#define PA22_AF_BMI_READ_REQ (GPIO_PORTA | GPIO_AF | 22) +#define PA23_AF_BMI_WRITE (GPIO_PORTA | GPIO_AF | 23) +#define PA29_AF_BMI_RX_FULL (GPIO_PORTA | GPIO_AF | 29) +#define PA30_AF_BMI_READ (GPIO_PORTA | GPIO_AF | 30) + +/* AIN GPIO pin functions */ + +#define PC14_AIN_SYS_CLK (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 14) +#define PD21_AIN_USBH2_FS (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 21) +#define PD22_AIN_USBH2_OE (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 22) +#define PD23_AIN_USBH2_TXDM (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 23) +#define PD24_AIN_USBH2_TXDP (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 24) +#define PE8_AIN_IR_TXD (GPIO_PORTE | GPIO_AIN | GPIO_OUT | 8) +#define PF0_AIN_PC_RST (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 0) +#define PF1_AIN_PC_CE1 (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 1) +#define PF2_AIN_PC_CE2 (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 2) +#define PF3_AIN_PC_POE (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 3) +#define PF4_AIN_PC_OE (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 4) +#define PF5_AIN_PC_RW (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 5) + +/* BIN GPIO pin functions */ + +#define PC14_BIN_SYS_CLK (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 14) +#define PD27_BIN_EXT_DMA_GRANT (GPIO_PORTD | GPIO_BIN | GPIO_OUT | 27) + +/* CIN GPIO pin functions */ + +#define PB26_CIN_USBH1_RXDAT (GPIO_PORTB | GPIO_CIN | GPIO_OUT | 26) + +/* AOUT GPIO pin functions */ + +#define PA29_AOUT_BMI_WAIT (GPIO_PORTA | GPIO_AOUT | GPIO_IN | 29) +#define PD19_AOUT_USBH2_RXDM (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 19) +#define PD20_AOUT_USBH2_RXDP (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 20) +#define PD25_AOUT_EXT_DMAREQ (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 25) +#define PD26_AOUT_USBOTG_RXDAT (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 26) +#define PE9_AOUT_IR_RXD (GPIO_PORTE | GPIO_AOUT | GPIO_IN | 9) +#define PF6_AOUT_PC_BVD2 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 6) +#define PF7_AOUT_PC_BVD1 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 7) +#define PF8_AOUT_PC_VS2 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 8) +#define PF9_AOUT_PC_VS1 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 9) +#define PF10_AOUT_PC_WP (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 10) +#define PF11_AOUT_PC_READY (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 11) +#define PF12_AOUT_PC_WAIT (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 12) +#define PF13_AOUT_PC_CD2 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 13) +#define PF14_AOUT_PC_CD1 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 14) + +#endif /* ifndef __MACH_IOMUX_MX21_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx25.h b/arch/arm/plat-mxc/include/mach/iomux-mx25.h new file mode 100644 index 00000000..2e5244de --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/iomux-mx25.h @@ -0,0 +1,520 @@ +/* + * arch/arm/plat-mxc/include/mach/iomux-mx25.h + * + * Copyright (C) 2009 by Lothar Wassmann <LW@KARO-electronics.de> + * + * based on arch/arm/mach-mx25/mx25_pins.h + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + * and + * arch/arm/plat-mxc/include/mach/iomux-mx35.h + * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH <armlinux@phytec.de> + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __MACH_IOMUX_MX25_H__ +#define __MACH_IOMUX_MX25_H__ + +#include <mach/iomux-v3.h> + +/* + * IOMUX/PAD Bit field definitions + */ + +#define MX25_PAD_A10__A10 IOMUX_PAD(0x000, 0x008, 0x00, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_A10__GPIO_4_0 IOMUX_PAD(0x000, 0x008, 0x05, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_A13__A13 IOMUX_PAD(0x22C, 0x00c, 0x00, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_A13__GPIO_4_1 IOMUX_PAD(0x22C, 0x00c, 0x05, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_A14__A14 IOMUX_PAD(0x230, 0x010, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_A14__GPIO_2_0 IOMUX_PAD(0x230, 0x010, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_A15__A15 IOMUX_PAD(0x234, 0x014, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_A15__GPIO_2_1 IOMUX_PAD(0x234, 0x014, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_A16__A16 IOMUX_PAD(0x000, 0x018, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_A16__GPIO_2_2 IOMUX_PAD(0x000, 0x018, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_A17__A17 IOMUX_PAD(0x238, 0x01c, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_A17__GPIO_2_3 IOMUX_PAD(0x238, 0x01c, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_A18__A18 IOMUX_PAD(0x23c, 0x020, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_A18__GPIO_2_4 IOMUX_PAD(0x23c, 0x020, 0x15, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_A18__FEC_COL IOMUX_PAD(0x23c, 0x020, 0x17, 0x504, 0, NO_PAD_CTRL) + +#define MX25_PAD_A19__A19 IOMUX_PAD(0x240, 0x024, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_A19__FEC_RX_ER IOMUX_PAD(0x240, 0x024, 0x17, 0x518, 0, NO_PAD_CTRL) +#define MX25_PAD_A19__GPIO_2_5 IOMUX_PAD(0x240, 0x024, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_A20__A20 IOMUX_PAD(0x244, 0x028, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_A20__GPIO_2_6 IOMUX_PAD(0x244, 0x028, 0x15, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_A20__FEC_RDATA2 IOMUX_PAD(0x244, 0x028, 0x17, 0x50c, 0, NO_PAD_CTRL) + +#define MX25_PAD_A21__A21 IOMUX_PAD(0x248, 0x02c, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_A21__GPIO_2_7 IOMUX_PAD(0x248, 0x02c, 0x15, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_A21__FEC_RDATA3 IOMUX_PAD(0x248, 0x02c, 0x17, 0x510, 0, NO_PAD_CTRL) + +#define MX25_PAD_A22__A22 IOMUX_PAD(0x000, 0x030, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_A22__GPIO_2_8 IOMUX_PAD(0x000, 0x030, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_A23__A23 IOMUX_PAD(0x24c, 0x034, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_A23__GPIO_2_9 IOMUX_PAD(0x24c, 0x034, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_A24__A24 IOMUX_PAD(0x250, 0x038, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_A24__GPIO_2_10 IOMUX_PAD(0x250, 0x038, 0x15, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_A24__FEC_RX_CLK IOMUX_PAD(0x250, 0x038, 0x17, 0x514, 0, NO_PAD_CTRL) + +#define MX25_PAD_A25__A25 IOMUX_PAD(0x254, 0x03c, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_A25__GPIO_2_11 IOMUX_PAD(0x254, 0x03c, 0x15, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_A25__FEC_CRS IOMUX_PAD(0x254, 0x03c, 0x17, 0x508, 0, NO_PAD_CTRL) + +#define MX25_PAD_EB0__EB0 IOMUX_PAD(0x258, 0x040, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_EB0__AUD4_TXD IOMUX_PAD(0x258, 0x040, 0x14, 0x464, 0, NO_PAD_CTRL) +#define MX25_PAD_EB0__GPIO_2_12 IOMUX_PAD(0x258, 0x040, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_EB1__EB1 IOMUX_PAD(0x25c, 0x044, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_EB1__AUD4_RXD IOMUX_PAD(0x25c, 0x044, 0x14, 0x460, 0, NO_PAD_CTRL) +#define MX25_PAD_EB1__GPIO_2_13 IOMUX_PAD(0x25c, 0x044, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_OE__OE IOMUX_PAD(0x260, 0x048, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_OE__AUD4_TXC IOMUX_PAD(0x260, 0x048, 0x14, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_OE__GPIO_2_14 IOMUX_PAD(0x260, 0x048, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_CS0__CS0 IOMUX_PAD(0x000, 0x04c, 0x00, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CS0__GPIO_4_2 IOMUX_PAD(0x000, 0x04c, 0x05, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_CS1__CS1 IOMUX_PAD(0x000, 0x050, 0x00, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CS1__NF_CE3 IOMUX_PAD(0x000, 0x050, 0x01, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CS1__GPIO_4_3 IOMUX_PAD(0x000, 0x050, 0x05, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_CS4__CS4 IOMUX_PAD(0x264, 0x054, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CS4__NF_CE1 IOMUX_PAD(0x264, 0x054, 0x01, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CS4__UART5_CTS IOMUX_PAD(0x264, 0x054, 0x13, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CS4__GPIO_3_20 IOMUX_PAD(0x264, 0x054, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_CS5__CS5 IOMUX_PAD(0x268, 0x058, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CS5__NF_CE2 IOMUX_PAD(0x268, 0x058, 0x01, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CS5__UART5_RTS IOMUX_PAD(0x268, 0x058, 0x13, 0x574, 0, NO_PAD_CTRL) +#define MX25_PAD_CS5__GPIO_3_21 IOMUX_PAD(0x268, 0x058, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_NF_CE0__NF_CE0 IOMUX_PAD(0x26c, 0x05c, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_NF_CE0__GPIO_3_22 IOMUX_PAD(0x26c, 0x05c, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_ECB__ECB IOMUX_PAD(0x270, 0x060, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_ECB__UART5_TXD_MUX IOMUX_PAD(0x270, 0x060, 0x13, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_ECB__GPIO_3_23 IOMUX_PAD(0x270, 0x060, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_LBA__LBA IOMUX_PAD(0x274, 0x064, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LBA__UART5_RXD_MUX IOMUX_PAD(0x274, 0x064, 0x13, 0x578, 0, NO_PAD_CTRL) +#define MX25_PAD_LBA__GPIO_3_24 IOMUX_PAD(0x274, 0x064, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_BCLK__BCLK IOMUX_PAD(0x000, 0x068, 0x00, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_BCLK__GPIO_4_4 IOMUX_PAD(0x000, 0x068, 0x05, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_RW__RW IOMUX_PAD(0x278, 0x06c, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_RW__AUD4_TXFS IOMUX_PAD(0x278, 0x06c, 0x14, 0x474, 0, NO_PAD_CTRL) +#define MX25_PAD_RW__GPIO_3_25 IOMUX_PAD(0x278, 0x06c, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_NFWE_B__NFWE_B IOMUX_PAD(0x000, 0x070, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_NFWE_B__GPIO_3_26 IOMUX_PAD(0x000, 0x070, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_NFRE_B__NFRE_B IOMUX_PAD(0x000, 0x074, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_NFRE_B__GPIO_3_27 IOMUX_PAD(0x000, 0x074, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_NFALE__NFALE IOMUX_PAD(0x000, 0x078, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_NFALE__GPIO_3_28 IOMUX_PAD(0x000, 0x078, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_NFCLE__NFCLE IOMUX_PAD(0x000, 0x07c, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_NFCLE__GPIO_3_29 IOMUX_PAD(0x000, 0x07c, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_NFWP_B__NFWP_B IOMUX_PAD(0x000, 0x080, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_NFWP_B__GPIO_3_30 IOMUX_PAD(0x000, 0x080, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_NFRB__NFRB IOMUX_PAD(0x27c, 0x084, 0x10, 0, 0, PAD_CTL_PKE) +#define MX25_PAD_NFRB__GPIO_3_31 IOMUX_PAD(0x27c, 0x084, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_D15__D15 IOMUX_PAD(0x280, 0x088, 0x00, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_D15__LD16 IOMUX_PAD(0x280, 0x088, 0x01, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_D15__GPIO_4_5 IOMUX_PAD(0x280, 0x088, 0x05, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_D14__D14 IOMUX_PAD(0x284, 0x08c, 0x00, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_D14__LD17 IOMUX_PAD(0x284, 0x08c, 0x01, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_D14__GPIO_4_6 IOMUX_PAD(0x284, 0x08c, 0x05, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_D13__D13 IOMUX_PAD(0x288, 0x090, 0x00, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_D13__LD18 IOMUX_PAD(0x288, 0x090, 0x01, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_D13__GPIO_4_7 IOMUX_PAD(0x288, 0x090, 0x05, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_D12__D12 IOMUX_PAD(0x28c, 0x094, 0x00, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_D12__GPIO_4_8 IOMUX_PAD(0x28c, 0x094, 0x05, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_D11__D11 IOMUX_PAD(0x290, 0x098, 0x00, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_D11__GPIO_4_9 IOMUX_PAD(0x290, 0x098, 0x05, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_D10__D10 IOMUX_PAD(0x294, 0x09c, 0x00, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_D10__GPIO_4_10 IOMUX_PAD(0x294, 0x09c, 0x05, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_D10__USBOTG_OC IOMUX_PAD(0x294, 0x09c, 0x06, 0x57c, 0, PAD_CTL_PUS_100K_UP) + +#define MX25_PAD_D9__D9 IOMUX_PAD(0x298, 0x0a0, 0x00, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_D9__GPIO_4_11 IOMUX_PAD(0x298, 0x0a0, 0x05, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_D9__USBH2_PWR IOMUX_PAD(0x298, 0x0a0, 0x06, 0, 0, PAD_CTL_PKE) + +#define MX25_PAD_D8__D8 IOMUX_PAD(0x29c, 0x0a4, 0x00, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_D8__GPIO_4_12 IOMUX_PAD(0x29c, 0x0a4, 0x05, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_D8__USBH2_OC IOMUX_PAD(0x29c, 0x0a4, 0x06, 0x580, 0, PAD_CTL_PUS_100K_UP) + +#define MX25_PAD_D7__D7 IOMUX_PAD(0x2a0, 0x0a8, 0x00, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_D7__GPIO_4_13 IOMUX_PAD(0x2a0, 0x0a8, 0x05, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_D6__D6 IOMUX_PAD(0x2a4, 0x0ac, 0x00, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_D6__GPIO_4_14 IOMUX_PAD(0x2a4, 0x0ac, 0x05, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_D5__D5 IOMUX_PAD(0x2a8, 0x0b0, 0x00, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_D5__GPIO_4_15 IOMUX_PAD(0x2a8, 0x0b0, 0x05, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_D4__D4 IOMUX_PAD(0x2ac, 0x0b4, 0x00, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_D4__GPIO_4_16 IOMUX_PAD(0x2ac, 0x0b4, 0x05, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_D3__D3 IOMUX_PAD(0x2b0, 0x0b8, 0x00, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_D3__GPIO_4_17 IOMUX_PAD(0x2b0, 0x0b8, 0x05, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_D2__D2 IOMUX_PAD(0x2b4, 0x0bc, 0x00, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_D2__GPIO_4_18 IOMUX_PAD(0x2b4, 0x0bc, 0x05, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_D1__D1 IOMUX_PAD(0x2b8, 0x0c0, 0x00, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_D1__GPIO_4_19 IOMUX_PAD(0x2b8, 0x0c0, 0x05, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_D0__D0 IOMUX_PAD(0x2bc, 0x0c4, 0x00, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_D0__GPIO_4_20 IOMUX_PAD(0x2bc, 0x0c4, 0x05, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_LD0__LD0 IOMUX_PAD(0x2c0, 0x0c8, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD0__CSI_D0 IOMUX_PAD(0x2c0, 0x0c8, 0x12, 0x488, 0, NO_PAD_CTRL) +#define MX25_PAD_LD0__GPIO_2_15 IOMUX_PAD(0x2c0, 0x0c8, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_LD1__LD1 IOMUX_PAD(0x2c4, 0x0cc, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD1__CSI_D1 IOMUX_PAD(0x2c4, 0x0cc, 0x12, 0x48c, 0, NO_PAD_CTRL) +#define MX25_PAD_LD1__GPIO_2_16 IOMUX_PAD(0x2c4, 0x0cc, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_LD2__LD2 IOMUX_PAD(0x2c8, 0x0d0, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD2__GPIO_2_17 IOMUX_PAD(0x2c8, 0x0d0, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_LD3__LD3 IOMUX_PAD(0x2cc, 0x0d4, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD3__GPIO_2_18 IOMUX_PAD(0x2cc, 0x0d4, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_LD4__LD4 IOMUX_PAD(0x2d0, 0x0d8, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD4__GPIO_2_19 IOMUX_PAD(0x2d0, 0x0d8, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_LD5__LD5 IOMUX_PAD(0x2d4, 0x0dc, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD5__GPIO_1_19 IOMUX_PAD(0x2d4, 0x0dc, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_LD6__LD6 IOMUX_PAD(0x2d8, 0x0e0, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD6__GPIO_1_20 IOMUX_PAD(0x2d8, 0x0e0, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_LD7__LD7 IOMUX_PAD(0x2dc, 0x0e4, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD7__GPIO_1_21 IOMUX_PAD(0x2dc, 0x0e4, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_LD8__LD8 IOMUX_PAD(0x2e0, 0x0e8, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD8__FEC_TX_ERR IOMUX_PAD(0x2e0, 0x0e8, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_LD9__LD9 IOMUX_PAD(0x2e4, 0x0ec, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD9__FEC_COL IOMUX_PAD(0x2e4, 0x0ec, 0x15, 0x504, 1, NO_PAD_CTRL) + +#define MX25_PAD_LD10__LD10 IOMUX_PAD(0x2e8, 0x0f0, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD10__FEC_RX_ER IOMUX_PAD(0x2e8, 0x0f0, 0x15, 0x518, 1, NO_PAD_CTRL) + +#define MX25_PAD_LD11__LD11 IOMUX_PAD(0x2ec, 0x0f4, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD11__FEC_RDATA2 IOMUX_PAD(0x2ec, 0x0f4, 0x15, 0x50c, 1, NO_PAD_CTRL) + +#define MX25_PAD_LD12__LD12 IOMUX_PAD(0x2f0, 0x0f8, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD12__FEC_RDATA3 IOMUX_PAD(0x2f0, 0x0f8, 0x15, 0x510, 1, NO_PAD_CTRL) + +#define MX25_PAD_LD13__LD13 IOMUX_PAD(0x2f4, 0x0fc, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD13__FEC_TDATA2 IOMUX_PAD(0x2f4, 0x0fc, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_LD14__LD14 IOMUX_PAD(0x2f8, 0x100, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD14__FEC_TDATA3 IOMUX_PAD(0x2f8, 0x100, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_LD15__LD15 IOMUX_PAD(0x2fc, 0x104, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD15__FEC_RX_CLK IOMUX_PAD(0x2fc, 0x104, 0x15, 0x514, 1, NO_PAD_CTRL) + +#define MX25_PAD_HSYNC__HSYNC IOMUX_PAD(0x300, 0x108, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_HSYNC__GPIO_1_22 IOMUX_PAD(0x300, 0x108, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_VSYNC__VSYNC IOMUX_PAD(0x304, 0x10c, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_VSYNC__GPIO_1_23 IOMUX_PAD(0x304, 0x10c, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_LSCLK__LSCLK IOMUX_PAD(0x308, 0x110, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LSCLK__GPIO_1_24 IOMUX_PAD(0x308, 0x110, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_OE_ACD__OE_ACD IOMUX_PAD(0x30c, 0x114, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_OE_ACD__GPIO_1_25 IOMUX_PAD(0x30c, 0x114, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_CONTRAST__CONTRAST IOMUX_PAD(0x310, 0x118, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CONTRAST__PWM4_PWMO IOMUX_PAD(0x310, 0x118, 0x14, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CONTRAST__FEC_CRS IOMUX_PAD(0x310, 0x118, 0x15, 0x508, 1, NO_PAD_CTRL) + +#define MX25_PAD_PWM__PWM IOMUX_PAD(0x314, 0x11c, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_PWM__GPIO_1_26 IOMUX_PAD(0x314, 0x11c, 0x15, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_PWM__USBH2_OC IOMUX_PAD(0x314, 0x11c, 0x16, 0x580, 1, PAD_CTL_PUS_100K_UP) + +#define MX25_PAD_CSI_D2__CSI_D2 IOMUX_PAD(0x318, 0x120, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_D2__UART5_RXD_MUX IOMUX_PAD(0x318, 0x120, 0x11, 0x578, 1, NO_PAD_CTRL) +#define MX25_PAD_CSI_D2__GPIO_1_27 IOMUX_PAD(0x318, 0x120, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_CSI_D3__CSI_D3 IOMUX_PAD(0x31c, 0x124, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_D3__GPIO_1_28 IOMUX_PAD(0x31c, 0x124, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_CSI_D4__CSI_D4 IOMUX_PAD(0x320, 0x128, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_D4__UART5_RTS IOMUX_PAD(0x320, 0x128, 0x11, 0x574, 1, NO_PAD_CTRL) +#define MX25_PAD_CSI_D4__GPIO_1_29 IOMUX_PAD(0x320, 0x128, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_CSI_D5__CSI_D5 IOMUX_PAD(0x324, 0x12c, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_D5__GPIO_1_30 IOMUX_PAD(0x324, 0x12c, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_CSI_D6__CSI_D6 IOMUX_PAD(0x328, 0x130, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_D6__GPIO_1_31 IOMUX_PAD(0x328, 0x130, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_CSI_D7__CSI_D7 IOMUX_PAD(0x32c, 0x134, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_D7__GPIO_1_6 IOMUX_PAD(0x32c, 0x134, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_CSI_D8__CSI_D8 IOMUX_PAD(0x330, 0x138, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_D8__GPIO_1_7 IOMUX_PAD(0x330, 0x138, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_CSI_D9__CSI_D9 IOMUX_PAD(0x334, 0x13c, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_D9__GPIO_4_21 IOMUX_PAD(0x334, 0x13c, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_CSI_MCLK__CSI_MCLK IOMUX_PAD(0x338, 0x140, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_MCLK__GPIO_1_8 IOMUX_PAD(0x338, 0x140, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_CSI_VSYNC__CSI_VSYNC IOMUX_PAD(0x33c, 0x144, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_VSYNC__GPIO_1_9 IOMUX_PAD(0x33c, 0x144, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_CSI_HSYNC__CSI_HSYNC IOMUX_PAD(0x340, 0x148, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_HSYNC__GPIO_1_10 IOMUX_PAD(0x340, 0x148, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_CSI_PIXCLK__CSI_PIXCLK IOMUX_PAD(0x344, 0x14c, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_PIXCLK__GPIO_1_11 IOMUX_PAD(0x344, 0x14c, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_I2C1_CLK__I2C1_CLK IOMUX_PAD(0x348, 0x150, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_I2C1_CLK__GPIO_1_12 IOMUX_PAD(0x348, 0x150, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_I2C1_DAT__I2C1_DAT IOMUX_PAD(0x34c, 0x154, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_I2C1_DAT__GPIO_1_13 IOMUX_PAD(0x34c, 0x154, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_CSPI1_MOSI__CSPI1_MOSI IOMUX_PAD(0x350, 0x158, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSPI1_MOSI__GPIO_1_14 IOMUX_PAD(0x350, 0x158, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_CSPI1_MISO__CSPI1_MISO IOMUX_PAD(0x354, 0x15c, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSPI1_MISO__GPIO_1_15 IOMUX_PAD(0x354, 0x15c, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_CSPI1_SS0__CSPI1_SS0 IOMUX_PAD(0x358, 0x160, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSPI1_SS0__GPIO_1_16 IOMUX_PAD(0x358, 0x160, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_CSPI1_SS1__CSPI1_SS1 IOMUX_PAD(0x35c, 0x164, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSPI1_SS1__GPIO_1_17 IOMUX_PAD(0x35c, 0x164, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_CSPI1_SCLK__CSPI1_SCLK IOMUX_PAD(0x360, 0x168, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSPI1_SCLK__GPIO_1_18 IOMUX_PAD(0x360, 0x168, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_CSPI1_RDY__CSPI1_RDY IOMUX_PAD(0x364, 0x16c, 0x10, 0, 0, PAD_CTL_PKE) +#define MX25_PAD_CSPI1_RDY__GPIO_2_22 IOMUX_PAD(0x364, 0x16c, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_UART1_RXD__UART1_RXD IOMUX_PAD(0x368, 0x170, 0x10, 0, 0, PAD_CTL_PUS_100K_DOWN) +#define MX25_PAD_UART1_RXD__GPIO_4_22 IOMUX_PAD(0x368, 0x170, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_UART1_TXD__UART1_TXD IOMUX_PAD(0x36c, 0x174, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_UART1_TXD__GPIO_4_23 IOMUX_PAD(0x36c, 0x174, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_UART1_RTS__UART1_RTS IOMUX_PAD(0x370, 0x178, 0x10, 0, 0, PAD_CTL_PUS_100K_UP) +#define MX25_PAD_UART1_RTS__CSI_D0 IOMUX_PAD(0x370, 0x178, 0x11, 0x488, 1, NO_PAD_CTRL) +#define MX25_PAD_UART1_RTS__GPIO_4_24 IOMUX_PAD(0x370, 0x178, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_UART1_CTS__UART1_CTS IOMUX_PAD(0x374, 0x17c, 0x10, 0, 0, PAD_CTL_PUS_100K_UP) +#define MX25_PAD_UART1_CTS__CSI_D1 IOMUX_PAD(0x374, 0x17c, 0x11, 0x48c, 1, NO_PAD_CTRL) +#define MX25_PAD_UART1_CTS__GPIO_4_25 IOMUX_PAD(0x374, 0x17c, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_UART2_RXD__UART2_RXD IOMUX_PAD(0x378, 0x180, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_UART2_RXD__GPIO_4_26 IOMUX_PAD(0x378, 0x180, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_UART2_TXD__UART2_TXD IOMUX_PAD(0x37c, 0x184, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_UART2_TXD__GPIO_4_27 IOMUX_PAD(0x37c, 0x184, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_UART2_RTS__UART2_RTS IOMUX_PAD(0x380, 0x188, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_UART2_RTS__FEC_COL IOMUX_PAD(0x380, 0x188, 0x12, 0x504, 2, NO_PAD_CTRL) +#define MX25_PAD_UART2_RTS__GPIO_4_28 IOMUX_PAD(0x380, 0x188, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_UART2_CTS__FEC_RX_ER IOMUX_PAD(0x384, 0x18c, 0x12, 0x518, 2, NO_PAD_CTRL) +#define MX25_PAD_UART2_CTS__UART2_CTS IOMUX_PAD(0x384, 0x18c, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_UART2_CTS__GPIO_4_29 IOMUX_PAD(0x384, 0x18c, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x388, 0x190, 0x10, 0, 0, PAD_CTL_PUS_47K_UP) +#define MX25_PAD_SD1_CMD__FEC_RDATA2 IOMUX_PAD(0x388, 0x190, 0x12, 0x50c, 2, NO_PAD_CTRL) +#define MX25_PAD_SD1_CMD__GPIO_2_23 IOMUX_PAD(0x388, 0x190, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x38c, 0x194, 0x10, 0, 0, PAD_CTL_PUS_47K_UP) +#define MX25_PAD_SD1_CLK__FEC_RDATA3 IOMUX_PAD(0x38c, 0x194, 0x12, 0x510, 2, NO_PAD_CTRL) +#define MX25_PAD_SD1_CLK__GPIO_2_24 IOMUX_PAD(0x38c, 0x194, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_SD1_DATA0__SD1_DATA0 IOMUX_PAD(0x390, 0x198, 0x10, 0, 0, PAD_CTL_PUS_47K_UP) +#define MX25_PAD_SD1_DATA0__GPIO_2_25 IOMUX_PAD(0x390, 0x198, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_SD1_DATA1__SD1_DATA1 IOMUX_PAD(0x394, 0x19c, 0x10, 0, 0, PAD_CTL_PUS_47K_UP) +#define MX25_PAD_SD1_DATA1__AUD7_RXD IOMUX_PAD(0x394, 0x19c, 0x13, 0x478, 0, NO_PAD_CTRL) +#define MX25_PAD_SD1_DATA1__GPIO_2_26 IOMUX_PAD(0x394, 0x19c, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_SD1_DATA2__SD1_DATA2 IOMUX_PAD(0x398, 0x1a0, 0x10, 0, 0, PAD_CTL_PUS_47K_UP) +#define MX25_PAD_SD1_DATA2__FEC_RX_CLK IOMUX_PAD(0x398, 0x1a0, 0x15, 0x514, 2, NO_PAD_CTRL) +#define MX25_PAD_SD1_DATA2__GPIO_2_27 IOMUX_PAD(0x398, 0x1a0, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_SD1_DATA3__SD1_DATA3 IOMUX_PAD(0x39c, 0x1a4, 0x10, 0, 0, PAD_CTL_PUS_47K_UP) +#define MX25_PAD_SD1_DATA3__FEC_CRS IOMUX_PAD(0x39c, 0x1a4, 0x10, 0x508, 2, NO_PAD_CTRL) +#define MX25_PAD_SD1_DATA3__GPIO_2_28 IOMUX_PAD(0x39c, 0x1a4, 0x15, 0, 0, NO_PAD_CTRL) + +#define KPP_CTL_ROW (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) +#define KPP_CTL_COL (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP | PAD_CTL_ODE) + +#define MX25_PAD_KPP_ROW0__KPP_ROW0 IOMUX_PAD(0x3a0, 0x1a8, 0x10, 0, 0, KPP_CTL_ROW) +#define MX25_PAD_KPP_ROW0__GPIO_2_29 IOMUX_PAD(0x3a0, 0x1a8, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_KPP_ROW1__KPP_ROW1 IOMUX_PAD(0x3a4, 0x1ac, 0x10, 0, 0, KPP_CTL_ROW) +#define MX25_PAD_KPP_ROW1__GPIO_2_30 IOMUX_PAD(0x3a4, 0x1ac, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_KPP_ROW2__KPP_ROW2 IOMUX_PAD(0x3a8, 0x1b0, 0x10, 0, 0, KPP_CTL_ROW) +#define MX25_PAD_KPP_ROW2__CSI_D0 IOMUX_PAD(0x3a8, 0x1b0, 0x13, 0x488, 2, NO_PAD_CTRL) +#define MX25_PAD_KPP_ROW2__GPIO_2_31 IOMUX_PAD(0x3a8, 0x1b0, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_KPP_ROW3__KPP_ROW3 IOMUX_PAD(0x3ac, 0x1b4, 0x10, 0, 0, KPP_CTL_ROW) +#define MX25_PAD_KPP_ROW3__CSI_LD1 IOMUX_PAD(0x3ac, 0x1b4, 0x13, 0x48c, 2, NO_PAD_CTRL) +#define MX25_PAD_KPP_ROW3__GPIO_3_0 IOMUX_PAD(0x3ac, 0x1b4, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_KPP_COL0__KPP_COL0 IOMUX_PAD(0x3b0, 0x1b8, 0x10, 0, 0, KPP_CTL_COL) +#define MX25_PAD_KPP_COL0__UART4_RXD_MUX IOMUX_PAD(0x3b0, 0x1b8, 0x11, 0x570, 1, NO_PAD_CTRL) +#define MX25_PAD_KPP_COL0__AUD5_TXD IOMUX_PAD(0x3b0, 0x1b8, 0x12, 0, 0, PAD_CTL_PKE | PAD_CTL_PUS_100K_UP) +#define MX25_PAD_KPP_COL0__GPIO_3_1 IOMUX_PAD(0x3b0, 0x1b8, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_KPP_COL1__KPP_COL1 IOMUX_PAD(0x3b4, 0x1bc, 0x10, 0, 0, KPP_CTL_COL) +#define MX25_PAD_KPP_COL1__UART4_TXD_MUX IOMUX_PAD(0x3b4, 0x1bc, 0x11, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_KPP_COL1__AUD5_RXD IOMUX_PAD(0x3b4, 0x1bc, 0x12, 0, 0, PAD_CTL_PKE | PAD_CTL_PUS_100K_UP) +#define MX25_PAD_KPP_COL1__GPIO_3_2 IOMUX_PAD(0x3b4, 0x1bc, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_KPP_COL2__KPP_COL2 IOMUX_PAD(0x3b8, 0x1c0, 0x10, 0, 0, KPP_CTL_COL) +#define MX25_PAD_KPP_COL2__UART4_RTS IOMUX_PAD(0x3b8, 0x1c0, 0x11, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_KPP_COL2__AUD5_TXC IOMUX_PAD(0x3b8, 0x1c0, 0x12, 0, 0, PAD_CTL_PKE | PAD_CTL_PUS_100K_UP) +#define MX25_PAD_KPP_COL2__GPIO_3_3 IOMUX_PAD(0x3b8, 0x1c0, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_KPP_COL3__KPP_COL3 IOMUX_PAD(0x3bc, 0x1c4, 0x10, 0, 0, KPP_CTL_COL) +#define MX25_PAD_KPP_COL3__UART4_CTS IOMUX_PAD(0x3bc, 0x1c4, 0x11, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_KPP_COL3__AUD5_TXFS IOMUX_PAD(0x3bc, 0x1c4, 0x12, 0, 0, PAD_CTL_PKE | PAD_CTL_PUS_100K_UP) +#define MX25_PAD_KPP_COL3__GPIO_3_4 IOMUX_PAD(0x3bc, 0x1c4, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_FEC_MDC__FEC_MDC IOMUX_PAD(0x3c0, 0x1c8, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_FEC_MDC__AUD4_TXD IOMUX_PAD(0x3c0, 0x1c8, 0x12, 0x464, 1, NO_PAD_CTRL) +#define MX25_PAD_FEC_MDC__GPIO_3_5 IOMUX_PAD(0x3c0, 0x1c8, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_FEC_MDIO__FEC_MDIO IOMUX_PAD(0x3c4, 0x1cc, 0x10, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_22K_UP) +#define MX25_PAD_FEC_MDIO__AUD4_RXD IOMUX_PAD(0x3c4, 0x1cc, 0x12, 0x460, 1, NO_PAD_CTRL) +#define MX25_PAD_FEC_MDIO__GPIO_3_6 IOMUX_PAD(0x3c4, 0x1cc, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_FEC_TDATA0__FEC_TDATA0 IOMUX_PAD(0x3c8, 0x1d0, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_FEC_TDATA0__GPIO_3_7 IOMUX_PAD(0x3c8, 0x1d0, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_FEC_TDATA1__FEC_TDATA1 IOMUX_PAD(0x3cc, 0x1d4, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_FEC_TDATA1__AUD4_TXFS IOMUX_PAD(0x3cc, 0x1d4, 0x12, 0x474, 1, NO_PAD_CTRL) +#define MX25_PAD_FEC_TDATA1__GPIO_3_8 IOMUX_PAD(0x3cc, 0x1d4, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_FEC_TX_EN__FEC_TX_EN IOMUX_PAD(0x3d0, 0x1d8, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_FEC_TX_EN__GPIO_3_9 IOMUX_PAD(0x3d0, 0x1d8, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_FEC_RDATA0__FEC_RDATA0 IOMUX_PAD(0x3d4, 0x1dc, 0x10, 0, 0, PAD_CTL_PUS_100K_DOWN | NO_PAD_CTRL) +#define MX25_PAD_FEC_RDATA0__GPIO_3_10 IOMUX_PAD(0x3d4, 0x1dc, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_FEC_RDATA1__FEC_RDATA1 IOMUX_PAD(0x3d8, 0x1e0, 0x10, 0, 0, PAD_CTL_PUS_100K_DOWN | NO_PAD_CTRL) +#define MX25_PAD_FEC_RDATA1__GPIO_3_11 IOMUX_PAD(0x3d8, 0x1e0, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_FEC_RX_DV__FEC_RX_DV IOMUX_PAD(0x3dc, 0x1e4, 0x10, 0, 0, PAD_CTL_PUS_100K_DOWN | NO_PAD_CTRL) +#define MX25_PAD_FEC_RX_DV__CAN2_RX IOMUX_PAD(0x3dc, 0x1e4, 0x14, 0x484, 0, PAD_CTL_PUS_22K_UP) +#define MX25_PAD_FEC_RX_DV__GPIO_3_12 IOMUX_PAD(0x3dc, 0x1e4, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_FEC_TX_CLK__FEC_TX_CLK IOMUX_PAD(0x3e0, 0x1e8, 0x10, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN) +#define MX25_PAD_FEC_TX_CLK__GPIO_3_13 IOMUX_PAD(0x3e0, 0x1e8, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_RTCK__RTCK IOMUX_PAD(0x3e4, 0x1ec, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_RTCK__OWIRE IOMUX_PAD(0x3e4, 0x1ec, 0x11, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_RTCK__GPIO_3_14 IOMUX_PAD(0x3e4, 0x1ec, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_DE_B__DE_B IOMUX_PAD(0x3ec, 0x1f0, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_DE_B__GPIO_2_20 IOMUX_PAD(0x3ec, 0x1f0, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_TDO__TDO IOMUX_PAD(0x3e8, 0x000, 0x00, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_GPIO_A__GPIO_A IOMUX_PAD(0x3f0, 0x1f4, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_GPIO_A__CAN1_TX IOMUX_PAD(0x3f0, 0x1f4, 0x16, 0, 0, PAD_CTL_PUS_22K_UP) +#define MX25_PAD_GPIO_A__USBOTG_PWR IOMUX_PAD(0x3f0, 0x1f4, 0x12, 0, 0, PAD_CTL_PKE) + +#define MX25_PAD_GPIO_B__GPIO_B IOMUX_PAD(0x3f4, 0x1f8, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_GPIO_B__CAN1_RX IOMUX_PAD(0x3f4, 0x1f8, 0x16, 0x480, 1, PAD_CTL_PUS_22K) +#define MX25_PAD_GPIO_B__USBOTG_OC IOMUX_PAD(0x3f4, 0x1f8, 0x12, 0x57c, 1, PAD_CTL_PUS_100K_UP) + +#define MX25_PAD_GPIO_C__GPIO_C IOMUX_PAD(0x3f8, 0x1fc, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_GPIO_C__CAN2_TX IOMUX_PAD(0x3f8, 0x1fc, 0x16, 0, 0, PAD_CTL_PUS_22K_UP) + +#define MX25_PAD_GPIO_D__GPIO_D IOMUX_PAD(0x3fc, 0x200, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_GPIO_E__LD16 IOMUX_PAD(0x400, 0x204, 0x02, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_GPIO_D__CAN2_RX IOMUX_PAD(0x3fc, 0x200, 0x16, 0x484, 1, PAD_CTL_PUS_22K_UP) + +#define MX25_PAD_GPIO_E__GPIO_E IOMUX_PAD(0x400, 0x204, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_GPIO_F__LD17 IOMUX_PAD(0x404, 0x208, 0x02, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_GPIO_E__AUD7_TXD IOMUX_PAD(0x400, 0x204, 0x14, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_GPIO_F__GPIO_F IOMUX_PAD(0x404, 0x208, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_GPIO_F__AUD7_TXC IOMUX_PAD(0x404, 0x208, 0x14, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_EXT_ARMCLK__EXT_ARMCLK IOMUX_PAD(0x000, 0x20c, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_EXT_ARMCLK__GPIO_3_15 IOMUX_PAD(0x000, 0x20c, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_UPLL_BYPCLK__UPLL_BYPCLK IOMUX_PAD(0x000, 0x210, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_UPLL_BYPCLK__GPIO_3_16 IOMUX_PAD(0x000, 0x210, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_VSTBY_REQ__VSTBY_REQ IOMUX_PAD(0x408, 0x214, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_VSTBY_REQ__AUD7_TXFS IOMUX_PAD(0x408, 0x214, 0x14, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_VSTBY_REQ__GPIO_3_17 IOMUX_PAD(0x408, 0x214, 0x15, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_VSTBY_ACK__VSTBY_ACK IOMUX_PAD(0x40c, 0x218, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_VSTBY_ACK__GPIO_3_18 IOMUX_PAD(0x40c, 0x218, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_POWER_FAIL__POWER_FAIL IOMUX_PAD(0x410, 0x21c, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_POWER_FAIL__AUD7_RXD IOMUX_PAD(0x410, 0x21c, 0x14, 0x478, 1, NO_PAD_CTRL) +#define MX25_PAD_POWER_FAIL__GPIO_3_19 IOMUX_PAD(0x410, 0x21c, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_CLKO__CLKO IOMUX_PAD(0x414, 0x220, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CLKO__GPIO_2_21 IOMUX_PAD(0x414, 0x220, 0x15, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_BOOT_MODE0__BOOT_MODE0 IOMUX_PAD(0x000, 0x224, 0x00, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_BOOT_MODE0__GPIO_4_30 IOMUX_PAD(0x000, 0x224, 0x05, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_BOOT_MODE1__BOOT_MODE1 IOMUX_PAD(0x000, 0x228, 0x00, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_BOOT_MODE1__GPIO_4_31 IOMUX_PAD(0x000, 0x228, 0x05, 0, 0, NO_PAD_CTRL) + +#define MX25_PAD_CTL_GRP_DVS_MISC IOMUX_PAD(0x418, 0x000, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CTL_GRP_DSE_FEC IOMUX_PAD(0x41c, 0x000, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CTL_GRP_DVS_JTAG IOMUX_PAD(0x420, 0x000, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CTL_GRP_DSE_NFC IOMUX_PAD(0x424, 0x000, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CTL_GRP_DSE_CSI IOMUX_PAD(0x428, 0x000, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CTL_GRP_DSE_WEIM IOMUX_PAD(0x42c, 0x000, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CTL_GRP_DSE_DDR IOMUX_PAD(0x430, 0x000, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CTL_GRP_DVS_CRM IOMUX_PAD(0x434, 0x000, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CTL_GRP_DSE_KPP IOMUX_PAD(0x438, 0x000, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CTL_GRP_DSE_SDHC1 IOMUX_PAD(0x43c, 0x000, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CTL_GRP_DSE_LCD IOMUX_PAD(0x440, 0x000, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CTL_GRP_DSE_UART IOMUX_PAD(0x444, 0x000, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CTL_GRP_DVS_NFC IOMUX_PAD(0x448, 0x000, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CTL_GRP_DVS_CSI IOMUX_PAD(0x44c, 0x000, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CTL_GRP_DSE_CSPI1 IOMUX_PAD(0x450, 0x000, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CTL_GRP_DDRTYPE IOMUX_PAD(0x454, 0x000, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CTL_GRP_DVS_SDHC1 IOMUX_PAD(0x458, 0x000, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CTL_GRP_DVS_LCD IOMUX_PAD(0x45c, 0x000, 0, 0, 0, NO_PAD_CTRL) + +#endif /* __MACH_IOMUX_MX25_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx27.h b/arch/arm/plat-mxc/include/mach/iomux-mx27.h new file mode 100644 index 00000000..d9f9a6e3 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/iomux-mx27.h @@ -0,0 +1,205 @@ +/* + * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> + * Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ +#ifndef __MACH_IOMUX_MX27_H__ +#define __MACH_IOMUX_MX27_H__ + +#include <mach/iomux-mx2x.h> +#include <mach/iomux-v1.h> + +/* Primary GPIO pin functions */ + +#define PA0_PF_USBH2_CLK (GPIO_PORTA | GPIO_PF | 0) +#define PA1_PF_USBH2_DIR (GPIO_PORTA | GPIO_PF | 1) +#define PA2_PF_USBH2_DATA7 (GPIO_PORTA | GPIO_PF | 2) +#define PA3_PF_USBH2_NXT (GPIO_PORTA | GPIO_PF | 3) +#define PA4_PF_USBH2_STP (GPIO_PORTA | GPIO_PF | 4) +#define PB22_PF_USBH1_SUSP (GPIO_PORTB | GPIO_PF | 22) +#define PB25_PF_USBH1_RCV (GPIO_PORTB | GPIO_PF | 25) +#define PC5_PF_I2C2_SDA (GPIO_PORTC | GPIO_PF | GPIO_IN | 5) +#define PC6_PF_I2C2_SCL (GPIO_PORTC | GPIO_PF | GPIO_IN | 6) +#define PC7_PF_USBOTG_DATA5 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 7) +#define PC8_PF_USBOTG_DATA6 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 8) +#define PC9_PF_USBOTG_DATA0 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 9) +#define PC10_PF_USBOTG_DATA2 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 10) +#define PC11_PF_USBOTG_DATA1 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 11) +#define PC12_PF_USBOTG_DATA4 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 12) +#define PC13_PF_USBOTG_DATA3 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 13) +#define PC16_PF_SSI4_FS (GPIO_PORTC | GPIO_PF | GPIO_IN | 16) +#define PC17_PF_SSI4_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 17) +#define PC18_PF_SSI4_TXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 18) +#define PC19_PF_SSI4_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 19) +#define PD0_PF_SD3_CMD (GPIO_PORTD | GPIO_PF | 0) +#define PD1_PF_SD3_CLK (GPIO_PORTD | GPIO_PF | 1) +#define PD2_PF_ATA_DATA0 (GPIO_PORTD | GPIO_PF | 2) +#define PD3_PF_ATA_DATA1 (GPIO_PORTD | GPIO_PF | 3) +#define PD4_PF_ATA_DATA2 (GPIO_PORTD | GPIO_PF | 4) +#define PD5_PF_ATA_DATA3 (GPIO_PORTD | GPIO_PF | 5) +#define PD6_PF_ATA_DATA4 (GPIO_PORTD | GPIO_PF | 6) +#define PD7_PF_ATA_DATA5 (GPIO_PORTD | GPIO_PF | 7) +#define PD8_PF_ATA_DATA6 (GPIO_PORTD | GPIO_PF | 8) +#define PD9_PF_ATA_DATA7 (GPIO_PORTD | GPIO_PF | 9) +#define PD10_PF_ATA_DATA8 (GPIO_PORTD | GPIO_PF | 10) +#define PD11_PF_ATA_DATA9 (GPIO_PORTD | GPIO_PF | 11) +#define PD12_PF_ATA_DATA10 (GPIO_PORTD | GPIO_PF | 12) +#define PD13_PF_ATA_DATA11 (GPIO_PORTD | GPIO_PF | 13) +#define PD14_PF_ATA_DATA12 (GPIO_PORTD | GPIO_PF | 14) +#define PD15_PF_ATA_DATA13 (GPIO_PORTD | GPIO_PF | 15) +#define PD16_PF_ATA_DATA14 (GPIO_PORTD | GPIO_PF | 16) +#define PE0_PF_USBOTG_NXT (GPIO_PORTE | GPIO_PF | GPIO_OUT | 0) +#define PE1_PF_USBOTG_STP (GPIO_PORTE | GPIO_PF | GPIO_OUT | 1) +#define PE2_PF_USBOTG_DIR (GPIO_PORTE | GPIO_PF | GPIO_OUT | 2) +#define PE24_PF_USBOTG_CLK (GPIO_PORTE | GPIO_PF | GPIO_OUT | 24) +#define PE25_PF_USBOTG_DATA7 (GPIO_PORTE | GPIO_PF | GPIO_OUT | 25) +#define PF1_PF_NFCLE (GPIO_PORTF | GPIO_PF | 1) +#define PF3_PF_NFCE (GPIO_PORTF | GPIO_PF | 3) +#define PF7_PF_PC_POE (GPIO_PORTF | GPIO_PF | 7) +#define PF8_PF_PC_RW (GPIO_PORTF | GPIO_PF | 8) +#define PF9_PF_PC_IOIS16 (GPIO_PORTF | GPIO_PF | 9) +#define PF10_PF_PC_RST (GPIO_PORTF | GPIO_PF | 10) +#define PF11_PF_PC_BVD2 (GPIO_PORTF | GPIO_PF | 11) +#define PF12_PF_PC_BVD1 (GPIO_PORTF | GPIO_PF | 12) +#define PF13_PF_PC_VS2 (GPIO_PORTF | GPIO_PF | 13) +#define PF14_PF_PC_VS1 (GPIO_PORTF | GPIO_PF | 14) +#define PF16_PF_PC_PWRON (GPIO_PORTF | GPIO_PF | 16) +#define PF17_PF_PC_READY (GPIO_PORTF | GPIO_PF | 17) +#define PF18_PF_PC_WAIT (GPIO_PORTF | GPIO_PF | 18) +#define PF19_PF_PC_CD2 (GPIO_PORTF | GPIO_PF | 19) +#define PF20_PF_PC_CD1 (GPIO_PORTF | GPIO_PF | 20) +#define PF23_PF_ATA_DATA15 (GPIO_PORTF | GPIO_PF | 23) + +/* Alternate GPIO pin functions */ + +#define PB4_AF_MSHC_DATA0 (GPIO_PORTB | GPIO_AF | GPIO_OUT | 4) +#define PB5_AF_MSHC_DATA1 (GPIO_PORTB | GPIO_AF | GPIO_OUT | 5) +#define PB6_AF_MSHC_DATA2 (GPIO_PORTB | GPIO_AF | GPIO_OUT | 6) +#define PB7_AF_MSHC_DATA4 (GPIO_PORTB | GPIO_AF | GPIO_OUT | 7) +#define PB8_AF_MSHC_BS (GPIO_PORTB | GPIO_AF | GPIO_OUT | 8) +#define PB9_AF_MSHC_SCLK (GPIO_PORTB | GPIO_AF | GPIO_OUT | 9) +#define PB10_AF_UART6_TXD (GPIO_PORTB | GPIO_AF | GPIO_OUT | 10) +#define PB11_AF_UART6_RXD (GPIO_PORTB | GPIO_AF | GPIO_IN | 11) +#define PB12_AF_UART6_CTS (GPIO_PORTB | GPIO_AF | GPIO_OUT | 12) +#define PB13_AF_UART6_RTS (GPIO_PORTB | GPIO_AF | GPIO_IN | 13) +#define PB18_AF_UART5_TXD (GPIO_PORTB | GPIO_AF | GPIO_OUT | 18) +#define PB19_AF_UART5_RXD (GPIO_PORTB | GPIO_AF | GPIO_IN | 19) +#define PB20_AF_UART5_CTS (GPIO_PORTB | GPIO_AF | GPIO_OUT | 20) +#define PB21_AF_UART5_RTS (GPIO_PORTB | GPIO_AF | GPIO_IN | 21) +#define PC8_AF_FEC_MDIO (GPIO_PORTC | GPIO_AF | GPIO_IN | 8) +#define PC24_AF_GPT5_TOUT (GPIO_PORTC | GPIO_AF | 24) +#define PC25_AF_GPT5_TIN (GPIO_PORTC | GPIO_AF | 25) +#define PC26_AF_GPT4_TOUT (GPIO_PORTC | GPIO_AF | 26) +#define PC27_AF_GPT4_TIN (GPIO_PORTC | GPIO_AF | 27) +#define PD1_AF_ETMTRACE_PKT15 (GPIO_PORTD | GPIO_AF | 1) +#define PD6_AF_ETMTRACE_PKT14 (GPIO_PORTD | GPIO_AF | 6) +#define PD7_AF_ETMTRACE_PKT13 (GPIO_PORTD | GPIO_AF | 7) +#define PD9_AF_ETMTRACE_PKT12 (GPIO_PORTD | GPIO_AF | 9) +#define PD2_AF_SD3_D0 (GPIO_PORTD | GPIO_AF | 2) +#define PD3_AF_SD3_D1 (GPIO_PORTD | GPIO_AF | 3) +#define PD4_AF_SD3_D2 (GPIO_PORTD | GPIO_AF | 4) +#define PD5_AF_SD3_D3 (GPIO_PORTD | GPIO_AF | 5) +#define PD8_AF_FEC_MDIO (GPIO_PORTD | GPIO_AF | GPIO_IN | 8) +#define PD10_AF_ETMTRACE_PKT11 (GPIO_PORTD | GPIO_AF | 10) +#define PD11_AF_ETMTRACE_PKT10 (GPIO_PORTD | GPIO_AF | 11) +#define PD12_AF_ETMTRACE_PKT9 (GPIO_PORTD | GPIO_AF | 12) +#define PD13_AF_ETMTRACE_PKT8 (GPIO_PORTD | GPIO_AF | 13) +#define PD14_AF_ETMTRACE_PKT7 (GPIO_PORTD | GPIO_AF | 14) +#define PD15_AF_ETMTRACE_PKT6 (GPIO_PORTD | GPIO_AF | 15) +#define PD16_AF_ETMTRACE_PKT5 (GPIO_PORTD | GPIO_AF | 16) +#define PF1_AF_ETMTRACE_PKT0 (GPIO_PORTF | GPIO_AF | 1) +#define PF3_AF_ETMTRACE_PKT2 (GPIO_PORTF | GPIO_AF | 3) +#define PF5_AF_ETMPIPESTAT11 (GPIO_PORTF | GPIO_AF | 5) +#define PF7_AF_ATA_BUFFER_EN (GPIO_PORTF | GPIO_AF | 7) +#define PF8_AF_ATA_IORDY (GPIO_PORTF | GPIO_AF | 8) +#define PF9_AF_ATA_INTRQ (GPIO_PORTF | GPIO_AF | 9) +#define PF10_AF_ATA_RESET (GPIO_PORTF | GPIO_AF | 10) +#define PF11_AF_ATA_DMACK (GPIO_PORTF | GPIO_AF | 11) +#define PF12_AF_ATA_DMAREQ (GPIO_PORTF | GPIO_AF | 12) +#define PF13_AF_ATA_DA0 (GPIO_PORTF | GPIO_AF | 13) +#define PF14_AF_ATA_DA1 (GPIO_PORTF | GPIO_AF | 14) +#define PF15_AF_ETMTRACE_SYNC (GPIO_PORTF | GPIO_AF | 15) +#define PF16_AF_ATA_DA2 (GPIO_PORTF | GPIO_AF | 16) +#define PF17_AF_ATA_CS0 (GPIO_PORTF | GPIO_AF | 17) +#define PF18_AF_ATA_CS1 (GPIO_PORTF | GPIO_AF | 18) +#define PF19_AF_ATA_DIOW (GPIO_PORTF | GPIO_AF | 19) +#define PF20_AF_ATA_DIOR (GPIO_PORTF | GPIO_AF | 20) +#define PF22_AF_ETMTRACE_CLK (GPIO_PORTF | GPIO_AF | 22) +#define PF23_AF_ETMTRACE_PKT4 (GPIO_PORTF | GPIO_AF | 23) + +/* AIN GPIO pin functions */ + +#define PC14_AIN_SSI1_MCLK (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 14) +#define PC15_AIN_GPT6_TOUT (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 15) +#define PD0_AIN_FEC_TXD0 (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 0) +#define PD1_AIN_FEC_TXD1 (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 1) +#define PD2_AIN_FEC_TXD2 (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 2) +#define PD3_AIN_FEC_TXD3 (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 3) +#define PD9_AIN_FEC_MDC (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 9) +#define PD16_AIN_FEC_TX_ER (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 16) +#define PD27_AIN_EXT_DMA_GRANT (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 27) +#define PF23_AIN_FEC_TX_EN (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 23) + +/* BIN GPIO pin functions */ + +#define PC14_BIN_SSI2_MCLK (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 14) + +/* CIN GPIO pin functions */ + +#define PD2_CIN_SLCDC1_DAT0 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 2) +#define PD3_CIN_SLCDC1_DAT1 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 3) +#define PD4_CIN_SLCDC1_DAT2 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 4) +#define PD5_CIN_SLCDC1_DAT3 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 5) +#define PD6_CIN_SLCDC1_DAT4 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 6) +#define PD7_CIN_SLCDC1_DAT5 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 7) +#define PD8_CIN_SLCDC1_DAT6 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 8) +#define PD9_CIN_SLCDC1_DAT7 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 9) +#define PD10_CIN_SLCDC1_DAT8 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 10) +#define PD11_CIN_SLCDC1_DAT9 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 11) +#define PD12_CIN_SLCDC1_DAT10 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 12) +#define PD13_CIN_SLCDC1_DAT11 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 13) +#define PD14_CIN_SLCDC1_DAT12 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 14) +#define PD15_CIN_SLCDC1_DAT13 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 15) +#define PD16_CIN_SLCDC1_DAT14 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 16) +#define PD23_CIN_SLCDC1_DAT15 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 23) +#define PF27_CIN_EXT_DMA_GRANT (GPIO_PORTF | GPIO_CIN | GPIO_OUT | 27) +/* LCDC_TESTx on PBxx omitted, because it's not clear what they do */ + +/* AOUT GPIO pin functions */ + +#define PC14_AOUT_GPT6_TIN (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 14) +#define PD4_AOUT_FEC_RX_ER (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 4) +#define PD5_AOUT_FEC_RXD1 (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 5) +#define PD6_AOUT_FEC_RXD2 (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 6) +#define PD7_AOUT_FEC_RXD3 (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 7) +#define PD10_AOUT_FEC_CRS (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 10) +#define PD11_AOUT_FEC_TX_CLK (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 11) +#define PD12_AOUT_FEC_RXD0 (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 12) +#define PD13_AOUT_FEC_RX_DV (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 13) +#define PD14_AOUT_FEC_RX_CLK (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 14) +#define PD15_AOUT_FEC_COL (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 15) + +/* BOUT GPIO pin functions */ + +#define PC17_BOUT_PC_IOIS16 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 17) +#define PC18_BOUT_PC_BVD2 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 18) +#define PC19_BOUT_PC_BVD1 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 19) +#define PC28_BOUT_PC_BVD2 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 28) +#define PC29_BOUT_PC_VS1 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 29) +#define PC30_BOUT_PC_READY (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 30) +#define PC31_BOUT_PC_WAIT (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 31) + +#endif /* __MACH_IOMUX_MX27_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx2x.h b/arch/arm/plat-mxc/include/mach/iomux-mx2x.h new file mode 100644 index 00000000..7a9b20ab --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/iomux-mx2x.h @@ -0,0 +1,230 @@ +/* + * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> + * Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ +#ifndef __MACH_IOMUX_MX2x_H__ +#define __MACH_IOMUX_MX2x_H__ + +/* Primary GPIO pin functions */ + +#define PA5_PF_LSCLK (GPIO_PORTA | GPIO_PF | GPIO_OUT | 5) +#define PA6_PF_LD0 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 6) +#define PA7_PF_LD1 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 7) +#define PA8_PF_LD2 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 8) +#define PA9_PF_LD3 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 9) +#define PA10_PF_LD4 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 10) +#define PA11_PF_LD5 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 11) +#define PA12_PF_LD6 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 12) +#define PA13_PF_LD7 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 13) +#define PA14_PF_LD8 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 14) +#define PA15_PF_LD9 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 15) +#define PA16_PF_LD10 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 16) +#define PA17_PF_LD11 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 17) +#define PA18_PF_LD12 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 18) +#define PA19_PF_LD13 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 19) +#define PA20_PF_LD14 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 20) +#define PA21_PF_LD15 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 21) +#define PA22_PF_LD16 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 22) +#define PA23_PF_LD17 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 23) +#define PA24_PF_REV (GPIO_PORTA | GPIO_PF | GPIO_OUT | 24) +#define PA25_PF_CLS (GPIO_PORTA | GPIO_PF | GPIO_OUT | 25) +#define PA26_PF_PS (GPIO_PORTA | GPIO_PF | GPIO_OUT | 26) +#define PA27_PF_SPL_SPR (GPIO_PORTA | GPIO_PF | GPIO_OUT | 27) +#define PA28_PF_HSYNC (GPIO_PORTA | GPIO_PF | GPIO_OUT | 28) +#define PA29_PF_VSYNC (GPIO_PORTA | GPIO_PF | GPIO_OUT | 29) +#define PA30_PF_CONTRAST (GPIO_PORTA | GPIO_PF | GPIO_OUT | 30) +#define PA31_PF_OE_ACD (GPIO_PORTA | GPIO_PF | GPIO_OUT | 31) +#define PB4_PF_SD2_D0 (GPIO_PORTB | GPIO_PF | 4) +#define PB5_PF_SD2_D1 (GPIO_PORTB | GPIO_PF | 5) +#define PB6_PF_SD2_D2 (GPIO_PORTB | GPIO_PF | 6) +#define PB7_PF_SD2_D3 (GPIO_PORTB | GPIO_PF | 7) +#define PB8_PF_SD2_CMD (GPIO_PORTB | GPIO_PF | 8) +#define PB9_PF_SD2_CLK (GPIO_PORTB | GPIO_PF | 9) +#define PB10_PF_CSI_D0 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 10) +#define PB11_PF_CSI_D1 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 11) +#define PB12_PF_CSI_D2 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 12) +#define PB13_PF_CSI_D3 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 13) +#define PB14_PF_CSI_D4 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 14) +#define PB15_PF_CSI_MCLK (GPIO_PORTB | GPIO_PF | GPIO_OUT | 15) +#define PB16_PF_CSI_PIXCLK (GPIO_PORTB | GPIO_PF | GPIO_OUT | 16) +#define PB17_PF_CSI_D5 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 17) +#define PB18_PF_CSI_D6 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 18) +#define PB19_PF_CSI_D7 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 19) +#define PB20_PF_CSI_VSYNC (GPIO_PORTB | GPIO_PF | GPIO_OUT | 20) +#define PB21_PF_CSI_HSYNC (GPIO_PORTB | GPIO_PF | GPIO_OUT | 21) +#define PB23_PF_USB_PWR (GPIO_PORTB | GPIO_PF | 23) +#define PB24_PF_USB_OC (GPIO_PORTB | GPIO_PF | 24) +#define PB26_PF_USBH1_FS (GPIO_PORTB | GPIO_PF | 26) +#define PB27_PF_USBH1_OE (GPIO_PORTB | GPIO_PF | 27) +#define PB28_PF_USBH1_TXDM (GPIO_PORTB | GPIO_PF | 28) +#define PB29_PF_USBH1_TXDP (GPIO_PORTB | GPIO_PF | 29) +#define PB30_PF_USBH1_RXDM (GPIO_PORTB | GPIO_PF | 30) +#define PB31_PF_USBH1_RXDP (GPIO_PORTB | GPIO_PF | 31) +#define PC14_PF_TOUT (GPIO_PORTC | GPIO_PF | 14) +#define PC15_PF_TIN (GPIO_PORTC | GPIO_PF | 15) +#define PC20_PF_SSI1_FS (GPIO_PORTC | GPIO_PF | GPIO_IN | 20) +#define PC21_PF_SSI1_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 21) +#define PC22_PF_SSI1_TXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 22) +#define PC23_PF_SSI1_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 23) +#define PC24_PF_SSI2_FS (GPIO_PORTC | GPIO_PF | GPIO_IN | 24) +#define PC25_PF_SSI2_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 25) +#define PC26_PF_SSI2_TXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 26) +#define PC27_PF_SSI2_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 27) +#define PC28_PF_SSI3_FS (GPIO_PORTC | GPIO_PF | GPIO_IN | 28) +#define PC29_PF_SSI3_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 29) +#define PC30_PF_SSI3_TXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 30) +#define PC31_PF_SSI3_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 31) +#define PD17_PF_I2C_DATA (GPIO_PORTD | GPIO_PF | GPIO_OUT | 17) +#define PD18_PF_I2C_CLK (GPIO_PORTD | GPIO_PF | GPIO_OUT | 18) +#define PD19_PF_CSPI2_SS2 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 19) +#define PD20_PF_CSPI2_SS1 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 20) +#define PD21_PF_CSPI2_SS0 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 21) +#define PD22_PF_CSPI2_SCLK (GPIO_PORTD | GPIO_PF | GPIO_OUT | 22) +#define PD23_PF_CSPI2_MISO (GPIO_PORTD | GPIO_PF | GPIO_IN | 23) +#define PD24_PF_CSPI2_MOSI (GPIO_PORTD | GPIO_PF | GPIO_OUT | 24) +#define PD25_PF_CSPI1_RDY (GPIO_PORTD | GPIO_PF | GPIO_OUT | 25) +#define PD26_PF_CSPI1_SS2 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 26) +#define PD27_PF_CSPI1_SS1 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 27) +#define PD28_PF_CSPI1_SS0 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 28) +#define PD29_PF_CSPI1_SCLK (GPIO_PORTD | GPIO_PF | GPIO_OUT | 29) +#define PD30_PF_CSPI1_MISO (GPIO_PORTD | GPIO_PF | GPIO_IN | 30) +#define PD31_PF_CSPI1_MOSI (GPIO_PORTD | GPIO_PF | GPIO_OUT | 31) +#define PE3_PF_UART2_CTS (GPIO_PORTE | GPIO_PF | GPIO_OUT | 3) +#define PE4_PF_UART2_RTS (GPIO_PORTE | GPIO_PF | GPIO_IN | 4) +#define PE5_PF_PWMO (GPIO_PORTE | GPIO_PF | 5) +#define PE6_PF_UART2_TXD (GPIO_PORTE | GPIO_PF | GPIO_OUT | 6) +#define PE7_PF_UART2_RXD (GPIO_PORTE | GPIO_PF | GPIO_IN | 7) +#define PE8_PF_UART3_TXD (GPIO_PORTE | GPIO_PF | GPIO_OUT | 8) +#define PE9_PF_UART3_RXD (GPIO_PORTE | GPIO_PF | GPIO_IN | 9) +#define PE10_PF_UART3_CTS (GPIO_PORTE | GPIO_PF | GPIO_OUT | 10) +#define PE11_PF_UART3_RTS (GPIO_PORTE | GPIO_PF | GPIO_IN | 11) +#define PE12_PF_UART1_TXD (GPIO_PORTE | GPIO_PF | GPIO_OUT | 12) +#define PE13_PF_UART1_RXD (GPIO_PORTE | GPIO_PF | GPIO_IN | 13) +#define PE14_PF_UART1_CTS (GPIO_PORTE | GPIO_PF | GPIO_OUT | 14) +#define PE15_PF_UART1_RTS (GPIO_PORTE | GPIO_PF | GPIO_IN | 15) +#define PE16_PF_RTCK (GPIO_PORTE | GPIO_PF | GPIO_OUT | 16) +#define PE17_PF_RESET_OUT (GPIO_PORTE | GPIO_PF | 17) +#define PE18_PF_SD1_D0 (GPIO_PORTE | GPIO_PF | 18) +#define PE19_PF_SD1_D1 (GPIO_PORTE | GPIO_PF | 19) +#define PE20_PF_SD1_D2 (GPIO_PORTE | GPIO_PF | 20) +#define PE21_PF_SD1_D3 (GPIO_PORTE | GPIO_PF | 21) +#define PE22_PF_SD1_CMD (GPIO_PORTE | GPIO_PF | 22) +#define PE23_PF_SD1_CLK (GPIO_PORTE | GPIO_PF | 23) +#define PF0_PF_NRFB (GPIO_PORTF | GPIO_PF | 0) +#define PF2_PF_NFWP (GPIO_PORTF | GPIO_PF | 2) +#define PF4_PF_NFALE (GPIO_PORTF | GPIO_PF | 4) +#define PF5_PF_NFRE (GPIO_PORTF | GPIO_PF | 5) +#define PF6_PF_NFWE (GPIO_PORTF | GPIO_PF | 6) +#define PF15_PF_CLKO (GPIO_PORTF | GPIO_PF | 15) +#define PF21_PF_CS4 (GPIO_PORTF | GPIO_PF | 21) +#define PF22_PF_CS5 (GPIO_PORTF | GPIO_PF | 22) + +/* Alternate GPIO pin functions */ + +#define PB26_AF_UART4_RTS (GPIO_PORTB | GPIO_AF | GPIO_IN | 26) +#define PB28_AF_UART4_TXD (GPIO_PORTB | GPIO_AF | GPIO_OUT | 28) +#define PB29_AF_UART4_CTS (GPIO_PORTB | GPIO_AF | GPIO_OUT | 29) +#define PB31_AF_UART4_RXD (GPIO_PORTB | GPIO_AF | GPIO_IN | 31) +#define PC28_AF_SLCDC2_D0 (GPIO_PORTC | GPIO_AF | 28) +#define PC29_AF_SLCDC2_RS (GPIO_PORTC | GPIO_AF | 29) +#define PC30_AF_SLCDC2_CS (GPIO_PORTC | GPIO_AF | 30) +#define PC31_AF_SLCDC2_CLK (GPIO_PORTC | GPIO_AF | 31) +#define PD19_AF_USBH2_DATA4 (GPIO_PORTD | GPIO_AF | 19) +#define PD20_AF_USBH2_DATA3 (GPIO_PORTD | GPIO_AF | 20) +#define PD21_AF_USBH2_DATA6 (GPIO_PORTD | GPIO_AF | 21) +#define PD22_AF_USBH2_DATA0 (GPIO_PORTD | GPIO_AF | 22) +#define PD23_AF_USBH2_DATA2 (GPIO_PORTD | GPIO_AF | 23) +#define PD24_AF_USBH2_DATA1 (GPIO_PORTD | GPIO_AF | 24) +#define PD26_AF_USBH2_DATA5 (GPIO_PORTD | GPIO_AF | 26) +#define PE0_AF_KP_COL6 (GPIO_PORTE | GPIO_AF | 0) +#define PE1_AF_KP_ROW6 (GPIO_PORTE | GPIO_AF | 1) +#define PE2_AF_KP_ROW7 (GPIO_PORTE | GPIO_AF | 2) +#define PE3_AF_KP_COL7 (GPIO_PORTE | GPIO_AF | 3) +#define PE4_AF_KP_ROW7 (GPIO_PORTE | GPIO_AF | 4) +#define PE6_AF_KP_COL6 (GPIO_PORTE | GPIO_AF | 6) +#define PE7_AF_KP_ROW6 (GPIO_PORTE | GPIO_AF | 7) +#define PE16_AF_OWIRE (GPIO_PORTE | GPIO_AF | 16) +#define PE18_AF_CSPI3_MISO (GPIO_PORTE | GPIO_AF | GPIO_IN | 18) +#define PE21_AF_CSPI3_SS (GPIO_PORTE | GPIO_AF | GPIO_OUT | 21) +#define PE22_AF_CSPI3_MOSI (GPIO_PORTE | GPIO_AF | GPIO_OUT | 22) +#define PE23_AF_CSPI3_SCLK (GPIO_PORTE | GPIO_AF | GPIO_OUT | 23) + +/* AIN GPIO pin functions */ + +#define PA6_AIN_SLCDC1_DAT0 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 6) +#define PA7_AIN_SLCDC1_DAT1 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 7) +#define PA8_AIN_SLCDC1_DAT2 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 8) +#define PA0_AIN_SLCDC1_DAT3 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 0) +#define PA11_AIN_SLCDC1_DAT5 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 11) +#define PA13_AIN_SLCDC1_DAT7 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 13) +#define PA15_AIN_SLCDC1_DAT9 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 15) +#define PA17_AIN_SLCDC1_DAT11 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 17) +#define PA19_AIN_SLCDC1_DAT13 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 19) +#define PA21_AIN_SLCDC1_DAT15 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 21) +#define PA22_AIN_EXT_DMAGRANT (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 22) +#define PA24_AIN_SLCDC1_D0 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 24) +#define PA25_AIN_SLCDC1_RS (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 25) +#define PA26_AIN_SLCDC1_CS (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 26) +#define PA27_AIN_SLCDC1_CLK (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 27) +#define PB6_AIN_SLCDC1_D0 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 6) +#define PB7_AIN_SLCDC1_RS (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 7) +#define PB8_AIN_SLCDC1_CS (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 8) +#define PB9_AIN_SLCDC1_CLK (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 9) +#define PB25_AIN_SLCDC1_DAT0 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 25) +#define PB26_AIN_SLCDC1_DAT1 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 26) +#define PB27_AIN_SLCDC1_DAT2 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 27) +#define PB28_AIN_SLCDC1_DAT3 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 28) +#define PB29_AIN_SLCDC1_DAT4 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 29) +#define PB30_AIN_SLCDC1_DAT5 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 30) +#define PB31_AIN_SLCDC1_DAT6 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 31) +#define PC5_AIN_SLCDC1_DAT7 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 5) +#define PC6_AIN_SLCDC1_DAT8 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 6) +#define PC7_AIN_SLCDC1_DAT9 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 7) +#define PC8_AIN_SLCDC1_DAT10 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 8) +#define PC9_AIN_SLCDC1_DAT11 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 9) +#define PC10_AIN_SLCDC1_DAT12 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 10) +#define PC11_AIN_SLCDC1_DAT13 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 11) +#define PC12_AIN_SLCDC1_DAT14 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 12) +#define PC13_AIN_SLCDC1_DAT15 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 13) +#define PE5_AIN_PC_SPKOUT (GPIO_PORTE | GPIO_AIN | GPIO_OUT | 5) + +/* BIN GPIO pin functions */ + +#define PE5_BIN_TOUT2 (GPIO_PORTE | GPIO_BIN | GPIO_OUT | 5) + +/* CIN GPIO pin functions */ + +#define PA14_CIN_SLCDC1_DAT0 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 14) +#define PA15_CIN_SLCDC1_DAT1 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 15) +#define PA16_CIN_SLCDC1_DAT2 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 16) +#define PA17_CIN_SLCDC1_DAT3 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 17) +#define PA18_CIN_SLCDC1_DAT4 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 18) +#define PA19_CIN_SLCDC1_DAT5 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 19) +#define PA20_CIN_SLCDC1_DAT6 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 20) +#define PA21_CIN_SLCDC1_DAT7 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 21) +#define PB30_CIN_UART4_CTS (GPIO_PORTB | GPIO_CIN | GPIO_OUT | 30) +#define PE5_CIN_TOUT3 (GPIO_PORTE | GPIO_CIN | GPIO_OUT | 5) + +/* AOUT GPIO pin functions */ + +#define PB29_AOUT_UART4_RXD (GPIO_PORTB | GPIO_AOUT | GPIO_IN | 29) +#define PB31_AOUT_UART4_RTS (GPIO_PORTB | GPIO_AOUT | GPIO_IN | 31) +#define PC8_AOUT_USBOTG_TXR_INT (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 8) +#define PC15_AOUT_WKGD (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 15) +#define PF21_AOUT_DTACK (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 21) + +#endif /* ifndef __MACH_IOMUX_MX2x_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx3.h b/arch/arm/plat-mxc/include/mach/iomux-mx3.h new file mode 100644 index 00000000..c92f0b1f --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/iomux-mx3.h @@ -0,0 +1,750 @@ +/* + * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ +#ifndef __MACH_IOMUX_MX3_H__ +#define __MACH_IOMUX_MX3_H__ + +#include <linux/types.h> +/* + * various IOMUX output functions + */ + +#define IOMUX_OCONFIG_GPIO (0 << 4) /* used as GPIO */ +#define IOMUX_OCONFIG_FUNC (1 << 4) /* used as function */ +#define IOMUX_OCONFIG_ALT1 (2 << 4) /* used as alternate function 1 */ +#define IOMUX_OCONFIG_ALT2 (3 << 4) /* used as alternate function 2 */ +#define IOMUX_OCONFIG_ALT3 (4 << 4) /* used as alternate function 3 */ +#define IOMUX_OCONFIG_ALT4 (5 << 4) /* used as alternate function 4 */ +#define IOMUX_OCONFIG_ALT5 (6 << 4) /* used as alternate function 5 */ +#define IOMUX_OCONFIG_ALT6 (7 << 4) /* used as alternate function 6 */ +#define IOMUX_ICONFIG_NONE 0 /* not configured for input */ +#define IOMUX_ICONFIG_GPIO 1 /* used as GPIO */ +#define IOMUX_ICONFIG_FUNC 2 /* used as function */ +#define IOMUX_ICONFIG_ALT1 4 /* used as alternate function 1 */ +#define IOMUX_ICONFIG_ALT2 8 /* used as alternate function 2 */ + +#define IOMUX_CONFIG_GPIO (IOMUX_OCONFIG_GPIO | IOMUX_ICONFIG_GPIO) +#define IOMUX_CONFIG_FUNC (IOMUX_OCONFIG_FUNC | IOMUX_ICONFIG_FUNC) +#define IOMUX_CONFIG_ALT1 (IOMUX_OCONFIG_ALT1 | IOMUX_ICONFIG_ALT1) +#define IOMUX_CONFIG_ALT2 (IOMUX_OCONFIG_ALT2 | IOMUX_ICONFIG_ALT2) + +/* + * various IOMUX pad functions + */ +enum iomux_pad_config { + PAD_CTL_NOLOOPBACK = 0x0 << 9, + PAD_CTL_LOOPBACK = 0x1 << 9, + PAD_CTL_PKE_NONE = 0x0 << 8, + PAD_CTL_PKE_ENABLE = 0x1 << 8, + PAD_CTL_PUE_KEEPER = 0x0 << 7, + PAD_CTL_PUE_PUD = 0x1 << 7, + PAD_CTL_100K_PD = 0x0 << 5, + PAD_CTL_100K_PU = 0x1 << 5, + PAD_CTL_47K_PU = 0x2 << 5, + PAD_CTL_22K_PU = 0x3 << 5, + PAD_CTL_HYS_CMOS = 0x0 << 4, + PAD_CTL_HYS_SCHMITZ = 0x1 << 4, + PAD_CTL_ODE_CMOS = 0x0 << 3, + PAD_CTL_ODE_OpenDrain = 0x1 << 3, + PAD_CTL_DRV_NORMAL = 0x0 << 1, + PAD_CTL_DRV_HIGH = 0x1 << 1, + PAD_CTL_DRV_MAX = 0x2 << 1, + PAD_CTL_SRE_SLOW = 0x0 << 0, + PAD_CTL_SRE_FAST = 0x1 << 0 +}; + +/* + * various IOMUX general purpose functions + */ +enum iomux_gp_func { + MUX_PGP_FIRI = 1 << 0, + MUX_DDR_MODE = 1 << 1, + MUX_PGP_CSPI_BB = 1 << 2, + MUX_PGP_ATA_1 = 1 << 3, + MUX_PGP_ATA_2 = 1 << 4, + MUX_PGP_ATA_3 = 1 << 5, + MUX_PGP_ATA_4 = 1 << 6, + MUX_PGP_ATA_5 = 1 << 7, + MUX_PGP_ATA_6 = 1 << 8, + MUX_PGP_ATA_7 = 1 << 9, + MUX_PGP_ATA_8 = 1 << 10, + MUX_PGP_UH2 = 1 << 11, + MUX_SDCTL_CSD0_SEL = 1 << 12, + MUX_SDCTL_CSD1_SEL = 1 << 13, + MUX_CSPI1_UART3 = 1 << 14, + MUX_EXTDMAREQ2_MBX_SEL = 1 << 15, + MUX_TAMPER_DETECT_EN = 1 << 16, + MUX_PGP_USB_4WIRE = 1 << 17, + MUX_PGP_USB_COMMON = 1 << 18, + MUX_SDHC_MEMSTICK1 = 1 << 19, + MUX_SDHC_MEMSTICK2 = 1 << 20, + MUX_PGP_SPLL_BYP = 1 << 21, + MUX_PGP_UPLL_BYP = 1 << 22, + MUX_PGP_MSHC1_CLK_SEL = 1 << 23, + MUX_PGP_MSHC2_CLK_SEL = 1 << 24, + MUX_CSPI3_UART5_SEL = 1 << 25, + MUX_PGP_ATA_9 = 1 << 26, + MUX_PGP_USB_SUSPEND = 1 << 27, + MUX_PGP_USB_OTG_LOOPBACK = 1 << 28, + MUX_PGP_USB_HS1_LOOPBACK = 1 << 29, + MUX_PGP_USB_HS2_LOOPBACK = 1 << 30, + MUX_CLKO_DDR_MODE = 1 << 31, +}; + +/* + * setups a single pin: + * - reserves the pin so that it is not claimed by another driver + * - setups the iomux according to the configuration + * - if the pin is configured as a GPIO, we claim it through kernel gpiolib + */ +int mxc_iomux_alloc_pin(unsigned int pin, const char *label); +/* + * setups mutliple pins + * convenient way to call the above function with tables + */ +int mxc_iomux_setup_multiple_pins(const unsigned int *pin_list, unsigned count, + const char *label); + +/* + * releases a single pin: + * - make it available for a future use by another driver + * - frees the GPIO if the pin was configured as GPIO + * - DOES NOT reconfigure the IOMUX in its reset state + */ +void mxc_iomux_release_pin(unsigned int pin); +/* + * releases multiple pins + * convenvient way to call the above function with tables + */ +void mxc_iomux_release_multiple_pins(const unsigned int *pin_list, int count); + +/* + * This function enables/disables the general purpose function for a particular + * signal. + */ +void mxc_iomux_set_gpr(enum iomux_gp_func, bool en); + +/* + * This function only configures the iomux hardware. + * It is called by the setup functions and should not be called directly anymore. + * It is here visible for backward compatibility + */ +int mxc_iomux_mode(unsigned int pin_mode); + +#define IOMUX_PADNUM_MASK 0x1ff +#define IOMUX_GPIONUM_SHIFT 9 +#define IOMUX_GPIONUM_MASK (0xff << IOMUX_GPIONUM_SHIFT) +#define IOMUX_MODE_SHIFT 17 +#define IOMUX_MODE_MASK (0xff << IOMUX_MODE_SHIFT) + +#define IOMUX_PIN(gpionum, padnum) \ + (((gpionum << IOMUX_GPIONUM_SHIFT) & IOMUX_GPIONUM_MASK) | \ + (padnum & IOMUX_PADNUM_MASK)) + +#define IOMUX_MODE(pin, mode) (pin | mode << IOMUX_MODE_SHIFT) + +#define IOMUX_TO_GPIO(iomux_pin) \ + ((iomux_pin & IOMUX_GPIONUM_MASK) >> IOMUX_GPIONUM_SHIFT) +#define IOMUX_TO_IRQ(iomux_pin) \ + (((iomux_pin & IOMUX_GPIONUM_MASK) >> IOMUX_GPIONUM_SHIFT) + \ + MXC_GPIO_IRQ_START) + +/* + * This enumeration is constructed based on the Section + * "sw_pad_ctl & sw_mux_ctl details" of the MX31 IC Spec. Each enumerated + * value is constructed based on the rules described above. + */ + +enum iomux_pins { + MX31_PIN_TTM_PAD = IOMUX_PIN(0xff, 0), + MX31_PIN_CSPI3_SPI_RDY = IOMUX_PIN(0xff, 1), + MX31_PIN_CSPI3_SCLK = IOMUX_PIN(0xff, 2), + MX31_PIN_CSPI3_MISO = IOMUX_PIN(0xff, 3), + MX31_PIN_CSPI3_MOSI = IOMUX_PIN(0xff, 4), + MX31_PIN_CLKSS = IOMUX_PIN(0xff, 5), + MX31_PIN_CE_CONTROL = IOMUX_PIN(0xff, 6), + MX31_PIN_ATA_RESET_B = IOMUX_PIN(95, 7), + MX31_PIN_ATA_DMACK = IOMUX_PIN(94, 8), + MX31_PIN_ATA_DIOW = IOMUX_PIN(93, 9), + MX31_PIN_ATA_DIOR = IOMUX_PIN(92, 10), + MX31_PIN_ATA_CS1 = IOMUX_PIN(91, 11), + MX31_PIN_ATA_CS0 = IOMUX_PIN(90, 12), + MX31_PIN_SD1_DATA3 = IOMUX_PIN(63, 13), + MX31_PIN_SD1_DATA2 = IOMUX_PIN(62, 14), + MX31_PIN_SD1_DATA1 = IOMUX_PIN(61, 15), + MX31_PIN_SD1_DATA0 = IOMUX_PIN(60, 16), + MX31_PIN_SD1_CLK = IOMUX_PIN(59, 17), + MX31_PIN_SD1_CMD = IOMUX_PIN(58, 18), + MX31_PIN_D3_SPL = IOMUX_PIN(0xff, 19), + MX31_PIN_D3_CLS = IOMUX_PIN(0xff, 20), + MX31_PIN_D3_REV = IOMUX_PIN(0xff, 21), + MX31_PIN_CONTRAST = IOMUX_PIN(0xff, 22), + MX31_PIN_VSYNC3 = IOMUX_PIN(0xff, 23), + MX31_PIN_READ = IOMUX_PIN(0xff, 24), + MX31_PIN_WRITE = IOMUX_PIN(0xff, 25), + MX31_PIN_PAR_RS = IOMUX_PIN(0xff, 26), + MX31_PIN_SER_RS = IOMUX_PIN(89, 27), + MX31_PIN_LCS1 = IOMUX_PIN(88, 28), + MX31_PIN_LCS0 = IOMUX_PIN(87, 29), + MX31_PIN_SD_D_CLK = IOMUX_PIN(86, 30), + MX31_PIN_SD_D_IO = IOMUX_PIN(85, 31), + MX31_PIN_SD_D_I = IOMUX_PIN(84, 32), + MX31_PIN_DRDY0 = IOMUX_PIN(0xff, 33), + MX31_PIN_FPSHIFT = IOMUX_PIN(0xff, 34), + MX31_PIN_HSYNC = IOMUX_PIN(0xff, 35), + MX31_PIN_VSYNC0 = IOMUX_PIN(0xff, 36), + MX31_PIN_LD17 = IOMUX_PIN(0xff, 37), + MX31_PIN_LD16 = IOMUX_PIN(0xff, 38), + MX31_PIN_LD15 = IOMUX_PIN(0xff, 39), + MX31_PIN_LD14 = IOMUX_PIN(0xff, 40), + MX31_PIN_LD13 = IOMUX_PIN(0xff, 41), + MX31_PIN_LD12 = IOMUX_PIN(0xff, 42), + MX31_PIN_LD11 = IOMUX_PIN(0xff, 43), + MX31_PIN_LD10 = IOMUX_PIN(0xff, 44), + MX31_PIN_LD9 = IOMUX_PIN(0xff, 45), + MX31_PIN_LD8 = IOMUX_PIN(0xff, 46), + MX31_PIN_LD7 = IOMUX_PIN(0xff, 47), + MX31_PIN_LD6 = IOMUX_PIN(0xff, 48), + MX31_PIN_LD5 = IOMUX_PIN(0xff, 49), + MX31_PIN_LD4 = IOMUX_PIN(0xff, 50), + MX31_PIN_LD3 = IOMUX_PIN(0xff, 51), + MX31_PIN_LD2 = IOMUX_PIN(0xff, 52), + MX31_PIN_LD1 = IOMUX_PIN(0xff, 53), + MX31_PIN_LD0 = IOMUX_PIN(0xff, 54), + MX31_PIN_USBH2_DATA1 = IOMUX_PIN(0xff, 55), + MX31_PIN_USBH2_DATA0 = IOMUX_PIN(0xff, 56), + MX31_PIN_USBH2_NXT = IOMUX_PIN(0xff, 57), + MX31_PIN_USBH2_STP = IOMUX_PIN(0xff, 58), + MX31_PIN_USBH2_DIR = IOMUX_PIN(0xff, 59), + MX31_PIN_USBH2_CLK = IOMUX_PIN(0xff, 60), + MX31_PIN_USBOTG_DATA7 = IOMUX_PIN(0xff, 61), + MX31_PIN_USBOTG_DATA6 = IOMUX_PIN(0xff, 62), + MX31_PIN_USBOTG_DATA5 = IOMUX_PIN(0xff, 63), + MX31_PIN_USBOTG_DATA4 = IOMUX_PIN(0xff, 64), + MX31_PIN_USBOTG_DATA3 = IOMUX_PIN(0xff, 65), + MX31_PIN_USBOTG_DATA2 = IOMUX_PIN(0xff, 66), + MX31_PIN_USBOTG_DATA1 = IOMUX_PIN(0xff, 67), + MX31_PIN_USBOTG_DATA0 = IOMUX_PIN(0xff, 68), + MX31_PIN_USBOTG_NXT = IOMUX_PIN(0xff, 69), + MX31_PIN_USBOTG_STP = IOMUX_PIN(0xff, 70), + MX31_PIN_USBOTG_DIR = IOMUX_PIN(0xff, 71), + MX31_PIN_USBOTG_CLK = IOMUX_PIN(0xff, 72), + MX31_PIN_USB_BYP = IOMUX_PIN(31, 73), + MX31_PIN_USB_OC = IOMUX_PIN(30, 74), + MX31_PIN_USB_PWR = IOMUX_PIN(29, 75), + MX31_PIN_SJC_MOD = IOMUX_PIN(0xff, 76), + MX31_PIN_DE_B = IOMUX_PIN(0xff, 77), + MX31_PIN_TRSTB = IOMUX_PIN(0xff, 78), + MX31_PIN_TDO = IOMUX_PIN(0xff, 79), + MX31_PIN_TDI = IOMUX_PIN(0xff, 80), + MX31_PIN_TMS = IOMUX_PIN(0xff, 81), + MX31_PIN_TCK = IOMUX_PIN(0xff, 82), + MX31_PIN_RTCK = IOMUX_PIN(0xff, 83), + MX31_PIN_KEY_COL7 = IOMUX_PIN(57, 84), + MX31_PIN_KEY_COL6 = IOMUX_PIN(56, 85), + MX31_PIN_KEY_COL5 = IOMUX_PIN(55, 86), + MX31_PIN_KEY_COL4 = IOMUX_PIN(54, 87), + MX31_PIN_KEY_COL3 = IOMUX_PIN(0xff, 88), + MX31_PIN_KEY_COL2 = IOMUX_PIN(0xff, 89), + MX31_PIN_KEY_COL1 = IOMUX_PIN(0xff, 90), + MX31_PIN_KEY_COL0 = IOMUX_PIN(0xff, 91), + MX31_PIN_KEY_ROW7 = IOMUX_PIN(53, 92), + MX31_PIN_KEY_ROW6 = IOMUX_PIN(52, 93), + MX31_PIN_KEY_ROW5 = IOMUX_PIN(51, 94), + MX31_PIN_KEY_ROW4 = IOMUX_PIN(50, 95), + MX31_PIN_KEY_ROW3 = IOMUX_PIN(0xff, 96), + MX31_PIN_KEY_ROW2 = IOMUX_PIN(0xff, 97), + MX31_PIN_KEY_ROW1 = IOMUX_PIN(0xff, 98), + MX31_PIN_KEY_ROW0 = IOMUX_PIN(0xff, 99), + MX31_PIN_BATT_LINE = IOMUX_PIN(49, 100), + MX31_PIN_CTS2 = IOMUX_PIN(0xff, 101), + MX31_PIN_RTS2 = IOMUX_PIN(0xff, 102), + MX31_PIN_TXD2 = IOMUX_PIN(28, 103), + MX31_PIN_RXD2 = IOMUX_PIN(27, 104), + MX31_PIN_DTR_DCE2 = IOMUX_PIN(48, 105), + MX31_PIN_DCD_DTE1 = IOMUX_PIN(47, 106), + MX31_PIN_RI_DTE1 = IOMUX_PIN(46, 107), + MX31_PIN_DSR_DTE1 = IOMUX_PIN(45, 108), + MX31_PIN_DTR_DTE1 = IOMUX_PIN(44, 109), + MX31_PIN_DCD_DCE1 = IOMUX_PIN(43, 110), + MX31_PIN_RI_DCE1 = IOMUX_PIN(42, 111), + MX31_PIN_DSR_DCE1 = IOMUX_PIN(41, 112), + MX31_PIN_DTR_DCE1 = IOMUX_PIN(40, 113), + MX31_PIN_CTS1 = IOMUX_PIN(39, 114), + MX31_PIN_RTS1 = IOMUX_PIN(38, 115), + MX31_PIN_TXD1 = IOMUX_PIN(37, 116), + MX31_PIN_RXD1 = IOMUX_PIN(36, 117), + MX31_PIN_CSPI2_SPI_RDY = IOMUX_PIN(0xff, 118), + MX31_PIN_CSPI2_SCLK = IOMUX_PIN(0xff, 119), + MX31_PIN_CSPI2_SS2 = IOMUX_PIN(0xff, 120), + MX31_PIN_CSPI2_SS1 = IOMUX_PIN(0xff, 121), + MX31_PIN_CSPI2_SS0 = IOMUX_PIN(0xff, 122), + MX31_PIN_CSPI2_MISO = IOMUX_PIN(0xff, 123), + MX31_PIN_CSPI2_MOSI = IOMUX_PIN(0xff, 124), + MX31_PIN_CSPI1_SPI_RDY = IOMUX_PIN(0xff, 125), + MX31_PIN_CSPI1_SCLK = IOMUX_PIN(0xff, 126), + MX31_PIN_CSPI1_SS2 = IOMUX_PIN(0xff, 127), + MX31_PIN_CSPI1_SS1 = IOMUX_PIN(0xff, 128), + MX31_PIN_CSPI1_SS0 = IOMUX_PIN(0xff, 129), + MX31_PIN_CSPI1_MISO = IOMUX_PIN(0xff, 130), + MX31_PIN_CSPI1_MOSI = IOMUX_PIN(0xff, 131), + MX31_PIN_SFS6 = IOMUX_PIN(26, 132), + MX31_PIN_SCK6 = IOMUX_PIN(25, 133), + MX31_PIN_SRXD6 = IOMUX_PIN(24, 134), + MX31_PIN_STXD6 = IOMUX_PIN(23, 135), + MX31_PIN_SFS5 = IOMUX_PIN(0xff, 136), + MX31_PIN_SCK5 = IOMUX_PIN(0xff, 137), + MX31_PIN_SRXD5 = IOMUX_PIN(22, 138), + MX31_PIN_STXD5 = IOMUX_PIN(21, 139), + MX31_PIN_SFS4 = IOMUX_PIN(0xff, 140), + MX31_PIN_SCK4 = IOMUX_PIN(0xff, 141), + MX31_PIN_SRXD4 = IOMUX_PIN(20, 142), + MX31_PIN_STXD4 = IOMUX_PIN(19, 143), + MX31_PIN_SFS3 = IOMUX_PIN(0xff, 144), + MX31_PIN_SCK3 = IOMUX_PIN(0xff, 145), + MX31_PIN_SRXD3 = IOMUX_PIN(18, 146), + MX31_PIN_STXD3 = IOMUX_PIN(17, 147), + MX31_PIN_I2C_DAT = IOMUX_PIN(0xff, 148), + MX31_PIN_I2C_CLK = IOMUX_PIN(0xff, 149), + MX31_PIN_CSI_PIXCLK = IOMUX_PIN(83, 150), + MX31_PIN_CSI_HSYNC = IOMUX_PIN(82, 151), + MX31_PIN_CSI_VSYNC = IOMUX_PIN(81, 152), + MX31_PIN_CSI_MCLK = IOMUX_PIN(80, 153), + MX31_PIN_CSI_D15 = IOMUX_PIN(79, 154), + MX31_PIN_CSI_D14 = IOMUX_PIN(78, 155), + MX31_PIN_CSI_D13 = IOMUX_PIN(77, 156), + MX31_PIN_CSI_D12 = IOMUX_PIN(76, 157), + MX31_PIN_CSI_D11 = IOMUX_PIN(75, 158), + MX31_PIN_CSI_D10 = IOMUX_PIN(74, 159), + MX31_PIN_CSI_D9 = IOMUX_PIN(73, 160), + MX31_PIN_CSI_D8 = IOMUX_PIN(72, 161), + MX31_PIN_CSI_D7 = IOMUX_PIN(71, 162), + MX31_PIN_CSI_D6 = IOMUX_PIN(70, 163), + MX31_PIN_CSI_D5 = IOMUX_PIN(69, 164), + MX31_PIN_CSI_D4 = IOMUX_PIN(68, 165), + MX31_PIN_M_GRANT = IOMUX_PIN(0xff, 166), + MX31_PIN_M_REQUEST = IOMUX_PIN(0xff, 167), + MX31_PIN_PC_POE = IOMUX_PIN(0xff, 168), + MX31_PIN_PC_RW_B = IOMUX_PIN(0xff, 169), + MX31_PIN_IOIS16 = IOMUX_PIN(0xff, 170), + MX31_PIN_PC_RST = IOMUX_PIN(0xff, 171), + MX31_PIN_PC_BVD2 = IOMUX_PIN(0xff, 172), + MX31_PIN_PC_BVD1 = IOMUX_PIN(0xff, 173), + MX31_PIN_PC_VS2 = IOMUX_PIN(0xff, 174), + MX31_PIN_PC_VS1 = IOMUX_PIN(0xff, 175), + MX31_PIN_PC_PWRON = IOMUX_PIN(0xff, 176), + MX31_PIN_PC_READY = IOMUX_PIN(0xff, 177), + MX31_PIN_PC_WAIT_B = IOMUX_PIN(0xff, 178), + MX31_PIN_PC_CD2_B = IOMUX_PIN(0xff, 179), + MX31_PIN_PC_CD1_B = IOMUX_PIN(0xff, 180), + MX31_PIN_D0 = IOMUX_PIN(0xff, 181), + MX31_PIN_D1 = IOMUX_PIN(0xff, 182), + MX31_PIN_D2 = IOMUX_PIN(0xff, 183), + MX31_PIN_D3 = IOMUX_PIN(0xff, 184), + MX31_PIN_D4 = IOMUX_PIN(0xff, 185), + MX31_PIN_D5 = IOMUX_PIN(0xff, 186), + MX31_PIN_D6 = IOMUX_PIN(0xff, 187), + MX31_PIN_D7 = IOMUX_PIN(0xff, 188), + MX31_PIN_D8 = IOMUX_PIN(0xff, 189), + MX31_PIN_D9 = IOMUX_PIN(0xff, 190), + MX31_PIN_D10 = IOMUX_PIN(0xff, 191), + MX31_PIN_D11 = IOMUX_PIN(0xff, 192), + MX31_PIN_D12 = IOMUX_PIN(0xff, 193), + MX31_PIN_D13 = IOMUX_PIN(0xff, 194), + MX31_PIN_D14 = IOMUX_PIN(0xff, 195), + MX31_PIN_D15 = IOMUX_PIN(0xff, 196), + MX31_PIN_NFRB = IOMUX_PIN(16, 197), + MX31_PIN_NFCE_B = IOMUX_PIN(15, 198), + MX31_PIN_NFWP_B = IOMUX_PIN(14, 199), + MX31_PIN_NFCLE = IOMUX_PIN(13, 200), + MX31_PIN_NFALE = IOMUX_PIN(12, 201), + MX31_PIN_NFRE_B = IOMUX_PIN(11, 202), + MX31_PIN_NFWE_B = IOMUX_PIN(10, 203), + MX31_PIN_SDQS3 = IOMUX_PIN(0xff, 204), + MX31_PIN_SDQS2 = IOMUX_PIN(0xff, 205), + MX31_PIN_SDQS1 = IOMUX_PIN(0xff, 206), + MX31_PIN_SDQS0 = IOMUX_PIN(0xff, 207), + MX31_PIN_SDCLK_B = IOMUX_PIN(0xff, 208), + MX31_PIN_SDCLK = IOMUX_PIN(0xff, 209), + MX31_PIN_SDCKE1 = IOMUX_PIN(0xff, 210), + MX31_PIN_SDCKE0 = IOMUX_PIN(0xff, 211), + MX31_PIN_SDWE = IOMUX_PIN(0xff, 212), + MX31_PIN_CAS = IOMUX_PIN(0xff, 213), + MX31_PIN_RAS = IOMUX_PIN(0xff, 214), + MX31_PIN_RW = IOMUX_PIN(0xff, 215), + MX31_PIN_BCLK = IOMUX_PIN(0xff, 216), + MX31_PIN_LBA = IOMUX_PIN(0xff, 217), + MX31_PIN_ECB = IOMUX_PIN(0xff, 218), + MX31_PIN_CS5 = IOMUX_PIN(0xff, 219), + MX31_PIN_CS4 = IOMUX_PIN(0xff, 220), + MX31_PIN_CS3 = IOMUX_PIN(0xff, 221), + MX31_PIN_CS2 = IOMUX_PIN(0xff, 222), + MX31_PIN_CS1 = IOMUX_PIN(0xff, 223), + MX31_PIN_CS0 = IOMUX_PIN(0xff, 224), + MX31_PIN_OE = IOMUX_PIN(0xff, 225), + MX31_PIN_EB1 = IOMUX_PIN(0xff, 226), + MX31_PIN_EB0 = IOMUX_PIN(0xff, 227), + MX31_PIN_DQM3 = IOMUX_PIN(0xff, 228), + MX31_PIN_DQM2 = IOMUX_PIN(0xff, 229), + MX31_PIN_DQM1 = IOMUX_PIN(0xff, 230), + MX31_PIN_DQM0 = IOMUX_PIN(0xff, 231), + MX31_PIN_SD31 = IOMUX_PIN(0xff, 232), + MX31_PIN_SD30 = IOMUX_PIN(0xff, 233), + MX31_PIN_SD29 = IOMUX_PIN(0xff, 234), + MX31_PIN_SD28 = IOMUX_PIN(0xff, 235), + MX31_PIN_SD27 = IOMUX_PIN(0xff, 236), + MX31_PIN_SD26 = IOMUX_PIN(0xff, 237), + MX31_PIN_SD25 = IOMUX_PIN(0xff, 238), + MX31_PIN_SD24 = IOMUX_PIN(0xff, 239), + MX31_PIN_SD23 = IOMUX_PIN(0xff, 240), + MX31_PIN_SD22 = IOMUX_PIN(0xff, 241), + MX31_PIN_SD21 = IOMUX_PIN(0xff, 242), + MX31_PIN_SD20 = IOMUX_PIN(0xff, 243), + MX31_PIN_SD19 = IOMUX_PIN(0xff, 244), + MX31_PIN_SD18 = IOMUX_PIN(0xff, 245), + MX31_PIN_SD17 = IOMUX_PIN(0xff, 246), + MX31_PIN_SD16 = IOMUX_PIN(0xff, 247), + MX31_PIN_SD15 = IOMUX_PIN(0xff, 248), + MX31_PIN_SD14 = IOMUX_PIN(0xff, 249), + MX31_PIN_SD13 = IOMUX_PIN(0xff, 250), + MX31_PIN_SD12 = IOMUX_PIN(0xff, 251), + MX31_PIN_SD11 = IOMUX_PIN(0xff, 252), + MX31_PIN_SD10 = IOMUX_PIN(0xff, 253), + MX31_PIN_SD9 = IOMUX_PIN(0xff, 254), + MX31_PIN_SD8 = IOMUX_PIN(0xff, 255), + MX31_PIN_SD7 = IOMUX_PIN(0xff, 256), + MX31_PIN_SD6 = IOMUX_PIN(0xff, 257), + MX31_PIN_SD5 = IOMUX_PIN(0xff, 258), + MX31_PIN_SD4 = IOMUX_PIN(0xff, 259), + MX31_PIN_SD3 = IOMUX_PIN(0xff, 260), + MX31_PIN_SD2 = IOMUX_PIN(0xff, 261), + MX31_PIN_SD1 = IOMUX_PIN(0xff, 262), + MX31_PIN_SD0 = IOMUX_PIN(0xff, 263), + MX31_PIN_SDBA0 = IOMUX_PIN(0xff, 264), + MX31_PIN_SDBA1 = IOMUX_PIN(0xff, 265), + MX31_PIN_A25 = IOMUX_PIN(0xff, 266), + MX31_PIN_A24 = IOMUX_PIN(0xff, 267), + MX31_PIN_A23 = IOMUX_PIN(0xff, 268), + MX31_PIN_A22 = IOMUX_PIN(0xff, 269), + MX31_PIN_A21 = IOMUX_PIN(0xff, 270), + MX31_PIN_A20 = IOMUX_PIN(0xff, 271), + MX31_PIN_A19 = IOMUX_PIN(0xff, 272), + MX31_PIN_A18 = IOMUX_PIN(0xff, 273), + MX31_PIN_A17 = IOMUX_PIN(0xff, 274), + MX31_PIN_A16 = IOMUX_PIN(0xff, 275), + MX31_PIN_A14 = IOMUX_PIN(0xff, 276), + MX31_PIN_A15 = IOMUX_PIN(0xff, 277), + MX31_PIN_A13 = IOMUX_PIN(0xff, 278), + MX31_PIN_A12 = IOMUX_PIN(0xff, 279), + MX31_PIN_A11 = IOMUX_PIN(0xff, 280), + MX31_PIN_MA10 = IOMUX_PIN(0xff, 281), + MX31_PIN_A10 = IOMUX_PIN(0xff, 282), + MX31_PIN_A9 = IOMUX_PIN(0xff, 283), + MX31_PIN_A8 = IOMUX_PIN(0xff, 284), + MX31_PIN_A7 = IOMUX_PIN(0xff, 285), + MX31_PIN_A6 = IOMUX_PIN(0xff, 286), + MX31_PIN_A5 = IOMUX_PIN(0xff, 287), + MX31_PIN_A4 = IOMUX_PIN(0xff, 288), + MX31_PIN_A3 = IOMUX_PIN(0xff, 289), + MX31_PIN_A2 = IOMUX_PIN(0xff, 290), + MX31_PIN_A1 = IOMUX_PIN(0xff, 291), + MX31_PIN_A0 = IOMUX_PIN(0xff, 292), + MX31_PIN_VPG1 = IOMUX_PIN(0xff, 293), + MX31_PIN_VPG0 = IOMUX_PIN(0xff, 294), + MX31_PIN_DVFS1 = IOMUX_PIN(0xff, 295), + MX31_PIN_DVFS0 = IOMUX_PIN(0xff, 296), + MX31_PIN_VSTBY = IOMUX_PIN(0xff, 297), + MX31_PIN_POWER_FAIL = IOMUX_PIN(0xff, 298), + MX31_PIN_CKIL = IOMUX_PIN(0xff, 299), + MX31_PIN_BOOT_MODE4 = IOMUX_PIN(0xff, 300), + MX31_PIN_BOOT_MODE3 = IOMUX_PIN(0xff, 301), + MX31_PIN_BOOT_MODE2 = IOMUX_PIN(0xff, 302), + MX31_PIN_BOOT_MODE1 = IOMUX_PIN(0xff, 303), + MX31_PIN_BOOT_MODE0 = IOMUX_PIN(0xff, 304), + MX31_PIN_CLKO = IOMUX_PIN(0xff, 305), + MX31_PIN_POR_B = IOMUX_PIN(0xff, 306), + MX31_PIN_RESET_IN_B = IOMUX_PIN(0xff, 307), + MX31_PIN_CKIH = IOMUX_PIN(0xff, 308), + MX31_PIN_SIMPD0 = IOMUX_PIN(35, 309), + MX31_PIN_SRX0 = IOMUX_PIN(34, 310), + MX31_PIN_STX0 = IOMUX_PIN(33, 311), + MX31_PIN_SVEN0 = IOMUX_PIN(32, 312), + MX31_PIN_SRST0 = IOMUX_PIN(67, 313), + MX31_PIN_SCLK0 = IOMUX_PIN(66, 314), + MX31_PIN_GPIO3_1 = IOMUX_PIN(65, 315), + MX31_PIN_GPIO3_0 = IOMUX_PIN(64, 316), + MX31_PIN_GPIO1_6 = IOMUX_PIN( 6, 317), + MX31_PIN_GPIO1_5 = IOMUX_PIN( 5, 318), + MX31_PIN_GPIO1_4 = IOMUX_PIN( 4, 319), + MX31_PIN_GPIO1_3 = IOMUX_PIN( 3, 320), + MX31_PIN_GPIO1_2 = IOMUX_PIN( 2, 321), + MX31_PIN_GPIO1_1 = IOMUX_PIN( 1, 322), + MX31_PIN_GPIO1_0 = IOMUX_PIN( 0, 323), + MX31_PIN_PWMO = IOMUX_PIN( 9, 324), + MX31_PIN_WATCHDOG_RST = IOMUX_PIN(0xff, 325), + MX31_PIN_COMPARE = IOMUX_PIN( 8, 326), + MX31_PIN_CAPTURE = IOMUX_PIN( 7, 327), +}; + +#define PIN_MAX 327 +#define NB_PORTS 12 /* NB_PINS/32, we chose 32 pins per "PORT" */ + +/* + * Convenience values for use with mxc_iomux_mode() + * + * Format here is MX31_PIN_(pin name)__(function) + */ +#define MX31_PIN_CSPI3_MOSI__RXD3 IOMUX_MODE(MX31_PIN_CSPI3_MOSI, IOMUX_CONFIG_ALT1) +#define MX31_PIN_CSPI3_MISO__TXD3 IOMUX_MODE(MX31_PIN_CSPI3_MISO, IOMUX_CONFIG_ALT1) +#define MX31_PIN_CSPI3_SCLK__RTS3 IOMUX_MODE(MX31_PIN_CSPI3_SCLK, IOMUX_CONFIG_ALT1) +#define MX31_PIN_CSPI3_SPI_RDY__CTS3 IOMUX_MODE(MX31_PIN_CSPI3_SPI_RDY, IOMUX_CONFIG_ALT1) +#define MX31_PIN_CTS1__CTS1 IOMUX_MODE(MX31_PIN_CTS1, IOMUX_CONFIG_FUNC) +#define MX31_PIN_RTS1__RTS1 IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_FUNC) +#define MX31_PIN_TXD1__TXD1 IOMUX_MODE(MX31_PIN_TXD1, IOMUX_CONFIG_FUNC) +#define MX31_PIN_RXD1__RXD1 IOMUX_MODE(MX31_PIN_RXD1, IOMUX_CONFIG_FUNC) +#define MX31_PIN_DCD_DCE1__DCD_DCE1 IOMUX_MODE(MX31_PIN_DCD_DCE1, IOMUX_CONFIG_FUNC) +#define MX31_PIN_RI_DCE1__RI_DCE1 IOMUX_MODE(MX31_PIN_RI_DCE1, IOMUX_CONFIG_FUNC) +#define MX31_PIN_DSR_DCE1__DSR_DCE1 IOMUX_MODE(MX31_PIN_DSR_DCE1, IOMUX_CONFIG_FUNC) +#define MX31_PIN_DTR_DCE1__DTR_DCE1 IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CTS2__CTS2 IOMUX_MODE(MX31_PIN_CTS2, IOMUX_CONFIG_FUNC) +#define MX31_PIN_RTS2__RTS2 IOMUX_MODE(MX31_PIN_RTS2, IOMUX_CONFIG_FUNC) +#define MX31_PIN_TXD2__TXD2 IOMUX_MODE(MX31_PIN_TXD2, IOMUX_CONFIG_FUNC) +#define MX31_PIN_RXD2__RXD2 IOMUX_MODE(MX31_PIN_RXD2, IOMUX_CONFIG_FUNC) +#define MX31_PIN_DCD_DTE1__DCD_DTE2 IOMUX_MODE(MX31_PIN_DCD_DTE1, IOMUX_CONFIG_ALT1) +#define MX31_PIN_RI_DTE1__RI_DTE2 IOMUX_MODE(MX31_PIN_RI_DTE1, IOMUX_CONFIG_ALT1) +#define MX31_PIN_DSR_DTE1__DSR_DTE2 IOMUX_MODE(MX31_PIN_DSR_DTE1, IOMUX_CONFIG_ALT1) +#define MX31_PIN_DTR_DTE1__DTR_DTE2 IOMUX_MODE(MX31_PIN_DTR_DTE1, IOMUX_OCONFIG_ALT3 | IOMUX_ICONFIG_NONE) +#define MX31_PIN_PC_RST__CTS5 IOMUX_MODE(MX31_PIN_PC_RST, IOMUX_CONFIG_ALT2) +#define MX31_PIN_PC_VS2__RTS5 IOMUX_MODE(MX31_PIN_PC_VS2, IOMUX_CONFIG_ALT2) +#define MX31_PIN_PC_BVD2__TXD5 IOMUX_MODE(MX31_PIN_PC_BVD2, IOMUX_CONFIG_ALT2) +#define MX31_PIN_PC_BVD1__RXD5 IOMUX_MODE(MX31_PIN_PC_BVD1, IOMUX_CONFIG_ALT2) +#define MX31_PIN_CSPI1_MOSI__MOSI IOMUX_MODE(MX31_PIN_CSPI1_MOSI, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSPI1_MISO__MISO IOMUX_MODE(MX31_PIN_CSPI1_MISO, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSPI1_SCLK__SCLK IOMUX_MODE(MX31_PIN_CSPI1_SCLK, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSPI1_SPI_RDY__SPI_RDY IOMUX_MODE(MX31_PIN_CSPI1_SPI_RDY, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSPI1_SS0__SS0 IOMUX_MODE(MX31_PIN_CSPI1_SS0, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSPI1_SS1__SS1 IOMUX_MODE(MX31_PIN_CSPI1_SS1, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSPI1_SS2__SS2 IOMUX_MODE(MX31_PIN_CSPI1_SS2, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSPI2_MOSI__MOSI IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSPI2_MOSI__SCL IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_ALT1) +#define MX31_PIN_CSPI2_MISO__MISO IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSPI2_MISO__SDA IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_ALT1) +#define MX31_PIN_CSPI2_SCLK__SCLK IOMUX_MODE(MX31_PIN_CSPI2_SCLK, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSPI2_SPI_RDY__SPI_RDY IOMUX_MODE(MX31_PIN_CSPI2_SPI_RDY, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSPI2_SS0__SS0 IOMUX_MODE(MX31_PIN_CSPI2_SS0, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSPI2_SS1__SS1 IOMUX_MODE(MX31_PIN_CSPI2_SS1, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSPI2_SS2__SS2 IOMUX_MODE(MX31_PIN_CSPI2_SS2, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSPI3_MOSI__MOSI IOMUX_MODE(MX31_PIN_CSPI3_MOSI, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSPI3_MISO__MISO IOMUX_MODE(MX31_PIN_CSPI3_MISO, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSPI3_SCLK__SCLK IOMUX_MODE(MX31_PIN_CSPI3_SCLK, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSPI3_SPI_RDY__SPI_RDY IOMUX_MODE(MX31_PIN_CSPI3_SPI_RDY, IOMUX_CONFIG_FUNC) +#define MX31_PIN_BATT_LINE__OWIRE IOMUX_MODE(MX31_PIN_BATT_LINE, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CS4__CS4 IOMUX_MODE(MX31_PIN_CS4, IOMUX_CONFIG_FUNC) +#define MX31_PIN_SD1_DATA3__SD1_DATA3 IOMUX_MODE(MX31_PIN_SD1_DATA3, IOMUX_CONFIG_FUNC) +#define MX31_PIN_SD1_DATA2__SD1_DATA2 IOMUX_MODE(MX31_PIN_SD1_DATA2, IOMUX_CONFIG_FUNC) +#define MX31_PIN_SD1_DATA1__SD1_DATA1 IOMUX_MODE(MX31_PIN_SD1_DATA1, IOMUX_CONFIG_FUNC) +#define MX31_PIN_SD1_DATA0__SD1_DATA0 IOMUX_MODE(MX31_PIN_SD1_DATA0, IOMUX_CONFIG_FUNC) +#define MX31_PIN_SD1_CLK__SD1_CLK IOMUX_MODE(MX31_PIN_SD1_CLK, IOMUX_CONFIG_FUNC) +#define MX31_PIN_SD1_CMD__SD1_CMD IOMUX_MODE(MX31_PIN_SD1_CMD, IOMUX_CONFIG_FUNC) +#define MX31_PIN_ATA_CS0__GPIO3_26 IOMUX_MODE(MX31_PIN_ATA_CS0, IOMUX_CONFIG_GPIO) +#define MX31_PIN_ATA_CS1__GPIO3_27 IOMUX_MODE(MX31_PIN_ATA_CS1, IOMUX_CONFIG_GPIO) +#define MX31_PIN_PC_PWRON__SD2_DATA3 IOMUX_MODE(MX31_PIN_PC_PWRON, IOMUX_CONFIG_ALT1) +#define MX31_PIN_PC_VS1__SD2_DATA2 IOMUX_MODE(MX31_PIN_PC_VS1, IOMUX_CONFIG_ALT1) +#define MX31_PIN_PC_READY__SD2_DATA1 IOMUX_MODE(MX31_PIN_PC_READY, IOMUX_CONFIG_ALT1) +#define MX31_PIN_PC_WAIT_B__SD2_DATA0 IOMUX_MODE(MX31_PIN_PC_WAIT_B, IOMUX_CONFIG_ALT1) +#define MX31_PIN_PC_CD2_B__SD2_CLK IOMUX_MODE(MX31_PIN_PC_CD2_B, IOMUX_CONFIG_ALT1) +#define MX31_PIN_PC_CD1_B__SD2_CMD IOMUX_MODE(MX31_PIN_PC_CD1_B, IOMUX_CONFIG_ALT1) +#define MX31_PIN_ATA_DIOR__GPIO3_28 IOMUX_MODE(MX31_PIN_ATA_DIOR, IOMUX_CONFIG_GPIO) +#define MX31_PIN_ATA_DIOW__GPIO3_29 IOMUX_MODE(MX31_PIN_ATA_DIOW, IOMUX_CONFIG_GPIO) +#define MX31_PIN_LD0__LD0 IOMUX_MODE(MX31_PIN_LD0, IOMUX_CONFIG_FUNC) +#define MX31_PIN_LD1__LD1 IOMUX_MODE(MX31_PIN_LD1, IOMUX_CONFIG_FUNC) +#define MX31_PIN_LD2__LD2 IOMUX_MODE(MX31_PIN_LD2, IOMUX_CONFIG_FUNC) +#define MX31_PIN_LD3__LD3 IOMUX_MODE(MX31_PIN_LD3, IOMUX_CONFIG_FUNC) +#define MX31_PIN_LD4__LD4 IOMUX_MODE(MX31_PIN_LD4, IOMUX_CONFIG_FUNC) +#define MX31_PIN_LD5__LD5 IOMUX_MODE(MX31_PIN_LD5, IOMUX_CONFIG_FUNC) +#define MX31_PIN_LD6__LD6 IOMUX_MODE(MX31_PIN_LD6, IOMUX_CONFIG_FUNC) +#define MX31_PIN_LD7__LD7 IOMUX_MODE(MX31_PIN_LD7, IOMUX_CONFIG_FUNC) +#define MX31_PIN_LD8__LD8 IOMUX_MODE(MX31_PIN_LD8, IOMUX_CONFIG_FUNC) +#define MX31_PIN_LD9__LD9 IOMUX_MODE(MX31_PIN_LD9, IOMUX_CONFIG_FUNC) +#define MX31_PIN_LD10__LD10 IOMUX_MODE(MX31_PIN_LD10, IOMUX_CONFIG_FUNC) +#define MX31_PIN_LD11__LD11 IOMUX_MODE(MX31_PIN_LD11, IOMUX_CONFIG_FUNC) +#define MX31_PIN_LD12__LD12 IOMUX_MODE(MX31_PIN_LD12, IOMUX_CONFIG_FUNC) +#define MX31_PIN_LD13__LD13 IOMUX_MODE(MX31_PIN_LD13, IOMUX_CONFIG_FUNC) +#define MX31_PIN_LD14__LD14 IOMUX_MODE(MX31_PIN_LD14, IOMUX_CONFIG_FUNC) +#define MX31_PIN_LD15__LD15 IOMUX_MODE(MX31_PIN_LD15, IOMUX_CONFIG_FUNC) +#define MX31_PIN_LD16__LD16 IOMUX_MODE(MX31_PIN_LD16, IOMUX_CONFIG_FUNC) +#define MX31_PIN_LD17__LD17 IOMUX_MODE(MX31_PIN_LD17, IOMUX_CONFIG_FUNC) +#define MX31_PIN_VSYNC3__VSYNC3 IOMUX_MODE(MX31_PIN_VSYNC3, IOMUX_CONFIG_FUNC) +#define MX31_PIN_HSYNC__HSYNC IOMUX_MODE(MX31_PIN_HSYNC, IOMUX_CONFIG_FUNC) +#define MX31_PIN_FPSHIFT__FPSHIFT IOMUX_MODE(MX31_PIN_FPSHIFT, IOMUX_CONFIG_FUNC) +#define MX31_PIN_DRDY0__DRDY0 IOMUX_MODE(MX31_PIN_DRDY0, IOMUX_CONFIG_FUNC) +#define MX31_PIN_D3_REV__D3_REV IOMUX_MODE(MX31_PIN_D3_REV, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CONTRAST__CONTRAST IOMUX_MODE(MX31_PIN_CONTRAST, IOMUX_CONFIG_FUNC) +#define MX31_PIN_D3_SPL__D3_SPL IOMUX_MODE(MX31_PIN_D3_SPL, IOMUX_CONFIG_FUNC) +#define MX31_PIN_D3_CLS__D3_CLS IOMUX_MODE(MX31_PIN_D3_CLS, IOMUX_CONFIG_FUNC) +#define MX31_PIN_LCS0__GPI03_23 IOMUX_MODE(MX31_PIN_LCS0, IOMUX_CONFIG_GPIO) +#define MX31_PIN_GPIO1_1__GPIO IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO) +#define MX31_PIN_I2C_CLK__SCL IOMUX_MODE(MX31_PIN_I2C_CLK, IOMUX_CONFIG_FUNC) +#define MX31_PIN_I2C_DAT__SDA IOMUX_MODE(MX31_PIN_I2C_DAT, IOMUX_CONFIG_FUNC) +#define MX31_PIN_DCD_DTE1__I2C2_SDA IOMUX_MODE(MX31_PIN_DCD_DTE1, IOMUX_CONFIG_ALT2) +#define MX31_PIN_RI_DTE1__I2C2_SCL IOMUX_MODE(MX31_PIN_RI_DTE1, IOMUX_CONFIG_ALT2) +#define MX31_PIN_CSPI2_SS2__I2C3_SDA IOMUX_MODE(MX31_PIN_CSPI2_SS2, IOMUX_CONFIG_ALT1) +#define MX31_PIN_CSPI2_SCLK__I2C3_SCL IOMUX_MODE(MX31_PIN_CSPI2_SCLK, IOMUX_CONFIG_ALT1) +#define MX31_PIN_CSI_D4__CSI_D4 IOMUX_MODE(MX31_PIN_CSI_D4, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_D5__CSI_D5 IOMUX_MODE(MX31_PIN_CSI_D5, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_D6__CSI_D6 IOMUX_MODE(MX31_PIN_CSI_D6, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_D7__CSI_D7 IOMUX_MODE(MX31_PIN_CSI_D7, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_D8__CSI_D8 IOMUX_MODE(MX31_PIN_CSI_D8, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_D9__CSI_D9 IOMUX_MODE(MX31_PIN_CSI_D9, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_D10__CSI_D10 IOMUX_MODE(MX31_PIN_CSI_D10, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_D11__CSI_D11 IOMUX_MODE(MX31_PIN_CSI_D11, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_D12__CSI_D12 IOMUX_MODE(MX31_PIN_CSI_D12, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_D13__CSI_D13 IOMUX_MODE(MX31_PIN_CSI_D13, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_D14__CSI_D14 IOMUX_MODE(MX31_PIN_CSI_D14, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_D15__CSI_D15 IOMUX_MODE(MX31_PIN_CSI_D15, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_HSYNC__CSI_HSYNC IOMUX_MODE(MX31_PIN_CSI_HSYNC, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_MCLK__CSI_MCLK IOMUX_MODE(MX31_PIN_CSI_MCLK, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_PIXCLK__CSI_PIXCLK IOMUX_MODE(MX31_PIN_CSI_PIXCLK, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_VSYNC__CSI_VSYNC IOMUX_MODE(MX31_PIN_CSI_VSYNC, IOMUX_CONFIG_FUNC) +#define MX31_PIN_GPIO3_0__GPIO3_0 IOMUX_MODE(MX31_PIN_GPIO3_0, IOMUX_CONFIG_GPIO) +#define MX31_PIN_GPIO3_1__GPIO3_1 IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO) +#define MX31_PIN_TXD2__GPIO1_28 IOMUX_MODE(MX31_PIN_TXD2, IOMUX_CONFIG_GPIO) +#define MX31_PIN_CSI_D4__GPIO3_4 IOMUX_MODE(MX31_PIN_CSI_D4, IOMUX_CONFIG_GPIO) +#define MX31_PIN_CSI_D5__GPIO3_5 IOMUX_MODE(MX31_PIN_CSI_D5, IOMUX_CONFIG_GPIO) +#define MX31_PIN_USBOTG_DATA0__USBOTG_DATA0 IOMUX_MODE(MX31_PIN_USBOTG_DATA0, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBOTG_DATA1__USBOTG_DATA1 IOMUX_MODE(MX31_PIN_USBOTG_DATA1, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBOTG_DATA2__USBOTG_DATA2 IOMUX_MODE(MX31_PIN_USBOTG_DATA2, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBOTG_DATA3__USBOTG_DATA3 IOMUX_MODE(MX31_PIN_USBOTG_DATA3, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBOTG_DATA4__USBOTG_DATA4 IOMUX_MODE(MX31_PIN_USBOTG_DATA4, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBOTG_DATA5__USBOTG_DATA5 IOMUX_MODE(MX31_PIN_USBOTG_DATA5, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBOTG_DATA6__USBOTG_DATA6 IOMUX_MODE(MX31_PIN_USBOTG_DATA6, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBOTG_DATA7__USBOTG_DATA7 IOMUX_MODE(MX31_PIN_USBOTG_DATA7, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBOTG_CLK__USBOTG_CLK IOMUX_MODE(MX31_PIN_USBOTG_CLK, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBOTG_DIR__USBOTG_DIR IOMUX_MODE(MX31_PIN_USBOTG_DIR, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBOTG_NXT__USBOTG_NXT IOMUX_MODE(MX31_PIN_USBOTG_NXT, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBOTG_STP__USBOTG_STP IOMUX_MODE(MX31_PIN_USBOTG_STP, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSPI1_MOSI__USBH1_RXDM IOMUX_MODE(MX31_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT1) +#define MX31_PIN_CSPI1_MISO__USBH1_RXDP IOMUX_MODE(MX31_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT1) +#define MX31_PIN_CSPI1_SS0__USBH1_TXDM IOMUX_MODE(MX31_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT1) +#define MX31_PIN_CSPI1_SS1__USBH1_TXDP IOMUX_MODE(MX31_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT1) +#define MX31_PIN_CSPI1_SS2__USBH1_RCV IOMUX_MODE(MX31_PIN_CSPI1_SS2, IOMUX_CONFIG_ALT1) +#define MX31_PIN_CSPI1_SCLK__USBH1_OEB IOMUX_MODE(MX31_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT1) +#define MX31_PIN_CSPI1_SPI_RDY__USBH1_FS IOMUX_MODE(MX31_PIN_CSPI1_SPI_RDY, IOMUX_CONFIG_ALT1) +#define MX31_PIN_SFS6__USBH1_SUSPEND IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_FUNC) +#define MX31_PIN_NFRE_B__GPIO1_11 IOMUX_MODE(MX31_PIN_NFRE_B, IOMUX_CONFIG_GPIO) +#define MX31_PIN_NFALE__GPIO1_12 IOMUX_MODE(MX31_PIN_NFALE, IOMUX_CONFIG_GPIO) +#define MX31_PIN_USBH2_DATA0__USBH2_DATA0 IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBH2_DATA1__USBH2_DATA1 IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC) +#define MX31_PIN_STXD3__USBH2_DATA2 IOMUX_MODE(MX31_PIN_STXD3, IOMUX_CONFIG_FUNC) +#define MX31_PIN_SRXD3__USBH2_DATA3 IOMUX_MODE(MX31_PIN_SRXD3, IOMUX_CONFIG_FUNC) +#define MX31_PIN_SCK3__USBH2_DATA4 IOMUX_MODE(MX31_PIN_SCK3, IOMUX_CONFIG_FUNC) +#define MX31_PIN_SFS3__USBH2_DATA5 IOMUX_MODE(MX31_PIN_SFS3, IOMUX_CONFIG_FUNC) +#define MX31_PIN_STXD6__USBH2_DATA6 IOMUX_MODE(MX31_PIN_STXD6, IOMUX_CONFIG_FUNC) +#define MX31_PIN_SRXD6__USBH2_DATA7 IOMUX_MODE(MX31_PIN_SRXD6, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBH2_CLK__USBH2_CLK IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBH2_DIR__USBH2_DIR IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBH2_NXT__USBH2_NXT IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBH2_STP__USBH2_STP IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC) +#define MX31_PIN_SCK6__GPIO1_25 IOMUX_MODE(MX31_PIN_SCK6, IOMUX_CONFIG_GPIO) +#define MX31_PIN_USB_OC__GPIO1_30 IOMUX_MODE(MX31_PIN_USB_OC, IOMUX_CONFIG_GPIO) +#define MX31_PIN_I2C_DAT__I2C1_SDA IOMUX_MODE(MX31_PIN_I2C_DAT, IOMUX_CONFIG_FUNC) +#define MX31_PIN_I2C_CLK__I2C1_SCL IOMUX_MODE(MX31_PIN_I2C_CLK, IOMUX_CONFIG_FUNC) +#define MX31_PIN_DCD_DTE1__I2C2_SDA IOMUX_MODE(MX31_PIN_DCD_DTE1, IOMUX_CONFIG_ALT2) +#define MX31_PIN_RI_DTE1__I2C2_SCL IOMUX_MODE(MX31_PIN_RI_DTE1, IOMUX_CONFIG_ALT2) +#define MX31_PIN_ATA_CS0__GPIO3_26 IOMUX_MODE(MX31_PIN_ATA_CS0, IOMUX_CONFIG_GPIO) +#define MX31_PIN_ATA_CS1__GPIO3_27 IOMUX_MODE(MX31_PIN_ATA_CS1, IOMUX_CONFIG_GPIO) +#define MX31_PIN_PC_PWRON__SD2_DATA3 IOMUX_MODE(MX31_PIN_PC_PWRON, IOMUX_CONFIG_ALT1) +#define MX31_PIN_PC_VS1__SD2_DATA2 IOMUX_MODE(MX31_PIN_PC_VS1, IOMUX_CONFIG_ALT1) +#define MX31_PIN_PC_READY__SD2_DATA1 IOMUX_MODE(MX31_PIN_PC_READY, IOMUX_CONFIG_ALT1) +#define MX31_PIN_PC_WAIT_B__SD2_DATA0 IOMUX_MODE(MX31_PIN_PC_WAIT_B, IOMUX_CONFIG_ALT1) +#define MX31_PIN_PC_CD2_B__SD2_CLK IOMUX_MODE(MX31_PIN_PC_CD2_B, IOMUX_CONFIG_ALT1) +#define MX31_PIN_PC_CD1_B__SD2_CMD IOMUX_MODE(MX31_PIN_PC_CD1_B, IOMUX_CONFIG_ALT1) +#define MX31_PIN_ATA_DIOR__GPIO3_28 IOMUX_MODE(MX31_PIN_ATA_DIOR, IOMUX_CONFIG_GPIO) +#define MX31_PIN_ATA_DIOW__GPIO3_29 IOMUX_MODE(MX31_PIN_ATA_DIOW, IOMUX_CONFIG_GPIO) +#define MX31_PIN_CSI_D4__CSI_D4 IOMUX_MODE(MX31_PIN_CSI_D4, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_D5__CSI_D5 IOMUX_MODE(MX31_PIN_CSI_D5, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_D6__CSI_D6 IOMUX_MODE(MX31_PIN_CSI_D6, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_D7__CSI_D7 IOMUX_MODE(MX31_PIN_CSI_D7, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_D8__CSI_D8 IOMUX_MODE(MX31_PIN_CSI_D8, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_D9__CSI_D9 IOMUX_MODE(MX31_PIN_CSI_D9, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_D10__CSI_D10 IOMUX_MODE(MX31_PIN_CSI_D10, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_D11__CSI_D11 IOMUX_MODE(MX31_PIN_CSI_D11, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_D12__CSI_D12 IOMUX_MODE(MX31_PIN_CSI_D12, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_D13__CSI_D13 IOMUX_MODE(MX31_PIN_CSI_D13, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_D14__CSI_D14 IOMUX_MODE(MX31_PIN_CSI_D14, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_D15__CSI_D15 IOMUX_MODE(MX31_PIN_CSI_D15, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_HSYNC__CSI_HSYNC IOMUX_MODE(MX31_PIN_CSI_HSYNC, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_MCLK__CSI_MCLK IOMUX_MODE(MX31_PIN_CSI_MCLK, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_PIXCLK__CSI_PIXCLK IOMUX_MODE(MX31_PIN_CSI_PIXCLK, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_VSYNC__CSI_VSYNC IOMUX_MODE(MX31_PIN_CSI_VSYNC, IOMUX_CONFIG_FUNC) +#define MX31_PIN_GPIO3_0__GPIO3_0 IOMUX_MODE(MX31_PIN_GPIO3_0, IOMUX_CONFIG_GPIO) +#define MX31_PIN_GPIO3_1__GPIO3_1 IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO) +#define MX31_PIN_TXD2__GPIO1_28 IOMUX_MODE(MX31_PIN_TXD2, IOMUX_CONFIG_GPIO) +#define MX31_PIN_GPIO1_0__GPIO1_0 IOMUX_MODE(MX31_PIN_GPIO1_0, IOMUX_CONFIG_GPIO) +#define MX31_PIN_SVEN0__GPIO2_0 IOMUX_MODE(MX31_PIN_SVEN0, IOMUX_CONFIG_GPIO) +#define MX31_PIN_STX0__GPIO2_1 IOMUX_MODE(MX31_PIN_STX0, IOMUX_CONFIG_GPIO) +#define MX31_PIN_SRX0__GPIO2_2 IOMUX_MODE(MX31_PIN_SRX0, IOMUX_CONFIG_GPIO) +#define MX31_PIN_SIMPD0__GPIO2_3 IOMUX_MODE(MX31_PIN_SIMPD0, IOMUX_CONFIG_GPIO) +#define MX31_PIN_DTR_DCE1__GPIO2_8 IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_GPIO) +#define MX31_PIN_DSR_DCE1__GPIO2_9 IOMUX_MODE(MX31_PIN_DSR_DCE1, IOMUX_CONFIG_GPIO) +#define MX31_PIN_RI_DCE1__GPIO2_10 IOMUX_MODE(MX31_PIN_RI_DCE1, IOMUX_CONFIG_GPIO) +#define MX31_PIN_DCD_DCE1__GPIO2_11 IOMUX_MODE(MX31_PIN_DCD_DCE1, IOMUX_CONFIG_GPIO) +#define MX31_PIN_STXD5__GPIO1_21 IOMUX_MODE(MX31_PIN_STXD5, IOMUX_CONFIG_GPIO) +#define MX31_PIN_SRXD5__GPIO1_22 IOMUX_MODE(MX31_PIN_SRXD5, IOMUX_CONFIG_GPIO) +#define MX31_PIN_GPIO1_3__GPIO1_3 IOMUX_MODE(MX31_PIN_GPIO1_3, IOMUX_CONFIG_GPIO) +#define MX31_PIN_CSPI2_SS1__CSPI3_SS1 IOMUX_MODE(MX31_PIN_CSPI2_SS1, IOMUX_CONFIG_ALT1) +#define MX31_PIN_RTS1__GPIO2_6 IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_GPIO) +#define MX31_PIN_CTS1__GPIO2_7 IOMUX_MODE(MX31_PIN_CTS1, IOMUX_CONFIG_GPIO) +#define MX31_PIN_LCS0__GPIO3_23 IOMUX_MODE(MX31_PIN_LCS0, IOMUX_CONFIG_GPIO) +#define MX31_PIN_STXD4__STXD4 IOMUX_MODE(MX31_PIN_STXD4, IOMUX_CONFIG_FUNC) +#define MX31_PIN_SRXD4__SRXD4 IOMUX_MODE(MX31_PIN_SRXD4, IOMUX_CONFIG_FUNC) +#define MX31_PIN_SCK4__SCK4 IOMUX_MODE(MX31_PIN_SCK4, IOMUX_CONFIG_FUNC) +#define MX31_PIN_SFS4__SFS4 IOMUX_MODE(MX31_PIN_SFS4, IOMUX_CONFIG_FUNC) +#define MX31_PIN_STXD5__STXD5 IOMUX_MODE(MX31_PIN_STXD5, IOMUX_CONFIG_FUNC) +#define MX31_PIN_SRXD5__SRXD5 IOMUX_MODE(MX31_PIN_SRXD5, IOMUX_CONFIG_FUNC) +#define MX31_PIN_SCK5__SCK5 IOMUX_MODE(MX31_PIN_SCK5, IOMUX_CONFIG_FUNC) +#define MX31_PIN_SFS5__SFS5 IOMUX_MODE(MX31_PIN_SFS5, IOMUX_CONFIG_FUNC) +#define MX31_PIN_KEY_ROW0_KEY_ROW0 IOMUX_MODE(MX31_PIN_KEY_ROW0, IOMUX_CONFIG_FUNC) +#define MX31_PIN_KEY_ROW1_KEY_ROW1 IOMUX_MODE(MX31_PIN_KEY_ROW1, IOMUX_CONFIG_FUNC) +#define MX31_PIN_KEY_ROW2_KEY_ROW2 IOMUX_MODE(MX31_PIN_KEY_ROW2, IOMUX_CONFIG_FUNC) +#define MX31_PIN_KEY_ROW3_KEY_ROW3 IOMUX_MODE(MX31_PIN_KEY_ROW3, IOMUX_CONFIG_FUNC) +#define MX31_PIN_KEY_ROW4_KEY_ROW4 IOMUX_MODE(MX31_PIN_KEY_ROW4, IOMUX_CONFIG_FUNC) +#define MX31_PIN_KEY_ROW5_KEY_ROW5 IOMUX_MODE(MX31_PIN_KEY_ROW5, IOMUX_CONFIG_FUNC) +#define MX31_PIN_KEY_ROW6_KEY_ROW6 IOMUX_MODE(MX31_PIN_KEY_ROW6, IOMUX_CONFIG_FUNC) +#define MX31_PIN_KEY_ROW7_KEY_ROW7 IOMUX_MODE(MX31_PIN_KEY_ROW7, IOMUX_CONFIG_FUNC) +#define MX31_PIN_KEY_COL0_KEY_COL0 IOMUX_MODE(MX31_PIN_KEY_COL0, IOMUX_CONFIG_FUNC) +#define MX31_PIN_KEY_COL1_KEY_COL1 IOMUX_MODE(MX31_PIN_KEY_COL1, IOMUX_CONFIG_FUNC) +#define MX31_PIN_KEY_COL2_KEY_COL2 IOMUX_MODE(MX31_PIN_KEY_COL2, IOMUX_CONFIG_FUNC) +#define MX31_PIN_KEY_COL3_KEY_COL3 IOMUX_MODE(MX31_PIN_KEY_COL3, IOMUX_CONFIG_FUNC) +#define MX31_PIN_KEY_COL4_KEY_COL4 IOMUX_MODE(MX31_PIN_KEY_COL4, IOMUX_CONFIG_FUNC) +#define MX31_PIN_KEY_COL5_KEY_COL5 IOMUX_MODE(MX31_PIN_KEY_COL5, IOMUX_CONFIG_FUNC) +#define MX31_PIN_KEY_COL6_KEY_COL6 IOMUX_MODE(MX31_PIN_KEY_COL6, IOMUX_CONFIG_FUNC) +#define MX31_PIN_KEY_COL7_KEY_COL7 IOMUX_MODE(MX31_PIN_KEY_COL7, IOMUX_CONFIG_FUNC) + + +/* + * XXX: The SS0, SS1, SS2, SS3 lines of spi3 are multiplexed with cspi2_ss0, + * cspi2_ss1, cspi1_ss0 cspi1_ss1 + */ + +/* + * This function configures the pad value for a IOMUX pin. + */ +void mxc_iomux_set_pad(enum iomux_pins, u32); + +#endif /* ifndef __MACH_IOMUX_MX3_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx35.h b/arch/arm/plat-mxc/include/mach/iomux-mx35.h new file mode 100644 index 00000000..3117c18b --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/iomux-mx35.h @@ -0,0 +1,1267 @@ +/* + * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH <armlinux@phytec.de> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option, NO_PAD_CTRL) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#ifndef __MACH_IOMUX_MX35_H__ +#define __MACH_IOMUX_MX35_H__ + +#include <mach/iomux-v3.h> + +/* + * The naming convention for the pad modes is MX35_PAD_<padname>__<padmode> + * If <padname> or <padmode> refers to a GPIO, it is named + * GPIO_<unit>_<num> see also iomux-v3.h + */ + +/* PAD MUX ALT INPSE PATH */ +#define MX35_PAD_CAPTURE__GPT_CAPIN1 IOMUX_PAD(0x328, 0x004, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CAPTURE__GPT_CMPOUT2 IOMUX_PAD(0x328, 0x004, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CAPTURE__CSPI2_SS1 IOMUX_PAD(0x328, 0x004, 2, 0x7f4, 0, NO_PAD_CTRL) +#define MX35_PAD_CAPTURE__EPIT1_EPITO IOMUX_PAD(0x328, 0x004, 3, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CAPTURE__CCM_CLK32K IOMUX_PAD(0x328, 0x004, 4, 0x7d0, 0, NO_PAD_CTRL) +#define MX35_PAD_CAPTURE__GPIO1_4 IOMUX_PAD(0x328, 0x004, 5, 0x850, 0, NO_PAD_CTRL) + +#define MX35_PAD_COMPARE__GPT_CMPOUT1 IOMUX_PAD(0x32c, 0x008, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_COMPARE__GPT_CAPIN2 IOMUX_PAD(0x32c, 0x008, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_COMPARE__GPT_CMPOUT3 IOMUX_PAD(0x32c, 0x008, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_COMPARE__EPIT2_EPITO IOMUX_PAD(0x32c, 0x008, 3, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_COMPARE__GPIO1_5 IOMUX_PAD(0x32c, 0x008, 5, 0x854, 0, NO_PAD_CTRL) +#define MX35_PAD_COMPARE__SDMA_EXTDMA_2 IOMUX_PAD(0x32c, 0x008, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_WDOG_RST__WDOG_WDOG_B IOMUX_PAD(0x330, 0x00c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_WDOG_RST__IPU_FLASH_STROBE IOMUX_PAD(0x330, 0x00c, 3, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_WDOG_RST__GPIO1_6 IOMUX_PAD(0x330, 0x00c, 5, 0x858, 0, NO_PAD_CTRL) + +#define MX35_PAD_GPIO1_0__GPIO1_0 IOMUX_PAD(0x334, 0x010, 0, 0x82c, 0, NO_PAD_CTRL) +#define MX35_PAD_GPIO1_0__CCM_PMIC_RDY IOMUX_PAD(0x334, 0x010, 1, 0x7d4, 0, NO_PAD_CTRL) +#define MX35_PAD_GPIO1_0__OWIRE_LINE IOMUX_PAD(0x334, 0x010, 2, 0x990, 0, NO_PAD_CTRL) +#define MX35_PAD_GPIO1_0__SDMA_EXTDMA_0 IOMUX_PAD(0x334, 0x010, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_GPIO1_1__GPIO1_1 IOMUX_PAD(0x338, 0x014, 0, 0x838, 0, NO_PAD_CTRL) +#define MX35_PAD_GPIO1_1__PWM_PWMO IOMUX_PAD(0x338, 0x014, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_GPIO1_1__CSPI1_SS2 IOMUX_PAD(0x338, 0x014, 3, 0x7d8, 0, NO_PAD_CTRL) +#define MX35_PAD_GPIO1_1__SCC_TAMPER_DETECT IOMUX_PAD(0x338, 0x014, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_GPIO1_1__SDMA_EXTDMA_1 IOMUX_PAD(0x338, 0x014, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_GPIO2_0__GPIO2_0 IOMUX_PAD(0x33c, 0x018, 0, 0x868, 0, NO_PAD_CTRL) +#define MX35_PAD_GPIO2_0__USB_TOP_USBOTG_CLK IOMUX_PAD(0x33c, 0x018, 1, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_GPIO3_0__GPIO3_0 IOMUX_PAD(0x340, 0x01c, 0, 0x8e8, 0, NO_PAD_CTRL) +#define MX35_PAD_GPIO3_0__USB_TOP_USBH2_CLK IOMUX_PAD(0x340, 0x01c, 1, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_RESET_IN_B__CCM_RESET_IN_B IOMUX_PAD(0x344, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_POR_B__CCM_POR_B IOMUX_PAD(0x348, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CLKO__CCM_CLKO IOMUX_PAD(0x34c, 0x020, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CLKO__GPIO1_8 IOMUX_PAD(0x34c, 0x020, 5, 0x860, 0, NO_PAD_CTRL) + +#define MX35_PAD_BOOT_MODE0__CCM_BOOT_MODE_0 IOMUX_PAD(0x350, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_BOOT_MODE1__CCM_BOOT_MODE_1 IOMUX_PAD(0x354, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CLK_MODE0__CCM_CLK_MODE_0 IOMUX_PAD(0x358, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CLK_MODE1__CCM_CLK_MODE_1 IOMUX_PAD(0x35c, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_POWER_FAIL__CCM_DSM_WAKEUP_INT_26 IOMUX_PAD(0x360, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_VSTBY__CCM_VSTBY IOMUX_PAD(0x364, 0x024, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_VSTBY__GPIO1_7 IOMUX_PAD(0x364, 0x024, 5, 0x85c, 0, NO_PAD_CTRL) + +#define MX35_PAD_A0__EMI_EIM_DA_L_0 IOMUX_PAD(0x368, 0x028, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_A1__EMI_EIM_DA_L_1 IOMUX_PAD(0x36c, 0x02c, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_A2__EMI_EIM_DA_L_2 IOMUX_PAD(0x370, 0x030, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_A3__EMI_EIM_DA_L_3 IOMUX_PAD(0x374, 0x034, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_A4__EMI_EIM_DA_L_4 IOMUX_PAD(0x378, 0x038, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_A5__EMI_EIM_DA_L_5 IOMUX_PAD(0x37c, 0x03c, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_A6__EMI_EIM_DA_L_6 IOMUX_PAD(0x380, 0x040, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_A7__EMI_EIM_DA_L_7 IOMUX_PAD(0x384, 0x044, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_A8__EMI_EIM_DA_H_8 IOMUX_PAD(0x388, 0x048, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_A9__EMI_EIM_DA_H_9 IOMUX_PAD(0x38c, 0x04c, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_A10__EMI_EIM_DA_H_10 IOMUX_PAD(0x390, 0x050, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_MA10__EMI_MA10 IOMUX_PAD(0x394, 0x054, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_A11__EMI_EIM_DA_H_11 IOMUX_PAD(0x398, 0x058, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_A12__EMI_EIM_DA_H_12 IOMUX_PAD(0x39c, 0x05c, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_A13__EMI_EIM_DA_H_13 IOMUX_PAD(0x3a0, 0x060, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_A14__EMI_EIM_DA_H2_14 IOMUX_PAD(0x3a4, 0x064, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_A15__EMI_EIM_DA_H2_15 IOMUX_PAD(0x3a8, 0x068, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_A16__EMI_EIM_A_16 IOMUX_PAD(0x3ac, 0x06c, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_A17__EMI_EIM_A_17 IOMUX_PAD(0x3b0, 0x070, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_A18__EMI_EIM_A_18 IOMUX_PAD(0x3b4, 0x074, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_A19__EMI_EIM_A_19 IOMUX_PAD(0x3b8, 0x078, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_A20__EMI_EIM_A_20 IOMUX_PAD(0x3bc, 0x07c, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_A21__EMI_EIM_A_21 IOMUX_PAD(0x3c0, 0x080, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_A22__EMI_EIM_A_22 IOMUX_PAD(0x3c4, 0x084, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_A23__EMI_EIM_A_23 IOMUX_PAD(0x3c8, 0x088, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_A24__EMI_EIM_A_24 IOMUX_PAD(0x3cc, 0x08c, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_A25__EMI_EIM_A_25 IOMUX_PAD(0x3d0, 0x090, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SDBA1__EMI_EIM_SDBA1 IOMUX_PAD(0x3d4, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SDBA0__EMI_EIM_SDBA0 IOMUX_PAD(0x3d8, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD0__EMI_DRAM_D_0 IOMUX_PAD(0x3dc, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD1__EMI_DRAM_D_1 IOMUX_PAD(0x3e0, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD2__EMI_DRAM_D_2 IOMUX_PAD(0x3e4, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD3__EMI_DRAM_D_3 IOMUX_PAD(0x3e8, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD4__EMI_DRAM_D_4 IOMUX_PAD(0x3ec, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD5__EMI_DRAM_D_5 IOMUX_PAD(0x3f0, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD6__EMI_DRAM_D_6 IOMUX_PAD(0x3f4, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD7__EMI_DRAM_D_7 IOMUX_PAD(0x3f8, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD8__EMI_DRAM_D_8 IOMUX_PAD(0x3fc, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD9__EMI_DRAM_D_9 IOMUX_PAD(0x400, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD10__EMI_DRAM_D_10 IOMUX_PAD(0x404, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD11__EMI_DRAM_D_11 IOMUX_PAD(0x408, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD12__EMI_DRAM_D_12 IOMUX_PAD(0x40c, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD13__EMI_DRAM_D_13 IOMUX_PAD(0x410, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD14__EMI_DRAM_D_14 IOMUX_PAD(0x414, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD15__EMI_DRAM_D_15 IOMUX_PAD(0x418, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD16__EMI_DRAM_D_16 IOMUX_PAD(0x41c, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD17__EMI_DRAM_D_17 IOMUX_PAD(0x420, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD18__EMI_DRAM_D_18 IOMUX_PAD(0x424, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD19__EMI_DRAM_D_19 IOMUX_PAD(0x428, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD20__EMI_DRAM_D_20 IOMUX_PAD(0x42c, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD21__EMI_DRAM_D_21 IOMUX_PAD(0x430, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD22__EMI_DRAM_D_22 IOMUX_PAD(0x434, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD23__EMI_DRAM_D_23 IOMUX_PAD(0x438, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD24__EMI_DRAM_D_24 IOMUX_PAD(0x43c, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD25__EMI_DRAM_D_25 IOMUX_PAD(0x440, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD26__EMI_DRAM_D_26 IOMUX_PAD(0x444, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD27__EMI_DRAM_D_27 IOMUX_PAD(0x448, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD28__EMI_DRAM_D_28 IOMUX_PAD(0x44c, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD29__EMI_DRAM_D_29 IOMUX_PAD(0x450, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD30__EMI_DRAM_D_30 IOMUX_PAD(0x454, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD31__EMI_DRAM_D_31 IOMUX_PAD(0x458, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_DQM0__EMI_DRAM_DQM_0 IOMUX_PAD(0x45c, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_DQM1__EMI_DRAM_DQM_1 IOMUX_PAD(0x460, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_DQM2__EMI_DRAM_DQM_2 IOMUX_PAD(0x464, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_DQM3__EMI_DRAM_DQM_3 IOMUX_PAD(0x468, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_EB0__EMI_EIM_EB0_B IOMUX_PAD(0x46c, 0x094, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_EB1__EMI_EIM_EB1_B IOMUX_PAD(0x470, 0x098, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_OE__EMI_EIM_OE IOMUX_PAD(0x474, 0x09c, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CS0__EMI_EIM_CS0 IOMUX_PAD(0x478, 0x0a0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CS1__EMI_EIM_CS1 IOMUX_PAD(0x47c, 0x0a4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CS1__EMI_NANDF_CE3 IOMUX_PAD(0x47c, 0x0a4, 3, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CS2__EMI_EIM_CS2 IOMUX_PAD(0x480, 0x0a8, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CS3__EMI_EIM_CS3 IOMUX_PAD(0x484, 0x0ac, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CS4__EMI_EIM_CS4 IOMUX_PAD(0x488, 0x0b0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CS4__EMI_DTACK_B IOMUX_PAD(0x488, 0x0b0, 1, 0x800, 0, NO_PAD_CTRL) +#define MX35_PAD_CS4__EMI_NANDF_CE1 IOMUX_PAD(0x488, 0x0b0, 3, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CS4__GPIO1_20 IOMUX_PAD(0x488, 0x0b0, 5, 0x83c, 0, NO_PAD_CTRL) + +#define MX35_PAD_CS5__EMI_EIM_CS5 IOMUX_PAD(0x48c, 0x0b4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CS5__CSPI2_SS2 IOMUX_PAD(0x48c, 0x0b4, 1, 0x7f8, 0, NO_PAD_CTRL) +#define MX35_PAD_CS5__CSPI1_SS2 IOMUX_PAD(0x48c, 0x0b4, 2, 0x7d8, 1, NO_PAD_CTRL) +#define MX35_PAD_CS5__EMI_NANDF_CE2 IOMUX_PAD(0x48c, 0x0b4, 3, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CS5__GPIO1_21 IOMUX_PAD(0x48c, 0x0b4, 5, 0x840, 0, NO_PAD_CTRL) + +#define MX35_PAD_NF_CE0__EMI_NANDF_CE0 IOMUX_PAD(0x490, 0x0b8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_NF_CE0__GPIO1_22 IOMUX_PAD(0x490, 0x0b8, 5, 0x844, 0, NO_PAD_CTRL) + +#define MX35_PAD_ECB__EMI_EIM_ECB IOMUX_PAD(0x494, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_LBA__EMI_EIM_LBA IOMUX_PAD(0x498, 0x0bc, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_BCLK__EMI_EIM_BCLK IOMUX_PAD(0x49c, 0x0c0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_RW__EMI_EIM_RW IOMUX_PAD(0x4a0, 0x0c4, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_RAS__EMI_DRAM_RAS IOMUX_PAD(0x4a4, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CAS__EMI_DRAM_CAS IOMUX_PAD(0x4a8, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SDWE__EMI_DRAM_SDWE IOMUX_PAD(0x4ac, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SDCKE0__EMI_DRAM_SDCKE_0 IOMUX_PAD(0x4b0, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SDCKE1__EMI_DRAM_SDCKE_1 IOMUX_PAD(0x4b4, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SDCLK__EMI_DRAM_SDCLK IOMUX_PAD(0x4b8, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SDQS0__EMI_DRAM_SDQS_0 IOMUX_PAD(0x4bc, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SDQS1__EMI_DRAM_SDQS_1 IOMUX_PAD(0x4c0, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SDQS2__EMI_DRAM_SDQS_2 IOMUX_PAD(0x4c4, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SDQS3__EMI_DRAM_SDQS_3 IOMUX_PAD(0x4c8, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_NFWE_B__EMI_NANDF_WE_B IOMUX_PAD(0x4cc, 0x0c8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_NFWE_B__USB_TOP_USBH2_DATA_3 IOMUX_PAD(0x4cc, 0x0c8, 1, 0x9d8, 0, NO_PAD_CTRL) +#define MX35_PAD_NFWE_B__IPU_DISPB_D0_VSYNC IOMUX_PAD(0x4cc, 0x0c8, 2, 0x924, 0, NO_PAD_CTRL) +#define MX35_PAD_NFWE_B__GPIO2_18 IOMUX_PAD(0x4cc, 0x0c8, 5, 0x88c, 0, NO_PAD_CTRL) +#define MX35_PAD_NFWE_B__ARM11P_TOP_TRACE_0 IOMUX_PAD(0x4cc, 0x0c8, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_NFRE_B__EMI_NANDF_RE_B IOMUX_PAD(0x4d0, 0x0cc, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_NFRE_B__USB_TOP_USBH2_DIR IOMUX_PAD(0x4d0, 0x0cc, 1, 0x9ec, 0, NO_PAD_CTRL) +#define MX35_PAD_NFRE_B__IPU_DISPB_BCLK IOMUX_PAD(0x4d0, 0x0cc, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_NFRE_B__GPIO2_19 IOMUX_PAD(0x4d0, 0x0cc, 5, 0x890, 0, NO_PAD_CTRL) +#define MX35_PAD_NFRE_B__ARM11P_TOP_TRACE_1 IOMUX_PAD(0x4d0, 0x0cc, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_NFALE__EMI_NANDF_ALE IOMUX_PAD(0x4d4, 0x0d0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_NFALE__USB_TOP_USBH2_STP IOMUX_PAD(0x4d4, 0x0d0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_NFALE__IPU_DISPB_CS0 IOMUX_PAD(0x4d4, 0x0d0, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_NFALE__GPIO2_20 IOMUX_PAD(0x4d4, 0x0d0, 5, 0x898, 0, NO_PAD_CTRL) +#define MX35_PAD_NFALE__ARM11P_TOP_TRACE_2 IOMUX_PAD(0x4d4, 0x0d0, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_NFCLE__EMI_NANDF_CLE IOMUX_PAD(0x4d8, 0x0d4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_NFCLE__USB_TOP_USBH2_NXT IOMUX_PAD(0x4d8, 0x0d4, 1, 0x9f0, 0, NO_PAD_CTRL) +#define MX35_PAD_NFCLE__IPU_DISPB_PAR_RS IOMUX_PAD(0x4d8, 0x0d4, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_NFCLE__GPIO2_21 IOMUX_PAD(0x4d8, 0x0d4, 5, 0x89c, 0, NO_PAD_CTRL) +#define MX35_PAD_NFCLE__ARM11P_TOP_TRACE_3 IOMUX_PAD(0x4d8, 0x0d4, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_NFWP_B__EMI_NANDF_WP_B IOMUX_PAD(0x4dc, 0x0d8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_NFWP_B__USB_TOP_USBH2_DATA_7 IOMUX_PAD(0x4dc, 0x0d8, 1, 0x9e8, 0, NO_PAD_CTRL) +#define MX35_PAD_NFWP_B__IPU_DISPB_WR IOMUX_PAD(0x4dc, 0x0d8, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_NFWP_B__GPIO2_22 IOMUX_PAD(0x4dc, 0x0d8, 5, 0x8a0, 0, NO_PAD_CTRL) +#define MX35_PAD_NFWP_B__ARM11P_TOP_TRCTL IOMUX_PAD(0x4dc, 0x0d8, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_NFRB__EMI_NANDF_RB IOMUX_PAD(0x4e0, 0x0dc, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_NFRB__IPU_DISPB_RD IOMUX_PAD(0x4e0, 0x0dc, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_NFRB__GPIO2_23 IOMUX_PAD(0x4e0, 0x0dc, 5, 0x8a4, 0, NO_PAD_CTRL) +#define MX35_PAD_NFRB__ARM11P_TOP_TRCLK IOMUX_PAD(0x4e0, 0x0dc, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_D15__EMI_EIM_D_15 IOMUX_PAD(0x4e4, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_D14__EMI_EIM_D_14 IOMUX_PAD(0x4e8, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_D13__EMI_EIM_D_13 IOMUX_PAD(0x4ec, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_D12__EMI_EIM_D_12 IOMUX_PAD(0x4f0, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_D11__EMI_EIM_D_11 IOMUX_PAD(0x4f4, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_D10__EMI_EIM_D_10 IOMUX_PAD(0x4f8, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_D9__EMI_EIM_D_9 IOMUX_PAD(0x4fc, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_D8__EMI_EIM_D_8 IOMUX_PAD(0x500, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_D7__EMI_EIM_D_7 IOMUX_PAD(0x504, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_D6__EMI_EIM_D_6 IOMUX_PAD(0x508, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_D5__EMI_EIM_D_5 IOMUX_PAD(0x50c, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_D4__EMI_EIM_D_4 IOMUX_PAD(0x510, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_D3__EMI_EIM_D_3 IOMUX_PAD(0x514, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_D2__EMI_EIM_D_2 IOMUX_PAD(0x518, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_D1__EMI_EIM_D_1 IOMUX_PAD(0x51c, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_D0__EMI_EIM_D_0 IOMUX_PAD(0x520, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CSI_D8__IPU_CSI_D_8 IOMUX_PAD(0x524, 0x0e0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CSI_D8__KPP_COL_0 IOMUX_PAD(0x524, 0x0e0, 1, 0x950, 0, NO_PAD_CTRL) +#define MX35_PAD_CSI_D8__GPIO1_20 IOMUX_PAD(0x524, 0x0e0, 5, 0x83c, 1, NO_PAD_CTRL) +#define MX35_PAD_CSI_D8__ARM11P_TOP_EVNTBUS_13 IOMUX_PAD(0x524, 0x0e0, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CSI_D9__IPU_CSI_D_9 IOMUX_PAD(0x528, 0x0e4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CSI_D9__KPP_COL_1 IOMUX_PAD(0x528, 0x0e4, 1, 0x954, 0, NO_PAD_CTRL) +#define MX35_PAD_CSI_D9__GPIO1_21 IOMUX_PAD(0x528, 0x0e4, 5, 0x840, 1, NO_PAD_CTRL) +#define MX35_PAD_CSI_D9__ARM11P_TOP_EVNTBUS_14 IOMUX_PAD(0x528, 0x0e4, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CSI_D10__IPU_CSI_D_10 IOMUX_PAD(0x52c, 0x0e8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CSI_D10__KPP_COL_2 IOMUX_PAD(0x52c, 0x0e8, 1, 0x958, 0, NO_PAD_CTRL) +#define MX35_PAD_CSI_D10__GPIO1_22 IOMUX_PAD(0x52c, 0x0e8, 5, 0x844, 1, NO_PAD_CTRL) +#define MX35_PAD_CSI_D10__ARM11P_TOP_EVNTBUS_15 IOMUX_PAD(0x52c, 0x0e8, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CSI_D11__IPU_CSI_D_11 IOMUX_PAD(0x530, 0x0ec, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CSI_D11__KPP_COL_3 IOMUX_PAD(0x530, 0x0ec, 1, 0x95c, 0, NO_PAD_CTRL) +#define MX35_PAD_CSI_D11__GPIO1_23 IOMUX_PAD(0x530, 0x0ec, 5, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CSI_D12__IPU_CSI_D_12 IOMUX_PAD(0x534, 0x0f0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CSI_D12__KPP_ROW_0 IOMUX_PAD(0x534, 0x0f0, 1, 0x970, 0, NO_PAD_CTRL) +#define MX35_PAD_CSI_D12__GPIO1_24 IOMUX_PAD(0x534, 0x0f0, 5, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CSI_D13__IPU_CSI_D_13 IOMUX_PAD(0x538, 0x0f4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CSI_D13__KPP_ROW_1 IOMUX_PAD(0x538, 0x0f4, 1, 0x974, 0, NO_PAD_CTRL) +#define MX35_PAD_CSI_D13__GPIO1_25 IOMUX_PAD(0x538, 0x0f4, 5, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CSI_D14__IPU_CSI_D_14 IOMUX_PAD(0x53c, 0x0f8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CSI_D14__KPP_ROW_2 IOMUX_PAD(0x53c, 0x0f8, 1, 0x978, 0, NO_PAD_CTRL) +#define MX35_PAD_CSI_D14__GPIO1_26 IOMUX_PAD(0x53c, 0x0f8, 5, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CSI_D15__IPU_CSI_D_15 IOMUX_PAD(0x540, 0x0fc, 0, 0x97c, 0, NO_PAD_CTRL) +#define MX35_PAD_CSI_D15__KPP_ROW_3 IOMUX_PAD(0x540, 0x0fc, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CSI_D15__GPIO1_27 IOMUX_PAD(0x540, 0x0fc, 5, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CSI_MCLK__IPU_CSI_MCLK IOMUX_PAD(0x544, 0x100, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CSI_MCLK__GPIO1_28 IOMUX_PAD(0x544, 0x100, 5, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CSI_VSYNC__IPU_CSI_VSYNC IOMUX_PAD(0x548, 0x104, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CSI_VSYNC__GPIO1_29 IOMUX_PAD(0x548, 0x104, 5, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CSI_HSYNC__IPU_CSI_HSYNC IOMUX_PAD(0x54c, 0x108, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CSI_HSYNC__GPIO1_30 IOMUX_PAD(0x54c, 0x108, 5, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CSI_PIXCLK__IPU_CSI_PIXCLK IOMUX_PAD(0x550, 0x10c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CSI_PIXCLK__GPIO1_31 IOMUX_PAD(0x550, 0x10c, 5, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_I2C1_CLK__I2C1_SCL IOMUX_PAD(0x554, 0x110, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_I2C1_CLK__GPIO2_24 IOMUX_PAD(0x554, 0x110, 5, 0x8a8, 0, NO_PAD_CTRL) +#define MX35_PAD_I2C1_CLK__CCM_USB_BYP_CLK IOMUX_PAD(0x554, 0x110, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_I2C1_DAT__I2C1_SDA IOMUX_PAD(0x558, 0x114, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_I2C1_DAT__GPIO2_25 IOMUX_PAD(0x558, 0x114, 5, 0x8ac, 0, NO_PAD_CTRL) + +#define MX35_PAD_I2C2_CLK__I2C2_SCL IOMUX_PAD(0x55c, 0x118, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_I2C2_CLK__CAN1_TXCAN IOMUX_PAD(0x55c, 0x118, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR IOMUX_PAD(0x55c, 0x118, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_I2C2_CLK__GPIO2_26 IOMUX_PAD(0x55c, 0x118, 5, 0x8b0, 0, NO_PAD_CTRL) +#define MX35_PAD_I2C2_CLK__SDMA_DEBUG_BUS_DEVICE_2 IOMUX_PAD(0x55c, 0x118, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_I2C2_DAT__I2C2_SDA IOMUX_PAD(0x560, 0x11c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_I2C2_DAT__CAN1_RXCAN IOMUX_PAD(0x560, 0x11c, 1, 0x7c8, 0, NO_PAD_CTRL) +#define MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC IOMUX_PAD(0x560, 0x11c, 2, 0x9f4, 0, NO_PAD_CTRL) +#define MX35_PAD_I2C2_DAT__GPIO2_27 IOMUX_PAD(0x560, 0x11c, 5, 0x8b4, 0, NO_PAD_CTRL) +#define MX35_PAD_I2C2_DAT__SDMA_DEBUG_BUS_DEVICE_3 IOMUX_PAD(0x560, 0x11c, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_STXD4__AUDMUX_AUD4_TXD IOMUX_PAD(0x564, 0x120, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_STXD4__GPIO2_28 IOMUX_PAD(0x564, 0x120, 5, 0x8b8, 0, NO_PAD_CTRL) +#define MX35_PAD_STXD4__ARM11P_TOP_ARM_COREASID0 IOMUX_PAD(0x564, 0x120, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SRXD4__AUDMUX_AUD4_RXD IOMUX_PAD(0x568, 0x124, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SRXD4__GPIO2_29 IOMUX_PAD(0x568, 0x124, 5, 0x8bc, 0, NO_PAD_CTRL) +#define MX35_PAD_SRXD4__ARM11P_TOP_ARM_COREASID1 IOMUX_PAD(0x568, 0x124, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SCK4__AUDMUX_AUD4_TXC IOMUX_PAD(0x56c, 0x128, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SCK4__GPIO2_30 IOMUX_PAD(0x56c, 0x128, 5, 0x8c4, 0, NO_PAD_CTRL) +#define MX35_PAD_SCK4__ARM11P_TOP_ARM_COREASID2 IOMUX_PAD(0x56c, 0x128, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS IOMUX_PAD(0x570, 0x12c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_STXFS4__GPIO2_31 IOMUX_PAD(0x570, 0x12c, 5, 0x8c8, 0, NO_PAD_CTRL) +#define MX35_PAD_STXFS4__ARM11P_TOP_ARM_COREASID3 IOMUX_PAD(0x570, 0x12c, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_STXD5__AUDMUX_AUD5_TXD IOMUX_PAD(0x574, 0x130, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_STXD5__SPDIF_SPDIF_OUT1 IOMUX_PAD(0x574, 0x130, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_STXD5__CSPI2_MOSI IOMUX_PAD(0x574, 0x130, 2, 0x7ec, 0, NO_PAD_CTRL) +#define MX35_PAD_STXD5__GPIO1_0 IOMUX_PAD(0x574, 0x130, 5, 0x82c, 1, NO_PAD_CTRL) +#define MX35_PAD_STXD5__ARM11P_TOP_ARM_COREASID4 IOMUX_PAD(0x574, 0x130, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SRXD5__AUDMUX_AUD5_RXD IOMUX_PAD(0x578, 0x134, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SRXD5__SPDIF_SPDIF_IN1 IOMUX_PAD(0x578, 0x134, 1, 0x998, 0, NO_PAD_CTRL) +#define MX35_PAD_SRXD5__CSPI2_MISO IOMUX_PAD(0x578, 0x134, 2, 0x7e8, 0, NO_PAD_CTRL) +#define MX35_PAD_SRXD5__GPIO1_1 IOMUX_PAD(0x578, 0x134, 5, 0x838, 1, NO_PAD_CTRL) +#define MX35_PAD_SRXD5__ARM11P_TOP_ARM_COREASID5 IOMUX_PAD(0x578, 0x134, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SCK5__AUDMUX_AUD5_TXC IOMUX_PAD(0x57c, 0x138, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SCK5__SPDIF_SPDIF_EXTCLK IOMUX_PAD(0x57c, 0x138, 1, 0x994, 0, NO_PAD_CTRL) +#define MX35_PAD_SCK5__CSPI2_SCLK IOMUX_PAD(0x57c, 0x138, 2, 0x7e0, 0, NO_PAD_CTRL) +#define MX35_PAD_SCK5__GPIO1_2 IOMUX_PAD(0x57c, 0x138, 5, 0x848, 0, NO_PAD_CTRL) +#define MX35_PAD_SCK5__ARM11P_TOP_ARM_COREASID6 IOMUX_PAD(0x57c, 0x138, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_STXFS5__AUDMUX_AUD5_TXFS IOMUX_PAD(0x580, 0x13c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_STXFS5__CSPI2_RDY IOMUX_PAD(0x580, 0x13c, 2, 0x7e4, 0, NO_PAD_CTRL) +#define MX35_PAD_STXFS5__GPIO1_3 IOMUX_PAD(0x580, 0x13c, 5, 0x84c, 0, NO_PAD_CTRL) +#define MX35_PAD_STXFS5__ARM11P_TOP_ARM_COREASID7 IOMUX_PAD(0x580, 0x13c, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SCKR__ESAI_SCKR IOMUX_PAD(0x584, 0x140, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SCKR__GPIO1_4 IOMUX_PAD(0x584, 0x140, 5, 0x850, 1, NO_PAD_CTRL) +#define MX35_PAD_SCKR__ARM11P_TOP_EVNTBUS_10 IOMUX_PAD(0x584, 0x140, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_FSR__ESAI_FSR IOMUX_PAD(0x588, 0x144, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FSR__GPIO1_5 IOMUX_PAD(0x588, 0x144, 5, 0x854, 1, NO_PAD_CTRL) +#define MX35_PAD_FSR__ARM11P_TOP_EVNTBUS_11 IOMUX_PAD(0x588, 0x144, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_HCKR__ESAI_HCKR IOMUX_PAD(0x58c, 0x148, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_HCKR__AUDMUX_AUD5_RXFS IOMUX_PAD(0x58c, 0x148, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_HCKR__CSPI2_SS0 IOMUX_PAD(0x58c, 0x148, 2, 0x7f0, 0, NO_PAD_CTRL) +#define MX35_PAD_HCKR__IPU_FLASH_STROBE IOMUX_PAD(0x58c, 0x148, 3, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_HCKR__GPIO1_6 IOMUX_PAD(0x58c, 0x148, 5, 0x858, 1, NO_PAD_CTRL) +#define MX35_PAD_HCKR__ARM11P_TOP_EVNTBUS_12 IOMUX_PAD(0x58c, 0x148, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SCKT__ESAI_SCKT IOMUX_PAD(0x590, 0x14c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SCKT__GPIO1_7 IOMUX_PAD(0x590, 0x14c, 5, 0x85c, 1, NO_PAD_CTRL) +#define MX35_PAD_SCKT__IPU_CSI_D_0 IOMUX_PAD(0x590, 0x14c, 6, 0x930, 0, NO_PAD_CTRL) +#define MX35_PAD_SCKT__KPP_ROW_2 IOMUX_PAD(0x590, 0x14c, 7, 0x978, 1, NO_PAD_CTRL) + +#define MX35_PAD_FST__ESAI_FST IOMUX_PAD(0x594, 0x150, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FST__GPIO1_8 IOMUX_PAD(0x594, 0x150, 5, 0x860, 1, NO_PAD_CTRL) +#define MX35_PAD_FST__IPU_CSI_D_1 IOMUX_PAD(0x594, 0x150, 6, 0x934, 0, NO_PAD_CTRL) +#define MX35_PAD_FST__KPP_ROW_3 IOMUX_PAD(0x594, 0x150, 7, 0x97c, 1, NO_PAD_CTRL) + +#define MX35_PAD_HCKT__ESAI_HCKT IOMUX_PAD(0x598, 0x154, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_HCKT__AUDMUX_AUD5_RXC IOMUX_PAD(0x598, 0x154, 1, 0x7a8, 0, NO_PAD_CTRL) +#define MX35_PAD_HCKT__GPIO1_9 IOMUX_PAD(0x598, 0x154, 5, 0x864, 0, NO_PAD_CTRL) +#define MX35_PAD_HCKT__IPU_CSI_D_2 IOMUX_PAD(0x598, 0x154, 6, 0x938, 0, NO_PAD_CTRL) +#define MX35_PAD_HCKT__KPP_COL_3 IOMUX_PAD(0x598, 0x154, 7, 0x95c, 1, NO_PAD_CTRL) + +#define MX35_PAD_TX5_RX0__ESAI_TX5_RX0 IOMUX_PAD(0x59c, 0x158, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_TX5_RX0__AUDMUX_AUD4_RXC IOMUX_PAD(0x59c, 0x158, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_TX5_RX0__CSPI2_SS2 IOMUX_PAD(0x59c, 0x158, 2, 0x7f8, 1, NO_PAD_CTRL) +#define MX35_PAD_TX5_RX0__CAN2_TXCAN IOMUX_PAD(0x59c, 0x158, 3, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_TX5_RX0__UART2_DTR IOMUX_PAD(0x59c, 0x158, 4, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_TX5_RX0__GPIO1_10 IOMUX_PAD(0x59c, 0x158, 5, 0x830, 0, NO_PAD_CTRL) +#define MX35_PAD_TX5_RX0__EMI_M3IF_CHOSEN_MASTER_0 IOMUX_PAD(0x59c, 0x158, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_TX4_RX1__ESAI_TX4_RX1 IOMUX_PAD(0x5a0, 0x15c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_TX4_RX1__AUDMUX_AUD4_RXFS IOMUX_PAD(0x5a0, 0x15c, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_TX4_RX1__CSPI2_SS3 IOMUX_PAD(0x5a0, 0x15c, 2, 0x7fc, 0, NO_PAD_CTRL) +#define MX35_PAD_TX4_RX1__CAN2_RXCAN IOMUX_PAD(0x5a0, 0x15c, 3, 0x7cc, 0, NO_PAD_CTRL) +#define MX35_PAD_TX4_RX1__UART2_DSR IOMUX_PAD(0x5a0, 0x15c, 4, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_TX4_RX1__GPIO1_11 IOMUX_PAD(0x5a0, 0x15c, 5, 0x834, 0, NO_PAD_CTRL) +#define MX35_PAD_TX4_RX1__IPU_CSI_D_3 IOMUX_PAD(0x5a0, 0x15c, 6, 0x93c, 0, NO_PAD_CTRL) +#define MX35_PAD_TX4_RX1__KPP_ROW_0 IOMUX_PAD(0x5a0, 0x15c, 7, 0x970, 1, NO_PAD_CTRL) + +#define MX35_PAD_TX3_RX2__ESAI_TX3_RX2 IOMUX_PAD(0x5a4, 0x160, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_TX3_RX2__I2C3_SCL IOMUX_PAD(0x5a4, 0x160, 1, 0x91c, 0, NO_PAD_CTRL) +#define MX35_PAD_TX3_RX2__EMI_NANDF_CE1 IOMUX_PAD(0x5a4, 0x160, 3, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_TX3_RX2__GPIO1_12 IOMUX_PAD(0x5a4, 0x160, 5, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_TX3_RX2__IPU_CSI_D_4 IOMUX_PAD(0x5a4, 0x160, 6, 0x940, 0, NO_PAD_CTRL) +#define MX35_PAD_TX3_RX2__KPP_ROW_1 IOMUX_PAD(0x5a4, 0x160, 7, 0x974, 1, NO_PAD_CTRL) + +#define MX35_PAD_TX2_RX3__ESAI_TX2_RX3 IOMUX_PAD(0x5a8, 0x164, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_TX2_RX3__I2C3_SDA IOMUX_PAD(0x5a8, 0x164, 1, 0x920, 0, NO_PAD_CTRL) +#define MX35_PAD_TX2_RX3__EMI_NANDF_CE2 IOMUX_PAD(0x5a8, 0x164, 3, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_TX2_RX3__GPIO1_13 IOMUX_PAD(0x5a8, 0x164, 5, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_TX2_RX3__IPU_CSI_D_5 IOMUX_PAD(0x5a8, 0x164, 6, 0x944, 0, NO_PAD_CTRL) +#define MX35_PAD_TX2_RX3__KPP_COL_0 IOMUX_PAD(0x5a8, 0x164, 7, 0x950, 1, NO_PAD_CTRL) + +#define MX35_PAD_TX1__ESAI_TX1 IOMUX_PAD(0x5ac, 0x168, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_TX1__CCM_PMIC_RDY IOMUX_PAD(0x5ac, 0x168, 1, 0x7d4, 1, NO_PAD_CTRL) +#define MX35_PAD_TX1__CSPI1_SS2 IOMUX_PAD(0x5ac, 0x168, 2, 0x7d8, 2, NO_PAD_CTRL) +#define MX35_PAD_TX1__EMI_NANDF_CE3 IOMUX_PAD(0x5ac, 0x168, 3, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_TX1__UART2_RI IOMUX_PAD(0x5ac, 0x168, 4, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_TX1__GPIO1_14 IOMUX_PAD(0x5ac, 0x168, 5, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_TX1__IPU_CSI_D_6 IOMUX_PAD(0x5ac, 0x168, 6, 0x948, 0, NO_PAD_CTRL) +#define MX35_PAD_TX1__KPP_COL_1 IOMUX_PAD(0x5ac, 0x168, 7, 0x954, 1, NO_PAD_CTRL) + +#define MX35_PAD_TX0__ESAI_TX0 IOMUX_PAD(0x5b0, 0x16c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_TX0__SPDIF_SPDIF_EXTCLK IOMUX_PAD(0x5b0, 0x16c, 1, 0x994, 1, NO_PAD_CTRL) +#define MX35_PAD_TX0__CSPI1_SS3 IOMUX_PAD(0x5b0, 0x16c, 2, 0x7dc, 0, NO_PAD_CTRL) +#define MX35_PAD_TX0__EMI_DTACK_B IOMUX_PAD(0x5b0, 0x16c, 3, 0x800, 1, NO_PAD_CTRL) +#define MX35_PAD_TX0__UART2_DCD IOMUX_PAD(0x5b0, 0x16c, 4, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_TX0__GPIO1_15 IOMUX_PAD(0x5b0, 0x16c, 5, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_TX0__IPU_CSI_D_7 IOMUX_PAD(0x5b0, 0x16c, 6, 0x94c, 0, NO_PAD_CTRL) +#define MX35_PAD_TX0__KPP_COL_2 IOMUX_PAD(0x5b0, 0x16c, 7, 0x958, 1, NO_PAD_CTRL) + +#define MX35_PAD_CSPI1_MOSI__CSPI1_MOSI IOMUX_PAD(0x5b4, 0x170, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CSPI1_MOSI__GPIO1_16 IOMUX_PAD(0x5b4, 0x170, 5, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CSPI1_MOSI__ECT_CTI_TRIG_OUT1_2 IOMUX_PAD(0x5b4, 0x170, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CSPI1_MISO__CSPI1_MISO IOMUX_PAD(0x5b8, 0x174, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CSPI1_MISO__GPIO1_17 IOMUX_PAD(0x5b8, 0x174, 5, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CSPI1_MISO__ECT_CTI_TRIG_OUT1_3 IOMUX_PAD(0x5b8, 0x174, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CSPI1_SS0__CSPI1_SS0 IOMUX_PAD(0x5bc, 0x178, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CSPI1_SS0__OWIRE_LINE IOMUX_PAD(0x5bc, 0x178, 1, 0x990, 1, NO_PAD_CTRL) +#define MX35_PAD_CSPI1_SS0__CSPI2_SS3 IOMUX_PAD(0x5bc, 0x178, 2, 0x7fc, 1, NO_PAD_CTRL) +#define MX35_PAD_CSPI1_SS0__GPIO1_18 IOMUX_PAD(0x5bc, 0x178, 5, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CSPI1_SS0__ECT_CTI_TRIG_OUT1_4 IOMUX_PAD(0x5bc, 0x178, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CSPI1_SS1__CSPI1_SS1 IOMUX_PAD(0x5c0, 0x17c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CSPI1_SS1__PWM_PWMO IOMUX_PAD(0x5c0, 0x17c, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CSPI1_SS1__CCM_CLK32K IOMUX_PAD(0x5c0, 0x17c, 2, 0x7d0, 1, NO_PAD_CTRL) +#define MX35_PAD_CSPI1_SS1__GPIO1_19 IOMUX_PAD(0x5c0, 0x17c, 5, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CSPI1_SS1__IPU_DIAGB_29 IOMUX_PAD(0x5c0, 0x17c, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CSPI1_SS1__ECT_CTI_TRIG_OUT1_5 IOMUX_PAD(0x5c0, 0x17c, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CSPI1_SCLK__CSPI1_SCLK IOMUX_PAD(0x5c4, 0x180, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CSPI1_SCLK__GPIO3_4 IOMUX_PAD(0x5c4, 0x180, 5, 0x904, 0, NO_PAD_CTRL) +#define MX35_PAD_CSPI1_SCLK__IPU_DIAGB_30 IOMUX_PAD(0x5c4, 0x180, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CSPI1_SCLK__EMI_M3IF_CHOSEN_MASTER_1 IOMUX_PAD(0x5c4, 0x180, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CSPI1_SPI_RDY__CSPI1_RDY IOMUX_PAD(0x5c8, 0x184, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CSPI1_SPI_RDY__GPIO3_5 IOMUX_PAD(0x5c8, 0x184, 5, 0x908, 0, NO_PAD_CTRL) +#define MX35_PAD_CSPI1_SPI_RDY__IPU_DIAGB_31 IOMUX_PAD(0x5c8, 0x184, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CSPI1_SPI_RDY__EMI_M3IF_CHOSEN_MASTER_2 IOMUX_PAD(0x5c8, 0x184, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_RXD1__UART1_RXD_MUX IOMUX_PAD(0x5cc, 0x188, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_RXD1__CSPI2_MOSI IOMUX_PAD(0x5cc, 0x188, 1, 0x7ec, 1, NO_PAD_CTRL) +#define MX35_PAD_RXD1__KPP_COL_4 IOMUX_PAD(0x5cc, 0x188, 4, 0x960, 0, NO_PAD_CTRL) +#define MX35_PAD_RXD1__GPIO3_6 IOMUX_PAD(0x5cc, 0x188, 5, 0x90c, 0, NO_PAD_CTRL) +#define MX35_PAD_RXD1__ARM11P_TOP_EVNTBUS_16 IOMUX_PAD(0x5cc, 0x188, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_TXD1__UART1_TXD_MUX IOMUX_PAD(0x5d0, 0x18c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_TXD1__CSPI2_MISO IOMUX_PAD(0x5d0, 0x18c, 1, 0x7e8, 1, NO_PAD_CTRL) +#define MX35_PAD_TXD1__KPP_COL_5 IOMUX_PAD(0x5d0, 0x18c, 4, 0x964, 0, NO_PAD_CTRL) +#define MX35_PAD_TXD1__GPIO3_7 IOMUX_PAD(0x5d0, 0x18c, 5, 0x910, 0, NO_PAD_CTRL) +#define MX35_PAD_TXD1__ARM11P_TOP_EVNTBUS_17 IOMUX_PAD(0x5d0, 0x18c, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_RTS1__UART1_RTS IOMUX_PAD(0x5d4, 0x190, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_RTS1__CSPI2_SCLK IOMUX_PAD(0x5d4, 0x190, 1, 0x7e0, 1, NO_PAD_CTRL) +#define MX35_PAD_RTS1__I2C3_SCL IOMUX_PAD(0x5d4, 0x190, 2, 0x91c, 1, NO_PAD_CTRL) +#define MX35_PAD_RTS1__IPU_CSI_D_0 IOMUX_PAD(0x5d4, 0x190, 3, 0x930, 1, NO_PAD_CTRL) +#define MX35_PAD_RTS1__KPP_COL_6 IOMUX_PAD(0x5d4, 0x190, 4, 0x968, 0, NO_PAD_CTRL) +#define MX35_PAD_RTS1__GPIO3_8 IOMUX_PAD(0x5d4, 0x190, 5, 0x914, 0, NO_PAD_CTRL) +#define MX35_PAD_RTS1__EMI_NANDF_CE1 IOMUX_PAD(0x5d4, 0x190, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_RTS1__ARM11P_TOP_EVNTBUS_18 IOMUX_PAD(0x5d4, 0x190, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CTS1__UART1_CTS IOMUX_PAD(0x5d8, 0x194, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CTS1__CSPI2_RDY IOMUX_PAD(0x5d8, 0x194, 1, 0x7e4, 1, NO_PAD_CTRL) +#define MX35_PAD_CTS1__I2C3_SDA IOMUX_PAD(0x5d8, 0x194, 2, 0x920, 1, NO_PAD_CTRL) +#define MX35_PAD_CTS1__IPU_CSI_D_1 IOMUX_PAD(0x5d8, 0x194, 3, 0x934, 1, NO_PAD_CTRL) +#define MX35_PAD_CTS1__KPP_COL_7 IOMUX_PAD(0x5d8, 0x194, 4, 0x96c, 0, NO_PAD_CTRL) +#define MX35_PAD_CTS1__GPIO3_9 IOMUX_PAD(0x5d8, 0x194, 5, 0x918, 0, NO_PAD_CTRL) +#define MX35_PAD_CTS1__EMI_NANDF_CE2 IOMUX_PAD(0x5d8, 0x194, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CTS1__ARM11P_TOP_EVNTBUS_19 IOMUX_PAD(0x5d8, 0x194, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_RXD2__UART2_RXD_MUX IOMUX_PAD(0x5dc, 0x198, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_RXD2__KPP_ROW_4 IOMUX_PAD(0x5dc, 0x198, 4, 0x980, 0, NO_PAD_CTRL) +#define MX35_PAD_RXD2__GPIO3_10 IOMUX_PAD(0x5dc, 0x198, 5, 0x8ec, 0, NO_PAD_CTRL) + +#define MX35_PAD_TXD2__UART2_TXD_MUX IOMUX_PAD(0x5e0, 0x19c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_TXD2__SPDIF_SPDIF_EXTCLK IOMUX_PAD(0x5e0, 0x19c, 1, 0x994, 2, NO_PAD_CTRL) +#define MX35_PAD_TXD2__KPP_ROW_5 IOMUX_PAD(0x5e0, 0x19c, 4, 0x984, 0, NO_PAD_CTRL) +#define MX35_PAD_TXD2__GPIO3_11 IOMUX_PAD(0x5e0, 0x19c, 5, 0x8f0, 0, NO_PAD_CTRL) + +#define MX35_PAD_RTS2__UART2_RTS IOMUX_PAD(0x5e4, 0x1a0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_RTS2__SPDIF_SPDIF_IN1 IOMUX_PAD(0x5e4, 0x1a0, 1, 0x998, 1, NO_PAD_CTRL) +#define MX35_PAD_RTS2__CAN2_RXCAN IOMUX_PAD(0x5e4, 0x1a0, 2, 0x7cc, 1, NO_PAD_CTRL) +#define MX35_PAD_RTS2__IPU_CSI_D_2 IOMUX_PAD(0x5e4, 0x1a0, 3, 0x938, 1, NO_PAD_CTRL) +#define MX35_PAD_RTS2__KPP_ROW_6 IOMUX_PAD(0x5e4, 0x1a0, 4, 0x988, 0, NO_PAD_CTRL) +#define MX35_PAD_RTS2__GPIO3_12 IOMUX_PAD(0x5e4, 0x1a0, 5, 0x8f4, 0, NO_PAD_CTRL) +#define MX35_PAD_RTS2__AUDMUX_AUD5_RXC IOMUX_PAD(0x5e4, 0x1a0, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_RTS2__UART3_RXD_MUX IOMUX_PAD(0x5e4, 0x1a0, 7, 0x9a0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CTS2__UART2_CTS IOMUX_PAD(0x5e8, 0x1a4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CTS2__SPDIF_SPDIF_OUT1 IOMUX_PAD(0x5e8, 0x1a4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CTS2__CAN2_TXCAN IOMUX_PAD(0x5e8, 0x1a4, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CTS2__IPU_CSI_D_3 IOMUX_PAD(0x5e8, 0x1a4, 3, 0x93c, 1, NO_PAD_CTRL) +#define MX35_PAD_CTS2__KPP_ROW_7 IOMUX_PAD(0x5e8, 0x1a4, 4, 0x98c, 0, NO_PAD_CTRL) +#define MX35_PAD_CTS2__GPIO3_13 IOMUX_PAD(0x5e8, 0x1a4, 5, 0x8f8, 0, NO_PAD_CTRL) +#define MX35_PAD_CTS2__AUDMUX_AUD5_RXFS IOMUX_PAD(0x5e8, 0x1a4, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CTS2__UART3_TXD_MUX IOMUX_PAD(0x5e8, 0x1a4, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_RTCK__ARM11P_TOP_RTCK IOMUX_PAD(0x5ec, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_TCK__SJC_TCK IOMUX_PAD(0x5f0, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_TMS__SJC_TMS IOMUX_PAD(0x5f4, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_TDI__SJC_TDI IOMUX_PAD(0x5f8, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_TDO__SJC_TDO IOMUX_PAD(0x5fc, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_TRSTB__SJC_TRSTB IOMUX_PAD(0x600, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_DE_B__SJC_DE_B IOMUX_PAD(0x604, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SJC_MOD__SJC_MOD IOMUX_PAD(0x608, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR IOMUX_PAD(0x60c, 0x1a8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_USBOTG_PWR__USB_TOP_USBH2_PWR IOMUX_PAD(0x60c, 0x1a8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_USBOTG_PWR__GPIO3_14 IOMUX_PAD(0x60c, 0x1a8, 5, 0x8fc, 0, NO_PAD_CTRL) + +#define MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC IOMUX_PAD(0x610, 0x1ac, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_USBOTG_OC__USB_TOP_USBH2_OC IOMUX_PAD(0x610, 0x1ac, 1, 0x9f4, 1, NO_PAD_CTRL) +#define MX35_PAD_USBOTG_OC__GPIO3_15 IOMUX_PAD(0x610, 0x1ac, 5, 0x900, 0, NO_PAD_CTRL) + +#define MX35_PAD_LD0__IPU_DISPB_DAT_0 IOMUX_PAD(0x614, 0x1b0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD0__GPIO2_0 IOMUX_PAD(0x614, 0x1b0, 5, 0x868, 1, NO_PAD_CTRL) +#define MX35_PAD_LD0__SDMA_SDMA_DEBUG_PC_0 IOMUX_PAD(0x614, 0x1b0, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_LD1__IPU_DISPB_DAT_1 IOMUX_PAD(0x618, 0x1b4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD1__GPIO2_1 IOMUX_PAD(0x618, 0x1b4, 5, 0x894, 0, NO_PAD_CTRL) +#define MX35_PAD_LD1__SDMA_SDMA_DEBUG_PC_1 IOMUX_PAD(0x618, 0x1b4, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_LD2__IPU_DISPB_DAT_2 IOMUX_PAD(0x61c, 0x1b8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD2__GPIO2_2 IOMUX_PAD(0x61c, 0x1b8, 5, 0x8c0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD2__SDMA_SDMA_DEBUG_PC_2 IOMUX_PAD(0x61c, 0x1b8, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_LD3__IPU_DISPB_DAT_3 IOMUX_PAD(0x620, 0x1bc, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD3__GPIO2_3 IOMUX_PAD(0x620, 0x1bc, 5, 0x8cc, 0, NO_PAD_CTRL) +#define MX35_PAD_LD3__SDMA_SDMA_DEBUG_PC_3 IOMUX_PAD(0x620, 0x1bc, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_LD4__IPU_DISPB_DAT_4 IOMUX_PAD(0x624, 0x1c0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD4__GPIO2_4 IOMUX_PAD(0x624, 0x1c0, 5, 0x8d0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD4__SDMA_SDMA_DEBUG_PC_4 IOMUX_PAD(0x624, 0x1c0, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_LD5__IPU_DISPB_DAT_5 IOMUX_PAD(0x628, 0x1c4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD5__GPIO2_5 IOMUX_PAD(0x628, 0x1c4, 5, 0x8d4, 0, NO_PAD_CTRL) +#define MX35_PAD_LD5__SDMA_SDMA_DEBUG_PC_5 IOMUX_PAD(0x628, 0x1c4, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_LD6__IPU_DISPB_DAT_6 IOMUX_PAD(0x62c, 0x1c8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD6__GPIO2_6 IOMUX_PAD(0x62c, 0x1c8, 5, 0x8d8, 0, NO_PAD_CTRL) +#define MX35_PAD_LD6__SDMA_SDMA_DEBUG_PC_6 IOMUX_PAD(0x62c, 0x1c8, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_LD7__IPU_DISPB_DAT_7 IOMUX_PAD(0x630, 0x1cc, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD7__GPIO2_7 IOMUX_PAD(0x630, 0x1cc, 5, 0x8dc, 0, NO_PAD_CTRL) +#define MX35_PAD_LD7__SDMA_SDMA_DEBUG_PC_7 IOMUX_PAD(0x630, 0x1cc, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_LD8__IPU_DISPB_DAT_8 IOMUX_PAD(0x634, 0x1d0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD8__GPIO2_8 IOMUX_PAD(0x634, 0x1d0, 5, 0x8e0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD8__SDMA_SDMA_DEBUG_PC_8 IOMUX_PAD(0x634, 0x1d0, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_LD9__IPU_DISPB_DAT_9 IOMUX_PAD(0x638, 0x1d4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD9__GPIO2_9 IOMUX_PAD(0x638, 0x1d4, 5, 0x8e4, 0, NO_PAD_CTRL) +#define MX35_PAD_LD9__SDMA_SDMA_DEBUG_PC_9 IOMUX_PAD(0x638, 0x1d4, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_LD10__IPU_DISPB_DAT_10 IOMUX_PAD(0x63c, 0x1d8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD10__GPIO2_10 IOMUX_PAD(0x63c, 0x1d8, 5, 0x86c, 0, NO_PAD_CTRL) +#define MX35_PAD_LD10__SDMA_SDMA_DEBUG_PC_10 IOMUX_PAD(0x63c, 0x1d8, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_LD11__IPU_DISPB_DAT_11 IOMUX_PAD(0x640, 0x1dc, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD11__GPIO2_11 IOMUX_PAD(0x640, 0x1dc, 5, 0x870, 0, NO_PAD_CTRL) +#define MX35_PAD_LD11__SDMA_SDMA_DEBUG_PC_11 IOMUX_PAD(0x640, 0x1dc, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD11__ARM11P_TOP_TRACE_4 IOMUX_PAD(0x640, 0x1dc, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_LD12__IPU_DISPB_DAT_12 IOMUX_PAD(0x644, 0x1e0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD12__GPIO2_12 IOMUX_PAD(0x644, 0x1e0, 5, 0x874, 0, NO_PAD_CTRL) +#define MX35_PAD_LD12__SDMA_SDMA_DEBUG_PC_12 IOMUX_PAD(0x644, 0x1e0, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD12__ARM11P_TOP_TRACE_5 IOMUX_PAD(0x644, 0x1e0, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_LD13__IPU_DISPB_DAT_13 IOMUX_PAD(0x648, 0x1e4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD13__GPIO2_13 IOMUX_PAD(0x648, 0x1e4, 5, 0x878, 0, NO_PAD_CTRL) +#define MX35_PAD_LD13__SDMA_SDMA_DEBUG_PC_13 IOMUX_PAD(0x648, 0x1e4, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD13__ARM11P_TOP_TRACE_6 IOMUX_PAD(0x648, 0x1e4, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_LD14__IPU_DISPB_DAT_14 IOMUX_PAD(0x64c, 0x1e8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD14__GPIO2_14 IOMUX_PAD(0x64c, 0x1e8, 5, 0x87c, 0, NO_PAD_CTRL) +#define MX35_PAD_LD14__SDMA_SDMA_DEBUG_EVENT_CHANNEL_0 IOMUX_PAD(0x64c, 0x1e8, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD14__ARM11P_TOP_TRACE_7 IOMUX_PAD(0x64c, 0x1e8, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_LD15__IPU_DISPB_DAT_15 IOMUX_PAD(0x650, 0x1ec, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD15__GPIO2_15 IOMUX_PAD(0x650, 0x1ec, 5, 0x880, 0, NO_PAD_CTRL) +#define MX35_PAD_LD15__SDMA_SDMA_DEBUG_EVENT_CHANNEL_1 IOMUX_PAD(0x650, 0x1ec, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD15__ARM11P_TOP_TRACE_8 IOMUX_PAD(0x650, 0x1ec, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_LD16__IPU_DISPB_DAT_16 IOMUX_PAD(0x654, 0x1f0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD16__IPU_DISPB_D12_VSYNC IOMUX_PAD(0x654, 0x1f0, 2, 0x928, 0, NO_PAD_CTRL) +#define MX35_PAD_LD16__GPIO2_16 IOMUX_PAD(0x654, 0x1f0, 5, 0x884, 0, NO_PAD_CTRL) +#define MX35_PAD_LD16__SDMA_SDMA_DEBUG_EVENT_CHANNEL_2 IOMUX_PAD(0x654, 0x1f0, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD16__ARM11P_TOP_TRACE_9 IOMUX_PAD(0x654, 0x1f0, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_LD17__IPU_DISPB_DAT_17 IOMUX_PAD(0x658, 0x1f4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD17__IPU_DISPB_CS2 IOMUX_PAD(0x658, 0x1f4, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD17__GPIO2_17 IOMUX_PAD(0x658, 0x1f4, 5, 0x888, 0, NO_PAD_CTRL) +#define MX35_PAD_LD17__SDMA_SDMA_DEBUG_EVENT_CHANNEL_3 IOMUX_PAD(0x658, 0x1f4, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD17__ARM11P_TOP_TRACE_10 IOMUX_PAD(0x658, 0x1f4, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_LD18__IPU_DISPB_DAT_18 IOMUX_PAD(0x65c, 0x1f8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD18__IPU_DISPB_D0_VSYNC IOMUX_PAD(0x65c, 0x1f8, 1, 0x924, 1, NO_PAD_CTRL) +#define MX35_PAD_LD18__IPU_DISPB_D12_VSYNC IOMUX_PAD(0x65c, 0x1f8, 2, 0x928, 1, NO_PAD_CTRL) +#define MX35_PAD_LD18__ESDHC3_CMD IOMUX_PAD(0x65c, 0x1f8, 3, 0x818, 0, NO_PAD_CTRL) +#define MX35_PAD_LD18__USB_TOP_USBOTG_DATA_3 IOMUX_PAD(0x65c, 0x1f8, 4, 0x9b0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD18__GPIO3_24 IOMUX_PAD(0x65c, 0x1f8, 5, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD18__SDMA_SDMA_DEBUG_EVENT_CHANNEL_4 IOMUX_PAD(0x65c, 0x1f8, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD18__ARM11P_TOP_TRACE_11 IOMUX_PAD(0x65c, 0x1f8, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_LD19__IPU_DISPB_DAT_19 IOMUX_PAD(0x660, 0x1fc, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD19__IPU_DISPB_BCLK IOMUX_PAD(0x660, 0x1fc, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD19__IPU_DISPB_CS1 IOMUX_PAD(0x660, 0x1fc, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD19__ESDHC3_CLK IOMUX_PAD(0x660, 0x1fc, 3, 0x814, 0, NO_PAD_CTRL) +#define MX35_PAD_LD19__USB_TOP_USBOTG_DIR IOMUX_PAD(0x660, 0x1fc, 4, 0x9c4, 0, NO_PAD_CTRL) +#define MX35_PAD_LD19__GPIO3_25 IOMUX_PAD(0x660, 0x1fc, 5, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD19__SDMA_SDMA_DEBUG_EVENT_CHANNEL_5 IOMUX_PAD(0x660, 0x1fc, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD19__ARM11P_TOP_TRACE_12 IOMUX_PAD(0x660, 0x1fc, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_LD20__IPU_DISPB_DAT_20 IOMUX_PAD(0x664, 0x200, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD20__IPU_DISPB_CS0 IOMUX_PAD(0x664, 0x200, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD20__IPU_DISPB_SD_CLK IOMUX_PAD(0x664, 0x200, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD20__ESDHC3_DAT0 IOMUX_PAD(0x664, 0x200, 3, 0x81c, 0, NO_PAD_CTRL) +#define MX35_PAD_LD20__GPIO3_26 IOMUX_PAD(0x664, 0x200, 5, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD20__SDMA_SDMA_DEBUG_CORE_STATUS_3 IOMUX_PAD(0x664, 0x200, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD20__ARM11P_TOP_TRACE_13 IOMUX_PAD(0x664, 0x200, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_LD21__IPU_DISPB_DAT_21 IOMUX_PAD(0x668, 0x204, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD21__IPU_DISPB_PAR_RS IOMUX_PAD(0x668, 0x204, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD21__IPU_DISPB_SER_RS IOMUX_PAD(0x668, 0x204, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD21__ESDHC3_DAT1 IOMUX_PAD(0x668, 0x204, 3, 0x820, 0, NO_PAD_CTRL) +#define MX35_PAD_LD21__USB_TOP_USBOTG_STP IOMUX_PAD(0x668, 0x204, 4, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD21__GPIO3_27 IOMUX_PAD(0x668, 0x204, 5, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD21__SDMA_DEBUG_EVENT_CHANNEL_SEL IOMUX_PAD(0x668, 0x204, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD21__ARM11P_TOP_TRACE_14 IOMUX_PAD(0x668, 0x204, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_LD22__IPU_DISPB_DAT_22 IOMUX_PAD(0x66c, 0x208, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD22__IPU_DISPB_WR IOMUX_PAD(0x66c, 0x208, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD22__IPU_DISPB_SD_D_I IOMUX_PAD(0x66c, 0x208, 2, 0x92c, 0, NO_PAD_CTRL) +#define MX35_PAD_LD22__ESDHC3_DAT2 IOMUX_PAD(0x66c, 0x208, 3, 0x824, 0, NO_PAD_CTRL) +#define MX35_PAD_LD22__USB_TOP_USBOTG_NXT IOMUX_PAD(0x66c, 0x208, 4, 0x9c8, 0, NO_PAD_CTRL) +#define MX35_PAD_LD22__GPIO3_28 IOMUX_PAD(0x66c, 0x208, 5, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD22__SDMA_DEBUG_BUS_ERROR IOMUX_PAD(0x66c, 0x208, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD22__ARM11P_TOP_TRCTL IOMUX_PAD(0x66c, 0x208, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_LD23__IPU_DISPB_DAT_23 IOMUX_PAD(0x670, 0x20c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD23__IPU_DISPB_RD IOMUX_PAD(0x670, 0x20c, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD23__IPU_DISPB_SD_D_IO IOMUX_PAD(0x670, 0x20c, 2, 0x92c, 1, NO_PAD_CTRL) +#define MX35_PAD_LD23__ESDHC3_DAT3 IOMUX_PAD(0x670, 0x20c, 3, 0x828, 0, NO_PAD_CTRL) +#define MX35_PAD_LD23__USB_TOP_USBOTG_DATA_7 IOMUX_PAD(0x670, 0x20c, 4, 0x9c0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD23__GPIO3_29 IOMUX_PAD(0x670, 0x20c, 5, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD23__SDMA_DEBUG_MATCHED_DMBUS IOMUX_PAD(0x670, 0x20c, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD23__ARM11P_TOP_TRCLK IOMUX_PAD(0x670, 0x20c, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC IOMUX_PAD(0x674, 0x210, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_D3_HSYNC__IPU_DISPB_SD_D_IO IOMUX_PAD(0x674, 0x210, 2, 0x92c, 2, NO_PAD_CTRL) +#define MX35_PAD_D3_HSYNC__GPIO3_30 IOMUX_PAD(0x674, 0x210, 5, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_D3_HSYNC__SDMA_DEBUG_RTBUFFER_WRITE IOMUX_PAD(0x674, 0x210, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_D3_HSYNC__ARM11P_TOP_TRACE_15 IOMUX_PAD(0x674, 0x210, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK IOMUX_PAD(0x678, 0x214, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_D3_FPSHIFT__IPU_DISPB_SD_CLK IOMUX_PAD(0x678, 0x214, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_D3_FPSHIFT__GPIO3_31 IOMUX_PAD(0x678, 0x214, 5, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_D3_FPSHIFT__SDMA_SDMA_DEBUG_CORE_STATUS_0 IOMUX_PAD(0x678, 0x214, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_D3_FPSHIFT__ARM11P_TOP_TRACE_16 IOMUX_PAD(0x678, 0x214, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY IOMUX_PAD(0x67c, 0x218, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_D3_DRDY__IPU_DISPB_SD_D_O IOMUX_PAD(0x67c, 0x218, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_D3_DRDY__GPIO1_0 IOMUX_PAD(0x67c, 0x218, 5, 0x82c, 2, NO_PAD_CTRL) +#define MX35_PAD_D3_DRDY__SDMA_SDMA_DEBUG_CORE_STATUS_1 IOMUX_PAD(0x67c, 0x218, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_D3_DRDY__ARM11P_TOP_TRACE_17 IOMUX_PAD(0x67c, 0x218, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CONTRAST__IPU_DISPB_CONTR IOMUX_PAD(0x680, 0x21c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CONTRAST__GPIO1_1 IOMUX_PAD(0x680, 0x21c, 5, 0x838, 2, NO_PAD_CTRL) +#define MX35_PAD_CONTRAST__SDMA_SDMA_DEBUG_CORE_STATUS_2 IOMUX_PAD(0x680, 0x21c, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CONTRAST__ARM11P_TOP_TRACE_18 IOMUX_PAD(0x680, 0x21c, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC IOMUX_PAD(0x684, 0x220, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_D3_VSYNC__IPU_DISPB_CS1 IOMUX_PAD(0x684, 0x220, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_D3_VSYNC__GPIO1_2 IOMUX_PAD(0x684, 0x220, 5, 0x848, 1, NO_PAD_CTRL) +#define MX35_PAD_D3_VSYNC__SDMA_DEBUG_YIELD IOMUX_PAD(0x684, 0x220, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_D3_VSYNC__ARM11P_TOP_TRACE_19 IOMUX_PAD(0x684, 0x220, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_D3_REV__IPU_DISPB_D3_REV IOMUX_PAD(0x688, 0x224, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_D3_REV__IPU_DISPB_SER_RS IOMUX_PAD(0x688, 0x224, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_D3_REV__GPIO1_3 IOMUX_PAD(0x688, 0x224, 5, 0x84c, 1, NO_PAD_CTRL) +#define MX35_PAD_D3_REV__SDMA_DEBUG_BUS_RWB IOMUX_PAD(0x688, 0x224, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_D3_REV__ARM11P_TOP_TRACE_20 IOMUX_PAD(0x688, 0x224, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS IOMUX_PAD(0x68c, 0x228, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_D3_CLS__IPU_DISPB_CS2 IOMUX_PAD(0x68c, 0x228, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_D3_CLS__GPIO1_4 IOMUX_PAD(0x68c, 0x228, 5, 0x850, 2, NO_PAD_CTRL) +#define MX35_PAD_D3_CLS__SDMA_DEBUG_BUS_DEVICE_0 IOMUX_PAD(0x68c, 0x228, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_D3_CLS__ARM11P_TOP_TRACE_21 IOMUX_PAD(0x68c, 0x228, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_D3_SPL__IPU_DISPB_D3_SPL IOMUX_PAD(0x690, 0x22c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_D3_SPL__IPU_DISPB_D12_VSYNC IOMUX_PAD(0x690, 0x22c, 2, 0x928, 2, NO_PAD_CTRL) +#define MX35_PAD_D3_SPL__GPIO1_5 IOMUX_PAD(0x690, 0x22c, 5, 0x854, 2, NO_PAD_CTRL) +#define MX35_PAD_D3_SPL__SDMA_DEBUG_BUS_DEVICE_1 IOMUX_PAD(0x690, 0x22c, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_D3_SPL__ARM11P_TOP_TRACE_22 IOMUX_PAD(0x690, 0x22c, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD1_CMD__ESDHC1_CMD IOMUX_PAD(0x694, 0x230, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD1_CMD__MSHC_SCLK IOMUX_PAD(0x694, 0x230, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD1_CMD__IPU_DISPB_D0_VSYNC IOMUX_PAD(0x694, 0x230, 3, 0x924, 2, NO_PAD_CTRL) +#define MX35_PAD_SD1_CMD__USB_TOP_USBOTG_DATA_4 IOMUX_PAD(0x694, 0x230, 4, 0x9b4, 0, NO_PAD_CTRL) +#define MX35_PAD_SD1_CMD__GPIO1_6 IOMUX_PAD(0x694, 0x230, 5, 0x858, 2, NO_PAD_CTRL) +#define MX35_PAD_SD1_CMD__ARM11P_TOP_TRCTL IOMUX_PAD(0x694, 0x230, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD1_CLK__ESDHC1_CLK IOMUX_PAD(0x698, 0x234, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD1_CLK__MSHC_BS IOMUX_PAD(0x698, 0x234, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD1_CLK__IPU_DISPB_BCLK IOMUX_PAD(0x698, 0x234, 3, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD1_CLK__USB_TOP_USBOTG_DATA_5 IOMUX_PAD(0x698, 0x234, 4, 0x9b8, 0, NO_PAD_CTRL) +#define MX35_PAD_SD1_CLK__GPIO1_7 IOMUX_PAD(0x698, 0x234, 5, 0x85c, 2, NO_PAD_CTRL) +#define MX35_PAD_SD1_CLK__ARM11P_TOP_TRCLK IOMUX_PAD(0x698, 0x234, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD1_DATA0__ESDHC1_DAT0 IOMUX_PAD(0x69c, 0x238, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD1_DATA0__MSHC_DATA_0 IOMUX_PAD(0x69c, 0x238, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD1_DATA0__IPU_DISPB_CS0 IOMUX_PAD(0x69c, 0x238, 3, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD1_DATA0__USB_TOP_USBOTG_DATA_6 IOMUX_PAD(0x69c, 0x238, 4, 0x9bc, 0, NO_PAD_CTRL) +#define MX35_PAD_SD1_DATA0__GPIO1_8 IOMUX_PAD(0x69c, 0x238, 5, 0x860, 2, NO_PAD_CTRL) +#define MX35_PAD_SD1_DATA0__ARM11P_TOP_TRACE_23 IOMUX_PAD(0x69c, 0x238, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD1_DATA1__ESDHC1_DAT1 IOMUX_PAD(0x6a0, 0x23c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD1_DATA1__MSHC_DATA_1 IOMUX_PAD(0x6a0, 0x23c, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD1_DATA1__IPU_DISPB_PAR_RS IOMUX_PAD(0x6a0, 0x23c, 3, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD1_DATA1__USB_TOP_USBOTG_DATA_0 IOMUX_PAD(0x6a0, 0x23c, 4, 0x9a4, 0, NO_PAD_CTRL) +#define MX35_PAD_SD1_DATA1__GPIO1_9 IOMUX_PAD(0x6a0, 0x23c, 5, 0x864, 1, NO_PAD_CTRL) +#define MX35_PAD_SD1_DATA1__ARM11P_TOP_TRACE_24 IOMUX_PAD(0x6a0, 0x23c, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD1_DATA2__ESDHC1_DAT2 IOMUX_PAD(0x6a4, 0x240, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD1_DATA2__MSHC_DATA_2 IOMUX_PAD(0x6a4, 0x240, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD1_DATA2__IPU_DISPB_WR IOMUX_PAD(0x6a4, 0x240, 3, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD1_DATA2__USB_TOP_USBOTG_DATA_1 IOMUX_PAD(0x6a4, 0x240, 4, 0x9a8, 0, NO_PAD_CTRL) +#define MX35_PAD_SD1_DATA2__GPIO1_10 IOMUX_PAD(0x6a4, 0x240, 5, 0x830, 1, NO_PAD_CTRL) +#define MX35_PAD_SD1_DATA2__ARM11P_TOP_TRACE_25 IOMUX_PAD(0x6a4, 0x240, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD1_DATA3__ESDHC1_DAT3 IOMUX_PAD(0x6a8, 0x244, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD1_DATA3__MSHC_DATA_3 IOMUX_PAD(0x6a8, 0x244, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD1_DATA3__IPU_DISPB_RD IOMUX_PAD(0x6a8, 0x244, 3, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD1_DATA3__USB_TOP_USBOTG_DATA_2 IOMUX_PAD(0x6a8, 0x244, 4, 0x9ac, 0, NO_PAD_CTRL) +#define MX35_PAD_SD1_DATA3__GPIO1_11 IOMUX_PAD(0x6a8, 0x244, 5, 0x834, 1, NO_PAD_CTRL) +#define MX35_PAD_SD1_DATA3__ARM11P_TOP_TRACE_26 IOMUX_PAD(0x6a8, 0x244, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD2_CMD__ESDHC2_CMD IOMUX_PAD(0x6ac, 0x248, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD2_CMD__I2C3_SCL IOMUX_PAD(0x6ac, 0x248, 1, 0x91c, 2, NO_PAD_CTRL) +#define MX35_PAD_SD2_CMD__ESDHC1_DAT4 IOMUX_PAD(0x6ac, 0x248, 2, 0x804, 0, NO_PAD_CTRL) +#define MX35_PAD_SD2_CMD__IPU_CSI_D_2 IOMUX_PAD(0x6ac, 0x248, 3, 0x938, 2, NO_PAD_CTRL) +#define MX35_PAD_SD2_CMD__USB_TOP_USBH2_DATA_4 IOMUX_PAD(0x6ac, 0x248, 4, 0x9dc, 0, NO_PAD_CTRL) +#define MX35_PAD_SD2_CMD__GPIO2_0 IOMUX_PAD(0x6ac, 0x248, 5, 0x868, 2, NO_PAD_CTRL) +#define MX35_PAD_SD2_CMD__SPDIF_SPDIF_OUT1 IOMUX_PAD(0x6ac, 0x248, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD2_CMD__IPU_DISPB_D12_VSYNC IOMUX_PAD(0x6ac, 0x248, 7, 0x928, 3, NO_PAD_CTRL) + +#define MX35_PAD_SD2_CLK__ESDHC2_CLK IOMUX_PAD(0x6b0, 0x24c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD2_CLK__I2C3_SDA IOMUX_PAD(0x6b0, 0x24c, 1, 0x920, 2, NO_PAD_CTRL) +#define MX35_PAD_SD2_CLK__ESDHC1_DAT5 IOMUX_PAD(0x6b0, 0x24c, 2, 0x808, 0, NO_PAD_CTRL) +#define MX35_PAD_SD2_CLK__IPU_CSI_D_3 IOMUX_PAD(0x6b0, 0x24c, 3, 0x93c, 2, NO_PAD_CTRL) +#define MX35_PAD_SD2_CLK__USB_TOP_USBH2_DATA_5 IOMUX_PAD(0x6b0, 0x24c, 4, 0x9e0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD2_CLK__GPIO2_1 IOMUX_PAD(0x6b0, 0x24c, 5, 0x894, 1, NO_PAD_CTRL) +#define MX35_PAD_SD2_CLK__SPDIF_SPDIF_IN1 IOMUX_PAD(0x6b0, 0x24c, 6, 0x998, 2, NO_PAD_CTRL) +#define MX35_PAD_SD2_CLK__IPU_DISPB_CS2 IOMUX_PAD(0x6b0, 0x24c, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD2_DATA0__ESDHC2_DAT0 IOMUX_PAD(0x6b4, 0x250, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD2_DATA0__UART3_RXD_MUX IOMUX_PAD(0x6b4, 0x250, 1, 0x9a0, 1, NO_PAD_CTRL) +#define MX35_PAD_SD2_DATA0__ESDHC1_DAT6 IOMUX_PAD(0x6b4, 0x250, 2, 0x80c, 0, NO_PAD_CTRL) +#define MX35_PAD_SD2_DATA0__IPU_CSI_D_4 IOMUX_PAD(0x6b4, 0x250, 3, 0x940, 1, NO_PAD_CTRL) +#define MX35_PAD_SD2_DATA0__USB_TOP_USBH2_DATA_6 IOMUX_PAD(0x6b4, 0x250, 4, 0x9e4, 0, NO_PAD_CTRL) +#define MX35_PAD_SD2_DATA0__GPIO2_2 IOMUX_PAD(0x6b4, 0x250, 5, 0x8c0, 1, NO_PAD_CTRL) +#define MX35_PAD_SD2_DATA0__SPDIF_SPDIF_EXTCLK IOMUX_PAD(0x6b4, 0x250, 6, 0x994, 3, NO_PAD_CTRL) + +#define MX35_PAD_SD2_DATA1__ESDHC2_DAT1 IOMUX_PAD(0x6b8, 0x254, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD2_DATA1__UART3_TXD_MUX IOMUX_PAD(0x6b8, 0x254, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD2_DATA1__ESDHC1_DAT7 IOMUX_PAD(0x6b8, 0x254, 2, 0x810, 0, NO_PAD_CTRL) +#define MX35_PAD_SD2_DATA1__IPU_CSI_D_5 IOMUX_PAD(0x6b8, 0x254, 3, 0x944, 1, NO_PAD_CTRL) +#define MX35_PAD_SD2_DATA1__USB_TOP_USBH2_DATA_0 IOMUX_PAD(0x6b8, 0x254, 4, 0x9cc, 0, NO_PAD_CTRL) +#define MX35_PAD_SD2_DATA1__GPIO2_3 IOMUX_PAD(0x6b8, 0x254, 5, 0x8cc, 1, NO_PAD_CTRL) + +#define MX35_PAD_SD2_DATA2__ESDHC2_DAT2 IOMUX_PAD(0x6bc, 0x258, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD2_DATA2__UART3_RTS IOMUX_PAD(0x6bc, 0x258, 1, 0x99c, 0, NO_PAD_CTRL) +#define MX35_PAD_SD2_DATA2__CAN1_RXCAN IOMUX_PAD(0x6bc, 0x258, 2, 0x7c8, 1, NO_PAD_CTRL) +#define MX35_PAD_SD2_DATA2__IPU_CSI_D_6 IOMUX_PAD(0x6bc, 0x258, 3, 0x948, 1, NO_PAD_CTRL) +#define MX35_PAD_SD2_DATA2__USB_TOP_USBH2_DATA_1 IOMUX_PAD(0x6bc, 0x258, 4, 0x9d0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD2_DATA2__GPIO2_4 IOMUX_PAD(0x6bc, 0x258, 5, 0x8d0, 1, NO_PAD_CTRL) + +#define MX35_PAD_SD2_DATA3__ESDHC2_DAT3 IOMUX_PAD(0x6c0, 0x25c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD2_DATA3__UART3_CTS IOMUX_PAD(0x6c0, 0x25c, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD2_DATA3__CAN1_TXCAN IOMUX_PAD(0x6c0, 0x25c, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD2_DATA3__IPU_CSI_D_7 IOMUX_PAD(0x6c0, 0x25c, 3, 0x94c, 1, NO_PAD_CTRL) +#define MX35_PAD_SD2_DATA3__USB_TOP_USBH2_DATA_2 IOMUX_PAD(0x6c0, 0x25c, 4, 0x9d4, 0, NO_PAD_CTRL) +#define MX35_PAD_SD2_DATA3__GPIO2_5 IOMUX_PAD(0x6c0, 0x25c, 5, 0x8d4, 1, NO_PAD_CTRL) + +#define MX35_PAD_ATA_CS0__ATA_CS0 IOMUX_PAD(0x6c4, 0x260, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_CS0__CSPI1_SS3 IOMUX_PAD(0x6c4, 0x260, 1, 0x7dc, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_CS0__IPU_DISPB_CS1 IOMUX_PAD(0x6c4, 0x260, 3, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_CS0__GPIO2_6 IOMUX_PAD(0x6c4, 0x260, 5, 0x8d8, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_CS0__IPU_DIAGB_0 IOMUX_PAD(0x6c4, 0x260, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_CS0__ARM11P_TOP_MAX1_HMASTER_0 IOMUX_PAD(0x6c4, 0x260, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_ATA_CS1__ATA_CS1 IOMUX_PAD(0x6c8, 0x264, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_CS1__IPU_DISPB_CS2 IOMUX_PAD(0x6c8, 0x264, 3, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_CS1__CSPI2_SS0 IOMUX_PAD(0x6c8, 0x264, 4, 0x7f0, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_CS1__GPIO2_7 IOMUX_PAD(0x6c8, 0x264, 5, 0x8dc, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_CS1__IPU_DIAGB_1 IOMUX_PAD(0x6c8, 0x264, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_CS1__ARM11P_TOP_MAX1_HMASTER_1 IOMUX_PAD(0x6c8, 0x264, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_ATA_DIOR__ATA_DIOR IOMUX_PAD(0x6cc, 0x268, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DIOR__ESDHC3_DAT0 IOMUX_PAD(0x6cc, 0x268, 1, 0x81c, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DIOR__USB_TOP_USBOTG_DIR IOMUX_PAD(0x6cc, 0x268, 2, 0x9c4, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DIOR__IPU_DISPB_BE0 IOMUX_PAD(0x6cc, 0x268, 3, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DIOR__CSPI2_SS1 IOMUX_PAD(0x6cc, 0x268, 4, 0x7f4, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DIOR__GPIO2_8 IOMUX_PAD(0x6cc, 0x268, 5, 0x8e0, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DIOR__IPU_DIAGB_2 IOMUX_PAD(0x6cc, 0x268, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DIOR__ARM11P_TOP_MAX1_HMASTER_2 IOMUX_PAD(0x6cc, 0x268, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_ATA_DIOW__ATA_DIOW IOMUX_PAD(0x6d0, 0x26c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DIOW__ESDHC3_DAT1 IOMUX_PAD(0x6d0, 0x26c, 1, 0x820, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DIOW__USB_TOP_USBOTG_STP IOMUX_PAD(0x6d0, 0x26c, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DIOW__IPU_DISPB_BE1 IOMUX_PAD(0x6d0, 0x26c, 3, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DIOW__CSPI2_MOSI IOMUX_PAD(0x6d0, 0x26c, 4, 0x7ec, 2, NO_PAD_CTRL) +#define MX35_PAD_ATA_DIOW__GPIO2_9 IOMUX_PAD(0x6d0, 0x26c, 5, 0x8e4, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DIOW__IPU_DIAGB_3 IOMUX_PAD(0x6d0, 0x26c, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DIOW__ARM11P_TOP_MAX1_HMASTER_3 IOMUX_PAD(0x6d0, 0x26c, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_ATA_DMACK__ATA_DMACK IOMUX_PAD(0x6d4, 0x270, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DMACK__ESDHC3_DAT2 IOMUX_PAD(0x6d4, 0x270, 1, 0x824, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DMACK__USB_TOP_USBOTG_NXT IOMUX_PAD(0x6d4, 0x270, 2, 0x9c8, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DMACK__CSPI2_MISO IOMUX_PAD(0x6d4, 0x270, 4, 0x7e8, 2, NO_PAD_CTRL) +#define MX35_PAD_ATA_DMACK__GPIO2_10 IOMUX_PAD(0x6d4, 0x270, 5, 0x86c, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DMACK__IPU_DIAGB_4 IOMUX_PAD(0x6d4, 0x270, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DMACK__ARM11P_TOP_MAX0_HMASTER_0 IOMUX_PAD(0x6d4, 0x270, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_ATA_RESET_B__ATA_RESET_B IOMUX_PAD(0x6d8, 0x274, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_RESET_B__ESDHC3_DAT3 IOMUX_PAD(0x6d8, 0x274, 1, 0x828, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_RESET_B__USB_TOP_USBOTG_DATA_0 IOMUX_PAD(0x6d8, 0x274, 2, 0x9a4, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_RESET_B__IPU_DISPB_SD_D_O IOMUX_PAD(0x6d8, 0x274, 3, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_RESET_B__CSPI2_RDY IOMUX_PAD(0x6d8, 0x274, 4, 0x7e4, 2, NO_PAD_CTRL) +#define MX35_PAD_ATA_RESET_B__GPIO2_11 IOMUX_PAD(0x6d8, 0x274, 5, 0x870, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_RESET_B__IPU_DIAGB_5 IOMUX_PAD(0x6d8, 0x274, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_RESET_B__ARM11P_TOP_MAX0_HMASTER_1 IOMUX_PAD(0x6d8, 0x274, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_ATA_IORDY__ATA_IORDY IOMUX_PAD(0x6dc, 0x278, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_IORDY__ESDHC3_DAT4 IOMUX_PAD(0x6dc, 0x278, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_IORDY__USB_TOP_USBOTG_DATA_1 IOMUX_PAD(0x6dc, 0x278, 2, 0x9a8, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_IORDY__IPU_DISPB_SD_D_IO IOMUX_PAD(0x6dc, 0x278, 3, 0x92c, 3, NO_PAD_CTRL) +#define MX35_PAD_ATA_IORDY__ESDHC2_DAT4 IOMUX_PAD(0x6dc, 0x278, 4, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_IORDY__GPIO2_12 IOMUX_PAD(0x6dc, 0x278, 5, 0x874, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_IORDY__IPU_DIAGB_6 IOMUX_PAD(0x6dc, 0x278, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_IORDY__ARM11P_TOP_MAX0_HMASTER_2 IOMUX_PAD(0x6dc, 0x278, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_ATA_DATA0__ATA_DATA_0 IOMUX_PAD(0x6e0, 0x27c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA0__ESDHC3_DAT5 IOMUX_PAD(0x6e0, 0x27c, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA0__USB_TOP_USBOTG_DATA_2 IOMUX_PAD(0x6e0, 0x27c, 2, 0x9ac, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA0__IPU_DISPB_D12_VSYNC IOMUX_PAD(0x6e0, 0x27c, 3, 0x928, 4, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA0__ESDHC2_DAT5 IOMUX_PAD(0x6e0, 0x27c, 4, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA0__GPIO2_13 IOMUX_PAD(0x6e0, 0x27c, 5, 0x878, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA0__IPU_DIAGB_7 IOMUX_PAD(0x6e0, 0x27c, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA0__ARM11P_TOP_MAX0_HMASTER_3 IOMUX_PAD(0x6e0, 0x27c, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_ATA_DATA1__ATA_DATA_1 IOMUX_PAD(0x6e4, 0x280, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA1__ESDHC3_DAT6 IOMUX_PAD(0x6e4, 0x280, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA1__USB_TOP_USBOTG_DATA_3 IOMUX_PAD(0x6e4, 0x280, 2, 0x9b0, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA1__IPU_DISPB_SD_CLK IOMUX_PAD(0x6e4, 0x280, 3, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA1__ESDHC2_DAT6 IOMUX_PAD(0x6e4, 0x280, 4, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA1__GPIO2_14 IOMUX_PAD(0x6e4, 0x280, 5, 0x87c, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA1__IPU_DIAGB_8 IOMUX_PAD(0x6e4, 0x280, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA1__ARM11P_TOP_TRACE_27 IOMUX_PAD(0x6e4, 0x280, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_ATA_DATA2__ATA_DATA_2 IOMUX_PAD(0x6e8, 0x284, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA2__ESDHC3_DAT7 IOMUX_PAD(0x6e8, 0x284, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA2__USB_TOP_USBOTG_DATA_4 IOMUX_PAD(0x6e8, 0x284, 2, 0x9b4, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA2__IPU_DISPB_SER_RS IOMUX_PAD(0x6e8, 0x284, 3, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA2__ESDHC2_DAT7 IOMUX_PAD(0x6e8, 0x284, 4, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA2__GPIO2_15 IOMUX_PAD(0x6e8, 0x284, 5, 0x880, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA2__IPU_DIAGB_9 IOMUX_PAD(0x6e8, 0x284, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA2__ARM11P_TOP_TRACE_28 IOMUX_PAD(0x6e8, 0x284, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_ATA_DATA3__ATA_DATA_3 IOMUX_PAD(0x6ec, 0x288, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA3__ESDHC3_CLK IOMUX_PAD(0x6ec, 0x288, 1, 0x814, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA3__USB_TOP_USBOTG_DATA_5 IOMUX_PAD(0x6ec, 0x288, 2, 0x9b8, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA3__CSPI2_SCLK IOMUX_PAD(0x6ec, 0x288, 4, 0x7e0, 2, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA3__GPIO2_16 IOMUX_PAD(0x6ec, 0x288, 5, 0x884, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA3__IPU_DIAGB_10 IOMUX_PAD(0x6ec, 0x288, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA3__ARM11P_TOP_TRACE_29 IOMUX_PAD(0x6ec, 0x288, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_ATA_DATA4__ATA_DATA_4 IOMUX_PAD(0x6f0, 0x28c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA4__ESDHC3_CMD IOMUX_PAD(0x6f0, 0x28c, 1, 0x818, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA4__USB_TOP_USBOTG_DATA_6 IOMUX_PAD(0x6f0, 0x28c, 2, 0x9bc, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA4__GPIO2_17 IOMUX_PAD(0x6f0, 0x28c, 5, 0x888, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA4__IPU_DIAGB_11 IOMUX_PAD(0x6f0, 0x28c, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA4__ARM11P_TOP_TRACE_30 IOMUX_PAD(0x6f0, 0x28c, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_ATA_DATA5__ATA_DATA_5 IOMUX_PAD(0x6f4, 0x290, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA5__USB_TOP_USBOTG_DATA_7 IOMUX_PAD(0x6f4, 0x290, 2, 0x9c0, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA5__GPIO2_18 IOMUX_PAD(0x6f4, 0x290, 5, 0x88c, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA5__IPU_DIAGB_12 IOMUX_PAD(0x6f4, 0x290, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA5__ARM11P_TOP_TRACE_31 IOMUX_PAD(0x6f4, 0x290, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_ATA_DATA6__ATA_DATA_6 IOMUX_PAD(0x6f8, 0x294, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA6__CAN1_TXCAN IOMUX_PAD(0x6f8, 0x294, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA6__UART1_DTR IOMUX_PAD(0x6f8, 0x294, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA6__AUDMUX_AUD6_TXD IOMUX_PAD(0x6f8, 0x294, 3, 0x7b4, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA6__GPIO2_19 IOMUX_PAD(0x6f8, 0x294, 5, 0x890, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA6__IPU_DIAGB_13 IOMUX_PAD(0x6f8, 0x294, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_ATA_DATA7__ATA_DATA_7 IOMUX_PAD(0x6fc, 0x298, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA7__CAN1_RXCAN IOMUX_PAD(0x6fc, 0x298, 1, 0x7c8, 2, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA7__UART1_DSR IOMUX_PAD(0x6fc, 0x298, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA7__AUDMUX_AUD6_RXD IOMUX_PAD(0x6fc, 0x298, 3, 0x7b0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA7__GPIO2_20 IOMUX_PAD(0x6fc, 0x298, 5, 0x898, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA7__IPU_DIAGB_14 IOMUX_PAD(0x6fc, 0x298, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_ATA_DATA8__ATA_DATA_8 IOMUX_PAD(0x700, 0x29c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA8__UART3_RTS IOMUX_PAD(0x700, 0x29c, 1, 0x99c, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA8__UART1_RI IOMUX_PAD(0x700, 0x29c, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA8__AUDMUX_AUD6_TXC IOMUX_PAD(0x700, 0x29c, 3, 0x7c0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA8__GPIO2_21 IOMUX_PAD(0x700, 0x29c, 5, 0x89c, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA8__IPU_DIAGB_15 IOMUX_PAD(0x700, 0x29c, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_ATA_DATA9__ATA_DATA_9 IOMUX_PAD(0x704, 0x2a0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA9__UART3_CTS IOMUX_PAD(0x704, 0x2a0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA9__UART1_DCD IOMUX_PAD(0x704, 0x2a0, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA9__AUDMUX_AUD6_TXFS IOMUX_PAD(0x704, 0x2a0, 3, 0x7c4, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA9__GPIO2_22 IOMUX_PAD(0x704, 0x2a0, 5, 0x8a0, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA9__IPU_DIAGB_16 IOMUX_PAD(0x704, 0x2a0, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_ATA_DATA10__ATA_DATA_10 IOMUX_PAD(0x708, 0x2a4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA10__UART3_RXD_MUX IOMUX_PAD(0x708, 0x2a4, 1, 0x9a0, 2, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA10__AUDMUX_AUD6_RXC IOMUX_PAD(0x708, 0x2a4, 3, 0x7b8, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA10__GPIO2_23 IOMUX_PAD(0x708, 0x2a4, 5, 0x8a4, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA10__IPU_DIAGB_17 IOMUX_PAD(0x708, 0x2a4, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_ATA_DATA11__ATA_DATA_11 IOMUX_PAD(0x70c, 0x2a8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA11__UART3_TXD_MUX IOMUX_PAD(0x70c, 0x2a8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA11__AUDMUX_AUD6_RXFS IOMUX_PAD(0x70c, 0x2a8, 3, 0x7bc, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA11__GPIO2_24 IOMUX_PAD(0x70c, 0x2a8, 5, 0x8a8, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA11__IPU_DIAGB_18 IOMUX_PAD(0x70c, 0x2a8, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_ATA_DATA12__ATA_DATA_12 IOMUX_PAD(0x710, 0x2ac, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA12__I2C3_SCL IOMUX_PAD(0x710, 0x2ac, 1, 0x91c, 3, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA12__GPIO2_25 IOMUX_PAD(0x710, 0x2ac, 5, 0x8ac, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA12__IPU_DIAGB_19 IOMUX_PAD(0x710, 0x2ac, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_ATA_DATA13__ATA_DATA_13 IOMUX_PAD(0x714, 0x2b0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA13__I2C3_SDA IOMUX_PAD(0x714, 0x2b0, 1, 0x920, 3, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA13__GPIO2_26 IOMUX_PAD(0x714, 0x2b0, 5, 0x8b0, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA13__IPU_DIAGB_20 IOMUX_PAD(0x714, 0x2b0, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_ATA_DATA14__ATA_DATA_14 IOMUX_PAD(0x718, 0x2b4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA14__IPU_CSI_D_0 IOMUX_PAD(0x718, 0x2b4, 1, 0x930, 2, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA14__KPP_ROW_0 IOMUX_PAD(0x718, 0x2b4, 3, 0x970, 2, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA14__GPIO2_27 IOMUX_PAD(0x718, 0x2b4, 5, 0x8b4, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA14__IPU_DIAGB_21 IOMUX_PAD(0x718, 0x2b4, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_ATA_DATA15__ATA_DATA_15 IOMUX_PAD(0x71c, 0x2b8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA15__IPU_CSI_D_1 IOMUX_PAD(0x71c, 0x2b8, 1, 0x934, 2, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA15__KPP_ROW_1 IOMUX_PAD(0x71c, 0x2b8, 3, 0x974, 2, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA15__GPIO2_28 IOMUX_PAD(0x71c, 0x2b8, 5, 0x8b8, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA15__IPU_DIAGB_22 IOMUX_PAD(0x71c, 0x2b8, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_ATA_INTRQ__ATA_INTRQ IOMUX_PAD(0x720, 0x2bc, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_INTRQ__IPU_CSI_D_2 IOMUX_PAD(0x720, 0x2bc, 1, 0x938, 3, NO_PAD_CTRL) +#define MX35_PAD_ATA_INTRQ__KPP_ROW_2 IOMUX_PAD(0x720, 0x2bc, 3, 0x978, 2, NO_PAD_CTRL) +#define MX35_PAD_ATA_INTRQ__GPIO2_29 IOMUX_PAD(0x720, 0x2bc, 5, 0x8bc, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_INTRQ__IPU_DIAGB_23 IOMUX_PAD(0x720, 0x2bc, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_ATA_BUFF_EN__ATA_BUFFER_EN IOMUX_PAD(0x724, 0x2c0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_BUFF_EN__IPU_CSI_D_3 IOMUX_PAD(0x724, 0x2c0, 1, 0x93c, 3, NO_PAD_CTRL) +#define MX35_PAD_ATA_BUFF_EN__KPP_ROW_3 IOMUX_PAD(0x724, 0x2c0, 3, 0x97c, 2, NO_PAD_CTRL) +#define MX35_PAD_ATA_BUFF_EN__GPIO2_30 IOMUX_PAD(0x724, 0x2c0, 5, 0x8c4, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_BUFF_EN__IPU_DIAGB_24 IOMUX_PAD(0x724, 0x2c0, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_ATA_DMARQ__ATA_DMARQ IOMUX_PAD(0x728, 0x2c4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DMARQ__IPU_CSI_D_4 IOMUX_PAD(0x728, 0x2c4, 1, 0x940, 2, NO_PAD_CTRL) +#define MX35_PAD_ATA_DMARQ__KPP_COL_0 IOMUX_PAD(0x728, 0x2c4, 3, 0x950, 2, NO_PAD_CTRL) +#define MX35_PAD_ATA_DMARQ__GPIO2_31 IOMUX_PAD(0x728, 0x2c4, 5, 0x8c8, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DMARQ__IPU_DIAGB_25 IOMUX_PAD(0x728, 0x2c4, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DMARQ__ECT_CTI_TRIG_IN1_4 IOMUX_PAD(0x728, 0x2c4, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_ATA_DA0__ATA_DA_0 IOMUX_PAD(0x72c, 0x2c8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DA0__IPU_CSI_D_5 IOMUX_PAD(0x72c, 0x2c8, 1, 0x944, 2, NO_PAD_CTRL) +#define MX35_PAD_ATA_DA0__KPP_COL_1 IOMUX_PAD(0x72c, 0x2c8, 3, 0x954, 2, NO_PAD_CTRL) +#define MX35_PAD_ATA_DA0__GPIO3_0 IOMUX_PAD(0x72c, 0x2c8, 5, 0x8e8, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DA0__IPU_DIAGB_26 IOMUX_PAD(0x72c, 0x2c8, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DA0__ECT_CTI_TRIG_IN1_5 IOMUX_PAD(0x72c, 0x2c8, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_ATA_DA1__ATA_DA_1 IOMUX_PAD(0x730, 0x2cc, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DA1__IPU_CSI_D_6 IOMUX_PAD(0x730, 0x2cc, 1, 0x948, 2, NO_PAD_CTRL) +#define MX35_PAD_ATA_DA1__KPP_COL_2 IOMUX_PAD(0x730, 0x2cc, 3, 0x958, 2, NO_PAD_CTRL) +#define MX35_PAD_ATA_DA1__GPIO3_1 IOMUX_PAD(0x730, 0x2cc, 5, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DA1__IPU_DIAGB_27 IOMUX_PAD(0x730, 0x2cc, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DA1__ECT_CTI_TRIG_IN1_6 IOMUX_PAD(0x730, 0x2cc, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_ATA_DA2__ATA_DA_2 IOMUX_PAD(0x734, 0x2d0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DA2__IPU_CSI_D_7 IOMUX_PAD(0x734, 0x2d0, 1, 0x94c, 2, NO_PAD_CTRL) +#define MX35_PAD_ATA_DA2__KPP_COL_3 IOMUX_PAD(0x734, 0x2d0, 3, 0x95c, 2, NO_PAD_CTRL) +#define MX35_PAD_ATA_DA2__GPIO3_2 IOMUX_PAD(0x734, 0x2d0, 5, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DA2__IPU_DIAGB_28 IOMUX_PAD(0x734, 0x2d0, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DA2__ECT_CTI_TRIG_IN1_7 IOMUX_PAD(0x734, 0x2d0, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_MLB_CLK__MLB_MLBCLK IOMUX_PAD(0x738, 0x2d4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_MLB_CLK__GPIO3_3 IOMUX_PAD(0x738, 0x2d4, 5, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_MLB_DAT__MLB_MLBDAT IOMUX_PAD(0x73c, 0x2d8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_MLB_DAT__GPIO3_4 IOMUX_PAD(0x73c, 0x2d8, 5, 0x904, 1, NO_PAD_CTRL) + +#define MX35_PAD_MLB_SIG__MLB_MLBSIG IOMUX_PAD(0x740, 0x2dc, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_MLB_SIG__GPIO3_5 IOMUX_PAD(0x740, 0x2dc, 5, 0x908, 1, NO_PAD_CTRL) + +#define MX35_PAD_FEC_TX_CLK__FEC_TX_CLK IOMUX_PAD(0x744, 0x2e0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_TX_CLK__ESDHC1_DAT4 IOMUX_PAD(0x744, 0x2e0, 1, 0x804, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_TX_CLK__UART3_RXD_MUX IOMUX_PAD(0x744, 0x2e0, 2, 0x9a0, 3, NO_PAD_CTRL) +#define MX35_PAD_FEC_TX_CLK__USB_TOP_USBH2_DIR IOMUX_PAD(0x744, 0x2e0, 3, 0x9ec, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_TX_CLK__CSPI2_MOSI IOMUX_PAD(0x744, 0x2e0, 4, 0x7ec, 3, NO_PAD_CTRL) +#define MX35_PAD_FEC_TX_CLK__GPIO3_6 IOMUX_PAD(0x744, 0x2e0, 5, 0x90c, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_TX_CLK__IPU_DISPB_D12_VSYNC IOMUX_PAD(0x744, 0x2e0, 6, 0x928, 5, NO_PAD_CTRL) +#define MX35_PAD_FEC_TX_CLK__ARM11P_TOP_EVNTBUS_0 IOMUX_PAD(0x744, 0x2e0, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_FEC_RX_CLK__FEC_RX_CLK IOMUX_PAD(0x748, 0x2e4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_RX_CLK__ESDHC1_DAT5 IOMUX_PAD(0x748, 0x2e4, 1, 0x808, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_RX_CLK__UART3_TXD_MUX IOMUX_PAD(0x748, 0x2e4, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_RX_CLK__USB_TOP_USBH2_STP IOMUX_PAD(0x748, 0x2e4, 3, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_RX_CLK__CSPI2_MISO IOMUX_PAD(0x748, 0x2e4, 4, 0x7e8, 3, NO_PAD_CTRL) +#define MX35_PAD_FEC_RX_CLK__GPIO3_7 IOMUX_PAD(0x748, 0x2e4, 5, 0x910, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_RX_CLK__IPU_DISPB_SD_D_I IOMUX_PAD(0x748, 0x2e4, 6, 0x92c, 4, NO_PAD_CTRL) +#define MX35_PAD_FEC_RX_CLK__ARM11P_TOP_EVNTBUS_1 IOMUX_PAD(0x748, 0x2e4, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_FEC_RX_DV__FEC_RX_DV IOMUX_PAD(0x74c, 0x2e8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_RX_DV__ESDHC1_DAT6 IOMUX_PAD(0x74c, 0x2e8, 1, 0x80c, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_RX_DV__UART3_RTS IOMUX_PAD(0x74c, 0x2e8, 2, 0x99c, 2, NO_PAD_CTRL) +#define MX35_PAD_FEC_RX_DV__USB_TOP_USBH2_NXT IOMUX_PAD(0x74c, 0x2e8, 3, 0x9f0, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_RX_DV__CSPI2_SCLK IOMUX_PAD(0x74c, 0x2e8, 4, 0x7e0, 3, NO_PAD_CTRL) +#define MX35_PAD_FEC_RX_DV__GPIO3_8 IOMUX_PAD(0x74c, 0x2e8, 5, 0x914, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_RX_DV__IPU_DISPB_SD_CLK IOMUX_PAD(0x74c, 0x2e8, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_RX_DV__ARM11P_TOP_EVNTBUS_2 IOMUX_PAD(0x74c, 0x2e8, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_FEC_COL__FEC_COL IOMUX_PAD(0x750, 0x2ec, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_COL__ESDHC1_DAT7 IOMUX_PAD(0x750, 0x2ec, 1, 0x810, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_COL__UART3_CTS IOMUX_PAD(0x750, 0x2ec, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_COL__USB_TOP_USBH2_DATA_0 IOMUX_PAD(0x750, 0x2ec, 3, 0x9cc, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_COL__CSPI2_RDY IOMUX_PAD(0x750, 0x2ec, 4, 0x7e4, 3, NO_PAD_CTRL) +#define MX35_PAD_FEC_COL__GPIO3_9 IOMUX_PAD(0x750, 0x2ec, 5, 0x918, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_COL__IPU_DISPB_SER_RS IOMUX_PAD(0x750, 0x2ec, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_COL__ARM11P_TOP_EVNTBUS_3 IOMUX_PAD(0x750, 0x2ec, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_FEC_RDATA0__FEC_RDATA_0 IOMUX_PAD(0x754, 0x2f0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_RDATA0__PWM_PWMO IOMUX_PAD(0x754, 0x2f0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_RDATA0__UART3_DTR IOMUX_PAD(0x754, 0x2f0, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_RDATA0__USB_TOP_USBH2_DATA_1 IOMUX_PAD(0x754, 0x2f0, 3, 0x9d0, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_RDATA0__CSPI2_SS0 IOMUX_PAD(0x754, 0x2f0, 4, 0x7f0, 2, NO_PAD_CTRL) +#define MX35_PAD_FEC_RDATA0__GPIO3_10 IOMUX_PAD(0x754, 0x2f0, 5, 0x8ec, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_RDATA0__IPU_DISPB_CS1 IOMUX_PAD(0x754, 0x2f0, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_RDATA0__ARM11P_TOP_EVNTBUS_4 IOMUX_PAD(0x754, 0x2f0, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_FEC_TDATA0__FEC_TDATA_0 IOMUX_PAD(0x758, 0x2f4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_TDATA0__SPDIF_SPDIF_OUT1 IOMUX_PAD(0x758, 0x2f4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_TDATA0__UART3_DSR IOMUX_PAD(0x758, 0x2f4, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_TDATA0__USB_TOP_USBH2_DATA_2 IOMUX_PAD(0x758, 0x2f4, 3, 0x9d4, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_TDATA0__CSPI2_SS1 IOMUX_PAD(0x758, 0x2f4, 4, 0x7f4, 2, NO_PAD_CTRL) +#define MX35_PAD_FEC_TDATA0__GPIO3_11 IOMUX_PAD(0x758, 0x2f4, 5, 0x8f0, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_TDATA0__IPU_DISPB_CS0 IOMUX_PAD(0x758, 0x2f4, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_TDATA0__ARM11P_TOP_EVNTBUS_5 IOMUX_PAD(0x758, 0x2f4, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_FEC_TX_EN__FEC_TX_EN IOMUX_PAD(0x75c, 0x2f8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_TX_EN__SPDIF_SPDIF_IN1 IOMUX_PAD(0x75c, 0x2f8, 1, 0x998, 3, NO_PAD_CTRL) +#define MX35_PAD_FEC_TX_EN__UART3_RI IOMUX_PAD(0x75c, 0x2f8, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_TX_EN__USB_TOP_USBH2_DATA_3 IOMUX_PAD(0x75c, 0x2f8, 3, 0x9d8, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_TX_EN__GPIO3_12 IOMUX_PAD(0x75c, 0x2f8, 5, 0x8f4, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_TX_EN__IPU_DISPB_PAR_RS IOMUX_PAD(0x75c, 0x2f8, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_TX_EN__ARM11P_TOP_EVNTBUS_6 IOMUX_PAD(0x75c, 0x2f8, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_FEC_MDC__FEC_MDC IOMUX_PAD(0x760, 0x2fc, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_MDC__CAN2_TXCAN IOMUX_PAD(0x760, 0x2fc, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_MDC__UART3_DCD IOMUX_PAD(0x760, 0x2fc, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_MDC__USB_TOP_USBH2_DATA_4 IOMUX_PAD(0x760, 0x2fc, 3, 0x9dc, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_MDC__GPIO3_13 IOMUX_PAD(0x760, 0x2fc, 5, 0x8f8, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_MDC__IPU_DISPB_WR IOMUX_PAD(0x760, 0x2fc, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_MDC__ARM11P_TOP_EVNTBUS_7 IOMUX_PAD(0x760, 0x2fc, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_FEC_MDIO__FEC_MDIO IOMUX_PAD(0x764, 0x300, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_MDIO__CAN2_RXCAN IOMUX_PAD(0x764, 0x300, 1, 0x7cc, 2, NO_PAD_CTRL) +#define MX35_PAD_FEC_MDIO__USB_TOP_USBH2_DATA_5 IOMUX_PAD(0x764, 0x300, 3, 0x9e0, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_MDIO__GPIO3_14 IOMUX_PAD(0x764, 0x300, 5, 0x8fc, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_MDIO__IPU_DISPB_RD IOMUX_PAD(0x764, 0x300, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_MDIO__ARM11P_TOP_EVNTBUS_8 IOMUX_PAD(0x764, 0x300, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_FEC_TX_ERR__FEC_TX_ERR IOMUX_PAD(0x768, 0x304, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_TX_ERR__OWIRE_LINE IOMUX_PAD(0x768, 0x304, 1, 0x990, 2, NO_PAD_CTRL) +#define MX35_PAD_FEC_TX_ERR__SPDIF_SPDIF_EXTCLK IOMUX_PAD(0x768, 0x304, 2, 0x994, 4, NO_PAD_CTRL) +#define MX35_PAD_FEC_TX_ERR__USB_TOP_USBH2_DATA_6 IOMUX_PAD(0x768, 0x304, 3, 0x9e4, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_TX_ERR__GPIO3_15 IOMUX_PAD(0x768, 0x304, 5, 0x900, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_TX_ERR__IPU_DISPB_D0_VSYNC IOMUX_PAD(0x768, 0x304, 6, 0x924, 3, NO_PAD_CTRL) +#define MX35_PAD_FEC_TX_ERR__ARM11P_TOP_EVNTBUS_9 IOMUX_PAD(0x768, 0x304, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_FEC_RX_ERR__FEC_RX_ERR IOMUX_PAD(0x76c, 0x308, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_RX_ERR__IPU_CSI_D_0 IOMUX_PAD(0x76c, 0x308, 1, 0x930, 3, NO_PAD_CTRL) +#define MX35_PAD_FEC_RX_ERR__USB_TOP_USBH2_DATA_7 IOMUX_PAD(0x76c, 0x308, 3, 0x9e8, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_RX_ERR__KPP_COL_4 IOMUX_PAD(0x76c, 0x308, 4, 0x960, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_RX_ERR__GPIO3_16 IOMUX_PAD(0x76c, 0x308, 5, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_RX_ERR__IPU_DISPB_SD_D_IO IOMUX_PAD(0x76c, 0x308, 6, 0x92c, 5, NO_PAD_CTRL) + +#define MX35_PAD_FEC_CRS__FEC_CRS IOMUX_PAD(0x770, 0x30c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_CRS__IPU_CSI_D_1 IOMUX_PAD(0x770, 0x30c, 1, 0x934, 3, NO_PAD_CTRL) +#define MX35_PAD_FEC_CRS__USB_TOP_USBH2_PWR IOMUX_PAD(0x770, 0x30c, 3, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_CRS__KPP_COL_5 IOMUX_PAD(0x770, 0x30c, 4, 0x964, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_CRS__GPIO3_17 IOMUX_PAD(0x770, 0x30c, 5, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_CRS__IPU_FLASH_STROBE IOMUX_PAD(0x770, 0x30c, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_FEC_RDATA1__FEC_RDATA_1 IOMUX_PAD(0x774, 0x310, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_RDATA1__IPU_CSI_D_2 IOMUX_PAD(0x774, 0x310, 1, 0x938, 4, NO_PAD_CTRL) +#define MX35_PAD_FEC_RDATA1__AUDMUX_AUD6_RXC IOMUX_PAD(0x774, 0x310, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_RDATA1__USB_TOP_USBH2_OC IOMUX_PAD(0x774, 0x310, 3, 0x9f4, 2, NO_PAD_CTRL) +#define MX35_PAD_FEC_RDATA1__KPP_COL_6 IOMUX_PAD(0x774, 0x310, 4, 0x968, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_RDATA1__GPIO3_18 IOMUX_PAD(0x774, 0x310, 5, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_RDATA1__IPU_DISPB_BE0 IOMUX_PAD(0x774, 0x310, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_FEC_TDATA1__FEC_TDATA_1 IOMUX_PAD(0x778, 0x314, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_TDATA1__IPU_CSI_D_3 IOMUX_PAD(0x778, 0x314, 1, 0x93c, 4, NO_PAD_CTRL) +#define MX35_PAD_FEC_TDATA1__AUDMUX_AUD6_RXFS IOMUX_PAD(0x778, 0x314, 2, 0x7bc, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_TDATA1__KPP_COL_7 IOMUX_PAD(0x778, 0x314, 4, 0x96c, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_TDATA1__GPIO3_19 IOMUX_PAD(0x778, 0x314, 5, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_TDATA1__IPU_DISPB_BE1 IOMUX_PAD(0x778, 0x314, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_FEC_RDATA2__FEC_RDATA_2 IOMUX_PAD(0x77c, 0x318, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_RDATA2__IPU_CSI_D_4 IOMUX_PAD(0x77c, 0x318, 1, 0x940, 3, NO_PAD_CTRL) +#define MX35_PAD_FEC_RDATA2__AUDMUX_AUD6_TXD IOMUX_PAD(0x77c, 0x318, 2, 0x7b4, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_RDATA2__KPP_ROW_4 IOMUX_PAD(0x77c, 0x318, 4, 0x980, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_RDATA2__GPIO3_20 IOMUX_PAD(0x77c, 0x318, 5, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_FEC_TDATA2__FEC_TDATA_2 IOMUX_PAD(0x780, 0x31c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_TDATA2__IPU_CSI_D_5 IOMUX_PAD(0x780, 0x31c, 1, 0x944, 3, NO_PAD_CTRL) +#define MX35_PAD_FEC_TDATA2__AUDMUX_AUD6_RXD IOMUX_PAD(0x780, 0x31c, 2, 0x7b0, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_TDATA2__KPP_ROW_5 IOMUX_PAD(0x780, 0x31c, 4, 0x984, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_TDATA2__GPIO3_21 IOMUX_PAD(0x780, 0x31c, 5, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_FEC_RDATA3__FEC_RDATA_3 IOMUX_PAD(0x784, 0x320, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_RDATA3__IPU_CSI_D_6 IOMUX_PAD(0x784, 0x320, 1, 0x948, 3, NO_PAD_CTRL) +#define MX35_PAD_FEC_RDATA3__AUDMUX_AUD6_TXC IOMUX_PAD(0x784, 0x320, 2, 0x7c0, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_RDATA3__KPP_ROW_6 IOMUX_PAD(0x784, 0x320, 4, 0x988, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_RDATA3__GPIO3_22 IOMUX_PAD(0x784, 0x320, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_FEC_TDATA3__FEC_TDATA_3 IOMUX_PAD(0x788, 0x324, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_TDATA3__IPU_CSI_D_7 IOMUX_PAD(0x788, 0x324, 1, 0x94c, 3, NO_PAD_CTRL) +#define MX35_PAD_FEC_TDATA3__AUDMUX_AUD6_TXFS IOMUX_PAD(0x788, 0x324, 2, 0x7c4, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_TDATA3__KPP_ROW_7 IOMUX_PAD(0x788, 0x324, 4, 0x98c, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_TDATA3__GPIO3_23 IOMUX_PAD(0x788, 0x324, 5, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_EXT_ARMCLK__CCM_EXT_ARMCLK IOMUX_PAD(0x78c, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_TEST_MODE__TCU_TEST_MODE IOMUX_PAD(0x790, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + + +#endif /* __MACH_IOMUX_MX35_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx50.h b/arch/arm/plat-mxc/include/mach/iomux-mx50.h new file mode 100644 index 00000000..16d26e7e --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/iomux-mx50.h @@ -0,0 +1,979 @@ +/* + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __MACH_IOMUX_MX50_H__ +#define __MACH_IOMUX_MX50_H__ + +#include <mach/iomux-v3.h> + +#define MX50_ELCDIF_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_DSE_HIGH) + +#define MX50_SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_HIGH) + +#define MX50_UART_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_PKE) + +#define MX50_I2C_PAD_CTRL (PAD_CTL_ODE | PAD_CTL_DSE_HIGH | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_HYS) + +#define MX50_USB_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_DSE_HIGH | PAD_CTL_PUS_47K_UP) + +#define MX50_FEC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_ODE | \ + PAD_CTL_DSE_HIGH) + +#define MX50_OWIRE_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_ODE | \ + PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST) + +#define MX50_KEYPAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_HIGH) + +#define MX50_CSPI_SS_PAD (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_DSE_HIGH) + +#define MX50_PAD_KEY_COL0__KEY_COL0 IOMUX_PAD(0x2CC, 0x20, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_COL0__GPIO_4_0 IOMUX_PAD(0x2CC, 0x20, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_COL0__NANDF_CLE IOMUX_PAD(0x2CC, 0x20, 2, 0x0, 0, PAD_CTL_DSE_HIGH) + +#define MX50_PAD_KEY_ROW0__KEY_ROW0 IOMUX_PAD(0x2D0, 0x24, 0, 0x0, 0, MX50_KEYPAD_CTRL) +#define MX50_PAD_KEY_ROW0__GPIO_4_1 IOMUX_PAD(0x2D0, 0x24, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_ROW0__NANDF_ALE IOMUX_PAD(0x2D0, 0x24, 2, 0x0, 0, PAD_CTL_DSE_HIGH) + +#define MX50_PAD_KEY_COL1__KEY_COL1 IOMUX_PAD(0x2D4, 0x28, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_COL1__GPIO_4_2 IOMUX_PAD(0x2D4, 0x28, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_COL1__NANDF_CE0 IOMUX_PAD(0x2D4, 0x28, 2, 0x0, 0, PAD_CTL_DSE_HIGH) + +#define MX50_PAD_KEY_ROW1__KEY_ROW1 IOMUX_PAD(0x2D8, 0x2C, 0, 0x0, 0, MX50_KEYPAD_CTRL) +#define MX50_PAD_KEY_ROW1__GPIO_4_3 IOMUX_PAD(0x2D8, 0x2C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_ROW1__NANDF_CE1 IOMUX_PAD(0x2D8, 0x2C, 2, 0x0, 0, PAD_CTL_DSE_HIGH) + +#define MX50_PAD_KEY_COL2__KEY_COL2 IOMUX_PAD(0x2DC, 0x30, 0, 0x0, 0, MX50_KEYPAD_CTRL) +#define MX50_PAD_KEY_COL2__GPIO_4_4 IOMUX_PAD(0x2DC, 0x30, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_COL2__NANDF_CE2 IOMUX_PAD(0x2DC, 0x30, 2, 0x0, 0, PAD_CTL_DSE_HIGH) + +#define MX50_PAD_KEY_ROW2__KEY_ROW2 IOMUX_PAD(0x2E0, 0x34, 0, 0x0, 0, MX50_KEYPAD_CTRL) +#define MX50_PAD_KEY_ROW2__GPIO_4_5 IOMUX_PAD(0x2E0, 0x34, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_ROW2__NANDF_CE3 IOMUX_PAD(0x2E0, 0x34, 2, 0x0, 0, PAD_CTL_DSE_HIGH) + +#define MX50_PAD_KEY_COL3__KEY_COL3 IOMUX_PAD(0x2E4, 0x38, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_COL3__GPIO_4_6 IOMUX_PAD(0x2E4, 0x38, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_COL3__NANDF_READY IOMUX_PAD(0x2E4, 0x38, 2, 0x7b4, 0, PAD_CTL_PKE | \ + PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) +#define MX50_PAD_KEY_COL3__SDMA_EXT0 IOMUX_PAD(0x2E4, 0x38, 6, 0x7b8, 0, NO_PAD_CTRL) + +#define MX50_PAD_KEY_ROW3__KEY_ROW3 IOMUX_PAD(0x2E8, 0x3C, 0, 0x0, 0, MX50_KEYPAD_CTRL) +#define MX50_PAD_KEY_ROW3__GPIO_4_7 IOMUX_PAD(0x2E8, 0x3C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_ROW3__NANDF_DQS IOMUX_PAD(0x2E8, 0x3C, 2, 0x7b0, 0, PAD_CTL_DSE_HIGH) +#define MX50_PAD_KEY_ROW3__SDMA_EXT1 IOMUX_PAD(0x2E8, 0x3C, 6, 0x7bc, 0, NO_PAD_CTRL) + +#define MX50_PAD_I2C1_SCL__I2C1_SCL IOMUX_PAD(0x2EC, 0x40, IOMUX_CONFIG_SION, 0x0, 0, \ + MX50_I2C_PAD_CTRL) +#define MX50_PAD_I2C1_SCL__GPIO_6_18 IOMUX_PAD(0x2EC, 0x40, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_I2C1_SCL__UART2_TXD IOMUX_PAD(0x2EC, 0x40, 2, 0x0, 0, MX50_UART_PAD_CTRL) + +#define MX50_PAD_I2C1_SDA__I2C1_SDA IOMUX_PAD(0x2F0, 0x44, IOMUX_CONFIG_SION, 0x0, 0, \ + MX50_I2C_PAD_CTRL) +#define MX50_PAD_I2C1_SDA__GPIO_6_19 IOMUX_PAD(0x2F0, 0x44, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_I2C1_SDA__UART2_RXD IOMUX_PAD(0x2F0, 0x44, 2, 0x7cc, 1, MX50_UART_PAD_CTRL) + +#define MX50_PAD_I2C2_SCL__I2C2_SCL IOMUX_PAD(0x2F4, 0x48, IOMUX_CONFIG_SION, 0x0, 0, \ + MX50_I2C_PAD_CTRL) +#define MX50_PAD_I2C2_SCL__GPIO_6_20 IOMUX_PAD(0x2F4, 0x48, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_I2C2_SCL__UART2_CTS IOMUX_PAD(0x2F4, 0x48, 2, 0x0, 0, MX50_UART_PAD_CTRL) +#define MX50_PAD_I2C2_SCL__DCDC_OK IOMUX_PAD(0x2F4, 0x48, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_I2C2_SDA__I2C2_SDA IOMUX_PAD(0x2F8, 0x4C, IOMUX_CONFIG_SION, 0x0, 0, \ + MX50_I2C_PAD_CTRL) +#define MX50_PAD_I2C2_SDA__GPIO_6_21 IOMUX_PAD(0x2F8, 0x4C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_I2C2_SDA__UART2_RTS IOMUX_PAD(0x2F8, 0x4C, 2, 0x7c8, 1, MX50_UART_PAD_CTRL) +#define MX50_PAD_I2C2_SDA__PWRSTABLE IOMUX_PAD(0x2F8, 0x4C, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_I2C3_SCL__I2C3_SCL IOMUX_PAD(0x2FC, 0x50, IOMUX_CONFIG_SION, 0x0, 0, \ + MX50_I2C_PAD_CTRL) +#define MX50_PAD_I2C3_SCL__GPIO_6_22 IOMUX_PAD(0x2FC, 0x50, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_I2C3_SCL__FEC_MDC IOMUX_PAD(0x2FC, 0x50, 2, 0x0, 0, PAD_CTL_DSE_HIGH) +#define MX50_PAD_I2C3_SCL__PMIC_RDY IOMUX_PAD(0x2FC, 0x50, 3, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_I2C3_SCL__GPT_CAPIN1 IOMUX_PAD(0x2FC, 0x50, 5, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_I2C3_SCL__USBOTG_OC IOMUX_PAD(0x2FC, 0x50, 7, 0x7E8, 0, MX50_USB_PAD_CTRL) + +#define MX50_PAD_I2C3_SDA__I2C3_SDA IOMUX_PAD(0x300, 0x54, IOMUX_CONFIG_SION, 0x0, 0, \ + MX50_I2C_PAD_CTRL) +#define MX50_PAD_I2C3_SDA__GPIO_6_23 IOMUX_PAD(0x300, 0x54, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_I2C3_SDA__FEC_MDIO IOMUX_PAD(0x300, 0x54, 2, 0x774, 0, MX50_FEC_PAD_CTRL) +#define MX50_PAD_I2C3_SDA__PWRFAIL_INT IOMUX_PAD(0x300, 0x54, 3, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_I2C3_SDA__ALARM_DEB IOMUX_PAD(0x300, 0x54, 4, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_I2C3_SDA__GPT_CAPIN1 IOMUX_PAD(0x300, 0x54, 5, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_I2C3_SDA__USBOTG_PWR IOMUX_PAD(0x300, 0x54, 7, 0x0, 0, \ + PAD_CTL_PKE | PAD_CTL_DSE_HIGH) + +#define MX50_PAD_PWM1__PWM1_PWMO IOMUX_PAD(0x304, 0x58, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_PWM1__GPIO_6_24 IOMUX_PAD(0x304, 0x58, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_PWM1__USBOTG_OC IOMUX_PAD(0x304, 0x58, 2, 0x7E8, 1, MX50_USB_PAD_CTRL) +#define MX50_PAD_PWM1__GPT_CMPOUT1 IOMUX_PAD(0x304, 0x58, 5, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_PWM2__PWM2_PWMO IOMUX_PAD(0x308, 0x5C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_PWM2__GPIO_6_25 IOMUX_PAD(0x308, 0x5C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_PWM2__USBOTG_PWR IOMUX_PAD(0x308, 0x5C, 2, 0x0, 0, \ + PAD_CTL_PKE | PAD_CTL_DSE_HIGH) +#define MX50_PAD_PWM2__DCDC_PWM IOMUX_PAD(0x308, 0x5C, 4, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_PWM2__GPT_CMPOUT2 IOMUX_PAD(0x308, 0x5C, 5, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_PWM2__ANY_PU_RST IOMUX_PAD(0x308, 0x5C, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_OWIRE__OWIRE IOMUX_PAD(0x30C, 0x60, 0, 0x0, 0, MX50_OWIRE_PAD_CTRL) +#define MX50_PAD_OWIRE__GPIO_6_26 IOMUX_PAD(0x30C, 0x60, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_OWIRE__USBH1_OC IOMUX_PAD(0x30C, 0x60, 2, 0x0, 0, MX50_USB_PAD_CTRL) +#define MX50_PAD_OWIRE__SSI_EXT1_CLK IOMUX_PAD(0x30C, 0x60, 3, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_OWIRE__EPDC_PWRIRQ IOMUX_PAD(0x30C, 0x60, 4, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_OWIRE__GPT_CMPOUT3 IOMUX_PAD(0x30C, 0x60, 5, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EPITO__EPITO IOMUX_PAD(0x310, 0x64, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPITO__GPIO_6_27 IOMUX_PAD(0x310, 0x64, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPITO__USBH1_PWR IOMUX_PAD(0x310, 0x64, 2, 0x0, 0, \ + PAD_CTL_PKE | PAD_CTL_DSE_HIGH) +#define MX50_PAD_EPITO__SSI_EXT2_CLK IOMUX_PAD(0x310, 0x64, 3, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPITO__TOG_EN IOMUX_PAD(0x310, 0x64, 4, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPITO__GPT_CLKIN IOMUX_PAD(0x310, 0x64, 5, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_WDOG__WDOG IOMUX_PAD(0x314, 0x68, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_WDOG__GPIO_6_28 IOMUX_PAD(0x314, 0x68, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_WDOG__WDOG_RST IOMUX_PAD(0x314, 0x68, 2, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_WDOG__XTAL32K IOMUX_PAD(0x314, 0x68, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_SSI_TXFS__SSI_TXFS IOMUX_PAD(0x318, 0x6C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SSI_TXFS__GPIO_6_0 IOMUX_PAD(0x318, 0x6C, 1, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_SSI_TXC__SSI_TXC IOMUX_PAD(0x31C, 0x70, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SSI_TXC__GPIO_6_1 IOMUX_PAD(0x31C, 0x70, 1, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_SSI_TXD__SSI_TXD IOMUX_PAD(0x320, 0x74, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SSI_TXD__GPIO_6_2 IOMUX_PAD(0x320, 0x74, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SSI_TXD__CSPI_RDY IOMUX_PAD(0x320, 0x74, 4, 0x6e8, 0, NO_PAD_CTRL) + +#define MX50_PAD_SSI_RXD__SSI_RXD IOMUX_PAD(0x324, 0x78, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SSI_RXD__GPIO_6_3 IOMUX_PAD(0x324, 0x78, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SSI_RXD__CSPI_SS3 IOMUX_PAD(0x324, 0x78, 4, 0x6f4, 0, MX50_CSPI_SS_PAD) + +#define MX50_PAD_SSI_RXFS__AUD3_RXFS IOMUX_PAD(0x328, 0x7C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SSI_RXFS__GPIO_6_4 IOMUX_PAD(0x328, 0x7C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SSI_RXFS__UART5_TXD IOMUX_PAD(0x328, 0x7C, 2, 0x0, 0, MX50_UART_PAD_CTRL) +#define MX50_PAD_SSI_RXFS__WEIM_D6 IOMUX_PAD(0x328, 0x7C, 3, 0x804, 0, NO_PAD_CTRL) +#define MX50_PAD_SSI_RXFS__CSPI_SS2 IOMUX_PAD(0x328, 0x7C, 4, 0x6f0, 0, MX50_CSPI_SS_PAD) +#define MX50_PAD_SSI_RXFS__FEC_COL IOMUX_PAD(0x328, 0x7C, 5, 0x770, 0, PAD_CTL_DSE_HIGH) +#define MX50_PAD_SSI_RXFS__FEC_MDC IOMUX_PAD(0x328, 0x7C, 6, 0x0, 0, PAD_CTL_DSE_HIGH) + +#define MX50_PAD_SSI_RXC__AUD3_RXC IOMUX_PAD(0x32C, 0x80, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SSI_RXC__GPIO_6_5 IOMUX_PAD(0x32C, 0x80, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SSI_RXC__UART5_RXD IOMUX_PAD(0x32C, 0x80, 2, 0x7e4, 1, MX50_UART_PAD_CTRL) +#define MX50_PAD_SSI_RXC__WEIM_D7 IOMUX_PAD(0x32C, 0x80, 3, 0x808, 0, NO_PAD_CTRL) +#define MX50_PAD_SSI_RXC__CSPI_SS1 IOMUX_PAD(0x32C, 0x80, 4, 0x6ec, 0, MX50_CSPI_SS_PAD) +#define MX50_PAD_SSI_RXC__FEC_RX_CLK IOMUX_PAD(0x32C, 0x80, 5, 0x780, 0, NO_PAD_CTRL) +#define MX50_PAD_SSI_RXC__FEC_MDIO IOMUX_PAD(0x32C, 0x80, 6, 0x774, 1, MX50_FEC_PAD_CTRL) + +#define MX50_PAD_UART1_TXD__UART1_TXD IOMUX_PAD(0x330, 0x84, 0, 0x0, 0, MX50_UART_PAD_CTRL) +#define MX50_PAD_UART1_TXD__GPIO_6_6 IOMUX_PAD(0x330, 0x84, 1, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_UART1_RXD__UART1_RXD IOMUX_PAD(0x334, 0x88, 0, 0x7c4, 1, MX50_UART_PAD_CTRL) +#define MX50_PAD_UART1_RXD__GPIO_6_7 IOMUX_PAD(0x334, 0x88, 1, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_UART1_CTS__UART1_CTS IOMUX_PAD(0x338, 0x8C, 0, 0x0, 0, MX50_UART_PAD_CTRL) +#define MX50_PAD_UART1_CTS__GPIO_6_8 IOMUX_PAD(0x338, 0x8C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_UART1_CTS__UART5_TXD IOMUX_PAD(0x338, 0x8C, 2, 0x0, 0, MX50_UART_PAD_CTRL) +#define MX50_PAD_UART1_CTS__SD4_D4 IOMUX_PAD(0x338, 0x8C, 4, 0x760, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_UART1_CTS__SD4_CMD IOMUX_PAD(0x338, 0x8C, 5, 0x74c, 0, MX50_SD_PAD_CTRL) + +#define MX50_PAD_UART1_RTS__UART1_RTS IOMUX_PAD(0x33C, 0x90, 0, 0x7c0, 1, MX50_UART_PAD_CTRL) +#define MX50_PAD_UART1_RTS__GPIO_6_9 IOMUX_PAD(0x33C, 0x90, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_UART1_RTS__UART5_RXD IOMUX_PAD(0x33C, 0x90, 2, 0x7e4, 3, MX50_UART_PAD_CTRL) +#define MX50_PAD_UART1_RTS__SD4_D5 IOMUX_PAD(0x33C, 0x90, 4, 0x764, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_UART1_RTS__SD4_CLK IOMUX_PAD(0x33C, 0x90, 5, 0x748, 0, MX50_SD_PAD_CTRL) + +#define MX50_PAD_UART2_TXD__UART2_TXD IOMUX_PAD(0x340, 0x94, 0, 0x0, 0, MX50_UART_PAD_CTRL) +#define MX50_PAD_UART2_TXD__GPIO_6_10 IOMUX_PAD(0x340, 0x94, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_UART2_TXD__SD4_D6 IOMUX_PAD(0x340, 0x94, 4, 0x768, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_UART2_TXD__SD4_D4 IOMUX_PAD(0x340, 0x94, 5, 0x760, 1, MX50_SD_PAD_CTRL) + +#define MX50_PAD_UART2_RXD__UART2_RXD IOMUX_PAD(0x344, 0x98, 0, 0x7cc, 3, MX50_UART_PAD_CTRL) +#define MX50_PAD_UART2_RXD__GPIO_6_11 IOMUX_PAD(0x344, 0x98, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_UART2_RXD__SD4_D7 IOMUX_PAD(0x344, 0x98, 4, 0x76c, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_UART2_RXD__SD4_D5 IOMUX_PAD(0x344, 0x98, 5, 0x764, 1, MX50_SD_PAD_CTRL) + +#define MX50_PAD_UART2_CTS__UART2_CTS IOMUX_PAD(0x348, 0x9C, 0, 0x0, 0, MX50_UART_PAD_CTRL) +#define MX50_PAD_UART2_CTS__GPIO_6_12 IOMUX_PAD(0x348, 0x9C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_UART2_CTS__SD4_CMD IOMUX_PAD(0x348, 0x9C, 4, 0x74c, 1, MX50_SD_PAD_CTRL) +#define MX50_PAD_UART2_CTS__SD4_D6 IOMUX_PAD(0x348, 0x9C, 5, 0x768, 1, MX50_SD_PAD_CTRL) + +#define MX50_PAD_UART2_RTS__UART2_RTS IOMUX_PAD(0x34C, 0xA0, 0, 0x7c8, 3, MX50_UART_PAD_CTRL) +#define MX50_PAD_UART2_RTS__GPIO_6_13 IOMUX_PAD(0x34C, 0xA0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_UART2_RTS__SD4_CLK IOMUX_PAD(0x34C, 0xA0, 4, 0x748, 1, MX50_SD_PAD_CTRL) +#define MX50_PAD_UART2_RTS__SD4_D7 IOMUX_PAD(0x34C, 0xA0, 5, 0x76c, 1, MX50_SD_PAD_CTRL) + +#define MX50_PAD_UART3_TXD__UART3_TXD IOMUX_PAD(0x350, 0xA4, 0, 0x0, 0, MX50_UART_PAD_CTRL) +#define MX50_PAD_UART3_TXD__GPIO_6_14 IOMUX_PAD(0x350, 0xA4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_UART3_TXD__SD1_D4 IOMUX_PAD(0x350, 0xA4, 3, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_UART3_TXD__SD4_D0 IOMUX_PAD(0x350, 0xA4, 4, 0x750, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_UART3_TXD__SD2_WP IOMUX_PAD(0x350, 0xA4, 5, 0x744, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_UART3_TXD__WEIM_D12 IOMUX_PAD(0x350, 0xA4, 6, 0x81c, 0, NO_PAD_CTRL) + +#define MX50_PAD_UART3_RXD__UART3_RXD IOMUX_PAD(0x354, 0xA8, 0, 0x7d4, 1, MX50_UART_PAD_CTRL) +#define MX50_PAD_UART3_RXD__GPIO_6_15 IOMUX_PAD(0x354, 0xA8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_UART3_RXD__SD1_D5 IOMUX_PAD(0x354, 0xA8, 3, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_UART3_RXD__SD4_D1 IOMUX_PAD(0x354, 0xA8, 4, 0x754, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_UART3_RXD__SD2_CD IOMUX_PAD(0x354, 0xA8, 5, 0x740, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_UART3_RXD__WEIM_D13 IOMUX_PAD(0x354, 0xA8, 6, 0x820, 0, NO_PAD_CTRL) + +#define MX50_PAD_UART4_TXD__UART4_TXD IOMUX_PAD(0x358, 0xAC, 0, 0x0, 0, MX50_UART_PAD_CTRL) +#define MX50_PAD_UART4_TXD__GPIO_6_16 IOMUX_PAD(0x358, 0xAC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_UART4_TXD__UART3_CTS IOMUX_PAD(0x358, 0xAC, 2, 0x0, 0, MX50_UART_PAD_CTRL) +#define MX50_PAD_UART4_TXD__SD1_D6 IOMUX_PAD(0x358, 0xAC, 3, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_UART4_TXD__SD4_D2 IOMUX_PAD(0x358, 0xAC, 4, 0x758, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_UART4_TXD__SD2_LCTL IOMUX_PAD(0x358, 0xAC, 5, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_UART4_TXD__WEIM_D14 IOMUX_PAD(0x358, 0xAC, 6, 0x824, 0, NO_PAD_CTRL) + +#define MX50_PAD_UART4_RXD__UART4_RXD IOMUX_PAD(0x35C, 0xB0, 0, 0x7dc, 1, MX50_UART_PAD_CTRL) +/* Remove the default keeper from this pad (for EPD PMIC intr) */ +#define MX50_PAD_UART4_RXD__GPIO_6_17 IOMUX_PAD(0x35C, 0xB0, 1, 0x0, 0, 0) +#define MX50_PAD_UART4_RXD__UART3_RTS IOMUX_PAD(0x35C, 0xB0, 2, 0x7d0, 1, MX50_UART_PAD_CTRL) +#define MX50_PAD_UART4_RXD__SD1_D7 IOMUX_PAD(0x35C, 0xB0, 3, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_UART4_RXD__SD4_D3 IOMUX_PAD(0x35C, 0xB0, 4, 0x75c, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_UART4_RXD__SD1_LCTL IOMUX_PAD(0x35C, 0xB0, 5, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_UART4_RXD__WEIM_D15 IOMUX_PAD(0x35C, 0xB0, 6, 0x828, 0, NO_PAD_CTRL) + +#define MX50_PAD_CSPI_SCLK__CSPI_SCLK IOMUX_PAD(0x360, 0xB4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_CSPI_SCLK__GPIO_4_8 IOMUX_PAD(0x360, 0xB4, 1, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_CSPI_MOSI__CSPI_MOSI IOMUX_PAD(0x364, 0xB8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_CSPI_MOSI__GPIO_4_9 IOMUX_PAD(0x364, 0xB8, 1, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_CSPI_MISO__CSPI_MISO IOMUX_PAD(0x368, 0xBC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_CSPI_MISO__GPIO_4_10 IOMUX_PAD(0x368, 0xBC, 1, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_CSPI_SS0__CSPI_SS0 IOMUX_PAD(0x36C, 0xC0, 0, 0x0, 0, MX50_CSPI_SS_PAD) +#define MX50_PAD_CSPI_SS0__GPIO_4_11 IOMUX_PAD(0x36C, 0xC0, 1, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_ECSPI1_SCLK__ECSPI1_SCLK IOMUX_PAD(0x370, 0xC4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI1_SCLK__GPIO_4_12 IOMUX_PAD(0x370, 0xC4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI1_SCLK__CSPI_RDY IOMUX_PAD(0x370, 0xC4, 2, 0x6e8, 1, NO_PAD_CTRL) +#define MX50_PAD_ECSPI1_SCLK__ECSPI2_RDY IOMUX_PAD(0x370, 0xC4, 3, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI1_SCLK__UART3_RTS IOMUX_PAD(0x370, 0xC4, 4, 0x7d0, 2, MX50_UART_PAD_CTRL) +#define MX50_PAD_ECSPI1_SCLK__EPDC_SDCE6 IOMUX_PAD(0x370, 0xC4, 5, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI1_SCLK__WEIM_D8 IOMUX_PAD(0x370, 0xC4, 7, 0x80c, 0, NO_PAD_CTRL) + +#define MX50_PAD_ECSPI1_MOSI__ECSPI1_MOSI IOMUX_PAD(0x374, 0xC8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI1_MOSI__GPIO_4_13 IOMUX_PAD(0x374, 0xC8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI1_MOSI__CSPI_SS1 IOMUX_PAD(0x374, 0xC8, 2, 0x6ec, 1, MX50_CSPI_SS_PAD) +#define MX50_PAD_ECSPI1_MOSI__ECSPI2_SS1 IOMUX_PAD(0x374, 0xC8, 3, 0x0, 0, MX50_CSPI_SS_PAD) +#define MX50_PAD_ECSPI1_MOSI__UART3_CTS IOMUX_PAD(0x374, 0xC8, 4, 0x0, 0, MX50_UART_PAD_CTRL) +#define MX50_PAD_ECSPI1_MOSI__EPDC_SDCE7 IOMUX_PAD(0x374, 0xC8, 5, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI1_MOSI__WEIM_D9 IOMUX_PAD(0x374, 0xC8, 7, 0x810, 0, NO_PAD_CTRL) + +#define MX50_PAD_ECSPI1_MISO__ECSPI1_MISO IOMUX_PAD(0x378, 0xCC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI1_MISO__GPIO_4_14 IOMUX_PAD(0x378, 0xCC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI1_MISO__CSPI_SS2 IOMUX_PAD(0x378, 0xCC, 2, 0x6f0, 1, MX50_CSPI_SS_PAD) +#define MX50_PAD_ECSPI1_MISO__ECSPI2_SS2 IOMUX_PAD(0x378, 0xCC, 3, 0x0, 0, MX50_CSPI_SS_PAD) +#define MX50_PAD_ECSPI1_MISO__UART4_RTS IOMUX_PAD(0x378, 0xCC, 4, 0x7d8, 0, MX50_UART_PAD_CTRL) +#define MX50_PAD_ECSPI1_MISO__EPDC_SDCE8 IOMUX_PAD(0x378, 0xCC, 5, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI1_MISO__WEIM_D10 IOMUX_PAD(0x378, 0xCC, 7, 0x814, 0, NO_PAD_CTRL) + +#define MX50_PAD_ECSPI1_SS0__ECSPI1_SS0 IOMUX_PAD(0x37C, 0xD0, 0, 0x0, 0, MX50_CSPI_SS_PAD) +#define MX50_PAD_ECSPI1_SS0__GPIO_4_15 IOMUX_PAD(0x37C, 0xD0, 1, 0x0, 0, PAD_CTL_PUS_100K_UP) +#define MX50_PAD_ECSPI1_SS0__CSPI_SS3 IOMUX_PAD(0x37C, 0xD0, 2, 0x6f4, 1, MX50_CSPI_SS_PAD) +#define MX50_PAD_ECSPI1_SS0__ECSPI2_SS3 IOMUX_PAD(0x37C, 0xD0, 3, 0x0, 0, MX50_CSPI_SS_PAD) +#define MX50_PAD_ECSPI1_SS0__UART4_CTS IOMUX_PAD(0x37C, 0xD0, 4, 0x0, 0, MX50_UART_PAD_CTRL) +#define MX50_PAD_ECSPI1_SS0__EPDC_SDCE9 IOMUX_PAD(0x37C, 0xD0, 5, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI1_SS0__WEIM_D11 IOMUX_PAD(0x37C, 0xD0, 7, 0x818, 0, NO_PAD_CTRL) + +#define MX50_PAD_ECSPI2_SCLK__ECSPI2_SCLK IOMUX_PAD(0x380, 0xD4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_SCLK__GPIO_4_16 IOMUX_PAD(0x380, 0xD4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_SCLK__ELCDIF_WR IOMUX_PAD(0x380, 0xD4, 2, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_SCLK__ECSPI1_RDY IOMUX_PAD(0x380, 0xD4, 3, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_SCLK__UART5_RTS IOMUX_PAD(0x380, 0xD4, 4, 0x7e0, 0, MX50_UART_PAD_CTRL) +#define MX50_PAD_ECSPI2_SCLK__ELCDIF_DOTCLK IOMUX_PAD(0x380, 0xD4, 5, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_SCLK__NANDF_CEN4 IOMUX_PAD(0x380, 0xD4, 6, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_SCLK__WEIM_D8 IOMUX_PAD(0x380, 0xD4, 7, 0x80c, 1, NO_PAD_CTRL) + +#define MX50_PAD_ECSPI2_MOSI__ECSPI2_MOSI IOMUX_PAD(0x384, 0xD8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_MOSI__GPIO_4_17 IOMUX_PAD(0x384, 0xD8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_MOSI__ELCDIF_RD IOMUX_PAD(0x384, 0xD8, 2, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_MOSI__ECSPI1_SS1 IOMUX_PAD(0x384, 0xD8, 3, 0x0, 0, MX50_CSPI_SS_PAD) +#define MX50_PAD_ECSPI2_MOSI__UART5_CTS IOMUX_PAD(0x384, 0xD8, 4, 0x0, 0, MX50_UART_PAD_CTRL) +#define MX50_PAD_ECSPI2_MOSI__ELCDIF_EN IOMUX_PAD(0x384, 0xD8, 5, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_MOSI__NANDF_CEN5 IOMUX_PAD(0x384, 0xD8, 6, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_MOSI__WEIM_D9 IOMUX_PAD(0x384, 0xD8, 7, 0x810, 1, NO_PAD_CTRL) + +#define MX50_PAD_ECSPI2_MISO__ECSPI2_MISO IOMUX_PAD(0x388, 0xDC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_MISO__GPIO_4_18 IOMUX_PAD(0x388, 0xDC, 1, 0x0, 0, PAD_CTL_PUS_100K_UP) +#define MX50_PAD_ECSPI2_MISO__ELCDIF_RS IOMUX_PAD(0x388, 0xDC, 2, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_MISO__ECSPI1_SS2 IOMUX_PAD(0x388, 0xDC, 3, 0x0, 0, MX50_CSPI_SS_PAD) +#define MX50_PAD_ECSPI2_MISO__UART5_TXD IOMUX_PAD(0x388, 0xDC, 4, 0x0, 0, MX50_UART_PAD_CTRL) +#define MX50_PAD_ECSPI2_MISO__ELCDIF_VSYNC IOMUX_PAD(0x388, 0xDC, 5, 0x73c, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_MISO__NANDF_CEN6 IOMUX_PAD(0x388, 0xDC, 6, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_MISO__WEIM_D10 IOMUX_PAD(0x388, 0xDC, 7, 0x814, 1, NO_PAD_CTRL) + +#define MX50_PAD_ECSPI2_SS0__ECSPI2_SS0 IOMUX_PAD(0x38C, 0xE0, 0, 0x0, 0, MX50_CSPI_SS_PAD) +#define MX50_PAD_ECSPI2_SS0__GPIO_4_19 IOMUX_PAD(0x38C, 0xE0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_SS0__ELCDIF_CS IOMUX_PAD(0x38C, 0xE0, 2, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_SS0__ECSPI1_SS3 IOMUX_PAD(0x38C, 0xE0, 3, 0x0, 0, MX50_CSPI_SS_PAD) +#define MX50_PAD_ECSPI2_SS0__UART5_RXD IOMUX_PAD(0x38C, 0xE0, 4, 0x7e4, 5, MX50_UART_PAD_CTRL) +#define MX50_PAD_ECSPI2_SS0__ELCDIF_HSYNC IOMUX_PAD(0x38C, 0xE0, 5, 0x6f8, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_SS0__NANDF_CEN7 IOMUX_PAD(0x38C, 0xE0, 6, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_SS0__WEIM_D11 IOMUX_PAD(0x38C, 0xE0, 7, 0x818, 1, NO_PAD_CTRL) + +#define MX50_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x390, 0xE4, IOMUX_CONFIG_SION, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD1_CLK__GPIO_5_0 IOMUX_PAD(0x390, 0xE4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD1_CLK__CLKO IOMUX_PAD(0x390, 0xE4, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x394, 0xE8, IOMUX_CONFIG_SION, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD1_CMD__GPIO_5_1 IOMUX_PAD(0x394, 0xE8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD1_CMD__CLKO2 IOMUX_PAD(0x394, 0xE8, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_SD1_D0__SD1_D0 IOMUX_PAD(0x398, 0xEC, 0, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD1_D0__GPIO_5_2 IOMUX_PAD(0x398, 0xEC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD1_D0__PLL1_BYP IOMUX_PAD(0x398, 0xEC, 7, 0x6dc, 0, NO_PAD_CTRL) + +#define MX50_PAD_SD1_D1__SD1_D1 IOMUX_PAD(0x39C, 0xF0, 0, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD1_D1__GPIO_5_3 IOMUX_PAD(0x39C, 0xF0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD1_D1__PLL2_BYP IOMUX_PAD(0x39C, 0xF0, 7, 0x6e0, 0, NO_PAD_CTRL) + +#define MX50_PAD_SD1_D2__SD1_D2 IOMUX_PAD(0x3A0, 0xF4, 0, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD1_D2__GPIO_5_4 IOMUX_PAD(0x3A0, 0xF4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD1_D2__PLL3_BYP IOMUX_PAD(0x3A0, 0xF4, 7, 0x6e4, 0, NO_PAD_CTRL) + +#define MX50_PAD_SD1_D3__SD1_D3 IOMUX_PAD(0x3A4, 0xF8, 0, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD1_D3__GPIO_5_5 IOMUX_PAD(0x3A4, 0xF8, 1, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_SD2_CLK__SD2_CLK IOMUX_PAD(0x3A8, 0xFC, IOMUX_CONFIG_SION, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD2_CLK__GPIO_5_6 IOMUX_PAD(0x3A8, 0xFC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_CLK__MSHC_SCLK IOMUX_PAD(0x3A8, 0xFC, 2, 0x0, 0, MX50_SD_PAD_CTRL) + +#define MX50_PAD_SD2_CMD__SD2_CMD IOMUX_PAD(0x3AC, 0x100, IOMUX_CONFIG_SION, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD2_CMD__GPIO_5_7 IOMUX_PAD(0x3AC, 0x100, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_CMD__MSHC_BS IOMUX_PAD(0x3AC, 0x100, 2, 0x0, 0, MX50_SD_PAD_CTRL) + +#define MX50_PAD_SD2_D0__SD2_D0 IOMUX_PAD(0x3B0, 0x104, 0, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD2_D0__GPIO_5_8 IOMUX_PAD(0x3B0, 0x104, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D0__MSHC_D0 IOMUX_PAD(0x3B0, 0x104, 2, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD2_D0__KEY_COL4 IOMUX_PAD(0x3B0, 0x104, 3, 0x790, 0, NO_PAD_CTRL) + +#define MX50_PAD_SD2_D1__SD2_D1 IOMUX_PAD(0x3B4, 0x108, 0, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD2_D1__GPIO_5_9 IOMUX_PAD(0x3B4, 0x108, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D1__MSHC_D1 IOMUX_PAD(0x3B4, 0x108, 2, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD2_D1__KEY_ROW4 IOMUX_PAD(0x3B4, 0x108, 3, 0x7a0, 0, NO_PAD_CTRL) + +#define MX50_PAD_SD2_D2__SD2_D2 IOMUX_PAD(0x3B8, 0x10C, 0, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD2_D2__GPIO_5_10 IOMUX_PAD(0x3B8, 0x10C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D2__MSHC_D2 IOMUX_PAD(0x3B8, 0x10C, 2, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD2_D2__KEY_COL5 IOMUX_PAD(0x3B8, 0x10C, 3, 0x794, 0, NO_PAD_CTRL) + +#define MX50_PAD_SD2_D3__SD2_D3 IOMUX_PAD(0x3BC, 0x110, 0, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD2_D3__GPIO_5_11 IOMUX_PAD(0x3BC, 0x110, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D3__MSHC_D3 IOMUX_PAD(0x3BC, 0x110, 2, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD2_D3__KEY_ROW5 IOMUX_PAD(0x3BC, 0x110, 3, 0x7a4, 0, NO_PAD_CTRL) + +#define MX50_PAD_SD2_D4__SD2_D4 IOMUX_PAD(0x3C0, 0x114, 0, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD2_D4__GPIO_5_12 IOMUX_PAD(0x3C0, 0x114, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D4__AUD4_RXFS IOMUX_PAD(0x3C0, 0x114, 2, 0x6d0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D4__KEY_COL6 IOMUX_PAD(0x3C0, 0x114, 3, 0x798, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D4__WEIM_D0 IOMUX_PAD(0x3C0, 0x114, 4, 0x7ec, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D4__CCM_OUT0 IOMUX_PAD(0x3C0, 0x114, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_SD2_D5__SD2_D5 IOMUX_PAD(0x3C4, 0x118, 0, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD2_D5__GPIO_5_13 IOMUX_PAD(0x3C4, 0x118, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D5__AUD4_RXC IOMUX_PAD(0x3C4, 0x118, 2, 0x6cc, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D5__KEY_ROW6 IOMUX_PAD(0x3C4, 0x118, 3, 0x7a8, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D5__WEIM_D1 IOMUX_PAD(0x3C4, 0x118, 4, 0x7f0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D5__CCM_OUT1 IOMUX_PAD(0x3C4, 0x118, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_SD2_D6__SD2_D6 IOMUX_PAD(0x3C8, 0x11C, 0, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD2_D6__GPIO_5_14 IOMUX_PAD(0x3C8, 0x11C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D6__AUD4_RXD IOMUX_PAD(0x3C8, 0x11C, 2, 0x6c4, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D6__KEY_COL7 IOMUX_PAD(0x3C8, 0x11C, 3, 0x79c, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D6__WEIM_D2 IOMUX_PAD(0x3C8, 0x11C, 4, 0x7f4, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D6__CCM_OUT2 IOMUX_PAD(0x3C8, 0x11C, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_SD2_D7__SD2_D7 IOMUX_PAD(0x3CC, 0x120, 0, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD2_D7__GPIO_5_15 IOMUX_PAD(0x3CC, 0x120, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D7__AUD4_TXFS IOMUX_PAD(0x3CC, 0x120, 2, 0x6d8, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D7__KEY_ROW7 IOMUX_PAD(0x3CC, 0x120, 3, 0x7ac, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D7__WEIM_D3 IOMUX_PAD(0x3CC, 0x120, 4, 0x7f8, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D7__CCM_STOP IOMUX_PAD(0x3CC, 0x120, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_SD2_WP__SD2_WP IOMUX_PAD(0x3D0, 0x124, 0, 0x744, 1, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD2_WP__GPIO_5_16 IOMUX_PAD(0x3D0, 0x124, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_WP__AUD4_TXD IOMUX_PAD(0x3D0, 0x124, 2, 0x6c8, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_WP__WEIM_D4 IOMUX_PAD(0x3D0, 0x124, 4, 0x7fc, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_WP__CCM_WAIT IOMUX_PAD(0x3D0, 0x124, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_SD2_CD__SD2_CD IOMUX_PAD(0x3D4, 0x128, 0, 0x740, 1, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD2_CD__GPIO_5_17 IOMUX_PAD(0x3D4, 0x128, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_CD__AUD4_TXC IOMUX_PAD(0x3D4, 0x128, 2, 0x6d4, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_CD__WEIM_D5 IOMUX_PAD(0x3D4, 0x128, 4, 0x800, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_CD__CCM_REF_EN IOMUX_PAD(0x3D4, 0x128, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_PMIC_ON_REQ__PMIC_ON_REQ IOMUX_PAD(0x3D8, 0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_PMIC_STBY_REQ__PMIC_STBY_REQ IOMUX_PAD(0x3DC, 0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_PMIC_PORT_B__PMIC_PORT_B IOMUX_PAD(0x3E0, 0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_PMIC_BOOT_MODE1__PMIC_BOOT_MODE1 IOMUX_PAD(0x3E4, 0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_PMIC_RESET_IN_B__PMIC_RESET_IN_B IOMUX_PAD(0x3E8, 0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_PMIC_BOOT_MODE0__PMIC_BOOT_MODE0 IOMUX_PAD(0x3EC, 0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_PMIC_TEST_MODE__PMIC_TEST_MODE IOMUX_PAD(0x3F0, 0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_PMIC_JTAG_TMS__PMIC_JTAG_TMS IOMUX_PAD(0x3F4, 0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_PMIC_JTAG_MOD__PMIC_JTAG_MOD IOMUX_PAD(0x3F8, 0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_PMIC_JTAG_TRSTB__PMIC_JTAG_TRSTB IOMUX_PAD(0x3FC, 0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_PMIC_JTAG_TDI__PMIC_JTAG_TDI IOMUX_PAD(0x400, 0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_PMIC_JTAG_TCK__PMIC_JTAG_TCK IOMUX_PAD(0x404, 0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_PMIC_JTAG_TDO__PMIC_JTAG_TDO IOMUX_PAD(0x408, 0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_DISP_D0__DISP_D0 IOMUX_PAD(0x40C, 0x12C, 0, 0x6fc, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_D0__GPIO_2_0 IOMUX_PAD(0x40C, 0x12C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D0__FEC_TXCLK IOMUX_PAD(0x40C, 0x12C, 2, 0x78c, 0, PAD_CTL_HYS | PAD_CTL_PKE) + +#define MX50_PAD_DISP_D1__DISP_D1 IOMUX_PAD(0x410, 0x130, 0, 0x700, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_D1__GPIO_2_1 IOMUX_PAD(0x410, 0x130, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D1__FEC_RX_ER IOMUX_PAD(0x410, 0x130, 2, 0x788, 0, PAD_CTL_HYS | PAD_CTL_PKE) +#define MX50_PAD_DISP_D1__WEIM_A17 IOMUX_PAD(0x410, 0x130, 3, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_DISP_D2__DISP_D2 IOMUX_PAD(0x414, 0x134, 0, 0x704, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_D2__GPIO_2_2 IOMUX_PAD(0x414, 0x134, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D2__FEC_RX_DV IOMUX_PAD(0x414, 0x134, 2, 0x784, 0, PAD_CTL_HYS | PAD_CTL_PKE) +#define MX50_PAD_DISP_D2__WEIM_A18 IOMUX_PAD(0x414, 0x134, 3, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_DISP_D3__DISP_D3 IOMUX_PAD(0x418, 0x138, 0, 0x708, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_D3__GPIO_2_3 IOMUX_PAD(0x418, 0x138, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D3__FEC_RXD1 IOMUX_PAD(0x418, 0x138, 2, 0x77C, 0, PAD_CTL_HYS | PAD_CTL_PKE) +#define MX50_PAD_DISP_D3__WEIM_A19 IOMUX_PAD(0x418, 0x138, 3, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D3__FEC_COL IOMUX_PAD(0x418, 0x138, 4, 0x770, 1, NO_PAD_CTRL) + +#define MX50_PAD_DISP_D4__DISP_D4 IOMUX_PAD(0x41C, 0x13C, 0, 0x70c, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_D4__GPIO_2_4 IOMUX_PAD(0x41C, 0x13C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D4__FEC_RXD0 IOMUX_PAD(0x41C, 0x13C, 2, 0x778, 0, PAD_CTL_HYS | PAD_CTL_PKE) +#define MX50_PAD_DISP_D4__WEIM_A20 IOMUX_PAD(0x41C, 0x13C, 3, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_DISP_D5__DISP_D5 IOMUX_PAD(0x420, 0x140, 0, 0x710, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_D5__GPIO_2_5 IOMUX_PAD(0x420, 0x140, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D5__FEC_TX_EN IOMUX_PAD(0x420, 0x140, 2, 0x0, 0, PAD_CTL_DSE_HIGH) +#define MX50_PAD_DISP_D5__WEIM_A21 IOMUX_PAD(0x420, 0x140, 3, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_DISP_D6__DISP_D6 IOMUX_PAD(0x424, 0x144, 0, 0x714, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_D6__GPIO_2_6 IOMUX_PAD(0x424, 0x144, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D6__FEC_TXD1 IOMUX_PAD(0x424, 0x144, 2, 0x0, 0, PAD_CTL_DSE_HIGH) +#define MX50_PAD_DISP_D6__WEIM_A22 IOMUX_PAD(0x424, 0x144, 3, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D6__FEC_RX_CLK IOMUX_PAD(0x424, 0x144, 4, 0x780, 1, NO_PAD_CTRL) + +#define MX50_PAD_DISP_D7__DISP_D7 IOMUX_PAD(0x428, 0x148, 0, 0x718, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_D7__GPIO_2_7 IOMUX_PAD(0x428, 0x148, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D7__FEC_TXD0 IOMUX_PAD(0x428, 0x148, 2, 0x0, 0, PAD_CTL_DSE_HIGH) +#define MX50_PAD_DISP_D7__WEIM_A23 IOMUX_PAD(0x428, 0x148, 3, 0x0, 0, NO_PAD_CTRL) + + +#define MX50_PAD_DISP_WR__ELCDIF_WR IOMUX_PAD(0x42C, 0x14C, 0, 0x0, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_WR__GPIO_2_16 IOMUX_PAD(0x42C, 0x14C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_WR__ELCDIF_PIXCLK IOMUX_PAD(0x42C, 0x14C, 2, 0x0, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_WR__WEIM_A24 IOMUX_PAD(0x42C, 0x14C, 3, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_DISP_RD__ELCDIF_RD IOMUX_PAD(0x430, 0x150, 0, 0x0, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_RD__GPIO_2_19 IOMUX_PAD(0x430, 0x150, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_RD__ELCDIF_EN IOMUX_PAD(0x430, 0x150, 2, 0x0, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_RD__WEIM_A25 IOMUX_PAD(0x430, 0x150, 3, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_DISP_RS__ELCDIF_RS IOMUX_PAD(0x434, 0x154, 0, 0x0, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_RS__GPIO_2_17 IOMUX_PAD(0x434, 0x154, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_RS__ELCDIF_VSYNC IOMUX_PAD(0x434, 0x154, 2, 0x73c, 1, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_RS__WEIM_A26 IOMUX_PAD(0x434, 0x154, 3, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_DISP_CS__ELCDIF_CS IOMUX_PAD(0x438, 0x158, 0, 0x0, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_CS__GPIO_2_21 IOMUX_PAD(0x438, 0x158, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_CS__ELCDIF_HSYNC IOMUX_PAD(0x438, 0x158, 2, 0x6f8, 1, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_CS__WEIM_A27 IOMUX_PAD(0x438, 0x158, 3, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_CS__WEIM_CS3 IOMUX_PAD(0x438, 0x158, 4, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_DISP_BUSY__ELCDIF_HSYNC IOMUX_PAD(0x43C, 0x15C, 0, 0x6f8, 2, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_BUSY__GPIO_2_18 IOMUX_PAD(0x43C, 0x15C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_BUSY__WEIM_CS3 IOMUX_PAD(0x43C, 0x15C, 3, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_DISP_RESET__ELCDIF_RST IOMUX_PAD(0x440, 0x160, 0, 0x0, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_RESET__GPIO_2_20 IOMUX_PAD(0x440, 0x160, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_RESET__WEIM_CS3 IOMUX_PAD(0x440, 0x160, 4, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_SD3_CMD__SD3_CMD IOMUX_PAD(0x444, 0x164, 0, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD3_CMD__GPIO_5_18 IOMUX_PAD(0x444, 0x164, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PIN_SD3_CMD__NANDF_WRN IOMUX_PAD(0x444, 0x164, 2, 0x0, 0, PAD_CTL_DSE_HIGH) +#define MX50_PAD_SD3_CMD__SSP_CMD IOMUX_PAD(0x444, 0x164, 3, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_SD3_CLK__SD3_CLK IOMUX_PAD(0x448, 0x168, 0, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD3_CLK__GPIO_5_19 IOMUX_PAD(0x448, 0x168, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PIN_SD3_CLK__NANDF_RDN IOMUX_PAD(0x448, 0x168, 2, 0x0, 0, PAD_CTL_DSE_HIGH) +#define MX50_PAD_SD3_CLK__SSP_CLK IOMUX_PAD(0x448, 0x168, 3, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_SD3_D0__SD3_D0 IOMUX_PAD(0x44C, 0x16C, 0, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD3_D0__GPIO_5_20 IOMUX_PAD(0x44C, 0x16C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PIN_SD3_D0__NANDF_D4 IOMUX_PAD(0x44C, 0x16C, 2, 0x0, 0, PAD_CTL_DSE_HIGH) +#define MX50_PAD_SD3_D0__SSP_D0 IOMUX_PAD(0x44C, 0x16C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD3_D0__PLL1_BYP IOMUX_PAD(0x44C, 0x16C, 7, 0x6dc, 1, NO_PAD_CTRL) + +#define MX50_PAD_SD3_D1__SD3_D1 IOMUX_PAD(0x450, 0x170, 0, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD3_D1__GPIO_5_21 IOMUX_PAD(0x450, 0x170, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PIN_SD3_D1__NANDF_D5 IOMUX_PAD(0x450, 0x170, 2, 0x0, 0, PAD_CTL_DSE_HIGH) +#define MX50_PAD_SD3_D1__PLL2_BYP IOMUX_PAD(0x450, 0x170, 7, 0x6e0, 1, NO_PAD_CTRL) + +#define MX50_PAD_SD3_D2__SD3_D2 IOMUX_PAD(0x454, 0x174, 0, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD3_D2__GPIO_5_22 IOMUX_PAD(0x454, 0x174, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PIN_SD3_D2__NANDF_D6 IOMUX_PAD(0x454, 0x174, 2, 0x0, 0, PAD_CTL_DSE_HIGH) +#define MX50_PAD_SD3_D2__SSP_D2 IOMUX_PAD(0x454, 0x174, 3, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD3_D2__PLL3_BYP IOMUX_PAD(0x454, 0x174, 7, 0x6e4, 1, NO_PAD_CTRL) + +#define MX50_PAD_SD3_D3__SD3_D3 IOMUX_PAD(0x458, 0x178, 0, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD3_D3__GPIO_5_23 IOMUX_PAD(0x458, 0x178, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PIN_SD3_D3__NANDF_D7 IOMUX_PAD(0x458, 0x178, 2, 0x0, 0, PAD_CTL_DSE_HIGH) +#define MX50_PAD_SD3_D3__SSP_D3 IOMUX_PAD(0x458, 0x178, 3, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_SD3_D4__SD3_D4 IOMUX_PAD(0x45C, 0x17C, 0, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD3_D4__GPIO_5_24 IOMUX_PAD(0x45C, 0x17C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PIN_SD3_D4__NANDF_D0 IOMUX_PAD(0x45C, 0x17C, 2, 0x0, 0, PAD_CTL_DSE_HIGH) +#define MX50_PAD_SD3_D4__SSP_D4 IOMUX_PAD(0x45C, 0x17C, 1, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_SD3_D5__SD3_D5 IOMUX_PAD(0x460, 0x180, 0, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD3_D5__GPIO_5_25 IOMUX_PAD(0x460, 0x180, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PIN_SD3_D5__NANDF_D1 IOMUX_PAD(0x460, 0x180, 2, 0x0, 0, PAD_CTL_DSE_HIGH) +#define MX50_PAD_SD3_D5__SSP_D5 IOMUX_PAD(0x460, 0x180, 3, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_SD3_D6__SD3_D6 IOMUX_PAD(0x464, 0x184, 0, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD3_D6__GPIO_5_26 IOMUX_PAD(0x464, 0x184, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PIN_SD3_D6__NANDF_D2 IOMUX_PAD(0x464, 0x184, 2, 0x0, 0, PAD_CTL_DSE_HIGH) +#define MX50_PAD_SD3_D6__SSP_D6 IOMUX_PAD(0x464, 0x184, 3, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_SD3_D7__SD3_D7 IOMUX_PAD(0x468, 0x188, 0, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD3_D7__GPIO_5_27 IOMUX_PAD(0x468, 0x188, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PIN_SD3_D7__NANDF_D3 IOMUX_PAD(0x468, 0x188, 2, 0x0, 0, PAD_CTL_DSE_HIGH) +#define MX50_PAD_SD3_D7__SSP_D7 IOMUX_PAD(0x468, 0x188, 3, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_SD3_WP__SD3_WP IOMUX_PAD(0x46C, 0x18C, 0, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD3_WP__GPIO_5_28 IOMUX_PAD(0x46C, 0x18C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PIN_SD3_WP__NANDF_RESETN IOMUX_PAD(0x46C, 0x18C, 2, 0x0, 0, PAD_CTL_DSE_HIGH) +#define MX50_PAD_SD3_WP__SSP_CD IOMUX_PAD(0x46C, 0x18C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD3_WP__SD4_LCTL IOMUX_PAD(0x46C, 0x18C, 4, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD3_WP__WEIM_CS3 IOMUX_PAD(0x46C, 0x18C, 5, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_DISP_D8__DISP_D8 IOMUX_PAD(0x470, 0x190, 0, 0x71c, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_D8__GPIO_2_8 IOMUX_PAD(0x470, 0x190, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D8__NANDF_CLE IOMUX_PAD(0x470, 0x190, 2, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D8__SD1_LCTL IOMUX_PAD(0x470, 0x190, 3, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_DISP_D8__SD4_CMD IOMUX_PAD(0x470, 0x190, 4, 0x74c, 2, MX50_SD_PAD_CTRL) +#define MX50_PAD_DISP_D8__KEY_COL4 IOMUX_PAD(0x470, 0x190, 5, 0x790, 1, NO_PAD_CTRL) +#define MX50_PAD_DISP_D8__FEC_TX_CLK IOMUX_PAD(0x470, 0x190, 6, 0x78c, 1, NO_PAD_CTRL) + +#define MX50_PAD_DISP_D9__DISP_D9 IOMUX_PAD(0x474, 0x194, 0, 0x720, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_D9__GPIO_2_9 IOMUX_PAD(0x474, 0x194, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D9__NANDF_ALE IOMUX_PAD(0x474, 0x194, 2, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D9__SD2_LCTL IOMUX_PAD(0x474, 0x194, 3, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_DISP_D9__SD4_CLK IOMUX_PAD(0x474, 0x194, 4, 0x748, 2, MX50_SD_PAD_CTRL) +#define MX50_PAD_DISP_D9__KEY_ROW4 IOMUX_PAD(0x474, 0x194, 5, 0x7a0, 1, NO_PAD_CTRL) +#define MX50_PAD_DISP_D9__FEC_RX_ER IOMUX_PAD(0x474, 0x194, 6, 0x788, 1, NO_PAD_CTRL) + +#define MX50_PAD_DISP_D10__DISP_D10 IOMUX_PAD(0x478, 0x198, 0, 0x724, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_D10__GPIO_2_10 IOMUX_PAD(0x478, 0x198, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D10__NANDF_CEN0 IOMUX_PAD(0x478, 0x198, 2, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D10__SD3_LCTL IOMUX_PAD(0x478, 0x198, 3, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_DISP_D10__SD4_D0 IOMUX_PAD(0x478, 0x198, 4, 0x750, 1, MX50_SD_PAD_CTRL) +#define MX50_PAD_DISP_D10__KEY_COL5 IOMUX_PAD(0x478, 0x198, 5, 0x794, 1, NO_PAD_CTRL) +#define MX50_PAD_DISP_D10__FEC_RX_DV IOMUX_PAD(0x478, 0x198, 6, 0x784, 1, NO_PAD_CTRL) + +#define MX50_PAD_DISP_D11__DISP_D11 IOMUX_PAD(0x47C, 0x19C, 0, 0x728, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_D11__GPIO_2_11 IOMUX_PAD(0x47C, 0x19C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D11__NANDF_CEN1 IOMUX_PAD(0x47C, 0x19C, 2, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D11__SD4_D1 IOMUX_PAD(0x47C, 0x19C, 4, 0x754, 1, MX50_SD_PAD_CTRL) +#define MX50_PAD_DISP_D11__KEY_ROW5 IOMUX_PAD(0x47C, 0x19C, 5, 0x7a4, 1, NO_PAD_CTRL) +#define MX50_PAD_DISP_D11__FEC_RDAT1 IOMUX_PAD(0x47C, 0x19C, 6, 0x77c, 1, NO_PAD_CTRL) + +#define MX50_PAD_DISP_D12__DISP_D12 IOMUX_PAD(0x480, 0x1A0, 0, 0x72c, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_D12__GPIO_2_12 IOMUX_PAD(0x480, 0x1A0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D12__NANDF_CEN2 IOMUX_PAD(0x480, 0x1A0, 2, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D12__SD1_CD IOMUX_PAD(0x480, 0x1A0, 3, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_DISP_D12__SD4_D2 IOMUX_PAD(0x480, 0x1A0, 4, 0x758, 1, MX50_SD_PAD_CTRL) +#define MX50_PAD_DISP_D12__KEY_COL6 IOMUX_PAD(0x480, 0x1A0, 5, 0x798, 1, NO_PAD_CTRL) +#define MX50_PAD_DISP_D12__FEC_RDAT0 IOMUX_PAD(0x480, 0x1A0, 6, 0x778, 1, NO_PAD_CTRL) + +#define MX50_PAD_DISP_D13__DISP_D13 IOMUX_PAD(0x484, 0x1A4, 0, 0x730, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_D13__GPIO_2_13 IOMUX_PAD(0x484, 0x1A4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D13__NANDF_CEN3 IOMUX_PAD(0x484, 0x1A4, 2, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D13__SD3_CD IOMUX_PAD(0x484, 0x1A4, 3, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_DISP_D13__SD4_D3 IOMUX_PAD(0x484, 0x1A4, 4, 0x75c, 1, MX50_SD_PAD_CTRL) +#define MX50_PAD_DISP_D13__KEY_ROW6 IOMUX_PAD(0x484, 0x1A4, 5, 0x7a8, 1, NO_PAD_CTRL) +#define MX50_PAD_DISP_D13__FEC_TX_EN IOMUX_PAD(0x484, 0x1A4, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_DISP_D14__DISP_D14 IOMUX_PAD(0x488, 0x1A8, 0, 0x734, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_D14__GPIO_2_14 IOMUX_PAD(0x488, 0x1A8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D14__NANDF_RDY0 IOMUX_PAD(0x488, 0x1A8, 2, 0x7b4, 1, NO_PAD_CTRL) +#define MX50_PAD_DISP_D14__SD1_WP IOMUX_PAD(0x488, 0x1A8, 3, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_DISP_D14__SD4_WP IOMUX_PAD(0x488, 0x1A8, 4, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_DISP_D14__KEY_COL7 IOMUX_PAD(0x488, 0x1A8, 5, 0x79c, 1, NO_PAD_CTRL) +#define MX50_PAD_DISP_D14__FEC_TDAT1 IOMUX_PAD(0x488, 0x1A8, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_DISP_D15__DISP_D15 IOMUX_PAD(0x48C, 0x1AC, 0, 0x738, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_D15__GPIO_2_15 IOMUX_PAD(0x48C, 0x1AC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D15__NANDF_DQS IOMUX_PAD(0x48C, 0x1AC, 2, 0x7b0, 1, NO_PAD_CTRL) +#define MX50_PAD_DISP_D15__SD3_RST IOMUX_PAD(0x48C, 0x1AC, 3, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_DISP_D15__SD4_CD IOMUX_PAD(0x48C, 0x1AC, 4, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_DISP_D15__KEY_ROW7 IOMUX_PAD(0x48C, 0x1AC, 5, 0x7ac, 1, NO_PAD_CTRL) +#define MX50_PAD_DISP_D15__FEC_TDAT0 IOMUX_PAD(0x48C, 0x1AC, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EPDC_D0__EPDC_D0 IOMUX_PAD(0x54C, 0x1B0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D0__GPIO_3_0 IOMUX_PAD(0x54C, 0x1B0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D0__WEIM_D0 IOMUX_PAD(0x54C, 0x1B0, 2, 0x7ec, 1, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D0__ELCDIF_RS IOMUX_PAD(0x54C, 0x1B0, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_EPDC_D0__ELCDIF_PIXCLK IOMUX_PAD(0x54C, 0x1B0, 4, 0x0, 0, MX50_ELCDIF_PAD_CTRL) + +#define MX50_PAD_EPDC_D1__EPDC_D1 IOMUX_PAD(0x550, 0x1B4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D1__GPIO_3_1 IOMUX_PAD(0x550, 0x1B4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D1__WEIM_D1 IOMUX_PAD(0x550, 0x1B4, 2, 0x7f0, 1, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D1__ELCDIF_CS IOMUX_PAD(0x550, 0x1B4, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_EPDC_D1__ELCDIF_EN IOMUX_PAD(0x550, 0x1B4, 4, 0x0, 0, MX50_ELCDIF_PAD_CTRL) + +#define MX50_PAD_EPDC_D2__EPDC_D2 IOMUX_PAD(0x554, 0x1B8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D2__GPIO_3_2 IOMUX_PAD(0x554, 0x1B8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D2__WEIM_D2 IOMUX_PAD(0x554, 0x1B8, 2, 0x7f4, 1, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D2__ELCDIF_WR IOMUX_PAD(0x554, 0x1B8, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_EPDC_D2__ELCDIF_VSYNC IOMUX_PAD(0x554, 0x1B8, 4, 0x73c, 2, MX50_ELCDIF_PAD_CTRL) + +#define MX50_PAD_EPDC_D3__EPDC_D3 IOMUX_PAD(0x558, 0x1BC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D3__GPIO_3_3 IOMUX_PAD(0x558, 0x1BC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D3__WEIM_D3 IOMUX_PAD(0x558, 0x1BC, 2, 0x7f8, 1, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D3__ELCDIF_RD IOMUX_PAD(0x558, 0x1BC, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_EPDC_D3__ELCDIF_HSYNC IOMUX_PAD(0x558, 0x1BC, 4, 0x6f8, 3, MX50_ELCDIF_PAD_CTRL) + +#define MX50_PAD_EPDC_D4__EPDC_D4 IOMUX_PAD(0x55C, 0x1C0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D4__GPIO_3_4 IOMUX_PAD(0x55C, 0x1C0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D4__WEIM_D4 IOMUX_PAD(0x55C, 0x1C0, 2, 0x7fc, 1, NO_PAD_CTRL) + +#define MX50_PAD_EPDC_D5__EPDC_D5 IOMUX_PAD(0x560, 0x1C4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D5__GPIO_3_5 IOMUX_PAD(0x560, 0x1C4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D5__WEIM_D5 IOMUX_PAD(0x560, 0x1C4, 2, 0x800, 1, NO_PAD_CTRL) + +#define MX50_PAD_EPDC_D6__EPDC_D6 IOMUX_PAD(0x564, 0x1C8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D6__GPIO_3_6 IOMUX_PAD(0x564, 0x1C8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D6__WEIM_D6 IOMUX_PAD(0x564, 0x1C8, 2, 0x804, 1, NO_PAD_CTRL) + +#define MX50_PAD_EPDC_D7__EPDC_D7 IOMUX_PAD(0x568, 0x1CC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D7__GPIO_3_7 IOMUX_PAD(0x568, 0x1CC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D7__WEIM_D7 IOMUX_PAD(0x568, 0x1CC, 2, 0x808, 1, NO_PAD_CTRL) + +#define MX50_PAD_EPDC_D8__EPDC_D8 IOMUX_PAD(0x56C, 0x1D0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D8__GPIO_3_8 IOMUX_PAD(0x56C, 0x1D0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D8__WEIM_D8 IOMUX_PAD(0x56C, 0x1D0, 2, 0x80c, 2, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D8__ELCDIF_D24 IOMUX_PAD(0x56C, 0x1D0, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) + +#define MX50_PAD_EPDC_D9__EPDC_D9 IOMUX_PAD(0x570, 0x1D4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D9__GPIO_3_9 IOMUX_PAD(0x570, 0x1D4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D9__WEIM_D9 IOMUX_PAD(0x570, 0x1D4, 2, 0x810, 2, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D9__ELCDIF_D25 IOMUX_PAD(0x570, 0x1D4, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) + +#define MX50_PAD_EPDC_D10__EPDC_D10 IOMUX_PAD(0x574, 0x1D8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D10__GPIO_3_10 IOMUX_PAD(0x574, 0x1D8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D10__WEIM_D10 IOMUX_PAD(0x574, 0x1D8, 2, 0x814, 2, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D10__ELCDIF_D26 IOMUX_PAD(0x574, 0x1D8, 3, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EPDC_D11__EPDC_D11 IOMUX_PAD(0x578, 0x1DC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D11__GPIO_3_11 IOMUX_PAD(0x578, 0x1DC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D11__WEIM_D11 IOMUX_PAD(0x578, 0x1DC, 2, 0x818, 2, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D11__ELCDIF_D27 IOMUX_PAD(0x578, 0x1DC, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) + +#define MX50_PAD_EPDC_D12__EPDC_D12 IOMUX_PAD(0x57C, 0x1E0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D12__GPIO_3_12 IOMUX_PAD(0x57C, 0x1E0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D12__WEIM_D12 IOMUX_PAD(0x57C, 0x1E0, 2, 0x81c, 1, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D12__ELCDIF_D28 IOMUX_PAD(0x57C, 0x1E0, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) + +#define MX50_PAD_EPDC_D13__EPDC_D13 IOMUX_PAD(0x580, 0x1E4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D13__GPIO_3_13 IOMUX_PAD(0x580, 0x1E4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D13__WEIM_D13 IOMUX_PAD(0x580, 0x1E4, 2, 0x820, 1, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D13__ELCDIF_D29 IOMUX_PAD(0x580, 0x1E4, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) + +#define MX50_PAD_EPDC_D14__EPDC_D14 IOMUX_PAD(0x584, 0x1E8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D14__GPIO_3_14 IOMUX_PAD(0x584, 0x1E8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D14__WEIM_D14 IOMUX_PAD(0x584, 0x1E8, 2, 0x824, 1, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D14__ELCDIF_D30 IOMUX_PAD(0x584, 0x1E8, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_EPDC_D14__AUD6_TXD IOMUX_PAD(0x584, 0x1E8, 4, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EPDC_D15__EPDC_D15 IOMUX_PAD(0x588, 0x1EC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D15__GPIO_3_15 IOMUX_PAD(0x588, 0x1EC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D15__WEIM_D15 IOMUX_PAD(0x588, 0x1EC, 2, 0x828, 1, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D15__ELCDIF_D31 IOMUX_PAD(0x588, 0x1EC, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_EPDC_D15__AUD6_TXC IOMUX_PAD(0x588, 0x1EC, 4, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EPDC_GDCLK__EPDC_GDCLK IOMUX_PAD(0x58C, 0x1F0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDCLK__GPIO_3_16 IOMUX_PAD(0x58C, 0x1F0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDCLK__WEIM_D16 IOMUX_PAD(0x58C, 0x1F0, 2, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDCLK__ELCDIF_D16 IOMUX_PAD(0x58C, 0x1F0, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_EPDC_GDCLK__AUD6_TXFS IOMUX_PAD(0x58C, 0x1F0, 4, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EPDC_GDSP__EPDC_GDSP IOMUX_PAD(0x590, 0x1F4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDSP__GPIO_3_17 IOMUX_PAD(0x590, 0x1F4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDSP__WEIM_D17 IOMUX_PAD(0x590, 0x1F4, 2, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDSP__ELCDIF_D17 IOMUX_PAD(0x590, 0x1F4, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_EPDC_GDSP__AUD6_RXD IOMUX_PAD(0x590, 0x1F4, 4, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EPDC_GDOE__EPDC_GDOE IOMUX_PAD(0x594, 0x1F8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDOE__GPIO_3_18 IOMUX_PAD(0x594, 0x1F8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDOE__WEIM_D18 IOMUX_PAD(0x594, 0x1F8, 2, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDOE__ELCDIF_D18 IOMUX_PAD(0x594, 0x1F8, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_EPDC_GDOE__AUD6_RXC IOMUX_PAD(0x594, 0x1F8, 4, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EPDC_GDRL__EPDC_GDRL IOMUX_PAD(0x598, 0x1FC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDRL__GPIO_3_19 IOMUX_PAD(0x598, 0x1FC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDRL__WEIM_D19 IOMUX_PAD(0x598, 0x1FC, 2, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDRL__ELCDIF_D19 IOMUX_PAD(0x598, 0x1FC, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_EPDC_GDRL__AUD6_RXFS IOMUX_PAD(0x598, 0x1FC, 4, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EPDC_SDCLK__EPDC_SDCLK IOMUX_PAD(0x59C, 0x200, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCLK__GPIO_3_20 IOMUX_PAD(0x59C, 0x200, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCLK__WEIM_D20 IOMUX_PAD(0x59C, 0x200, 2, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCLK__ELCDIF_D20 IOMUX_PAD(0x59C, 0x200, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_EPDC_SDCLK__AUD5_TXD IOMUX_PAD(0x59C, 0x200, 4, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EPDC_SDOEZ__EPDC_SDOEZ IOMUX_PAD(0x5A0, 0x204, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDOEZ__GPIO_3_21 IOMUX_PAD(0x5A0, 0x204, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDOEZ__WEIM_D21 IOMUX_PAD(0x5A0, 0x204, 2, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDOEZ__ELCDIF_D21 IOMUX_PAD(0x5A0, 0x204, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_EPDC_SDOEZ__AUD5_TXC IOMUX_PAD(0x5A0, 0x204, 4, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EPDC_SDOED__EPDC_SDOED IOMUX_PAD(0x5A4, 0x208, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDOED__GPIO_3_22 IOMUX_PAD(0x5A4, 0x208, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDOED__WEIM_D22 IOMUX_PAD(0x5A4, 0x208, 2, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDOED__ELCDIF_D22 IOMUX_PAD(0x5A4, 0x208, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_EPDC_SDOED__AUD5_TXFS IOMUX_PAD(0x5A4, 0x208, 4, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EPDC_SDOE__EPDC_SDOE IOMUX_PAD(0x5A8, 0x20C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDOE__GPIO_3_23 IOMUX_PAD(0x5A8, 0x20C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDOE__WEIM_D23 IOMUX_PAD(0x5A8, 0x20C, 2, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDOE__ELCDIF_D23 IOMUX_PAD(0x5A8, 0x20C, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_EPDC_SDOE__AUD5_RXD IOMUX_PAD(0x5A8, 0x20C, 4, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EPDC_SDLE__EPDC_SDLE IOMUX_PAD(0x5AC, 0x210, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDLE__GPIO_3_24 IOMUX_PAD(0x5AC, 0x210, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDLE__WEIM_D24 IOMUX_PAD(0x5AC, 0x210, 2, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDLE__ELCDIF_D8 IOMUX_PAD(0x5AC, 0x210, 3, 0x71c, 1, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_EPDC_SDLE__AUD5_RXC IOMUX_PAD(0x5AC, 0x210, 4, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EPDC_SDCLKN__EPDC_SDCLKN IOMUX_PAD(0x5B0, 0x214, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCLKN__GPIO_3_25 IOMUX_PAD(0x5B0, 0x214, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCLKN__WEIM_D25 IOMUX_PAD(0x5B0, 0x214, 2, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCLKN__ELCDIF_D9 IOMUX_PAD(0x5B0, 0x214, 3, 0x720, 1, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_EPDC_SDCLKN__AUD5_RXFS IOMUX_PAD(0x5B0, 0x214, 4, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EPDC_SDSHR__EPDC_SDSHR IOMUX_PAD(0x5B4, 0x218, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDSHR__GPIO_3_26 IOMUX_PAD(0x5B4, 0x218, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDSHR__WEIM_D26 IOMUX_PAD(0x5B4, 0x218, 2, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDSHR__ELCDIF_D10 IOMUX_PAD(0x5B4, 0x218, 3, 0x724, 1, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_EPDC_SDSHR__AUD4_TXD IOMUX_PAD(0x5B4, 0x218, 4, 0x6c8, 1, NO_PAD_CTRL) + +#define MX50_PAD_EPDC_PWRCOM__EPDC_PWRCOM IOMUX_PAD(0x5B8, 0x21C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCOM__GPIO_3_27 IOMUX_PAD(0x5B8, 0x21C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCOM__WEIM_D27 IOMUX_PAD(0x5B8, 0x21C, 2, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCOM__ELCDIF_D11 IOMUX_PAD(0x5B8, 0x21C, 3, 0x728, 1, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCOM__AUD4_TXC IOMUX_PAD(0x5B8, 0x21C, 4, 0x6d4, 1, NO_PAD_CTRL) + +#define MX50_PAD_EPDC_PWRSTAT__EPDC_PWRSTAT IOMUX_PAD(0x5BC, 0x220, 0, 0x0, 0, NO_PAD_CTRL) +/* Remove the default keeper from this pad (for EPD) */ +#define MX50_PAD_EPDC_PWRSTAT__GPIO_3_28 IOMUX_PAD(0x5BC, 0x220, 1, 0x0, 0, 0) +#define MX50_PAD_EPDC_PWRSTAT__WEIM_D28 IOMUX_PAD(0x5BC, 0x220, 2, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRSTAT__ELCDIF_D12 IOMUX_PAD(0x5BC, 0x220, 3, 0x72c, 1, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_EPDC_PWRSTAT__AUD4_TXFS IOMUX_PAD(0x5BC, 0x220, 4, 0x6d8, 1, NO_PAD_CTRL) + +#define MX50_PAD_EPDC_PWRCTRL0__EPDC_PWRCTRL0 IOMUX_PAD(0x5C0, 0x224, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCTRL0__GPIO_3_29 IOMUX_PAD(0x5C0, 0x224, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCTRL0__WEIM_D29 IOMUX_PAD(0x5C0, 0x224, 2, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCTRL0__ELCDIF_D13 IOMUX_PAD(0x5C0, 0x224, 3, 0x730, 1, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCTRL0__AUD4_RXD IOMUX_PAD(0x5C0, 0x224, 4, 0x6c4, 1, NO_PAD_CTRL) + +#define MX50_PAD_EPDC_PWRCTRL1__EPDC_PWRCTRL1 IOMUX_PAD(0x5C4, 0x228, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCTRL1__GPIO_3_30 IOMUX_PAD(0x5C4, 0x228, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCTRL1__WEIM_D30 IOMUX_PAD(0x5C4, 0x228, 2, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCTRL1__ELCDIF_D14 IOMUX_PAD(0x5C4, 0x228, 3, 0x734, 1, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCTRL1__AUD4_RXC IOMUX_PAD(0x5C4, 0x228, 4, 0x6cc, 1, NO_PAD_CTRL) + +#define MX50_PAD_EPDC_PWRCTRL2__EPDC_PWRCTRL2 IOMUX_PAD(0x5C8, 0x22C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCTRL2__GPIO_3_31 IOMUX_PAD(0x5C8, 0x22C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCTRL2__WEIM_D31 IOMUX_PAD(0x5C8, 0x22C, 2, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCTRL2__ELCDIF_D15 IOMUX_PAD(0x5C8, 0x22C, 3, 0x738, 1, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCTRL2__AUD4_RXFS IOMUX_PAD(0x5C8, 0x22C, 4, 0x6d0, 1, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCTRL2__SDMA_EXT0 IOMUX_PAD(0x5C8, 0x22C, 6, 0x7b8, 1, NO_PAD_CTRL) + +#define MX50_PAD_EPDC_PWRCTRL3__PWRCTRL3 IOMUX_PAD(0x5CC, 0x230, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCTRL3__GPIO_4_20 IOMUX_PAD(0x5CC, 0x230, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCTRL3__WEIM_EB2 IOMUX_PAD(0x5CC, 0x230, 2, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCTRL3__SDMA_EXT1 IOMUX_PAD(0x5CC, 0x230, 6, 0x7bc, 1, NO_PAD_CTRL) + +#define MX50_PAD_EPDC_VCOM0__EPDC_VCOM0 IOMUX_PAD(0x5D0, 0x234, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_VCOM0__GPIO_4_21 IOMUX_PAD(0x5D0, 0x234, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_VCOM0__WEIM_EB3 IOMUX_PAD(0x5D0, 0x234, 2, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EPDC_VCOM1__EPDC_VCOM1 IOMUX_PAD(0x5D4, 0x238, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_VCOM1__GPIO_4_22 IOMUX_PAD(0x5D4, 0x238, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_VCOM1__WEIM_CS3 IOMUX_PAD(0x5D4, 0x238, 2, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EPDC_BDR0__EPDC_BDR0 IOMUX_PAD(0x5D8, 0x23C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_BDR0__GPIO_4_23 IOMUX_PAD(0x5D8, 0x23C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_BDR0__ELCDIF_D7 IOMUX_PAD(0x5D8, 0x23C, 3, 0x718, 1, MX50_ELCDIF_PAD_CTRL) + +#define MX50_PAD_EPDC_BDR1__EPDC_BDR1 IOMUX_PAD(0x5DC, 0x240, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_BDR1__GPIO_4_24 IOMUX_PAD(0x5DC, 0x240, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_BDR1__ELCDIF_D6 IOMUX_PAD(0x5DC, 0x240, 3, 0x714, 1, MX50_ELCDIF_PAD_CTRL) + +#define MX50_PAD_EPDC_SDCE0__EPDC_SDCE0 IOMUX_PAD(0x5E0, 0x244, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCE0__GPIO_4_25 IOMUX_PAD(0x5E0, 0x244, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCE0__ELCDIF_D5 IOMUX_PAD(0x5E0, 0x244, 3, 0x710, 1, MX50_ELCDIF_PAD_CTRL) + +#define MX50_PAD_EPDC_SDCE1__EPDC_SDCE1 IOMUX_PAD(0x5E4, 0x248, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCE1__GPIO_4_26 IOMUX_PAD(0x5E4, 0x248, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCE1__ELCDIF_D4 IOMUX_PAD(0x5E4, 0x248, 2, 0x70c, 1, MX50_ELCDIF_PAD_CTRL) + +#define MX50_PAD_EPDC_SDCE2__EPDC_SDCE2 IOMUX_PAD(0x5E8, 0x24C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCE2__GPIO_4_27 IOMUX_PAD(0x5E8, 0x24C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCE2__ELCDIF_DAT3 IOMUX_PAD(0x5E8, 0x24C, 3, 0x708, 1, MX50_ELCDIF_PAD_CTRL) + +#define MX50_PAD_EPDC_SDCE3__EPDC_SDCE3 IOMUX_PAD(0x5EC, 0x250, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCE3__GPIO_4_28 IOMUX_PAD(0x5EC, 0x250, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCE3__ELCDIF_D2 IOMUX_PAD(0x5EC, 0x250, 3, 0x704, 1, MX50_ELCDIF_PAD_CTRL) + +#define MX50_PAD_EPDC_SDCE4__EPDC_SDCE4 IOMUX_PAD(0x5F0, 0x254, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCE4__GPIO_4_29 IOMUX_PAD(0x5F0, 0x254, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCE4__ELCDIF_D1 IOMUX_PAD(0x5F0, 0x254, 3, 0x700, 1, MX50_ELCDIF_PAD_CTRL) + +#define MX50_PAD_EPDC_SDCE5__EPDC_SDCE5 IOMUX_PAD(0x5F4, 0x258, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCE5__GPIO_4_30 IOMUX_PAD(0x5F4, 0x258, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCE5__ELCDIF_D0 IOMUX_PAD(0x5F4, 0x258, 3, 0x6fc, 1, MX50_ELCDIF_PAD_CTRL) + +#define MX50_PAD_EIM_DA0__WEIM_A0 IOMUX_PAD(0x5F8, 0x25C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA0__GPIO_1_0 IOMUX_PAD(0x5F8, 0x25C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA0__KEY_COL4 IOMUX_PAD(0x5f8, 0x25C, 3, 0x790, 2, NO_PAD_CTRL) + +#define MX50_PAD_EIM_DA1__WEIM_A1 IOMUX_PAD(0x5FC, 0x260, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA1__GPIO_1_1 IOMUX_PAD(0x5FC, 0x260, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA1__KEY_ROW4 IOMUX_PAD(0x5fc, 0x260, 3, 0x7a0, 2, MX50_KEYPAD_CTRL) + +#define MX50_PAD_EIM_DA2__WEIM_A2 IOMUX_PAD(0x600, 0x264, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA2__GPIO_1_2 IOMUX_PAD(0x600, 0x264, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA2__KEY_COL5 IOMUX_PAD(0x600, 0x264, 3, 0x794, 2, NO_PAD_CTRL) + +#define MX50_PAD_EIM_DA3__WEIM_A3 IOMUX_PAD(0x604, 0x268, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA3__GPIO_1_3 IOMUX_PAD(0x604, 0x268, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA3__KEY_ROW5 IOMUX_PAD(0x604, 0x268, 3, 0x7a4, 2, MX50_KEYPAD_CTRL) + +#define MX50_PAD_EIM_DA4__WEIM_A4 IOMUX_PAD(0x608, 0x26C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA4__GPIO_1_4 IOMUX_PAD(0x608, 0x26C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA4__KEY_COL6 IOMUX_PAD(0x608, 0x26C, 3, 0x798, 2, NO_PAD_CTRL) + +#define MX50_PAD_EIM_DA5__WEIM_A5 IOMUX_PAD(0x60C, 0x270, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA5__GPIO_1_5 IOMUX_PAD(0x60C, 0x270, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA5__KEY_ROW6 IOMUX_PAD(0x60C, 0x270, 3, 0x7a8, 2, MX50_KEYPAD_CTRL) + +#define MX50_PAD_EIM_DA6__WEIM_A6 IOMUX_PAD(0x610, 0x274, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA6__GPIO_1_6 IOMUX_PAD(0x610, 0x274, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA6__KEY_COL7 IOMUX_PAD(0x610, 0x274, 3, 0x79c, 2, NO_PAD_CTRL) + +#define MX50_PAD_EIM_DA7__WEIM_A7 IOMUX_PAD(0x614, 0x278, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA7__GPIO_1_7 IOMUX_PAD(0x614, 0x278, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA7__KEY_ROW7 IOMUX_PAD(0x614, 0x278, 3, 0x7ac, 2, MX50_KEYPAD_CTRL) + +#define MX50_PAD_EIM_DA8__WEIM_A8 IOMUX_PAD(0x618, 0x27C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA8__GPIO_1_8 IOMUX_PAD(0x618, 0x27C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PIN_EIM_DA8__NANDF_CLE IOMUX_PAD(0x618, 0x27C, 2, 0x0, 0, PAD_CTL_DSE_HIGH) + +#define MX50_PAD_EIM_DA9__WEIM_A9 IOMUX_PAD(0x61C, 0x280, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA9__GPIO_1_9 IOMUX_PAD(0x61C, 0x280, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PIN_EIM_DA9__NANDF_ALE IOMUX_PAD(0x61C, 0x280, 2, 0x0, 0, PAD_CTL_DSE_HIGH) + +#define MX50_PAD_EIM_DA10__WEIM_A10 IOMUX_PAD(0x620, 0x284, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA10__GPIO_1_10 IOMUX_PAD(0x620, 0x284, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PIN_EIM_DA10__NANDF_CE0 IOMUX_PAD(0x620, 0x284, 2, 0x0, 0, PAD_CTL_DSE_HIGH) + +#define MX50_PAD_EIM_DA11__WEIM_A11 IOMUX_PAD(0x624, 0x288, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA11__GPIO_1_11 IOMUX_PAD(0x624, 0x288, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PIN_EIM_DA11__NANDF_CE1 IOMUX_PAD(0x624, 0x288, 2, 0x0, 0, PAD_CTL_DSE_HIGH) + +#define MX50_PAD_EIM_DA12__WEIM_A12 IOMUX_PAD(0x628, 0x28C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA12__GPIO_1_12 IOMUX_PAD(0x628, 0x28C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PIN_EIM_DA12__NANDF_CE2 IOMUX_PAD(0x628, 0x28C, 2, 0x0, 0, PAD_CTL_DSE_HIGH) +#define MX50_PAD_EIM_DA12__EPDC_SDCE6 IOMUX_PAD(0x628, 0x28C, 3, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EIM_DA13__WEIM_A13 IOMUX_PAD(0x62C, 0x290, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA13__GPIO_1_13 IOMUX_PAD(0x62C, 0x290, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PIN_EIM_DA13__NANDF_CE3 IOMUX_PAD(0x62C, 0x290, 2, 0x0, 0, PAD_CTL_DSE_HIGH) +#define MX50_PIN_EIM_DA13__EPDC_SDCE7 IOMUX_PAD(0x62C, 0x290, 3, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EIM_DA14__WEIM_A14 IOMUX_PAD(0x630, 0x294, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA14__GPIO_1_14 IOMUX_PAD(0x630, 0x294, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA14__NANDF_READY IOMUX_PAD(0x630, 0x294, 2, 0x7B4, 2, PAD_CTL_PKE | \ + PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) +#define MX50_PAD_EIM_DA14__EPDC_SDCE8 IOMUX_PAD(0x630, 0x294, 3, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EIM_DA15__WEIM_A15 IOMUX_PAD(0x634, 0x298, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA15__GPIO_1_15 IOMUX_PAD(0x634, 0x298, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PIN_EIM_DA15__NANDF_DQS IOMUX_PAD(0x634, 0x298, 2, 0x7B0, 2, PAD_CTL_DSE_HIGH) +#define MX50_PAD_EIM_DA15__EPDC_SDCE9 IOMUX_PAD(0x634, 0x298, 3, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EIM_CS2__WEIM_CS2 IOMUX_PAD(0x638, 0x29C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_CS2__GPIO_1_16 IOMUX_PAD(0x638, 0x29C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_CS2__WEIM_A27 IOMUX_PAD(0x638, 0x29C, 2, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EIM_CS1__WEIM_CS1 IOMUX_PAD(0x63C, 0x2A0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_CS1__GPIO_1_17 IOMUX_PAD(0x63C, 0x2A0, 1, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EIM_CS0__WEIM_CS0 IOMUX_PAD(0x640, 0x2A4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_CS0__GPIO_1_18 IOMUX_PAD(0x640, 0x2A4, 1, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EIM_EB0__WEIM_EB0 IOMUX_PAD(0x644, 0x2A8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_EB0__GPIO_1_19 IOMUX_PAD(0x644, 0x2A8, 1, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EIM_EB1__WEIM_EB1 IOMUX_PAD(0x648, 0x2AC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_EB1__GPIO_1_20 IOMUX_PAD(0x648, 0x2AC, 1, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EIM_WAIT__WEIM_WAIT IOMUX_PAD(0x64C, 0x2B0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_WAIT__GPIO_1_21 IOMUX_PAD(0x64C, 0x2B0, 1, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EIM_BCLK__WEIM_BCLK IOMUX_PAD(0x650, 0x2B4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_BCLK__GPIO_1_22 IOMUX_PAD(0x650, 0x2B4, 1, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EIM_RDY__WEIM_RDY IOMUX_PAD(0x654, 0x2B8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_RDY__GPIO_1_23 IOMUX_PAD(0x654, 0x2B8, 1, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EIM_OE__WEIM_OE IOMUX_PAD(0x658, 0x2BC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_OE__GPIO_1_24 IOMUX_PAD(0x658, 0x2BC, 1, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EIM_RW__WEIM_RW IOMUX_PAD(0x65C, 0x2C0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_RW__GPIO_1_25 IOMUX_PAD(0x65C, 0x2C0, 1, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EIM_LBA__WEIM_LBA IOMUX_PAD(0x660, 0x2C4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_LBA__GPIO_1_26 IOMUX_PAD(0x660, 0x2C4, 1, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EIM_CRE__WEIM_CRE IOMUX_PAD(0x664, 0x2C8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_CRE__GPIO_1_27 IOMUX_PAD(0x664, 0x2C8, 1, 0x0, 0, NO_PAD_CTRL) + +#endif /* __MACH_IOMUX_MX50_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51.h b/arch/arm/plat-mxc/include/mach/iomux-mx51.h new file mode 100644 index 00000000..df6acc06 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/iomux-mx51.h @@ -0,0 +1,1567 @@ +/* + * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com> + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __MACH_IOMUX_MX51_H__ +#define __MACH_IOMUX_MX51_H__ + +#include <mach/iomux-v3.h> + +/* Pad control groupings */ +#define MX51_UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_DSE_HIGH | \ + PAD_CTL_HYS | PAD_CTL_SRE_FAST) +#define MX51_I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_ODE | \ + PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \ + PAD_CTL_HYS) +#define MX51_ESDHC_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_ODE | \ + PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \ + PAD_CTL_HYS) +#define MX51_USBH1_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_SRE_FAST | \ + PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \ + PAD_CTL_HYS | PAD_CTL_PUE) +#define MX51_ECSPI_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_HYS | \ + PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST) +#define MX51_SDHCI_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_PUE | \ + PAD_CTL_SRE_FAST | PAD_CTL_DVS) +#define MX51_GPIO_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_PKE | PAD_CTL_SRE_FAST) + +#define MX51_PAD_CTRL_2 (PAD_CTL_PKE | PAD_CTL_HYS) +#define MX51_PAD_CTRL_3 (PAD_CTL_PKE | PAD_CTL_PUS_100K_UP) +#define MX51_PAD_CTRL_4 (PAD_CTL_PKE | PAD_CTL_DVS | PAD_CTL_HYS) +#define MX51_PAD_CTRL_5 (PAD_CTL_DVS | PAD_CTL_DSE_HIGH) + +/* + * The naming convention for the pad modes is MX51_PAD_<padname>__<padmode> + * If <padname> or <padmode> refers to a GPIO, it is named GPIO<unit>_<num> + * See also iomux-v3.h + */ + +/* Raw pin modes without pad control */ +/* PAD MUX ALT INPSE PATH PADCTRL */ +#define _MX51_PAD_EIM_D16__AUD4_RXFS IOMUX_PAD(0x3f0, 0x5c, 5, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D16__AUD5_TXD IOMUX_PAD(0x3f0, 0x5c, 7, 0x08d8, 0, 0) +#define _MX51_PAD_EIM_D16__EIM_D16 IOMUX_PAD(0x3f0, 0x5c, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D16__GPIO2_0 IOMUX_PAD(0x3f0, 0x5c, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D16__I2C1_SDA IOMUX_PAD(0x3f0, 0x5c, 0x14, 0x09b4, 0, 0) +#define _MX51_PAD_EIM_D16__UART2_CTS IOMUX_PAD(0x3f0, 0x5c, 3, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D16__USBH2_DATA0 IOMUX_PAD(0x3f0, 0x5c, 2, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D17__AUD5_RXD IOMUX_PAD(0x3f4, 0x60, 7, 0x08d4, 0, 0) +#define _MX51_PAD_EIM_D17__EIM_D17 IOMUX_PAD(0x3f4, 0x60, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D17__GPIO2_1 IOMUX_PAD(0x3f4, 0x60, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D17__UART2_RXD IOMUX_PAD(0x3f4, 0x60, 3, 0x09ec, 0, 0) +#define _MX51_PAD_EIM_D17__UART3_CTS IOMUX_PAD(0x3f4, 0x60, 4, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D17__USBH2_DATA1 IOMUX_PAD(0x3f4, 0x60, 2, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D18__AUD5_TXC IOMUX_PAD(0x3f8, 0x64, 7, 0x08e4, 0, 0) +#define _MX51_PAD_EIM_D18__EIM_D18 IOMUX_PAD(0x3f8, 0x64, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D18__GPIO2_2 IOMUX_PAD(0x3f8, 0x64, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D18__UART2_TXD IOMUX_PAD(0x3f8, 0x64, 3, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D18__UART3_RTS IOMUX_PAD(0x3f8, 0x64, 4, 0x09f0, 1, 0) +#define _MX51_PAD_EIM_D18__USBH2_DATA2 IOMUX_PAD(0x3f8, 0x64, 2, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D19__AUD4_RXC IOMUX_PAD(0x3fc, 0x68, 5, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D19__AUD5_TXFS IOMUX_PAD(0x3fc, 0x68, 7, 0x08e8, 0, 0) +#define _MX51_PAD_EIM_D19__EIM_D19 IOMUX_PAD(0x3fc, 0x68, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D19__GPIO2_3 IOMUX_PAD(0x3fc, 0x68, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D19__I2C1_SCL IOMUX_PAD(0x3fc, 0x68, 0x14, 0x09b0, 0, 0) +#define _MX51_PAD_EIM_D19__UART2_RTS IOMUX_PAD(0x3fc, 0x68, 3, 0x09e8, 1, 0) +#define _MX51_PAD_EIM_D19__USBH2_DATA3 IOMUX_PAD(0x3fc, 0x68, 2, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D20__AUD4_TXD IOMUX_PAD(0x400, 0x6c, 5, 0x08c8, 0, 0) +#define _MX51_PAD_EIM_D20__EIM_D20 IOMUX_PAD(0x400, 0x6c, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D20__GPIO2_4 IOMUX_PAD(0x400, 0x6c, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D20__SRTC_ALARM_DEB IOMUX_PAD(0x400, 0x6c, 4, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D20__USBH2_DATA4 IOMUX_PAD(0x400, 0x6c, 2, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D21__AUD4_RXD IOMUX_PAD(0x404, 0x70, 5, 0x08c4, 0, 0) +#define _MX51_PAD_EIM_D21__EIM_D21 IOMUX_PAD(0x404, 0x70, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D21__GPIO2_5 IOMUX_PAD(0x404, 0x70, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D21__SRTC_ALARM_DEB IOMUX_PAD(0x404, 0x70, 3, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D21__USBH2_DATA5 IOMUX_PAD(0x404, 0x70, 2, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D22__AUD4_TXC IOMUX_PAD(0x408, 0x74, 5, 0x08cc, 0, 0) +#define _MX51_PAD_EIM_D22__EIM_D22 IOMUX_PAD(0x408, 0x74, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D22__GPIO2_6 IOMUX_PAD(0x408, 0x74, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D22__USBH2_DATA6 IOMUX_PAD(0x408, 0x74, 2, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D23__AUD4_TXFS IOMUX_PAD(0x40c, 0x78, 5, 0x08d0, 0, 0) +#define _MX51_PAD_EIM_D23__EIM_D23 IOMUX_PAD(0x40c, 0x78, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D23__GPIO2_7 IOMUX_PAD(0x40c, 0x78, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D23__SPDIF_OUT1 IOMUX_PAD(0x40c, 0x78, 4, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D23__USBH2_DATA7 IOMUX_PAD(0x40c, 0x78, 2, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D24__AUD6_RXFS IOMUX_PAD(0x410, 0x7c, 5, 0x08f8, 0, 0) +#define _MX51_PAD_EIM_D24__EIM_D24 IOMUX_PAD(0x410, 0x7c, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D24__GPIO2_8 IOMUX_PAD(0x410, 0x7c, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D24__I2C2_SDA IOMUX_PAD(0x410, 0x7c, 0x14, 0x09bc, 0, 0) +#define _MX51_PAD_EIM_D24__UART3_CTS IOMUX_PAD(0x410, 0x7c, 3, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D24__USBOTG_DATA0 IOMUX_PAD(0x410, 0x7c, 2, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D25__EIM_D25 IOMUX_PAD(0x414, 0x80, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D25__KEY_COL6 IOMUX_PAD(0x414, 0x80, 1, 0x09c8, 0, 0) +#define _MX51_PAD_EIM_D25__UART2_CTS IOMUX_PAD(0x414, 0x80, 4, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D25__UART3_RXD IOMUX_PAD(0x414, 0x80, 3, 0x09f4, 0, 0) +#define _MX51_PAD_EIM_D25__USBOTG_DATA1 IOMUX_PAD(0x414, 0x80, 2, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D26__EIM_D26 IOMUX_PAD(0x418, 0x84, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D26__KEY_COL7 IOMUX_PAD(0x418, 0x84, 1, 0x09cc, 0, 0) +#define _MX51_PAD_EIM_D26__UART2_RTS IOMUX_PAD(0x418, 0x84, 4, 0x09e8, 3, 0) +#define _MX51_PAD_EIM_D26__UART3_TXD IOMUX_PAD(0x418, 0x84, 3, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D26__USBOTG_DATA2 IOMUX_PAD(0x418, 0x84, 2, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D27__AUD6_RXC IOMUX_PAD(0x41c, 0x88, 5, 0x08f4, 0, 0) +#define _MX51_PAD_EIM_D27__EIM_D27 IOMUX_PAD(0x41c, 0x88, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D27__GPIO2_9 IOMUX_PAD(0x41c, 0x88, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D27__I2C2_SCL IOMUX_PAD(0x41c, 0x88, 0x14, 0x09b8, 0, 0) +#define _MX51_PAD_EIM_D27__UART3_RTS IOMUX_PAD(0x41c, 0x88, 3, 0x09f0, 3, 0) +#define _MX51_PAD_EIM_D27__USBOTG_DATA3 IOMUX_PAD(0x41c, 0x88, 2, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D28__AUD6_TXD IOMUX_PAD(0x420, 0x8c, 5, 0x08f0, 0, 0) +#define _MX51_PAD_EIM_D28__EIM_D28 IOMUX_PAD(0x420, 0x8c, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D28__KEY_ROW4 IOMUX_PAD(0x420, 0x8c, 1, 0x09d0, 0, 0) +#define _MX51_PAD_EIM_D28__USBOTG_DATA4 IOMUX_PAD(0x420, 0x8c, 2, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D29__AUD6_RXD IOMUX_PAD(0x424, 0x90, 5, 0x08ec, 0, 0) +#define _MX51_PAD_EIM_D29__EIM_D29 IOMUX_PAD(0x424, 0x90, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D29__KEY_ROW5 IOMUX_PAD(0x424, 0x90, 1, 0x09d4, 0, 0) +#define _MX51_PAD_EIM_D29__USBOTG_DATA5 IOMUX_PAD(0x424, 0x90, 2, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D30__AUD6_TXC IOMUX_PAD(0x428, 0x94, 5, 0x08fc, 0, 0) +#define _MX51_PAD_EIM_D30__EIM_D30 IOMUX_PAD(0x428, 0x94, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D30__KEY_ROW6 IOMUX_PAD(0x428, 0x94, 1, 0x09d8, 0, 0) +#define _MX51_PAD_EIM_D30__USBOTG_DATA6 IOMUX_PAD(0x428, 0x94, 2, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D31__AUD6_TXFS IOMUX_PAD(0x42c, 0x98, 5, 0x0900, 0, 0) +#define _MX51_PAD_EIM_D31__EIM_D31 IOMUX_PAD(0x42c, 0x98, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D31__KEY_ROW7 IOMUX_PAD(0x42c, 0x98, 1, 0x09dc, 0, 0) +#define _MX51_PAD_EIM_D31__USBOTG_DATA7 IOMUX_PAD(0x42c, 0x98, 2, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A16__EIM_A16 IOMUX_PAD(0x430, 0x9c, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A16__GPIO2_10 IOMUX_PAD(0x430, 0x9c, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A16__OSC_FREQ_SEL0 IOMUX_PAD(0x430, 0x9c, 7, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A17__EIM_A17 IOMUX_PAD(0x434, 0xa0, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A17__GPIO2_11 IOMUX_PAD(0x434, 0xa0, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A17__OSC_FREQ_SEL1 IOMUX_PAD(0x434, 0xa0, 7, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A18__BOOT_LPB0 IOMUX_PAD(0x438, 0xa4, 7, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A18__EIM_A18 IOMUX_PAD(0x438, 0xa4, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A18__GPIO2_12 IOMUX_PAD(0x438, 0xa4, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A19__BOOT_LPB1 IOMUX_PAD(0x43c, 0xa8, 7, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A19__EIM_A19 IOMUX_PAD(0x43c, 0xa8, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A19__GPIO2_13 IOMUX_PAD(0x43c, 0xa8, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A20__BOOT_UART_SRC0 IOMUX_PAD(0x440, 0xac, 7, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A20__EIM_A20 IOMUX_PAD(0x440, 0xac, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A20__GPIO2_14 IOMUX_PAD(0x440, 0xac, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A21__BOOT_UART_SRC1 IOMUX_PAD(0x444, 0xb0, 7, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A21__EIM_A21 IOMUX_PAD(0x444, 0xb0, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A21__GPIO2_15 IOMUX_PAD(0x444, 0xb0, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A22__EIM_A22 IOMUX_PAD(0x448, 0xb4, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A22__GPIO2_16 IOMUX_PAD(0x448, 0xb4, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A23__BOOT_HPN_EN IOMUX_PAD(0x44c, 0xb8, 7, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A23__EIM_A23 IOMUX_PAD(0x44c, 0xb8, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A23__GPIO2_17 IOMUX_PAD(0x44c, 0xb8, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A24__EIM_A24 IOMUX_PAD(0x450, 0xbc, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A24__GPIO2_18 IOMUX_PAD(0x450, 0xbc, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A24__USBH2_CLK IOMUX_PAD(0x450, 0xbc, 2, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A25__DISP1_PIN4 IOMUX_PAD(0x454, 0xc0, 6, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A25__EIM_A25 IOMUX_PAD(0x454, 0xc0, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A25__GPIO2_19 IOMUX_PAD(0x454, 0xc0, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A25__USBH2_DIR IOMUX_PAD(0x454, 0xc0, 2, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A26__CSI1_DATA_EN IOMUX_PAD(0x458, 0xc4, 5, 0x09a0, 0, 0) +#define _MX51_PAD_EIM_A26__DISP2_EXT_CLK IOMUX_PAD(0x458, 0xc4, 6, 0x0908, 0, 0) +#define _MX51_PAD_EIM_A26__EIM_A26 IOMUX_PAD(0x458, 0xc4, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A26__GPIO2_20 IOMUX_PAD(0x458, 0xc4, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A26__USBH2_STP IOMUX_PAD(0x458, 0xc4, 2, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A27__CSI2_DATA_EN IOMUX_PAD(0x45c, 0xc8, 5, 0x099c, 0, 0) +#define _MX51_PAD_EIM_A27__DISP1_PIN1 IOMUX_PAD(0x45c, 0xc8, 6, 0x09a4, 0, 0) +#define _MX51_PAD_EIM_A27__EIM_A27 IOMUX_PAD(0x45c, 0xc8, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A27__GPIO2_21 IOMUX_PAD(0x45c, 0xc8, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A27__USBH2_NXT IOMUX_PAD(0x45c, 0xc8, 2, 0x0000, 0, 0) +#define _MX51_PAD_EIM_EB0__EIM_EB0 IOMUX_PAD(0x460, 0xcc, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_EB1__EIM_EB1 IOMUX_PAD(0x464, 0xd0, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_EB2__AUD5_RXFS IOMUX_PAD(0x468, 0xd4, 6, 0x08e0, 0, 0) +#define _MX51_PAD_EIM_EB2__CSI1_D2 IOMUX_PAD(0x468, 0xd4, 5, 0x0000, 0, 0) +#define _MX51_PAD_EIM_EB2__EIM_EB2 IOMUX_PAD(0x468, 0xd4, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_EB2__FEC_MDIO IOMUX_PAD(0x468, 0xd4, 3, 0x0954, 0, 0) +#define _MX51_PAD_EIM_EB2__GPIO2_22 IOMUX_PAD(0x468, 0xd4, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_EB2__GPT_CMPOUT1 IOMUX_PAD(0x468, 0xd4, 7, 0x0000, 0, 0) +#define _MX51_PAD_EIM_EB3__AUD5_RXC IOMUX_PAD(0x46c, 0xd8, 6, 0x08dc, 0, 0) +#define _MX51_PAD_EIM_EB3__CSI1_D3 IOMUX_PAD(0x46c, 0xd8, 5, 0x0000, 0, 0) +#define _MX51_PAD_EIM_EB3__EIM_EB3 IOMUX_PAD(0x46c, 0xd8, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_EB3__FEC_RDATA1 IOMUX_PAD(0x46c, 0xd8, 3, 0x095c, 0, 0) +#define _MX51_PAD_EIM_EB3__GPIO2_23 IOMUX_PAD(0x46c, 0xd8, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_EB3__GPT_CMPOUT2 IOMUX_PAD(0x46c, 0xd8, 7, 0x0000, 0, 0) +#define _MX51_PAD_EIM_OE__EIM_OE IOMUX_PAD(0x470, 0xdc, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_OE__GPIO2_24 IOMUX_PAD(0x470, 0xdc, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_CS0__EIM_CS0 IOMUX_PAD(0x474, 0xe0, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_CS0__GPIO2_25 IOMUX_PAD(0x474, 0xe0, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_CS1__EIM_CS1 IOMUX_PAD(0x478, 0xe4, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_CS1__GPIO2_26 IOMUX_PAD(0x478, 0xe4, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_CS2__AUD5_TXD IOMUX_PAD(0x47c, 0xe8, 6, 0x08d8, 1, 0) +#define _MX51_PAD_EIM_CS2__CSI1_D4 IOMUX_PAD(0x47c, 0xe8, 5, 0x0000, 0, 0) +#define _MX51_PAD_EIM_CS2__EIM_CS2 IOMUX_PAD(0x47c, 0xe8, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_CS2__FEC_RDATA2 IOMUX_PAD(0x47c, 0xe8, 3, 0x0960, 0, 0) +#define _MX51_PAD_EIM_CS2__GPIO2_27 IOMUX_PAD(0x47c, 0xe8, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_CS2__USBOTG_STP IOMUX_PAD(0x47c, 0xe8, 2, 0x0000, 0, 0) +#define _MX51_PAD_EIM_CS3__AUD5_RXD IOMUX_PAD(0x480, 0xec, 6, 0x08d4, 1, 0) +#define _MX51_PAD_EIM_CS3__CSI1_D5 IOMUX_PAD(0x480, 0xec, 5, 0x0000, 0, 0) +#define _MX51_PAD_EIM_CS3__EIM_CS3 IOMUX_PAD(0x480, 0xec, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_CS3__FEC_RDATA3 IOMUX_PAD(0x480, 0xec, 3, 0x0964, 0, 0) +#define _MX51_PAD_EIM_CS3__GPIO2_28 IOMUX_PAD(0x480, 0xec, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_CS3__USBOTG_NXT IOMUX_PAD(0x480, 0xec, 2, 0x0000, 0, 0) +#define _MX51_PAD_EIM_CS4__AUD5_TXC IOMUX_PAD(0x484, 0xf0, 6, 0x08e4, 1, 0) +#define _MX51_PAD_EIM_CS4__CSI1_D6 IOMUX_PAD(0x484, 0xf0, 5, 0x0000, 0, 0) +#define _MX51_PAD_EIM_CS4__EIM_CS4 IOMUX_PAD(0x484, 0xf0, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_CS4__FEC_RX_ER IOMUX_PAD(0x484, 0xf0, 3, 0x0970, 0, 0) +#define _MX51_PAD_EIM_CS4__GPIO2_29 IOMUX_PAD(0x484, 0xf0, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_CS4__USBOTG_CLK IOMUX_PAD(0x484, 0xf0, 2, 0x0000, 0, 0) +#define _MX51_PAD_EIM_CS5__AUD5_TXFS IOMUX_PAD(0x488, 0xf4, 6, 0x08e8, 1, 0) +#define _MX51_PAD_EIM_CS5__CSI1_D7 IOMUX_PAD(0x488, 0xf4, 5, 0x0000, 0, 0) +#define _MX51_PAD_EIM_CS5__DISP1_EXT_CLK IOMUX_PAD(0x488, 0xf4, 4, 0x0904, 0, 0) +#define _MX51_PAD_EIM_CS5__EIM_CS5 IOMUX_PAD(0x488, 0xf4, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_CS5__FEC_CRS IOMUX_PAD(0x488, 0xf4, 3, 0x0950, 0, 0) +#define _MX51_PAD_EIM_CS5__GPIO2_30 IOMUX_PAD(0x488, 0xf4, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_CS5__USBOTG_DIR IOMUX_PAD(0x488, 0xf4, 2, 0x0000, 0, 0) +#define _MX51_PAD_EIM_DTACK__EIM_DTACK IOMUX_PAD(0x48c, 0xf8, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_DTACK__GPIO2_31 IOMUX_PAD(0x48c, 0xf8, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_LBA__EIM_LBA IOMUX_PAD(0x494, 0xfc, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_LBA__GPIO3_1 IOMUX_PAD(0x494, 0xfc, 1, 0x0978, 0, 0) +#define _MX51_PAD_EIM_CRE__EIM_CRE IOMUX_PAD(0x4a0, 0x100, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_CRE__GPIO3_2 IOMUX_PAD(0x4a0, 0x100, 1, 0x097c, 0, 0) +#define _MX51_PAD_DRAM_CS1__DRAM_CS1 IOMUX_PAD(0x4d0, 0x104, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_WE_B__GPIO3_3 IOMUX_PAD(0x4e4, 0x108, 3, 0x0980, 0, 0) +#define _MX51_PAD_NANDF_WE_B__NANDF_WE_B IOMUX_PAD(0x4e4, 0x108, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_WE_B__PATA_DIOW IOMUX_PAD(0x4e4, 0x108, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_WE_B__SD3_DATA0 IOMUX_PAD(0x4e4, 0x108, 2, 0x093c, 0, 0) +#define _MX51_PAD_NANDF_RE_B__GPIO3_4 IOMUX_PAD(0x4e8, 0x10c, 3, 0x0984, 0, 0) +#define _MX51_PAD_NANDF_RE_B__NANDF_RE_B IOMUX_PAD(0x4e8, 0x10c, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_RE_B__PATA_DIOR IOMUX_PAD(0x4e8, 0x10c, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_RE_B__SD3_DATA1 IOMUX_PAD(0x4e8, 0x10c, 2, 0x0940, 0, 0) +#define _MX51_PAD_NANDF_ALE__GPIO3_5 IOMUX_PAD(0x4ec, 0x110, 3, 0x0988, 0, 0) +#define _MX51_PAD_NANDF_ALE__NANDF_ALE IOMUX_PAD(0x4ec, 0x110, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_ALE__PATA_BUFFER_EN IOMUX_PAD(0x4ec, 0x110, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CLE__GPIO3_6 IOMUX_PAD(0x4f0, 0x114, 3, 0x098c, 0, 0) +#define _MX51_PAD_NANDF_CLE__NANDF_CLE IOMUX_PAD(0x4f0, 0x114, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CLE__PATA_RESET_B IOMUX_PAD(0x4f0, 0x114, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_WP_B__GPIO3_7 IOMUX_PAD(0x4f4, 0x118, 3, 0x0990, 0, 0) +#define _MX51_PAD_NANDF_WP_B__NANDF_WP_B IOMUX_PAD(0x4f4, 0x118, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_WP_B__PATA_DMACK IOMUX_PAD(0x4f4, 0x118, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_WP_B__SD3_DATA2 IOMUX_PAD(0x4f4, 0x118, 2, 0x0944, 0, 0) +#define _MX51_PAD_NANDF_RB0__ECSPI2_SS1 IOMUX_PAD(0x4f8, 0x11c, 5, 0x0930, 0, 0) +#define _MX51_PAD_NANDF_RB0__GPIO3_8 IOMUX_PAD(0x4f8, 0x11c, 3, 0x0994, 0, 0) +#define _MX51_PAD_NANDF_RB0__NANDF_RB0 IOMUX_PAD(0x4f8, 0x11c, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_RB0__PATA_DMARQ IOMUX_PAD(0x4f8, 0x11c, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_RB0__SD3_DATA3 IOMUX_PAD(0x4f8, 0x11c, 2, 0x0948, 0, 0) +#define _MX51_PAD_NANDF_RB1__CSPI_MOSI IOMUX_PAD(0x4fc, 0x120, 6, 0x091c, 0, 0) +#define _MX51_PAD_NANDF_RB1__ECSPI2_RDY IOMUX_PAD(0x4fc, 0x120, 2, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_RB1__GPIO3_9 IOMUX_PAD(0x4fc, 0x120, 3, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_RB1__NANDF_RB1 IOMUX_PAD(0x4fc, 0x120, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_RB1__PATA_IORDY IOMUX_PAD(0x4fc, 0x120, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_RB1__SD4_CMD IOMUX_PAD(0x4fc, 0x120, 5, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_RB2__DISP2_WAIT IOMUX_PAD(0x500, 0x124, 5, 0x09a8, 0, 0) +#define _MX51_PAD_NANDF_RB2__ECSPI2_SCLK IOMUX_PAD(0x500, 0x124, 2, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_RB2__FEC_COL IOMUX_PAD(0x500, 0x124, 1, 0x094c, 0, 0) +#define _MX51_PAD_NANDF_RB2__GPIO3_10 IOMUX_PAD(0x500, 0x124, 3, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_RB2__NANDF_RB2 IOMUX_PAD(0x500, 0x124, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_RB2__USBH3_H3_DP IOMUX_PAD(0x500, 0x124, 7, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_RB2__USBH3_NXT IOMUX_PAD(0x500, 0x124, 6, 0x0a20, 0, 0) +#define _MX51_PAD_NANDF_RB3__DISP1_WAIT IOMUX_PAD(0x504, 0x128, 5, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_RB3__ECSPI2_MISO IOMUX_PAD(0x504, 0x128, 2, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_RB3__FEC_RX_CLK IOMUX_PAD(0x504, 0x128, 1, 0x0968, 0, 0) +#define _MX51_PAD_NANDF_RB3__GPIO3_11 IOMUX_PAD(0x504, 0x128, 3, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_RB3__NANDF_RB3 IOMUX_PAD(0x504, 0x128, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_RB3__USBH3_CLK IOMUX_PAD(0x504, 0x128, 6, 0x09f8, 0, 0) +#define _MX51_PAD_NANDF_RB3__USBH3_H3_DM IOMUX_PAD(0x504, 0x128, 7, 0x0000, 0, 0) +#define _MX51_PAD_GPIO_NAND__GPIO_NAND IOMUX_PAD(0x514, 0x12c, 0, 0x0998, 0, 0) +#define _MX51_PAD_GPIO_NAND__PATA_INTRQ IOMUX_PAD(0x514, 0x12c, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS0__GPIO3_16 IOMUX_PAD(0x518, 0x130, 3, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS0__NANDF_CS0 IOMUX_PAD(0x518, 0x130, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS1__GPIO3_17 IOMUX_PAD(0x51c, 0x134, 3, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS1__NANDF_CS1 IOMUX_PAD(0x51c, 0x134, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS2__CSPI_SCLK IOMUX_PAD(0x520, 0x138, 6, 0x0914, 0, 0) +#define _MX51_PAD_NANDF_CS2__FEC_TX_ER IOMUX_PAD(0x520, 0x138, 2, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS2__GPIO3_18 IOMUX_PAD(0x520, 0x138, 3, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS2__NANDF_CS2 IOMUX_PAD(0x520, 0x138, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS2__PATA_CS_0 IOMUX_PAD(0x520, 0x138, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS2__SD4_CLK IOMUX_PAD(0x520, 0x138, 5, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS2__USBH3_H1_DP IOMUX_PAD(0x520, 0x138, 7, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS3__FEC_MDC IOMUX_PAD(0x524, 0x13c, 2, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS3__GPIO3_19 IOMUX_PAD(0x524, 0x13c, 3, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS3__NANDF_CS3 IOMUX_PAD(0x524, 0x13c, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS3__PATA_CS_1 IOMUX_PAD(0x524, 0x13c, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS3__SD4_DAT0 IOMUX_PAD(0x524, 0x13c, 5, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS3__USBH3_H1_DM IOMUX_PAD(0x524, 0x13c, 7, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS4__FEC_TDATA1 IOMUX_PAD(0x528, 0x140, 2, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS4__GPIO3_20 IOMUX_PAD(0x528, 0x140, 3, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS4__NANDF_CS4 IOMUX_PAD(0x528, 0x140, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS4__PATA_DA_0 IOMUX_PAD(0x528, 0x140, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS4__SD4_DAT1 IOMUX_PAD(0x528, 0x140, 5, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS4__USBH3_STP IOMUX_PAD(0x528, 0x140, 7, 0x0a24, 0, 0) +#define _MX51_PAD_NANDF_CS5__FEC_TDATA2 IOMUX_PAD(0x52c, 0x144, 2, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS5__GPIO3_21 IOMUX_PAD(0x52c, 0x144, 3, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS5__NANDF_CS5 IOMUX_PAD(0x52c, 0x144, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS5__PATA_DA_1 IOMUX_PAD(0x52c, 0x144, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS5__SD4_DAT2 IOMUX_PAD(0x52c, 0x144, 5, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS5__USBH3_DIR IOMUX_PAD(0x52c, 0x144, 7, 0x0a1c, 0, 0) +#define _MX51_PAD_NANDF_CS6__CSPI_SS3 IOMUX_PAD(0x530, 0x148, 7, 0x0928, 0, 0) +#define _MX51_PAD_NANDF_CS6__FEC_TDATA3 IOMUX_PAD(0x530, 0x148, 2, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS6__GPIO3_22 IOMUX_PAD(0x530, 0x148, 3, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS6__NANDF_CS6 IOMUX_PAD(0x530, 0x148, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS6__PATA_DA_2 IOMUX_PAD(0x530, 0x148, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS6__SD4_DAT3 IOMUX_PAD(0x530, 0x148, 5, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS7__FEC_TX_EN IOMUX_PAD(0x534, 0x14c, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS7__GPIO3_23 IOMUX_PAD(0x534, 0x14c, 3, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS7__NANDF_CS7 IOMUX_PAD(0x534, 0x14c, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS7__SD3_CLK IOMUX_PAD(0x534, 0x14c, 5, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0 IOMUX_PAD(0x538, 0x150, 2, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK IOMUX_PAD(0x538, 0x150, 1, 0x0974, 0, 0) +#define _MX51_PAD_NANDF_RDY_INT__GPIO3_24 IOMUX_PAD(0x538, 0x150, 3, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT IOMUX_PAD(0x538, 0x150, 0, 0x0938, 0, 0) +#define _MX51_PAD_NANDF_RDY_INT__SD3_CMD IOMUX_PAD(0x538, 0x150, 5, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D15__ECSPI2_MOSI IOMUX_PAD(0x53c, 0x154, 2, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D15__GPIO3_25 IOMUX_PAD(0x53c, 0x154, 3, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D15__NANDF_D15 IOMUX_PAD(0x53c, 0x154, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D15__PATA_DATA15 IOMUX_PAD(0x53c, 0x154, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D15__SD3_DAT7 IOMUX_PAD(0x53c, 0x154, 5, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D14__ECSPI2_SS3 IOMUX_PAD(0x540, 0x158, 2, 0x0934, 0, 0) +#define _MX51_PAD_NANDF_D14__GPIO3_26 IOMUX_PAD(0x540, 0x158, 3, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D14__NANDF_D14 IOMUX_PAD(0x540, 0x158, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D14__PATA_DATA14 IOMUX_PAD(0x540, 0x158, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D14__SD3_DAT6 IOMUX_PAD(0x540, 0x158, 5, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D13__ECSPI2_SS2 IOMUX_PAD(0x544, 0x15c, 2, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D13__GPIO3_27 IOMUX_PAD(0x544, 0x15c, 3, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D13__NANDF_D13 IOMUX_PAD(0x544, 0x15c, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D13__PATA_DATA13 IOMUX_PAD(0x544, 0x15c, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D13__SD3_DAT5 IOMUX_PAD(0x544, 0x15c, 5, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D12__ECSPI2_SS1 IOMUX_PAD(0x548, 0x160, 2, 0x0930, 1, 0) +#define _MX51_PAD_NANDF_D12__GPIO3_28 IOMUX_PAD(0x548, 0x160, 3, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D12__NANDF_D12 IOMUX_PAD(0x548, 0x160, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D12__PATA_DATA12 IOMUX_PAD(0x548, 0x160, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D12__SD3_DAT4 IOMUX_PAD(0x548, 0x160, 5, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D11__FEC_RX_DV IOMUX_PAD(0x54c, 0x164, 2, 0x096c, 0, 0) +#define _MX51_PAD_NANDF_D11__GPIO3_29 IOMUX_PAD(0x54c, 0x164, 3, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D11__NANDF_D11 IOMUX_PAD(0x54c, 0x164, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D11__PATA_DATA11 IOMUX_PAD(0x54c, 0x164, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D11__SD3_DATA3 IOMUX_PAD(0x54c, 0x164, 5, 0x0948, 1, 0) +#define _MX51_PAD_NANDF_D10__GPIO3_30 IOMUX_PAD(0x550, 0x168, 3, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D10__NANDF_D10 IOMUX_PAD(0x550, 0x168, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D10__PATA_DATA10 IOMUX_PAD(0x550, 0x168, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D10__SD3_DATA2 IOMUX_PAD(0x550, 0x168, 5, 0x0944, 1, 0) +#define _MX51_PAD_NANDF_D9__FEC_RDATA0 IOMUX_PAD(0x554, 0x16c, 0x12, 0x0958, 0, 0) +#define _MX51_PAD_NANDF_D9__GPIO3_31 IOMUX_PAD(0x554, 0x16c, 3, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D9__NANDF_D9 IOMUX_PAD(0x554, 0x16c, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D9__PATA_DATA9 IOMUX_PAD(0x554, 0x16c, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D9__SD3_DATA1 IOMUX_PAD(0x554, 0x16c, 5, 0x0940, 1, 0) +#define _MX51_PAD_NANDF_D8__FEC_TDATA0 IOMUX_PAD(0x558, 0x170, 2, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D8__GPIO4_0 IOMUX_PAD(0x558, 0x170, 3, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D8__NANDF_D8 IOMUX_PAD(0x558, 0x170, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D8__PATA_DATA8 IOMUX_PAD(0x558, 0x170, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D8__SD3_DATA0 IOMUX_PAD(0x558, 0x170, 5, 0x093c, 1, 0) +#define _MX51_PAD_NANDF_D7__GPIO4_1 IOMUX_PAD(0x55c, 0x174, 3, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D7__NANDF_D7 IOMUX_PAD(0x55c, 0x174, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D7__PATA_DATA7 IOMUX_PAD(0x55c, 0x174, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D7__USBH3_DATA0 IOMUX_PAD(0x55c, 0x174, 5, 0x09fc, 0, 0) +#define _MX51_PAD_NANDF_D6__GPIO4_2 IOMUX_PAD(0x560, 0x178, 3, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D6__NANDF_D6 IOMUX_PAD(0x560, 0x178, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D6__PATA_DATA6 IOMUX_PAD(0x560, 0x178, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D6__SD4_LCTL IOMUX_PAD(0x560, 0x178, 2, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D6__USBH3_DATA1 IOMUX_PAD(0x560, 0x178, 5, 0x0a00, 0, 0) +#define _MX51_PAD_NANDF_D5__GPIO4_3 IOMUX_PAD(0x564, 0x17c, 3, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D5__NANDF_D5 IOMUX_PAD(0x564, 0x17c, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D5__PATA_DATA5 IOMUX_PAD(0x564, 0x17c, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D5__SD4_WP IOMUX_PAD(0x564, 0x17c, 2, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D5__USBH3_DATA2 IOMUX_PAD(0x564, 0x17c, 5, 0x0a04, 0, 0) +#define _MX51_PAD_NANDF_D4__GPIO4_4 IOMUX_PAD(0x568, 0x180, 3, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D4__NANDF_D4 IOMUX_PAD(0x568, 0x180, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D4__PATA_DATA4 IOMUX_PAD(0x568, 0x180, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D4__SD4_CD IOMUX_PAD(0x568, 0x180, 2, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D4__USBH3_DATA3 IOMUX_PAD(0x568, 0x180, 5, 0x0a08, 0, 0) +#define _MX51_PAD_NANDF_D3__GPIO4_5 IOMUX_PAD(0x56c, 0x184, 3, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D3__NANDF_D3 IOMUX_PAD(0x56c, 0x184, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D3__PATA_DATA3 IOMUX_PAD(0x56c, 0x184, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D3__SD4_DAT4 IOMUX_PAD(0x56c, 0x184, 2, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D3__USBH3_DATA4 IOMUX_PAD(0x56c, 0x184, 5, 0x0a0c, 0, 0) +#define _MX51_PAD_NANDF_D2__GPIO4_6 IOMUX_PAD(0x570, 0x188, 3, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D2__NANDF_D2 IOMUX_PAD(0x570, 0x188, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D2__PATA_DATA2 IOMUX_PAD(0x570, 0x188, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D2__SD4_DAT5 IOMUX_PAD(0x570, 0x188, 2, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D2__USBH3_DATA5 IOMUX_PAD(0x570, 0x188, 5, 0x0a10, 0, 0) +#define _MX51_PAD_NANDF_D1__GPIO4_7 IOMUX_PAD(0x574, 0x18c, 3, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D1__NANDF_D1 IOMUX_PAD(0x574, 0x18c, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D1__PATA_DATA1 IOMUX_PAD(0x574, 0x18c, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D1__SD4_DAT6 IOMUX_PAD(0x574, 0x18c, 2, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D1__USBH3_DATA6 IOMUX_PAD(0x574, 0x18c, 5, 0x0a14, 0, 0) +#define _MX51_PAD_NANDF_D0__GPIO4_8 IOMUX_PAD(0x578, 0x190, 3, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D0__NANDF_D0 IOMUX_PAD(0x578, 0x190, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D0__PATA_DATA0 IOMUX_PAD(0x578, 0x190, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D0__SD4_DAT7 IOMUX_PAD(0x578, 0x190, 2, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D0__USBH3_DATA7 IOMUX_PAD(0x578, 0x190, 5, 0x0a18, 0, 0) +#define _MX51_PAD_CSI1_D8__CSI1_D8 IOMUX_PAD(0x57c, 0x194, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSI1_D8__GPIO3_12 IOMUX_PAD(0x57c, 0x194, 3, 0x0998, 1, 0) +#define _MX51_PAD_CSI1_D9__CSI1_D9 IOMUX_PAD(0x580, 0x198, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSI1_D9__GPIO3_13 IOMUX_PAD(0x580, 0x198, 3, 0x0000, 0, 0) +#define _MX51_PAD_CSI1_D10__CSI1_D10 IOMUX_PAD(0x584, 0x19c, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSI1_D11__CSI1_D11 IOMUX_PAD(0x588, 0x1a0, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSI1_D12__CSI1_D12 IOMUX_PAD(0x58c, 0x1a4, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSI1_D13__CSI1_D13 IOMUX_PAD(0x590, 0x1a8, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSI1_D14__CSI1_D14 IOMUX_PAD(0x594, 0x1ac, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSI1_D15__CSI1_D15 IOMUX_PAD(0x598, 0x1b0, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSI1_D16__CSI1_D16 IOMUX_PAD(0x59c, 0x1b4, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSI1_D17__CSI1_D17 IOMUX_PAD(0x5a0, 0x1b8, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSI1_D18__CSI1_D18 IOMUX_PAD(0x5a4, 0x1bc, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSI1_D19__CSI1_D19 IOMUX_PAD(0x5a8, 0x1c0, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSI1_VSYNC__CSI1_VSYNC IOMUX_PAD(0x5ac, 0x1c4, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSI1_VSYNC__GPIO3_14 IOMUX_PAD(0x5ac, 0x1c4, 3, 0x0000, 0, 0) +#define _MX51_PAD_CSI1_HSYNC__CSI1_HSYNC IOMUX_PAD(0x5b0, 0x1c8, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSI1_HSYNC__GPIO3_15 IOMUX_PAD(0x5b0, 0x1c8, 3, 0x0000, 0, 0) +#define _MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK IOMUX_PAD(0x5b4, 0x000, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSI1_MCLK__CSI1_MCLK IOMUX_PAD(0x5b8, 0x000, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSI2_D12__CSI2_D12 IOMUX_PAD(0x5bc, 0x1cc, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSI2_D12__GPIO4_9 IOMUX_PAD(0x5bc, 0x1cc, 3, 0x0000, 0, 0) +#define _MX51_PAD_CSI2_D13__CSI2_D13 IOMUX_PAD(0x5c0, 0x1d0, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSI2_D13__GPIO4_10 IOMUX_PAD(0x5c0, 0x1d0, 3, 0x0000, 0, 0) +#define _MX51_PAD_CSI2_D14__CSI2_D14 IOMUX_PAD(0x5c4, 0x1d4, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSI2_D15__CSI2_D15 IOMUX_PAD(0x5c8, 0x1d8, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSI2_D16__CSI2_D16 IOMUX_PAD(0x5cc, 0x1dc, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSI2_D17__CSI2_D17 IOMUX_PAD(0x5d0, 0x1e0, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSI2_D18__CSI2_D18 IOMUX_PAD(0x5d4, 0x1e4, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSI2_D18__GPIO4_11 IOMUX_PAD(0x5d4, 0x1e4, 3, 0x0000, 0, 0) +#define _MX51_PAD_CSI2_D19__CSI2_D19 IOMUX_PAD(0x5d8, 0x1e8, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSI2_D19__GPIO4_12 IOMUX_PAD(0x5d8, 0x1e8, 3, 0x0000, 0, 0) +#define _MX51_PAD_CSI2_VSYNC__CSI2_VSYNC IOMUX_PAD(0x5dc, 0x1ec, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSI2_VSYNC__GPIO4_13 IOMUX_PAD(0x5dc, 0x1ec, 3, 0x0000, 0, 0) +#define _MX51_PAD_CSI2_HSYNC__CSI2_HSYNC IOMUX_PAD(0x5e0, 0x1f0, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSI2_HSYNC__GPIO4_14 IOMUX_PAD(0x5e0, 0x1f0, 3, 0x0000, 0, 0) +#define _MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK IOMUX_PAD(0x5e4, 0x1f4, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSI2_PIXCLK__GPIO4_15 IOMUX_PAD(0x5e4, 0x1f4, 3, 0x0000, 0, 0) +#define _MX51_PAD_I2C1_CLK__GPIO4_16 IOMUX_PAD(0x5e8, 0x1f8, 3, 0x0000, 0, 0) +#define _MX51_PAD_I2C1_CLK__I2C1_CLK IOMUX_PAD(0x5e8, 0x1f8, 0x10, 0x0000, 0, 0) +#define _MX51_PAD_I2C1_DAT__GPIO4_17 IOMUX_PAD(0x5ec, 0x1fc, 3, 0x0000, 0, 0) +#define _MX51_PAD_I2C1_DAT__I2C1_DAT IOMUX_PAD(0x5ec, 0x1fc, 0x10, 0x0000, 0, 0) +#define _MX51_PAD_AUD3_BB_TXD__AUD3_TXD IOMUX_PAD(0x5f0, 0x200, 0, 0x0000, 0, 0) +#define _MX51_PAD_AUD3_BB_TXD__GPIO4_18 IOMUX_PAD(0x5f0, 0x200, 3, 0x0000, 0, 0) +#define _MX51_PAD_AUD3_BB_RXD__AUD3_RXD IOMUX_PAD(0x5f4, 0x204, 0, 0x0000, 0, 0) +#define _MX51_PAD_AUD3_BB_RXD__GPIO4_19 IOMUX_PAD(0x5f4, 0x204, 3, 0x0000, 0, 0) +#define _MX51_PAD_AUD3_BB_RXD__UART3_RXD IOMUX_PAD(0x5f4, 0x204, 1, 0x09f4, 2, 0) +#define _MX51_PAD_AUD3_BB_CK__AUD3_TXC IOMUX_PAD(0x5f8, 0x208, 0, 0x0000, 0, 0) +#define _MX51_PAD_AUD3_BB_CK__GPIO4_20 IOMUX_PAD(0x5f8, 0x208, 3, 0x0000, 0, 0) +#define _MX51_PAD_AUD3_BB_FS__AUD3_TXFS IOMUX_PAD(0x5fc, 0x20c, 0, 0x0000, 0, 0) +#define _MX51_PAD_AUD3_BB_FS__GPIO4_21 IOMUX_PAD(0x5fc, 0x20c, 3, 0x0000, 0, 0) +#define _MX51_PAD_AUD3_BB_FS__UART3_TXD IOMUX_PAD(0x5fc, 0x20c, 1, 0x0000, 0, 0) +#define _MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI IOMUX_PAD(0x600, 0x210, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSPI1_MOSI__GPIO4_22 IOMUX_PAD(0x600, 0x210, 3, 0x0000, 0, 0) +#define _MX51_PAD_CSPI1_MOSI__I2C1_SDA IOMUX_PAD(0x600, 0x210, 0x11, 0x09b4, 1, 0) +#define _MX51_PAD_CSPI1_MISO__AUD4_RXD IOMUX_PAD(0x604, 0x214, 1, 0x08c4, 1, 0) +#define _MX51_PAD_CSPI1_MISO__ECSPI1_MISO IOMUX_PAD(0x604, 0x214, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSPI1_MISO__GPIO4_23 IOMUX_PAD(0x604, 0x214, 3, 0x0000, 0, 0) +#define _MX51_PAD_CSPI1_SS0__AUD4_TXC IOMUX_PAD(0x608, 0x218, 1, 0x08cc, 1, 0) +#define _MX51_PAD_CSPI1_SS0__ECSPI1_SS0 IOMUX_PAD(0x608, 0x218, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSPI1_SS0__GPIO4_24 IOMUX_PAD(0x608, 0x218, 3, 0x0000, 0, 0) +#define _MX51_PAD_CSPI1_SS1__AUD4_TXD IOMUX_PAD(0x60c, 0x21c, 1, 0x08c8, 1, 0) +#define _MX51_PAD_CSPI1_SS1__ECSPI1_SS1 IOMUX_PAD(0x60c, 0x21c, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSPI1_SS1__GPIO4_25 IOMUX_PAD(0x60c, 0x21c, 3, 0x0000, 0, 0) +#define _MX51_PAD_CSPI1_RDY__AUD4_TXFS IOMUX_PAD(0x610, 0x220, 1, 0x08d0, 1, 0) +#define _MX51_PAD_CSPI1_RDY__ECSPI1_RDY IOMUX_PAD(0x610, 0x220, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSPI1_RDY__GPIO4_26 IOMUX_PAD(0x610, 0x220, 3, 0x0000, 0, 0) +#define _MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK IOMUX_PAD(0x614, 0x224, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSPI1_SCLK__GPIO4_27 IOMUX_PAD(0x614, 0x224, 3, 0x0000, 0, 0) +#define _MX51_PAD_CSPI1_SCLK__I2C1_SCL IOMUX_PAD(0x614, 0x224, 0x11, 0x09b0, 1, 0) +#define _MX51_PAD_UART1_RXD__GPIO4_28 IOMUX_PAD(0x618, 0x228, 3, 0x0000, 0, 0) +#define _MX51_PAD_UART1_RXD__UART1_RXD IOMUX_PAD(0x618, 0x228, 0, 0x09e4, 0, 0) +#define _MX51_PAD_UART1_TXD__GPIO4_29 IOMUX_PAD(0x61c, 0x22c, 3, 0x0000, 0, 0) +#define _MX51_PAD_UART1_TXD__PWM2_PWMO IOMUX_PAD(0x61c, 0x22c, 1, 0x0000, 0, 0) +#define _MX51_PAD_UART1_TXD__UART1_TXD IOMUX_PAD(0x61c, 0x22c, 0, 0x0000, 0, 0) +#define _MX51_PAD_UART1_RTS__GPIO4_30 IOMUX_PAD(0x620, 0x230, 3, 0x0000, 0, 0) +#define _MX51_PAD_UART1_RTS__UART1_RTS IOMUX_PAD(0x620, 0x230, 0, 0x09e0, 0, 0) +#define _MX51_PAD_UART1_CTS__GPIO4_31 IOMUX_PAD(0x624, 0x234, 3, 0x0000, 0, 0) +#define _MX51_PAD_UART1_CTS__UART1_CTS IOMUX_PAD(0x624, 0x234, 0, 0x0000, 0, 0) +#define _MX51_PAD_UART2_RXD__FIRI_TXD IOMUX_PAD(0x628, 0x238, 1, 0x0000, 0, 0) +#define _MX51_PAD_UART2_RXD__GPIO1_20 IOMUX_PAD(0x628, 0x238, 3, 0x0000, 0, 0) +#define _MX51_PAD_UART2_RXD__UART2_RXD IOMUX_PAD(0x628, 0x238, 0, 0x09ec, 2, 0) +#define _MX51_PAD_UART2_TXD__FIRI_RXD IOMUX_PAD(0x62c, 0x23c, 1, 0x0000, 0, 0) +#define _MX51_PAD_UART2_TXD__GPIO1_21 IOMUX_PAD(0x62c, 0x23c, 3, 0x0000, 0, 0) +#define _MX51_PAD_UART2_TXD__UART2_TXD IOMUX_PAD(0x62c, 0x23c, 0, 0x0000, 0, 0) +#define _MX51_PAD_UART3_RXD__CSI1_D0 IOMUX_PAD(0x630, 0x240, 2, 0x0000, 0, 0) +#define _MX51_PAD_UART3_RXD__GPIO1_22 IOMUX_PAD(0x630, 0x240, 3, 0x0000, 0, 0) +#define _MX51_PAD_UART3_RXD__UART1_DTR IOMUX_PAD(0x630, 0x240, 0, 0x0000, 0, 0) +#define _MX51_PAD_UART3_RXD__UART3_RXD IOMUX_PAD(0x630, 0x240, 1, 0x09f4, 4, 0) +#define _MX51_PAD_UART3_TXD__CSI1_D1 IOMUX_PAD(0x634, 0x244, 2, 0x0000, 0, 0) +#define _MX51_PAD_UART3_TXD__GPIO1_23 IOMUX_PAD(0x634, 0x244, 3, 0x0000, 0, 0) +#define _MX51_PAD_UART3_TXD__UART1_DSR IOMUX_PAD(0x634, 0x244, 0, 0x0000, 0, 0) +#define _MX51_PAD_UART3_TXD__UART3_TXD IOMUX_PAD(0x634, 0x244, 1, 0x0000, 0, 0) +#define _MX51_PAD_OWIRE_LINE__GPIO1_24 IOMUX_PAD(0x638, 0x248, 3, 0x0000, 0, 0) +#define _MX51_PAD_OWIRE_LINE__OWIRE_LINE IOMUX_PAD(0x638, 0x248, 0, 0x0000, 0, 0) +#define _MX51_PAD_OWIRE_LINE__SPDIF_OUT IOMUX_PAD(0x638, 0x248, 6, 0x0000, 0, 0) +#define _MX51_PAD_KEY_ROW0__KEY_ROW0 IOMUX_PAD(0x63c, 0x24c, 0, 0x0000, 0, 0) +#define _MX51_PAD_KEY_ROW1__KEY_ROW1 IOMUX_PAD(0x640, 0x250, 0, 0x0000, 0, 0) +#define _MX51_PAD_KEY_ROW2__KEY_ROW2 IOMUX_PAD(0x644, 0x254, 0, 0x0000, 0, 0) +#define _MX51_PAD_KEY_ROW3__KEY_ROW3 IOMUX_PAD(0x648, 0x258, 0, 0x0000, 0, 0) +#define _MX51_PAD_KEY_COL0__KEY_COL0 IOMUX_PAD(0x64c, 0x25c, 0, 0x0000, 0, 0) +#define _MX51_PAD_KEY_COL0__PLL1_BYP IOMUX_PAD(0x64c, 0x25c, 7, 0x090c, 0, 0) +#define _MX51_PAD_KEY_COL1__KEY_COL1 IOMUX_PAD(0x650, 0x260, 0, 0x0000, 0, 0) +#define _MX51_PAD_KEY_COL1__PLL2_BYP IOMUX_PAD(0x650, 0x260, 7, 0x0910, 0, 0) +#define _MX51_PAD_KEY_COL2__KEY_COL2 IOMUX_PAD(0x654, 0x264, 0, 0x0000, 0, 0) +#define _MX51_PAD_KEY_COL2__PLL3_BYP IOMUX_PAD(0x654, 0x264, 7, 0x0000, 0, 0) +#define _MX51_PAD_KEY_COL3__KEY_COL3 IOMUX_PAD(0x658, 0x268, 0, 0x0000, 0, 0) +#define _MX51_PAD_KEY_COL4__I2C2_SCL IOMUX_PAD(0x65c, 0x26c, 0x13, 0x09b8, 1, 0) +#define _MX51_PAD_KEY_COL4__KEY_COL4 IOMUX_PAD(0x65c, 0x26c, 0, 0x0000, 0, 0) +#define _MX51_PAD_KEY_COL4__SPDIF_OUT1 IOMUX_PAD(0x65c, 0x26c, 6, 0x0000, 0, 0) +#define _MX51_PAD_KEY_COL4__UART1_RI IOMUX_PAD(0x65c, 0x26c, 1, 0x0000, 0, 0) +#define _MX51_PAD_KEY_COL4__UART3_RTS IOMUX_PAD(0x65c, 0x26c, 2, 0x09f0, 4, 0) +#define _MX51_PAD_KEY_COL5__I2C2_SDA IOMUX_PAD(0x660, 0x270, 0x13, 0x09bc, 1, 0) +#define _MX51_PAD_KEY_COL5__KEY_COL5 IOMUX_PAD(0x660, 0x270, 0, 0x0000, 0, 0) +#define _MX51_PAD_KEY_COL5__UART1_DCD IOMUX_PAD(0x660, 0x270, 1, 0x0000, 0, 0) +#define _MX51_PAD_KEY_COL5__UART3_CTS IOMUX_PAD(0x660, 0x270, 2, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_CLK__CSPI_SCLK IOMUX_PAD(0x678, 0x278, 1, 0x0914, 1, 0) +#define _MX51_PAD_USBH1_CLK__GPIO1_25 IOMUX_PAD(0x678, 0x278, 2, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_CLK__I2C2_SCL IOMUX_PAD(0x678, 0x278, 0x15, 0x09b8, 2, 0) +#define _MX51_PAD_USBH1_CLK__USBH1_CLK IOMUX_PAD(0x678, 0x278, 0, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_DIR__CSPI_MOSI IOMUX_PAD(0x67c, 0x27c, 1, 0x091c, 1, 0) +#define _MX51_PAD_USBH1_DIR__GPIO1_26 IOMUX_PAD(0x67c, 0x27c, 2, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_DIR__I2C2_SDA IOMUX_PAD(0x67c, 0x27c, 0x15, 0x09bc, 2, 0) +#define _MX51_PAD_USBH1_DIR__USBH1_DIR IOMUX_PAD(0x67c, 0x27c, 0, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_STP__CSPI_RDY IOMUX_PAD(0x680, 0x280, 1, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_STP__GPIO1_27 IOMUX_PAD(0x680, 0x280, 2, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_STP__UART3_RXD IOMUX_PAD(0x680, 0x280, 5, 0x09f4, 6, 0) +#define _MX51_PAD_USBH1_STP__USBH1_STP IOMUX_PAD(0x680, 0x280, 0, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_NXT__CSPI_MISO IOMUX_PAD(0x684, 0x284, 1, 0x0918, 0, 0) +#define _MX51_PAD_USBH1_NXT__GPIO1_28 IOMUX_PAD(0x684, 0x284, 2, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_NXT__UART3_TXD IOMUX_PAD(0x684, 0x284, 5, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_NXT__USBH1_NXT IOMUX_PAD(0x684, 0x284, 0, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_DATA0__GPIO1_11 IOMUX_PAD(0x688, 0x288, 2, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_DATA0__UART2_CTS IOMUX_PAD(0x688, 0x288, 1, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_DATA0__USBH1_DATA0 IOMUX_PAD(0x688, 0x288, 0, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_DATA1__GPIO1_12 IOMUX_PAD(0x68c, 0x28c, 2, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_DATA1__UART2_RXD IOMUX_PAD(0x68c, 0x28c, 1, 0x09ec, 4, 0) +#define _MX51_PAD_USBH1_DATA1__USBH1_DATA1 IOMUX_PAD(0x68c, 0x28c, 0, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_DATA2__GPIO1_13 IOMUX_PAD(0x690, 0x290, 2, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_DATA2__UART2_TXD IOMUX_PAD(0x690, 0x290, 1, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_DATA2__USBH1_DATA2 IOMUX_PAD(0x690, 0x290, 0, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_DATA3__GPIO1_14 IOMUX_PAD(0x694, 0x294, 2, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_DATA3__UART2_RTS IOMUX_PAD(0x694, 0x294, 1, 0x09e8, 5, 0) +#define _MX51_PAD_USBH1_DATA3__USBH1_DATA3 IOMUX_PAD(0x694, 0x294, 0, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_DATA4__CSPI_SS0 IOMUX_PAD(0x698, 0x298, 1, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_DATA4__GPIO1_15 IOMUX_PAD(0x698, 0x298, 2, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_DATA4__USBH1_DATA4 IOMUX_PAD(0x698, 0x298, 0, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_DATA5__CSPI_SS1 IOMUX_PAD(0x69c, 0x29c, 1, 0x0920, 0, 0) +#define _MX51_PAD_USBH1_DATA5__GPIO1_16 IOMUX_PAD(0x69c, 0x29c, 2, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_DATA5__USBH1_DATA5 IOMUX_PAD(0x69c, 0x29c, 0, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_DATA6__CSPI_SS3 IOMUX_PAD(0x6a0, 0x2a0, 1, 0x0928, 1, 0) +#define _MX51_PAD_USBH1_DATA6__GPIO1_17 IOMUX_PAD(0x6a0, 0x2a0, 2, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_DATA6__USBH1_DATA6 IOMUX_PAD(0x6a0, 0x2a0, 0, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_DATA7__ECSPI1_SS3 IOMUX_PAD(0x6a4, 0x2a4, 1, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_DATA7__ECSPI2_SS3 IOMUX_PAD(0x6a4, 0x2a4, 5, 0x0934, 1, 0) +#define _MX51_PAD_USBH1_DATA7__GPIO1_18 IOMUX_PAD(0x6a4, 0x2a4, 2, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_DATA7__USBH1_DATA7 IOMUX_PAD(0x6a4, 0x2a4, 0, 0x0000, 0, 0) +#define _MX51_PAD_DI1_PIN11__DI1_PIN11 IOMUX_PAD(0x6a8, 0x2a8, 0, 0x0000, 0, 0) +#define _MX51_PAD_DI1_PIN11__ECSPI1_SS2 IOMUX_PAD(0x6a8, 0x2a8, 7, 0x0000, 0, 0) +#define _MX51_PAD_DI1_PIN11__GPIO3_0 IOMUX_PAD(0x6a8, 0x2a8, 4, 0x0000, 0, 0) +#define _MX51_PAD_DI1_PIN12__DI1_PIN12 IOMUX_PAD(0x6ac, 0x2ac, 0, 0x0000, 0, 0) +#define _MX51_PAD_DI1_PIN12__GPIO3_1 IOMUX_PAD(0x6ac, 0x2ac, 4, 0x0978, 1, 0) +#define _MX51_PAD_DI1_PIN13__DI1_PIN13 IOMUX_PAD(0x6b0, 0x2b0, 0, 0x0000, 0, 0) +#define _MX51_PAD_DI1_PIN13__GPIO3_2 IOMUX_PAD(0x6b0, 0x2b0, 4, 0x097c, 1, 0) +#define _MX51_PAD_DI1_D0_CS__DI1_D0_CS IOMUX_PAD(0x6b4, 0x2b4, 0, 0x0000, 0, 0) +#define _MX51_PAD_DI1_D0_CS__GPIO3_3 IOMUX_PAD(0x6b4, 0x2b4, 4, 0x0980, 1, 0) +#define _MX51_PAD_DI1_D1_CS__DI1_D1_CS IOMUX_PAD(0x6b8, 0x2b8, 0, 0x0000, 0, 0) +#define _MX51_PAD_DI1_D1_CS__DISP1_PIN14 IOMUX_PAD(0x6b8, 0x2b8, 2, 0x0000, 0, 0) +#define _MX51_PAD_DI1_D1_CS__DISP1_PIN5 IOMUX_PAD(0x6b8, 0x2b8, 3, 0x0000, 0, 0) +#define _MX51_PAD_DI1_D1_CS__GPIO3_4 IOMUX_PAD(0x6b8, 0x2b8, 4, 0x0984, 1, 0) +#define _MX51_PAD_DISPB2_SER_DIN__DISP1_PIN1 IOMUX_PAD(0x6bc, 0x2bc, 2, 0x09a4, 1, 0) +#define _MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN IOMUX_PAD(0x6bc, 0x2bc, 0, 0x09c4, 0, 0) +#define _MX51_PAD_DISPB2_SER_DIN__GPIO3_5 IOMUX_PAD(0x6bc, 0x2bc, 4, 0x0988, 1, 0) +#define _MX51_PAD_DISPB2_SER_DIO__DISP1_PIN6 IOMUX_PAD(0x6c0, 0x2c0, 3, 0x0000, 0, 0) +#define _MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO IOMUX_PAD(0x6c0, 0x2c0, 0, 0x09c4, 1, 0) +#define _MX51_PAD_DISPB2_SER_DIO__GPIO3_6 IOMUX_PAD(0x6c0, 0x2c0, 4, 0x098c, 1, 0) +#define _MX51_PAD_DISPB2_SER_CLK__DISP1_PIN17 IOMUX_PAD(0x6c4, 0x2c4, 2, 0x0000, 0, 0) +#define _MX51_PAD_DISPB2_SER_CLK__DISP1_PIN7 IOMUX_PAD(0x6c4, 0x2c4, 3, 0x0000, 0, 0) +#define _MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK IOMUX_PAD(0x6c4, 0x2c4, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISPB2_SER_CLK__GPIO3_7 IOMUX_PAD(0x6c4, 0x2c4, 4, 0x0990, 1, 0) +#define _MX51_PAD_DISPB2_SER_RS__DISP1_EXT_CLK IOMUX_PAD(0x6c8, 0x2c8, 2, 0x0000, 0, 0) +#define _MX51_PAD_DISPB2_SER_RS__DISP1_PIN16 IOMUX_PAD(0x6c8, 0x2c8, 2, 0x0000, 0, 0) +#define _MX51_PAD_DISPB2_SER_RS__DISP1_PIN8 IOMUX_PAD(0x6c8, 0x2c8, 3, 0x0000, 0, 0) +#define _MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS IOMUX_PAD(0x6c8, 0x2c8, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS IOMUX_PAD(0x6c8, 0x2c8, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISPB2_SER_RS__GPIO3_8 IOMUX_PAD(0x6c8, 0x2c8, 4, 0x0994, 1, 0) +#define _MX51_PAD_DISP1_DAT0__DISP1_DAT0 IOMUX_PAD(0x6cc, 0x2cc, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT1__DISP1_DAT1 IOMUX_PAD(0x6d0, 0x2d0, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT2__DISP1_DAT2 IOMUX_PAD(0x6d4, 0x2d4, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT3__DISP1_DAT3 IOMUX_PAD(0x6d8, 0x2d8, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT4__DISP1_DAT4 IOMUX_PAD(0x6dc, 0x2dc, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT5__DISP1_DAT5 IOMUX_PAD(0x6e0, 0x2e0, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT6__BOOT_USB_SRC IOMUX_PAD(0x6e4, 0x2e4, 7, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT6__DISP1_DAT6 IOMUX_PAD(0x6e4, 0x2e4, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT7__BOOT_EEPROM_CFG IOMUX_PAD(0x6e8, 0x2e8, 7, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT7__DISP1_DAT7 IOMUX_PAD(0x6e8, 0x2e8, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT8__BOOT_SRC0 IOMUX_PAD(0x6ec, 0x2ec, 7, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT8__DISP1_DAT8 IOMUX_PAD(0x6ec, 0x2ec, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT9__BOOT_SRC1 IOMUX_PAD(0x6f0, 0x2f0, 7, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT9__DISP1_DAT9 IOMUX_PAD(0x6f0, 0x2f0, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT10__BOOT_SPARE_SIZE IOMUX_PAD(0x6f4, 0x2f4, 7, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT10__DISP1_DAT10 IOMUX_PAD(0x6f4, 0x2f4, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT11__BOOT_LPB_FREQ2 IOMUX_PAD(0x6f8, 0x2f8, 7, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT11__DISP1_DAT11 IOMUX_PAD(0x6f8, 0x2f8, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT12__BOOT_MLC_SEL IOMUX_PAD(0x6fc, 0x2fc, 7, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT12__DISP1_DAT12 IOMUX_PAD(0x6fc, 0x2fc, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT13__BOOT_MEM_CTL0 IOMUX_PAD(0x700, 0x300, 7, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT13__DISP1_DAT13 IOMUX_PAD(0x700, 0x300, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT14__BOOT_MEM_CTL1 IOMUX_PAD(0x704, 0x304, 7, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT14__DISP1_DAT14 IOMUX_PAD(0x704, 0x304, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT15__BOOT_BUS_WIDTH IOMUX_PAD(0x708, 0x308, 7, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT15__DISP1_DAT15 IOMUX_PAD(0x708, 0x308, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT16__BOOT_PAGE_SIZE0 IOMUX_PAD(0x70c, 0x30c, 7, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT16__DISP1_DAT16 IOMUX_PAD(0x70c, 0x30c, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT17__BOOT_PAGE_SIZE1 IOMUX_PAD(0x710, 0x310, 7, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT17__DISP1_DAT17 IOMUX_PAD(0x710, 0x310, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT18__BOOT_WEIM_MUXED0 IOMUX_PAD(0x714, 0x314, 7, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT18__DISP1_DAT18 IOMUX_PAD(0x714, 0x314, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT18__DISP2_PIN11 IOMUX_PAD(0x714, 0x314, 5, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT18__DISP2_PIN5 IOMUX_PAD(0x714, 0x314, 4, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT19__BOOT_WEIM_MUXED1 IOMUX_PAD(0x718, 0x318, 7, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT19__DISP1_DAT19 IOMUX_PAD(0x718, 0x318, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT19__DISP2_PIN12 IOMUX_PAD(0x718, 0x318, 5, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT19__DISP2_PIN6 IOMUX_PAD(0x718, 0x318, 4, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT20__BOOT_MEM_TYPE0 IOMUX_PAD(0x71c, 0x31c, 7, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT20__DISP1_DAT20 IOMUX_PAD(0x71c, 0x31c, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT20__DISP2_PIN13 IOMUX_PAD(0x71c, 0x31c, 5, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT20__DISP2_PIN7 IOMUX_PAD(0x71c, 0x31c, 4, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT21__BOOT_MEM_TYPE1 IOMUX_PAD(0x720, 0x320, 7, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT21__DISP1_DAT21 IOMUX_PAD(0x720, 0x320, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT21__DISP2_PIN14 IOMUX_PAD(0x720, 0x320, 5, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT21__DISP2_PIN8 IOMUX_PAD(0x720, 0x320, 4, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT22__BOOT_LPB_FREQ0 IOMUX_PAD(0x724, 0x324, 7, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT22__DISP1_DAT22 IOMUX_PAD(0x724, 0x324, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT22__DISP2_D0_CS IOMUX_PAD(0x724, 0x324, 6, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT22__DISP2_DAT16 IOMUX_PAD(0x724, 0x324, 5, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT23__BOOT_LPB_FREQ1 IOMUX_PAD(0x728, 0x328, 7, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT23__DISP1_DAT23 IOMUX_PAD(0x728, 0x328, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT23__DISP2_D1_CS IOMUX_PAD(0x728, 0x328, 6, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT23__DISP2_DAT17 IOMUX_PAD(0x728, 0x328, 5, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT23__DISP2_SER_CS IOMUX_PAD(0x728, 0x328, 4, 0x0000, 0, 0) +#define _MX51_PAD_DI1_PIN3__DI1_PIN3 IOMUX_PAD(0x72c, 0x32c, 0, 0x0000, 0, 0) +#define _MX51_PAD_DI1_PIN2__DI1_PIN2 IOMUX_PAD(0x734, 0x330, 0, 0x0000, 0, 0) +#define _MX51_PAD_DI_GP2__DISP1_SER_CLK IOMUX_PAD(0x740, 0x338, 0, 0x0000, 0, 0) +#define _MX51_PAD_DI_GP2__DISP2_WAIT IOMUX_PAD(0x740, 0x338, 2, 0x09a8, 1, 0) +#define _MX51_PAD_DI_GP3__CSI1_DATA_EN IOMUX_PAD(0x744, 0x33c, 3, 0x09a0, 1, 0) +#define _MX51_PAD_DI_GP3__DISP1_SER_DIO IOMUX_PAD(0x744, 0x33c, 0, 0x09c0, 0, 0) +#define _MX51_PAD_DI_GP3__FEC_TX_ER IOMUX_PAD(0x744, 0x33c, 2, 0x0000, 0, 0) +#define _MX51_PAD_DI2_PIN4__CSI2_DATA_EN IOMUX_PAD(0x748, 0x340, 3, 0x099c, 1, 0) +#define _MX51_PAD_DI2_PIN4__DI2_PIN4 IOMUX_PAD(0x748, 0x340, 0, 0x0000, 0, 0) +#define _MX51_PAD_DI2_PIN4__FEC_CRS IOMUX_PAD(0x748, 0x340, 2, 0x0950, 1, 0) +#define _MX51_PAD_DI2_PIN2__DI2_PIN2 IOMUX_PAD(0x74c, 0x344, 0, 0x0000, 0, 0) +#define _MX51_PAD_DI2_PIN2__FEC_MDC IOMUX_PAD(0x74c, 0x344, 2, 0x0000, 0, 0) +#define _MX51_PAD_DI2_PIN3__DI2_PIN3 IOMUX_PAD(0x750, 0x348, 0, 0x0000, 0, 0) +#define _MX51_PAD_DI2_PIN3__FEC_MDIO IOMUX_PAD(0x750, 0x348, 2, 0x0954, 1, 0) +#define _MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK IOMUX_PAD(0x754, 0x34c, 0, 0x0000, 0, 0) +#define _MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 IOMUX_PAD(0x754, 0x34c, 2, 0x095c, 1, 0) +#define _MX51_PAD_DI_GP4__DI2_PIN15 IOMUX_PAD(0x758, 0x350, 4, 0x0000, 0, 0) +#define _MX51_PAD_DI_GP4__DISP1_SER_DIN IOMUX_PAD(0x758, 0x350, 0, 0x09c0, 1, 0) +#define _MX51_PAD_DI_GP4__DISP2_PIN1 IOMUX_PAD(0x758, 0x350, 3, 0x0000, 0, 0) +#define _MX51_PAD_DI_GP4__FEC_RDATA2 IOMUX_PAD(0x758, 0x350, 2, 0x0960, 1, 0) +#define _MX51_PAD_DISP2_DAT0__DISP2_DAT0 IOMUX_PAD(0x75c, 0x354, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT0__FEC_RDATA3 IOMUX_PAD(0x75c, 0x354, 2, 0x0964, 1, 0) +#define _MX51_PAD_DISP2_DAT0__KEY_COL6 IOMUX_PAD(0x75c, 0x354, 4, 0x09c8, 1, 0) +#define _MX51_PAD_DISP2_DAT0__UART3_RXD IOMUX_PAD(0x75c, 0x354, 5, 0x09f4, 8, 0) +#define _MX51_PAD_DISP2_DAT0__USBH3_CLK IOMUX_PAD(0x75c, 0x354, 3, 0x09f8, 1, 0) +#define _MX51_PAD_DISP2_DAT1__DISP2_DAT1 IOMUX_PAD(0x760, 0x358, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT1__FEC_RX_ER IOMUX_PAD(0x760, 0x358, 2, 0x0970, 1, 0) +#define _MX51_PAD_DISP2_DAT1__KEY_COL7 IOMUX_PAD(0x760, 0x358, 4, 0x09cc, 1, 0) +#define _MX51_PAD_DISP2_DAT1__UART3_TXD IOMUX_PAD(0x760, 0x358, 5, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT1__USBH3_DIR IOMUX_PAD(0x760, 0x358, 3, 0x0a1c, 1, 0) +#define _MX51_PAD_DISP2_DAT2__DISP2_DAT2 IOMUX_PAD(0x764, 0x35c, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT3__DISP2_DAT3 IOMUX_PAD(0x768, 0x360, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT4__DISP2_DAT4 IOMUX_PAD(0x76c, 0x364, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT5__DISP2_DAT5 IOMUX_PAD(0x770, 0x368, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT6__DISP2_DAT6 IOMUX_PAD(0x774, 0x36c, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT6__FEC_TDATA1 IOMUX_PAD(0x774, 0x36c, 2, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT6__GPIO1_19 IOMUX_PAD(0x774, 0x36c, 5, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT6__KEY_ROW4 IOMUX_PAD(0x774, 0x36c, 4, 0x09d0, 1, 0) +#define _MX51_PAD_DISP2_DAT6__USBH3_STP IOMUX_PAD(0x774, 0x36c, 3, 0x0a24, 1, 0) +#define _MX51_PAD_DISP2_DAT7__DISP2_DAT7 IOMUX_PAD(0x778, 0x370, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT7__FEC_TDATA2 IOMUX_PAD(0x778, 0x370, 2, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT7__GPIO1_29 IOMUX_PAD(0x778, 0x370, 5, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT7__KEY_ROW5 IOMUX_PAD(0x778, 0x370, 4, 0x09d4, 1, 0) +#define _MX51_PAD_DISP2_DAT7__USBH3_NXT IOMUX_PAD(0x778, 0x370, 3, 0x0a20, 1, 0) +#define _MX51_PAD_DISP2_DAT8__DISP2_DAT8 IOMUX_PAD(0x77c, 0x374, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT8__FEC_TDATA3 IOMUX_PAD(0x77c, 0x374, 2, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT8__GPIO1_30 IOMUX_PAD(0x77c, 0x374, 5, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT8__KEY_ROW6 IOMUX_PAD(0x77c, 0x374, 4, 0x09d8, 1, 0) +#define _MX51_PAD_DISP2_DAT8__USBH3_DATA0 IOMUX_PAD(0x77c, 0x374, 3, 0x09fc, 1, 0) +#define _MX51_PAD_DISP2_DAT9__AUD6_RXC IOMUX_PAD(0x780, 0x378, 4, 0x08f4, 1, 0) +#define _MX51_PAD_DISP2_DAT9__DISP2_DAT9 IOMUX_PAD(0x780, 0x378, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT9__FEC_TX_EN IOMUX_PAD(0x780, 0x378, 2, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT9__GPIO1_31 IOMUX_PAD(0x780, 0x378, 5, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT9__USBH3_DATA1 IOMUX_PAD(0x780, 0x378, 3, 0x0a00, 1, 0) +#define _MX51_PAD_DISP2_DAT10__DISP2_DAT10 IOMUX_PAD(0x784, 0x37c, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT10__DISP2_SER_CS IOMUX_PAD(0x784, 0x37c, 5, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT10__FEC_COL IOMUX_PAD(0x784, 0x37c, 2, 0x094c, 1, 0) +#define _MX51_PAD_DISP2_DAT10__KEY_ROW7 IOMUX_PAD(0x784, 0x37c, 4, 0x09dc, 1, 0) +#define _MX51_PAD_DISP2_DAT10__USBH3_DATA2 IOMUX_PAD(0x784, 0x37c, 3, 0x0a04, 1, 0) +#define _MX51_PAD_DISP2_DAT11__AUD6_TXD IOMUX_PAD(0x788, 0x380, 4, 0x08f0, 1, 0) +#define _MX51_PAD_DISP2_DAT11__DISP2_DAT11 IOMUX_PAD(0x788, 0x380, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT11__FEC_RX_CLK IOMUX_PAD(0x788, 0x380, 2, 0x0968, 1, 0) +#define _MX51_PAD_DISP2_DAT11__GPIO1_10 IOMUX_PAD(0x788, 0x380, 7, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT11__USBH3_DATA3 IOMUX_PAD(0x788, 0x380, 3, 0x0a08, 1, 0) +#define _MX51_PAD_DISP2_DAT12__AUD6_RXD IOMUX_PAD(0x78c, 0x384, 4, 0x08ec, 1, 0) +#define _MX51_PAD_DISP2_DAT12__DISP2_DAT12 IOMUX_PAD(0x78c, 0x384, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT12__FEC_RX_DV IOMUX_PAD(0x78c, 0x384, 2, 0x096c, 1, 0) +#define _MX51_PAD_DISP2_DAT12__USBH3_DATA4 IOMUX_PAD(0x78c, 0x384, 3, 0x0a0c, 1, 0) +#define _MX51_PAD_DISP2_DAT13__AUD6_TXC IOMUX_PAD(0x790, 0x388, 4, 0x08fc, 1, 0) +#define _MX51_PAD_DISP2_DAT13__DISP2_DAT13 IOMUX_PAD(0x790, 0x388, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT13__FEC_TX_CLK IOMUX_PAD(0x790, 0x388, 2, 0x0974, 1, 0) +#define _MX51_PAD_DISP2_DAT13__USBH3_DATA5 IOMUX_PAD(0x790, 0x388, 3, 0x0a10, 1, 0) +#define _MX51_PAD_DISP2_DAT14__AUD6_TXFS IOMUX_PAD(0x794, 0x38c, 4, 0x0900, 1, 0) +#define _MX51_PAD_DISP2_DAT14__DISP2_DAT14 IOMUX_PAD(0x794, 0x38c, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT14__FEC_RDATA0 IOMUX_PAD(0x794, 0x38c, 2, 0x0958, 1, 0) +#define _MX51_PAD_DISP2_DAT14__USBH3_DATA6 IOMUX_PAD(0x794, 0x38c, 3, 0x0a14, 1, 0) +#define _MX51_PAD_DISP2_DAT15__AUD6_RXFS IOMUX_PAD(0x798, 0x390, 4, 0x08f8, 1, 0) +#define _MX51_PAD_DISP2_DAT15__DISP1_SER_CS IOMUX_PAD(0x798, 0x390, 5, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT15__DISP2_DAT15 IOMUX_PAD(0x798, 0x390, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT15__FEC_TDATA0 IOMUX_PAD(0x798, 0x390, 2, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT15__USBH3_DATA7 IOMUX_PAD(0x798, 0x390, 3, 0x0a18, 1, 0) +#define _MX51_PAD_SD1_CMD__AUD5_RXFS IOMUX_PAD(0x79c, 0x394, 1, 0x08e0, 1, 0) +#define _MX51_PAD_SD1_CMD__CSPI_MOSI IOMUX_PAD(0x79c, 0x394, 2, 0x091c, 2, 0) +#define _MX51_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x79c, 0x394, 0x10, 0x0000, 0, 0) +#define _MX51_PAD_SD1_CLK__AUD5_RXC IOMUX_PAD(0x7a0, 0x398, 1, 0x08dc, 1, 0) +#define _MX51_PAD_SD1_CLK__CSPI_SCLK IOMUX_PAD(0x7a0, 0x398, 2, 0x0914, 2, 0) +#define _MX51_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x7a0, 0x398, 0x10, 0x0000, 0, 0) +#define _MX51_PAD_SD1_DATA0__AUD5_TXD IOMUX_PAD(0x7a4, 0x39c, 1, 0x08d8, 2, 0) +#define _MX51_PAD_SD1_DATA0__CSPI_MISO IOMUX_PAD(0x7a4, 0x39c, 2, 0x0918, 1, 0) +#define _MX51_PAD_SD1_DATA0__SD1_DATA0 IOMUX_PAD(0x7a4, 0x39c, 0x10, 0x0000, 0, 0) +#define _MX51_PAD_EIM_DA0__EIM_DA0 IOMUX_PAD(0x000, 0x01c, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_DA1__EIM_DA1 IOMUX_PAD(0x000, 0x020, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_DA2__EIM_DA2 IOMUX_PAD(0x000, 0x024, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_DA3__EIM_DA3 IOMUX_PAD(0x000, 0x028, 0, 0x0000, 0, 0) +#define _MX51_PAD_SD1_DATA1__AUD5_RXD IOMUX_PAD(0x7a8, 0x3a0, 1, 0x08d4, 2, 0) +#define _MX51_PAD_SD1_DATA1__SD1_DATA1 IOMUX_PAD(0x7a8, 0x3a0, 0x10, 0x0000, 0, 0) +#define _MX51_PAD_EIM_DA4__EIM_DA4 IOMUX_PAD(0x000, 0x02c, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_DA5__EIM_DA5 IOMUX_PAD(0x000, 0x030, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_DA6__EIM_DA6 IOMUX_PAD(0x000, 0x034, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_DA7__EIM_DA7 IOMUX_PAD(0x000, 0x038, 0, 0x0000, 0, 0) +#define _MX51_PAD_SD1_DATA2__AUD5_TXC IOMUX_PAD(0x7ac, 0x3a4, 1, 0x08e4, 2, 0) +#define _MX51_PAD_SD1_DATA2__SD1_DATA2 IOMUX_PAD(0x7ac, 0x3a4, 0x10, 0x0000, 0, 0) +#define _MX51_PAD_EIM_DA10__EIM_DA10 IOMUX_PAD(0x000, 0x044, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_DA11__EIM_DA11 IOMUX_PAD(0x000, 0x048, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_DA8__EIM_DA8 IOMUX_PAD(0x000, 0x03c, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_DA9__EIM_DA9 IOMUX_PAD(0x000, 0x040, 0, 0x0000, 0, 0) +#define _MX51_PAD_SD1_DATA3__AUD5_TXFS IOMUX_PAD(0x7b0, 0x3a8, 1, 0x08e8, 2, 0) +#define _MX51_PAD_SD1_DATA3__CSPI_SS1 IOMUX_PAD(0x7b0, 0x3a8, 2, 0x0920, 1, 0) +#define _MX51_PAD_SD1_DATA3__SD1_DATA3 IOMUX_PAD(0x7b0, 0x3a8, 0x10, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_0__CSPI_SS2 IOMUX_PAD(0x7b4, 0x3ac, 2, 0x0924, 0, 0) +#define _MX51_PAD_GPIO1_0__GPIO1_0 IOMUX_PAD(0x7b4, 0x3ac, 1, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_0__SD1_CD IOMUX_PAD(0x7b4, 0x3ac, 0, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_1__CSPI_MISO IOMUX_PAD(0x7b8, 0x3b0, 2, 0x0918, 2, 0) +#define _MX51_PAD_GPIO1_1__GPIO1_1 IOMUX_PAD(0x7b8, 0x3b0, 1, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_1__SD1_WP IOMUX_PAD(0x7b8, 0x3b0, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_DA12__EIM_DA12 IOMUX_PAD(0x000, 0x04c, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_DA13__EIM_DA13 IOMUX_PAD(0x000, 0x050, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_DA14__EIM_DA14 IOMUX_PAD(0x000, 0x054, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_DA15__EIM_DA15 IOMUX_PAD(0x000, 0x058, 0, 0x0000, 0, 0) +#define _MX51_PAD_SD2_CMD__CSPI_MOSI IOMUX_PAD(0x000, 0x3b4, 2, 0x091c, 3, 0) +#define _MX51_PAD_SD2_CMD__I2C1_SCL IOMUX_PAD(0x7bc, 0x3b4, 0x11, 0x09b0, 2, 0) +#define _MX51_PAD_SD2_CMD__SD2_CMD IOMUX_PAD(0x7bc, 0x3b4, 0x10, 0x0000, 0, 0) +#define _MX51_PAD_SD2_CLK__CSPI_SCLK IOMUX_PAD(0x7c0, 0x3b8, 2, 0x0914, 3, 0) +#define _MX51_PAD_SD2_CLK__I2C1_SDA IOMUX_PAD(0x7c0, 0x3b8, 0x11, 0x09b4, 2, 0) +#define _MX51_PAD_SD2_CLK__SD2_CLK IOMUX_PAD(0x7c0, 0x3b8, 0x10, 0x0000, 0, 0) +#define _MX51_PAD_SD2_DATA0__CSPI_MISO IOMUX_PAD(0x7c4, 0x3bc, 2, 0x0918, 3, 0) +#define _MX51_PAD_SD2_DATA0__SD1_DAT4 IOMUX_PAD(0x7c4, 0x3bc, 1, 0x0000, 0, 0) +#define _MX51_PAD_SD2_DATA0__SD2_DATA0 IOMUX_PAD(0x7c4, 0x3bc, 0x10, 0x0000, 0, 0) +#define _MX51_PAD_SD2_DATA1__SD1_DAT5 IOMUX_PAD(0x7c8, 0x3c0, 1, 0x0000, 0, 0) +#define _MX51_PAD_SD2_DATA1__SD2_DATA1 IOMUX_PAD(0x7c8, 0x3c0, 0x10, 0x0000, 0, 0) +#define _MX51_PAD_SD2_DATA1__USBH3_H2_DP IOMUX_PAD(0x7c8, 0x3c0, 2, 0x0000, 0, 0) +#define _MX51_PAD_SD2_DATA2__SD1_DAT6 IOMUX_PAD(0x7cc, 0x3c4, 1, 0x0000, 0, 0) +#define _MX51_PAD_SD2_DATA2__SD2_DATA2 IOMUX_PAD(0x7cc, 0x3c4, 0x10, 0x0000, 0, 0) +#define _MX51_PAD_SD2_DATA2__USBH3_H2_DM IOMUX_PAD(0x7cc, 0x3c4, 2, 0x0000, 0, 0) +#define _MX51_PAD_SD2_DATA3__CSPI_SS2 IOMUX_PAD(0x7d0, 0x3c8, 2, 0x0924, 1, 0) +#define _MX51_PAD_SD2_DATA3__SD1_DAT7 IOMUX_PAD(0x7d0, 0x3c8, 1, 0x0000, 0, 0) +#define _MX51_PAD_SD2_DATA3__SD2_DATA3 IOMUX_PAD(0x7d0, 0x3c8, 0x10, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_2__CCM_OUT_2 IOMUX_PAD(0x7d4, 0x3cc, 5, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_2__GPIO1_2 IOMUX_PAD(0x7d4, 0x3cc, 0, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_2__I2C2_SCL IOMUX_PAD(0x7d4, 0x3cc, 0x12, 0x09b8, 3, 0) +#define _MX51_PAD_GPIO1_2__PLL1_BYP IOMUX_PAD(0x7d4, 0x3cc, 7, 0x090c, 1, 0) +#define _MX51_PAD_GPIO1_2__PWM1_PWMO IOMUX_PAD(0x7d4, 0x3cc, 1, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_3__GPIO1_3 IOMUX_PAD(0x7d8, 0x3d0, 0, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_3__I2C2_SDA IOMUX_PAD(0x7d8, 0x3d0, 0x12, 0x09bc, 3, 0) +#define _MX51_PAD_GPIO1_3__PLL2_BYP IOMUX_PAD(0x7d8, 0x3d0, 7, 0x0910, 1, 0) +#define _MX51_PAD_GPIO1_3__PWM2_PWMO IOMUX_PAD(0x7d8, 0x3d0, 1, 0x0000, 0, 0) +#define _MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ IOMUX_PAD(0x7fc, 0x3d4, 0, 0x0000, 0, 0) +#define _MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B IOMUX_PAD(0x7fc, 0x3d4, 1, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_4__DISP2_EXT_CLK IOMUX_PAD(0x804, 0x3d8, 4, 0x0908, 1, 0) +#define _MX51_PAD_GPIO1_4__EIM_RDY IOMUX_PAD(0x804, 0x3d8, 3, 0x0938, 1, 0) +#define _MX51_PAD_GPIO1_4__GPIO1_4 IOMUX_PAD(0x804, 0x3d8, 0, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_4__WDOG1_WDOG_B IOMUX_PAD(0x804, 0x3d8, 2, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_5__CSI2_MCLK IOMUX_PAD(0x808, 0x3dc, 6, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_5__DISP2_PIN16 IOMUX_PAD(0x808, 0x3dc, 3, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_5__GPIO1_5 IOMUX_PAD(0x808, 0x3dc, 0, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_5__WDOG2_WDOG_B IOMUX_PAD(0x808, 0x3dc, 2, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_6__DISP2_PIN17 IOMUX_PAD(0x80c, 0x3e0, 4, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_6__GPIO1_6 IOMUX_PAD(0x80c, 0x3e0, 0, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_6__REF_EN_B IOMUX_PAD(0x80c, 0x3e0, 3, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_7__CCM_OUT_0 IOMUX_PAD(0x810, 0x3e4, 3, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_7__GPIO1_7 IOMUX_PAD(0x810, 0x3e4, 0, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_7__SD2_WP IOMUX_PAD(0x810, 0x3e4, 6, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_7__SPDIF_OUT1 IOMUX_PAD(0x810, 0x3e4, 2, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_8__CSI2_DATA_EN IOMUX_PAD(0x814, 0x3e8, 2, 0x099c, 2, 0) +#define _MX51_PAD_GPIO1_8__GPIO1_8 IOMUX_PAD(0x814, 0x3e8, 0, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_8__SD2_CD IOMUX_PAD(0x814, 0x3e8, 6, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_8__USBH3_PWR IOMUX_PAD(0x814, 0x3e8, 1, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_9__CCM_OUT_1 IOMUX_PAD(0x818, 0x3ec, 3, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_9__DISP2_D1_CS IOMUX_PAD(0x818, 0x3ec, 2, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_9__DISP2_SER_CS IOMUX_PAD(0x818, 0x3ec, 7, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_9__GPIO1_9 IOMUX_PAD(0x818, 0x3ec, 0, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_9__SD2_LCTL IOMUX_PAD(0x818, 0x3ec, 6, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_9__USBH3_OC IOMUX_PAD(0x818, 0x3ec, 1, 0x0000, 0, 0) + +/* The same pins as above but with the default pad control values applied */ +#define MX51_PAD_EIM_D16__AUD4_RXFS (_MX51_PAD_EIM_D16__AUD4_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D16__AUD5_TXD (_MX51_PAD_EIM_D16__AUD5_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D16__EIM_D16 (_MX51_PAD_EIM_D16__EIM_D16 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D16__GPIO2_0 (_MX51_PAD_EIM_D16__GPIO2_0 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_D16__I2C1_SDA (_MX51_PAD_EIM_D16__I2C1_SDA | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) +#define MX51_PAD_EIM_D16__UART2_CTS (_MX51_PAD_EIM_D16__UART2_CTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_EIM_D16__USBH2_DATA0 (_MX51_PAD_EIM_D16__USBH2_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D17__AUD5_RXD (_MX51_PAD_EIM_D17__AUD5_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D17__EIM_D17 (_MX51_PAD_EIM_D17__EIM_D17 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D17__GPIO2_1 (_MX51_PAD_EIM_D17__GPIO2_1 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_D17__UART2_RXD (_MX51_PAD_EIM_D17__UART2_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_EIM_D17__UART3_CTS (_MX51_PAD_EIM_D17__UART3_CTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_EIM_D17__USBH2_DATA1 (_MX51_PAD_EIM_D17__USBH2_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D18__AUD5_TXC (_MX51_PAD_EIM_D18__AUD5_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D18__EIM_D18 (_MX51_PAD_EIM_D18__EIM_D18 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D18__GPIO2_2 (_MX51_PAD_EIM_D18__GPIO2_2 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_D18__UART2_TXD (_MX51_PAD_EIM_D18__UART2_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_EIM_D18__UART3_RTS (_MX51_PAD_EIM_D18__UART3_RTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_EIM_D18__USBH2_DATA2 (_MX51_PAD_EIM_D18__USBH2_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D19__AUD4_RXC (_MX51_PAD_EIM_D19__AUD4_RXC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D19__AUD5_TXFS (_MX51_PAD_EIM_D19__AUD5_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D19__EIM_D19 (_MX51_PAD_EIM_D19__EIM_D19 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D19__GPIO2_3 (_MX51_PAD_EIM_D19__GPIO2_3 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_D19__I2C1_SCL (_MX51_PAD_EIM_D19__I2C1_SCL | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) +#define MX51_PAD_EIM_D19__UART2_RTS (_MX51_PAD_EIM_D19__UART2_RTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_EIM_D19__USBH2_DATA3 (_MX51_PAD_EIM_D19__USBH2_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D20__AUD4_TXD (_MX51_PAD_EIM_D20__AUD4_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D20__EIM_D20 (_MX51_PAD_EIM_D20__EIM_D20 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D20__GPIO2_4 (_MX51_PAD_EIM_D20__GPIO2_4 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_D20__SRTC_ALARM_DEB (_MX51_PAD_EIM_D20__SRTC_ALARM_DEB | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D20__USBH2_DATA4 (_MX51_PAD_EIM_D20__USBH2_DATA4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D21__AUD4_RXD (_MX51_PAD_EIM_D21__AUD4_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D21__EIM_D21 (_MX51_PAD_EIM_D21__EIM_D21 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D21__GPIO2_5 (_MX51_PAD_EIM_D21__GPIO2_5 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_D21__SRTC_ALARM_DEB (_MX51_PAD_EIM_D21__SRTC_ALARM_DEB | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D21__USBH2_DATA5 (_MX51_PAD_EIM_D21__USBH2_DATA5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D22__AUD4_TXC (_MX51_PAD_EIM_D22__AUD4_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D22__EIM_D22 (_MX51_PAD_EIM_D22__EIM_D22 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D22__GPIO2_6 (_MX51_PAD_EIM_D22__GPIO2_6 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_D22__USBH2_DATA6 (_MX51_PAD_EIM_D22__USBH2_DATA6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D23__AUD4_TXFS (_MX51_PAD_EIM_D23__AUD4_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D23__EIM_D23 (_MX51_PAD_EIM_D23__EIM_D23 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D23__GPIO2_7 (_MX51_PAD_EIM_D23__GPIO2_7 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_D23__SPDIF_OUT1 (_MX51_PAD_EIM_D23__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D23__USBH2_DATA7 (_MX51_PAD_EIM_D23__USBH2_DATA7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D24__AUD6_RXFS (_MX51_PAD_EIM_D24__AUD6_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D24__EIM_D24 (_MX51_PAD_EIM_D24__EIM_D24 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D24__GPIO2_8 (_MX51_PAD_EIM_D24__GPIO2_8 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_D24__I2C2_SDA (_MX51_PAD_EIM_D24__I2C2_SDA | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) +#define MX51_PAD_EIM_D24__UART3_CTS (_MX51_PAD_EIM_D24__UART3_CTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_EIM_D24__USBOTG_DATA0 (_MX51_PAD_EIM_D24__USBOTG_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D25__EIM_D25 (_MX51_PAD_EIM_D25__EIM_D25 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D25__KEY_COL6 (_MX51_PAD_EIM_D25__KEY_COL6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D25__UART2_CTS (_MX51_PAD_EIM_D25__UART2_CTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_EIM_D25__UART3_RXD (_MX51_PAD_EIM_D25__UART3_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_EIM_D25__USBOTG_DATA1 (_MX51_PAD_EIM_D25__USBOTG_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D26__EIM_D26 (_MX51_PAD_EIM_D26__EIM_D26 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D26__KEY_COL7 (_MX51_PAD_EIM_D26__KEY_COL7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D26__UART2_RTS (_MX51_PAD_EIM_D26__UART2_RTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_EIM_D26__UART3_TXD (_MX51_PAD_EIM_D26__UART3_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_EIM_D26__USBOTG_DATA2 (_MX51_PAD_EIM_D26__USBOTG_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D27__AUD6_RXC (_MX51_PAD_EIM_D27__AUD6_RXC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D27__EIM_D27 (_MX51_PAD_EIM_D27__EIM_D27 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D27__GPIO2_9 (_MX51_PAD_EIM_D27__GPIO2_9 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_D27__I2C2_SCL (_MX51_PAD_EIM_D27__I2C2_SCL | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) +#define MX51_PAD_EIM_D27__UART3_RTS (_MX51_PAD_EIM_D27__UART3_RTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_EIM_D27__USBOTG_DATA3 (_MX51_PAD_EIM_D27__USBOTG_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D28__AUD6_TXD (_MX51_PAD_EIM_D28__AUD6_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D28__EIM_D28 (_MX51_PAD_EIM_D28__EIM_D28 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D28__KEY_ROW4 (_MX51_PAD_EIM_D28__KEY_ROW4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D28__USBOTG_DATA4 (_MX51_PAD_EIM_D28__USBOTG_DATA4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D29__AUD6_RXD (_MX51_PAD_EIM_D29__AUD6_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D29__EIM_D29 (_MX51_PAD_EIM_D29__EIM_D29 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D29__KEY_ROW5 (_MX51_PAD_EIM_D29__KEY_ROW5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D29__USBOTG_DATA5 (_MX51_PAD_EIM_D29__USBOTG_DATA5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D30__AUD6_TXC (_MX51_PAD_EIM_D30__AUD6_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D30__EIM_D30 (_MX51_PAD_EIM_D30__EIM_D30 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D30__KEY_ROW6 (_MX51_PAD_EIM_D30__KEY_ROW6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D30__USBOTG_DATA6 (_MX51_PAD_EIM_D30__USBOTG_DATA6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D31__AUD6_TXFS (_MX51_PAD_EIM_D31__AUD6_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D31__EIM_D31 (_MX51_PAD_EIM_D31__EIM_D31 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D31__KEY_ROW7 (_MX51_PAD_EIM_D31__KEY_ROW7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D31__USBOTG_DATA7 (_MX51_PAD_EIM_D31__USBOTG_DATA7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_A16__EIM_A16 (_MX51_PAD_EIM_A16__EIM_A16 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_A16__GPIO2_10 (_MX51_PAD_EIM_A16__GPIO2_10 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_A16__OSC_FREQ_SEL0 (_MX51_PAD_EIM_A16__OSC_FREQ_SEL0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_A17__EIM_A17 (_MX51_PAD_EIM_A17__EIM_A17 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_A17__GPIO2_11 (_MX51_PAD_EIM_A17__GPIO2_11 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_A17__OSC_FREQ_SEL1 (_MX51_PAD_EIM_A17__OSC_FREQ_SEL1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_A18__BOOT_LPB0 (_MX51_PAD_EIM_A18__BOOT_LPB0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_A18__EIM_A18 (_MX51_PAD_EIM_A18__EIM_A18 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_A18__GPIO2_12 (_MX51_PAD_EIM_A18__GPIO2_12 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_A19__BOOT_LPB1 (_MX51_PAD_EIM_A19__BOOT_LPB1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_A19__EIM_A19 (_MX51_PAD_EIM_A19__EIM_A19 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_A19__GPIO2_13 (_MX51_PAD_EIM_A19__GPIO2_13 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_A20__BOOT_UART_SRC0 (_MX51_PAD_EIM_A20__BOOT_UART_SRC0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_A20__EIM_A20 (_MX51_PAD_EIM_A20__EIM_A20 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_A20__GPIO2_14 (_MX51_PAD_EIM_A20__GPIO2_14 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_A21__BOOT_UART_SRC1 (_MX51_PAD_EIM_A21__BOOT_UART_SRC1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_A21__EIM_A21 (_MX51_PAD_EIM_A21__EIM_A21 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_A21__GPIO2_15 (_MX51_PAD_EIM_A21__GPIO2_15 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_A22__EIM_A22 (_MX51_PAD_EIM_A22__EIM_A22 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_A22__GPIO2_16 (_MX51_PAD_EIM_A22__GPIO2_16 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_A23__BOOT_HPN_EN (_MX51_PAD_EIM_A23__BOOT_HPN_EN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_A23__EIM_A23 (_MX51_PAD_EIM_A23__EIM_A23 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_A23__GPIO2_17 (_MX51_PAD_EIM_A23__GPIO2_17 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_A24__EIM_A24 (_MX51_PAD_EIM_A24__EIM_A24 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_A24__GPIO2_18 (_MX51_PAD_EIM_A24__GPIO2_18 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_A24__USBH2_CLK (_MX51_PAD_EIM_A24__USBH2_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_A25__DISP1_PIN4 (_MX51_PAD_EIM_A25__DISP1_PIN4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_A25__EIM_A25 (_MX51_PAD_EIM_A25__EIM_A25 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_A25__GPIO2_19 (_MX51_PAD_EIM_A25__GPIO2_19 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_A25__USBH2_DIR (_MX51_PAD_EIM_A25__USBH2_DIR | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_A26__CSI1_DATA_EN (_MX51_PAD_EIM_A26__CSI1_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_A26__DISP2_EXT_CLK (_MX51_PAD_EIM_A26__DISP2_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_A26__EIM_A26 (_MX51_PAD_EIM_A26__EIM_A26 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_A26__GPIO2_20 (_MX51_PAD_EIM_A26__GPIO2_20 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_A26__USBH2_STP (_MX51_PAD_EIM_A26__USBH2_STP | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_A27__CSI2_DATA_EN (_MX51_PAD_EIM_A27__CSI2_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_A27__DISP1_PIN1 (_MX51_PAD_EIM_A27__DISP1_PIN1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_A27__EIM_A27 (_MX51_PAD_EIM_A27__EIM_A27 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_A27__GPIO2_21 (_MX51_PAD_EIM_A27__GPIO2_21 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_A27__USBH2_NXT (_MX51_PAD_EIM_A27__USBH2_NXT | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_EB0__EIM_EB0 (_MX51_PAD_EIM_EB0__EIM_EB0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_EB1__EIM_EB1 (_MX51_PAD_EIM_EB1__EIM_EB1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_EB2__AUD5_RXFS (_MX51_PAD_EIM_EB2__AUD5_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_EB2__CSI1_D2 (_MX51_PAD_EIM_EB2__CSI1_D2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_EB2__EIM_EB2 (_MX51_PAD_EIM_EB2__EIM_EB2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_EB2__FEC_MDIO (_MX51_PAD_EIM_EB2__FEC_MDIO | \ + MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP | PAD_CTL_PKE | PAD_CTL_SRE_FAST | \ + PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS)) +#define MX51_PAD_EIM_EB2__GPIO2_22 (_MX51_PAD_EIM_EB2__GPIO2_22 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_EB2__GPT_CMPOUT1 (_MX51_PAD_EIM_EB2__GPT_CMPOUT1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_EB3__AUD5_RXC (_MX51_PAD_EIM_EB3__AUD5_RXC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_EB3__CSI1_D3 (_MX51_PAD_EIM_EB3__CSI1_D3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_EB3__EIM_EB3 (_MX51_PAD_EIM_EB3__EIM_EB3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_EB3__FEC_RDATA1 (_MX51_PAD_EIM_EB3__FEC_RDATA1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_EB3__GPIO2_23 (_MX51_PAD_EIM_EB3__GPIO2_23 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_EB3__GPT_CMPOUT2 (_MX51_PAD_EIM_EB3__GPT_CMPOUT2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_OE__EIM_OE (_MX51_PAD_EIM_OE__EIM_OE | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_OE__GPIO2_24 (_MX51_PAD_EIM_OE__GPIO2_24 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_CS0__EIM_CS0 (_MX51_PAD_EIM_CS0__EIM_CS0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_CS0__GPIO2_25 (_MX51_PAD_EIM_CS0__GPIO2_25 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_CS1__EIM_CS1 (_MX51_PAD_EIM_CS1__EIM_CS1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_CS1__GPIO2_26 (_MX51_PAD_EIM_CS1__GPIO2_26 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_CS2__AUD5_TXD (_MX51_PAD_EIM_CS2__AUD5_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_CS2__CSI1_D4 (_MX51_PAD_EIM_CS2__CSI1_D4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_CS2__EIM_CS2 (_MX51_PAD_EIM_CS2__EIM_CS2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_CS2__FEC_RDATA2 (_MX51_PAD_EIM_CS2__FEC_RDATA2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_CS2__GPIO2_27 (_MX51_PAD_EIM_CS2__GPIO2_27 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_CS2__USBOTG_STP (_MX51_PAD_EIM_CS2__USBOTG_STP | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_CS3__AUD5_RXD (_MX51_PAD_EIM_CS3__AUD5_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_CS3__CSI1_D5 (_MX51_PAD_EIM_CS3__CSI1_D5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_CS3__EIM_CS3 (_MX51_PAD_EIM_CS3__EIM_CS3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_CS3__FEC_RDATA3 (_MX51_PAD_EIM_CS3__FEC_RDATA3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_CS3__GPIO2_28 (_MX51_PAD_EIM_CS3__GPIO2_28 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_CS3__USBOTG_NXT (_MX51_PAD_EIM_CS3__USBOTG_NXT | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_CS4__AUD5_TXC (_MX51_PAD_EIM_CS4__AUD5_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_CS4__CSI1_D6 (_MX51_PAD_EIM_CS4__CSI1_D6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_CS4__EIM_CS4 (_MX51_PAD_EIM_CS4__EIM_CS4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_CS4__FEC_RX_ER (_MX51_PAD_EIM_CS4__FEC_RX_ER | MUX_PAD_CTRL(MX51_PAD_CTRL_2)) +#define MX51_PAD_EIM_CS4__GPIO2_29 (_MX51_PAD_EIM_CS4__GPIO2_29 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_CS4__USBOTG_CLK (_MX51_PAD_EIM_CS4__USBOTG_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_CS5__AUD5_TXFS (_MX51_PAD_EIM_CS5__AUD5_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_CS5__CSI1_D7 (_MX51_PAD_EIM_CS5__CSI1_D7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_CS5__DISP1_EXT_CLK (_MX51_PAD_EIM_CS5__DISP1_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_CS5__EIM_CS5 (_MX51_PAD_EIM_CS5__EIM_CS5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_CS5__FEC_CRS (_MX51_PAD_EIM_CS5__FEC_CRS | MUX_PAD_CTRL(MX51_PAD_CTRL_2)) +#define MX51_PAD_EIM_CS5__GPIO2_30 (_MX51_PAD_EIM_CS5__GPIO2_30 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_CS5__USBOTG_DIR (_MX51_PAD_EIM_CS5__USBOTG_DIR | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_DTACK__EIM_DTACK (_MX51_PAD_EIM_DTACK__EIM_DTACK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_DTACK__GPIO2_31 (_MX51_PAD_EIM_DTACK__GPIO2_31 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_LBA__EIM_LBA (_MX51_PAD_EIM_LBA__EIM_LBA | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_LBA__GPIO3_1 (_MX51_PAD_EIM_LBA__GPIO3_1 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_CRE__EIM_CRE (_MX51_PAD_EIM_CRE__EIM_CRE | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_CRE__GPIO3_2 (_MX51_PAD_EIM_CRE__GPIO3_2 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_DRAM_CS1__DRAM_CS1 (_MX51_PAD_DRAM_CS1__DRAM_CS1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_WE_B__GPIO3_3 (_MX51_PAD_NANDF_WE_B__GPIO3_3 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_WE_B__NANDF_WE_B (_MX51_PAD_NANDF_WE_B__NANDF_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_WE_B__PATA_DIOW (_MX51_PAD_NANDF_WE_B__PATA_DIOW | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_WE_B__SD3_DATA0 (_MX51_PAD_NANDF_WE_B__SD3_DATA0 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL)) +#define MX51_PAD_NANDF_RE_B__GPIO3_4 (_MX51_PAD_NANDF_RE_B__GPIO3_4 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_RE_B__NANDF_RE_B (_MX51_PAD_NANDF_RE_B__NANDF_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_RE_B__PATA_DIOR (_MX51_PAD_NANDF_RE_B__PATA_DIOR | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_RE_B__SD3_DATA1 (_MX51_PAD_NANDF_RE_B__SD3_DATA1 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL)) +#define MX51_PAD_NANDF_ALE__GPIO3_5 (_MX51_PAD_NANDF_ALE__GPIO3_5 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_ALE__NANDF_ALE (_MX51_PAD_NANDF_ALE__NANDF_ALE | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_ALE__PATA_BUFFER_EN (_MX51_PAD_NANDF_ALE__PATA_BUFFER_EN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_CLE__GPIO3_6 (_MX51_PAD_NANDF_CLE__GPIO3_6 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_CLE__NANDF_CLE (_MX51_PAD_NANDF_CLE__NANDF_CLE | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_CLE__PATA_RESET_B (_MX51_PAD_NANDF_CLE__PATA_RESET_B | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_WP_B__GPIO3_7 (_MX51_PAD_NANDF_WP_B__GPIO3_7 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_WP_B__NANDF_WP_B (_MX51_PAD_NANDF_WP_B__NANDF_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_WP_B__PATA_DMACK (_MX51_PAD_NANDF_WP_B__PATA_DMACK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_WP_B__SD3_DATA2 (_MX51_PAD_NANDF_WP_B__SD3_DATA2 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL)) +#define MX51_PAD_NANDF_RB0__ECSPI2_SS1 (_MX51_PAD_NANDF_RB0__ECSPI2_SS1 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_NANDF_RB0__GPIO3_8 (_MX51_PAD_NANDF_RB0__GPIO3_8 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_RB0__NANDF_RB0 (_MX51_PAD_NANDF_RB0__NANDF_RB0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_RB0__PATA_DMARQ (_MX51_PAD_NANDF_RB0__PATA_DMARQ | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_RB0__SD3_DATA3 (_MX51_PAD_NANDF_RB0__SD3_DATA3 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL)) +#define MX51_PAD_NANDF_RB1__CSPI_MOSI (_MX51_PAD_NANDF_RB1__CSPI_MOSI | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_NANDF_RB1__ECSPI2_RDY (_MX51_PAD_NANDF_RB1__ECSPI2_RDY | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_NANDF_RB1__GPIO3_9 (_MX51_PAD_NANDF_RB1__GPIO3_9 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_RB1__NANDF_RB1 (_MX51_PAD_NANDF_RB1__NANDF_RB1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_RB1__PATA_IORDY (_MX51_PAD_NANDF_RB1__PATA_IORDY | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_RB1__SD4_CMD (_MX51_PAD_NANDF_RB1__SD4_CMD | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL)) +#define MX51_PAD_NANDF_RB2__DISP2_WAIT (_MX51_PAD_NANDF_RB2__DISP2_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_RB2__ECSPI2_SCLK (_MX51_PAD_NANDF_RB2__ECSPI2_SCLK | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_NANDF_RB2__FEC_COL (_MX51_PAD_NANDF_RB2__FEC_COL | MUX_PAD_CTRL(MX51_PAD_CTRL_2)) +#define MX51_PAD_NANDF_RB2__GPIO3_10 (_MX51_PAD_NANDF_RB2__GPIO3_10 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_RB2__NANDF_RB2 (_MX51_PAD_NANDF_RB2__NANDF_RB2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_RB2__USBH3_H3_DP (_MX51_PAD_NANDF_RB2__USBH3_H3_DP | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_RB2__USBH3_NXT (_MX51_PAD_NANDF_RB2__USBH3_NXT | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_RB3__DISP1_WAIT (_MX51_PAD_NANDF_RB3__DISP1_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_RB3__ECSPI2_MISO (_MX51_PAD_NANDF_RB3__ECSPI2_MISO | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_NANDF_RB3__FEC_RX_CLK (_MX51_PAD_NANDF_RB3__FEC_RX_CLK | MUX_PAD_CTRL(MX51_PAD_CTRL_2)) +#define MX51_PAD_NANDF_RB3__GPIO3_11 (_MX51_PAD_NANDF_RB3__GPIO3_11 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_RB3__NANDF_RB3 (_MX51_PAD_NANDF_RB3__NANDF_RB3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_RB3__USBH3_CLK (_MX51_PAD_NANDF_RB3__USBH3_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_RB3__USBH3_H3_DM (_MX51_PAD_NANDF_RB3__USBH3_H3_DM | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO_NAND__GPIO_NAND (_MX51_PAD_GPIO_NAND__GPIO_NAND | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_GPIO_NAND__PATA_INTRQ (_MX51_PAD_GPIO_NAND__PATA_INTRQ | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS0__GPIO3_16 (_MX51_PAD_NANDF_CS0__GPIO3_16 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS0__NANDF_CS0 (_MX51_PAD_NANDF_CS0__NANDF_CS0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS1__GPIO3_17 (_MX51_PAD_NANDF_CS1__GPIO3_17 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS1__NANDF_CS1 (_MX51_PAD_NANDF_CS1__NANDF_CS1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS2__CSPI_SCLK (_MX51_PAD_NANDF_CS2__CSPI_SCLK | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_NANDF_CS2__FEC_TX_ER (_MX51_PAD_NANDF_CS2__FEC_TX_ER | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) +#define MX51_PAD_NANDF_CS2__GPIO3_18 (_MX51_PAD_NANDF_CS2__GPIO3_18 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS2__NANDF_CS2 (_MX51_PAD_NANDF_CS2__NANDF_CS2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS2__PATA_CS_0 (_MX51_PAD_NANDF_CS2__PATA_CS_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS2__SD4_CLK (_MX51_PAD_NANDF_CS2__SD4_CLK | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS)) +#define MX51_PAD_NANDF_CS2__USBH3_H1_DP (_MX51_PAD_NANDF_CS2__USBH3_H1_DP | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS3__FEC_MDC (_MX51_PAD_NANDF_CS3__FEC_MDC | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) +#define MX51_PAD_NANDF_CS3__GPIO3_19 (_MX51_PAD_NANDF_CS3__GPIO3_19 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS3__NANDF_CS3 (_MX51_PAD_NANDF_CS3__NANDF_CS3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS3__PATA_CS_1 (_MX51_PAD_NANDF_CS3__PATA_CS_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS3__SD4_DAT0 (_MX51_PAD_NANDF_CS3__SD4_DAT0 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL)) +#define MX51_PAD_NANDF_CS3__USBH3_H1_DM (_MX51_PAD_NANDF_CS3__USBH3_H1_DM | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS4__FEC_TDATA1 (_MX51_PAD_NANDF_CS4__FEC_TDATA1 | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) +#define MX51_PAD_NANDF_CS4__GPIO3_20 (_MX51_PAD_NANDF_CS4__GPIO3_20 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS4__NANDF_CS4 (_MX51_PAD_NANDF_CS4__NANDF_CS4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS4__PATA_DA_0 (_MX51_PAD_NANDF_CS4__PATA_DA_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS4__SD4_DAT1 (_MX51_PAD_NANDF_CS4__SD4_DAT1 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL)) +#define MX51_PAD_NANDF_CS4__USBH3_STP (_MX51_PAD_NANDF_CS4__USBH3_STP | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS5__FEC_TDATA2 (_MX51_PAD_NANDF_CS5__FEC_TDATA2 | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) +#define MX51_PAD_NANDF_CS5__GPIO3_21 (_MX51_PAD_NANDF_CS5__GPIO3_21 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS5__NANDF_CS5 (_MX51_PAD_NANDF_CS5__NANDF_CS5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS5__PATA_DA_1 (_MX51_PAD_NANDF_CS5__PATA_DA_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS5__SD4_DAT2 (_MX51_PAD_NANDF_CS5__SD4_DAT2 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL)) +#define MX51_PAD_NANDF_CS5__USBH3_DIR (_MX51_PAD_NANDF_CS5__USBH3_DIR | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS6__CSPI_SS3 (_MX51_PAD_NANDF_CS6__CSPI_SS3 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_NANDF_CS6__FEC_TDATA3 (_MX51_PAD_NANDF_CS6__FEC_TDATA3 | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) +#define MX51_PAD_NANDF_CS6__GPIO3_22 (_MX51_PAD_NANDF_CS6__GPIO3_22 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS6__NANDF_CS6 (_MX51_PAD_NANDF_CS6__NANDF_CS6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS6__PATA_DA_2 (_MX51_PAD_NANDF_CS6__PATA_DA_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS6__SD4_DAT3 (_MX51_PAD_NANDF_CS6__SD4_DAT3 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL)) +#define MX51_PAD_NANDF_CS7__FEC_TX_EN (_MX51_PAD_NANDF_CS7__FEC_TX_EN | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) +#define MX51_PAD_NANDF_CS7__GPIO3_23 (_MX51_PAD_NANDF_CS7__GPIO3_23 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS7__NANDF_CS7 (_MX51_PAD_NANDF_CS7__NANDF_CS7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS7__SD3_CLK (_MX51_PAD_NANDF_CS7__SD3_CLK | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS)) +#define MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0 (_MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK (_MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK | MUX_PAD_CTRL(MX51_PAD_CTRL_4)) +#define MX51_PAD_NANDF_RDY_INT__GPIO3_24 (_MX51_PAD_NANDF_RDY_INT__GPIO3_24 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT (_MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_RDY_INT__SD3_CMD (_MX51_PAD_NANDF_RDY_INT__SD3_CMD | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL)) +#define MX51_PAD_NANDF_D15__ECSPI2_MOSI (_MX51_PAD_NANDF_D15__ECSPI2_MOSI | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_NANDF_D15__GPIO3_25 (_MX51_PAD_NANDF_D15__GPIO3_25 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_D15__NANDF_D15 (_MX51_PAD_NANDF_D15__NANDF_D15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D15__PATA_DATA15 (_MX51_PAD_NANDF_D15__PATA_DATA15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D15__SD3_DAT7 (_MX51_PAD_NANDF_D15__SD3_DAT7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D14__ECSPI2_SS3 (_MX51_PAD_NANDF_D14__ECSPI2_SS3 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_NANDF_D14__GPIO3_26 (_MX51_PAD_NANDF_D14__GPIO3_26 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_D14__NANDF_D14 (_MX51_PAD_NANDF_D14__NANDF_D14 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D14__PATA_DATA14 (_MX51_PAD_NANDF_D14__PATA_DATA14 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D14__SD3_DAT6 (_MX51_PAD_NANDF_D14__SD3_DAT6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D13__ECSPI2_SS2 (_MX51_PAD_NANDF_D13__ECSPI2_SS2 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_NANDF_D13__GPIO3_27 (_MX51_PAD_NANDF_D13__GPIO3_27 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_D13__NANDF_D13 (_MX51_PAD_NANDF_D13__NANDF_D13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D13__PATA_DATA13 (_MX51_PAD_NANDF_D13__PATA_DATA13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D13__SD3_DAT5 (_MX51_PAD_NANDF_D13__SD3_DAT5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D12__ECSPI2_SS1 (_MX51_PAD_NANDF_D12__ECSPI2_SS1 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_NANDF_D12__GPIO3_28 (_MX51_PAD_NANDF_D12__GPIO3_28 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_D12__NANDF_D12 (_MX51_PAD_NANDF_D12__NANDF_D12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D12__PATA_DATA12 (_MX51_PAD_NANDF_D12__PATA_DATA12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D12__SD3_DAT4 (_MX51_PAD_NANDF_D12__SD3_DAT4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D11__FEC_RX_DV (_MX51_PAD_NANDF_D11__FEC_RX_DV | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D11__GPIO3_29 (_MX51_PAD_NANDF_D11__GPIO3_29 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_D11__NANDF_D11 (_MX51_PAD_NANDF_D11__NANDF_D11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D11__PATA_DATA11 (_MX51_PAD_NANDF_D11__PATA_DATA11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D11__SD3_DATA3 (_MX51_PAD_NANDF_D11__SD3_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D10__GPIO3_30 (_MX51_PAD_NANDF_D10__GPIO3_30 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_D10__NANDF_D10 (_MX51_PAD_NANDF_D10__NANDF_D10 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D10__PATA_DATA10 (_MX51_PAD_NANDF_D10__PATA_DATA10 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D10__SD3_DATA2 (_MX51_PAD_NANDF_D10__SD3_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D9__FEC_RDATA0 (_MX51_PAD_NANDF_D9__FEC_RDATA0 | MUX_PAD_CTRL(MX51_PAD_CTRL_4)) +#define MX51_PAD_NANDF_D9__GPIO3_31 (_MX51_PAD_NANDF_D9__GPIO3_31 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_D9__NANDF_D9 (_MX51_PAD_NANDF_D9__NANDF_D9 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D9__PATA_DATA9 (_MX51_PAD_NANDF_D9__PATA_DATA9 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D9__SD3_DATA1 (_MX51_PAD_NANDF_D9__SD3_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D8__FEC_TDATA0 (_MX51_PAD_NANDF_D8__FEC_TDATA0 | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) +#define MX51_PAD_NANDF_D8__GPIO4_0 (_MX51_PAD_NANDF_D8__GPIO4_0 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_D8__NANDF_D8 (_MX51_PAD_NANDF_D8__NANDF_D8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D8__PATA_DATA8 (_MX51_PAD_NANDF_D8__PATA_DATA8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D8__SD3_DATA0 (_MX51_PAD_NANDF_D8__SD3_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D7__GPIO4_1 (_MX51_PAD_NANDF_D7__GPIO4_1 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_D7__NANDF_D7 (_MX51_PAD_NANDF_D7__NANDF_D7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D7__PATA_DATA7 (_MX51_PAD_NANDF_D7__PATA_DATA7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D7__USBH3_DATA0 (_MX51_PAD_NANDF_D7__USBH3_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D6__GPIO4_2 (_MX51_PAD_NANDF_D6__GPIO4_2 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_D6__NANDF_D6 (_MX51_PAD_NANDF_D6__NANDF_D6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D6__PATA_DATA6 (_MX51_PAD_NANDF_D6__PATA_DATA6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D6__SD4_LCTL (_MX51_PAD_NANDF_D6__SD4_LCTL | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D6__USBH3_DATA1 (_MX51_PAD_NANDF_D6__USBH3_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D5__GPIO4_3 (_MX51_PAD_NANDF_D5__GPIO4_3 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_D5__NANDF_D5 (_MX51_PAD_NANDF_D5__NANDF_D5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D5__PATA_DATA5 (_MX51_PAD_NANDF_D5__PATA_DATA5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D5__SD4_WP (_MX51_PAD_NANDF_D5__SD4_WP | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D5__USBH3_DATA2 (_MX51_PAD_NANDF_D5__USBH3_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D4__GPIO4_4 (_MX51_PAD_NANDF_D4__GPIO4_4 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_D4__NANDF_D4 (_MX51_PAD_NANDF_D4__NANDF_D4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D4__PATA_DATA4 (_MX51_PAD_NANDF_D4__PATA_DATA4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D4__SD4_CD (_MX51_PAD_NANDF_D4__SD4_CD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D4__USBH3_DATA3 (_MX51_PAD_NANDF_D4__USBH3_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D3__GPIO4_5 (_MX51_PAD_NANDF_D3__GPIO4_5 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_D3__NANDF_D3 (_MX51_PAD_NANDF_D3__NANDF_D3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D3__PATA_DATA3 (_MX51_PAD_NANDF_D3__PATA_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D3__SD4_DAT4 (_MX51_PAD_NANDF_D3__SD4_DAT4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D3__USBH3_DATA4 (_MX51_PAD_NANDF_D3__USBH3_DATA4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D2__GPIO4_6 (_MX51_PAD_NANDF_D2__GPIO4_6 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_D2__NANDF_D2 (_MX51_PAD_NANDF_D2__NANDF_D2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D2__PATA_DATA2 (_MX51_PAD_NANDF_D2__PATA_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D2__SD4_DAT5 (_MX51_PAD_NANDF_D2__SD4_DAT5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D2__USBH3_DATA5 (_MX51_PAD_NANDF_D2__USBH3_DATA5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D1__GPIO4_7 (_MX51_PAD_NANDF_D1__GPIO4_7 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_D1__NANDF_D1 (_MX51_PAD_NANDF_D1__NANDF_D1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D1__PATA_DATA1 (_MX51_PAD_NANDF_D1__PATA_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D1__SD4_DAT6 (_MX51_PAD_NANDF_D1__SD4_DAT6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D1__USBH3_DATA6 (_MX51_PAD_NANDF_D1__USBH3_DATA6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D0__GPIO4_8 (_MX51_PAD_NANDF_D0__GPIO4_8 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_D0__NANDF_D0 (_MX51_PAD_NANDF_D0__NANDF_D0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D0__PATA_DATA0 (_MX51_PAD_NANDF_D0__PATA_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D0__SD4_DAT7 (_MX51_PAD_NANDF_D0__SD4_DAT7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D0__USBH3_DATA7 (_MX51_PAD_NANDF_D0__USBH3_DATA7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSI1_D8__CSI1_D8 (_MX51_PAD_CSI1_D8__CSI1_D8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSI1_D8__GPIO3_12 (_MX51_PAD_CSI1_D8__GPIO3_12 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_CSI1_D9__CSI1_D9 (_MX51_PAD_CSI1_D9__CSI1_D9 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSI1_D9__GPIO3_13 (_MX51_PAD_CSI1_D9__GPIO3_13 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_CSI1_D10__CSI1_D10 (_MX51_PAD_CSI1_D10__CSI1_D10 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSI1_D11__CSI1_D11 (_MX51_PAD_CSI1_D11__CSI1_D11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSI1_D12__CSI1_D12 (_MX51_PAD_CSI1_D12__CSI1_D12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSI1_D13__CSI1_D13 (_MX51_PAD_CSI1_D13__CSI1_D13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSI1_D14__CSI1_D14 (_MX51_PAD_CSI1_D14__CSI1_D14 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSI1_D15__CSI1_D15 (_MX51_PAD_CSI1_D15__CSI1_D15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSI1_D16__CSI1_D16 (_MX51_PAD_CSI1_D16__CSI1_D16 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSI1_D17__CSI1_D17 (_MX51_PAD_CSI1_D17__CSI1_D17 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSI1_D18__CSI1_D18 (_MX51_PAD_CSI1_D18__CSI1_D18 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSI1_D19__CSI1_D19 (_MX51_PAD_CSI1_D19__CSI1_D19 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC (_MX51_PAD_CSI1_VSYNC__CSI1_VSYNC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSI1_VSYNC__GPIO3_14 (_MX51_PAD_CSI1_VSYNC__GPIO3_14 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC (_MX51_PAD_CSI1_HSYNC__CSI1_HSYNC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSI1_HSYNC__GPIO3_15 (_MX51_PAD_CSI1_HSYNC__GPIO3_15 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK (_MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSI1_MCLK__CSI1_MCLK (_MX51_PAD_CSI1_MCLK__CSI1_MCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSI2_D12__CSI2_D12 (_MX51_PAD_CSI2_D12__CSI2_D12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSI2_D12__GPIO4_9 (_MX51_PAD_CSI2_D12__GPIO4_9 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_CSI2_D13__CSI2_D13 (_MX51_PAD_CSI2_D13__CSI2_D13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSI2_D13__GPIO4_10 (_MX51_PAD_CSI2_D13__GPIO4_10 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_CSI2_D14__CSI2_D14 (_MX51_PAD_CSI2_D14__CSI2_D14 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSI2_D15__CSI2_D15 (_MX51_PAD_CSI2_D15__CSI2_D15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSI2_D16__CSI2_D16 (_MX51_PAD_CSI2_D16__CSI2_D16 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSI2_D17__CSI2_D17 (_MX51_PAD_CSI2_D17__CSI2_D17 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSI2_D18__CSI2_D18 (_MX51_PAD_CSI2_D18__CSI2_D18 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSI2_D18__GPIO4_11 (_MX51_PAD_CSI2_D18__GPIO4_11 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_CSI2_D19__CSI2_D19 (_MX51_PAD_CSI2_D19__CSI2_D19 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSI2_D19__GPIO4_12 (_MX51_PAD_CSI2_D19__GPIO4_12 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_CSI2_VSYNC__CSI2_VSYNC (_MX51_PAD_CSI2_VSYNC__CSI2_VSYNC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSI2_VSYNC__GPIO4_13 (_MX51_PAD_CSI2_VSYNC__GPIO4_13 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_CSI2_HSYNC__CSI2_HSYNC (_MX51_PAD_CSI2_HSYNC__CSI2_HSYNC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSI2_HSYNC__GPIO4_14 (_MX51_PAD_CSI2_HSYNC__GPIO4_14 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK (_MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSI2_PIXCLK__GPIO4_15 (_MX51_PAD_CSI2_PIXCLK__GPIO4_15 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_I2C1_CLK__GPIO4_16 (_MX51_PAD_I2C1_CLK__GPIO4_16 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_I2C1_CLK__I2C1_CLK (_MX51_PAD_I2C1_CLK__I2C1_CLK | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) +#define MX51_PAD_I2C1_DAT__GPIO4_17 (_MX51_PAD_I2C1_DAT__GPIO4_17 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_I2C1_DAT__I2C1_DAT (_MX51_PAD_I2C1_DAT__I2C1_DAT | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) +#define MX51_PAD_AUD3_BB_TXD__AUD3_TXD (_MX51_PAD_AUD3_BB_TXD__AUD3_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_AUD3_BB_TXD__GPIO4_18 (_MX51_PAD_AUD3_BB_TXD__GPIO4_18 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_AUD3_BB_RXD__AUD3_RXD (_MX51_PAD_AUD3_BB_RXD__AUD3_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_AUD3_BB_RXD__GPIO4_19 (_MX51_PAD_AUD3_BB_RXD__GPIO4_19 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_AUD3_BB_RXD__UART3_RXD (_MX51_PAD_AUD3_BB_RXD__UART3_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_AUD3_BB_CK__AUD3_TXC (_MX51_PAD_AUD3_BB_CK__AUD3_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_AUD3_BB_CK__GPIO4_20 (_MX51_PAD_AUD3_BB_CK__GPIO4_20 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_AUD3_BB_FS__AUD3_TXFS (_MX51_PAD_AUD3_BB_FS__AUD3_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_AUD3_BB_FS__GPIO4_21 (_MX51_PAD_AUD3_BB_FS__GPIO4_21 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_AUD3_BB_FS__UART3_TXD (_MX51_PAD_AUD3_BB_FS__UART3_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI (_MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_CSPI1_MOSI__GPIO4_22 (_MX51_PAD_CSPI1_MOSI__GPIO4_22 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_CSPI1_MOSI__I2C1_SDA (_MX51_PAD_CSPI1_MOSI__I2C1_SDA | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) +#define MX51_PAD_CSPI1_MISO__AUD4_RXD (_MX51_PAD_CSPI1_MISO__AUD4_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSPI1_MISO__ECSPI1_MISO (_MX51_PAD_CSPI1_MISO__ECSPI1_MISO | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_CSPI1_MISO__GPIO4_23 (_MX51_PAD_CSPI1_MISO__GPIO4_23 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_CSPI1_SS0__AUD4_TXC (_MX51_PAD_CSPI1_SS0__AUD4_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSPI1_SS0__ECSPI1_SS0 (_MX51_PAD_CSPI1_SS0__ECSPI1_SS0 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_CSPI1_SS0__GPIO4_24 (_MX51_PAD_CSPI1_SS0__GPIO4_24 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_CSPI1_SS1__AUD4_TXD (_MX51_PAD_CSPI1_SS1__AUD4_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSPI1_SS1__ECSPI1_SS1 (_MX51_PAD_CSPI1_SS1__ECSPI1_SS1 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_CSPI1_SS1__GPIO4_25 (_MX51_PAD_CSPI1_SS1__GPIO4_25 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_CSPI1_RDY__AUD4_TXFS (_MX51_PAD_CSPI1_RDY__AUD4_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSPI1_RDY__ECSPI1_RDY (_MX51_PAD_CSPI1_RDY__ECSPI1_RDY | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_CSPI1_RDY__GPIO4_26 (_MX51_PAD_CSPI1_RDY__GPIO4_26 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK (_MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_CSPI1_SCLK__GPIO4_27 (_MX51_PAD_CSPI1_SCLK__GPIO4_27 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_CSPI1_SCLK__I2C1_SCL (_MX51_PAD_CSPI1_SCLK__I2C1_SCL | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) +#define MX51_PAD_UART1_RXD__GPIO4_28 (_MX51_PAD_UART1_RXD__GPIO4_28 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_UART1_RXD__UART1_RXD (_MX51_PAD_UART1_RXD__UART1_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_UART1_TXD__GPIO4_29 (_MX51_PAD_UART1_TXD__GPIO4_29 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_UART1_TXD__PWM2_PWMO (_MX51_PAD_UART1_TXD__PWM2_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_UART1_TXD__UART1_TXD (_MX51_PAD_UART1_TXD__UART1_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_UART1_RTS__GPIO4_30 (_MX51_PAD_UART1_RTS__GPIO4_30 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_UART1_RTS__UART1_RTS (_MX51_PAD_UART1_RTS__UART1_RTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_UART1_CTS__GPIO4_31 (_MX51_PAD_UART1_CTS__GPIO4_31 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_UART1_CTS__UART1_CTS (_MX51_PAD_UART1_CTS__UART1_CTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_UART2_RXD__FIRI_TXD (_MX51_PAD_UART2_RXD__FIRI_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_UART2_RXD__GPIO1_20 (_MX51_PAD_UART2_RXD__GPIO1_20 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_UART2_RXD__UART2_RXD (_MX51_PAD_UART2_RXD__UART2_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_UART2_TXD__FIRI_RXD (_MX51_PAD_UART2_TXD__FIRI_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_UART2_TXD__GPIO1_21 (_MX51_PAD_UART2_TXD__GPIO1_21 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_UART2_TXD__UART2_TXD (_MX51_PAD_UART2_TXD__UART2_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_UART3_RXD__CSI1_D0 (_MX51_PAD_UART3_RXD__CSI1_D0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_UART3_RXD__GPIO1_22 (_MX51_PAD_UART3_RXD__GPIO1_22 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_UART3_RXD__UART1_DTR (_MX51_PAD_UART3_RXD__UART1_DTR | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_UART3_RXD__UART3_RXD (_MX51_PAD_UART3_RXD__UART3_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_UART3_TXD__CSI1_D1 (_MX51_PAD_UART3_TXD__CSI1_D1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_UART3_TXD__GPIO1_23 (_MX51_PAD_UART3_TXD__GPIO1_23 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_UART3_TXD__UART1_DSR (_MX51_PAD_UART3_TXD__UART1_DSR | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_UART3_TXD__UART3_TXD (_MX51_PAD_UART3_TXD__UART3_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_OWIRE_LINE__GPIO1_24 (_MX51_PAD_OWIRE_LINE__GPIO1_24 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_OWIRE_LINE__OWIRE_LINE (_MX51_PAD_OWIRE_LINE__OWIRE_LINE | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_OWIRE_LINE__SPDIF_OUT (_MX51_PAD_OWIRE_LINE__SPDIF_OUT | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_KEY_ROW0__KEY_ROW0 (_MX51_PAD_KEY_ROW0__KEY_ROW0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_KEY_ROW1__KEY_ROW1 (_MX51_PAD_KEY_ROW1__KEY_ROW1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_KEY_ROW2__KEY_ROW2 (_MX51_PAD_KEY_ROW2__KEY_ROW2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_KEY_ROW3__KEY_ROW3 (_MX51_PAD_KEY_ROW3__KEY_ROW3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_KEY_COL0__KEY_COL0 (_MX51_PAD_KEY_COL0__KEY_COL0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_KEY_COL0__PLL1_BYP (_MX51_PAD_KEY_COL0__PLL1_BYP | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_KEY_COL1__KEY_COL1 (_MX51_PAD_KEY_COL1__KEY_COL1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_KEY_COL1__PLL2_BYP (_MX51_PAD_KEY_COL1__PLL2_BYP | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_KEY_COL2__KEY_COL2 (_MX51_PAD_KEY_COL2__KEY_COL2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_KEY_COL2__PLL3_BYP (_MX51_PAD_KEY_COL2__PLL3_BYP | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_KEY_COL3__KEY_COL3 (_MX51_PAD_KEY_COL3__KEY_COL3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_KEY_COL4__I2C2_SCL (_MX51_PAD_KEY_COL4__I2C2_SCL | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) +#define MX51_PAD_KEY_COL4__KEY_COL4 (_MX51_PAD_KEY_COL4__KEY_COL4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_KEY_COL4__SPDIF_OUT1 (_MX51_PAD_KEY_COL4__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_KEY_COL4__UART1_RI (_MX51_PAD_KEY_COL4__UART1_RI | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_KEY_COL4__UART3_RTS (_MX51_PAD_KEY_COL4__UART3_RTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_KEY_COL5__I2C2_SDA (_MX51_PAD_KEY_COL5__I2C2_SDA | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) +#define MX51_PAD_KEY_COL5__KEY_COL5 (_MX51_PAD_KEY_COL5__KEY_COL5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_KEY_COL5__UART1_DCD (_MX51_PAD_KEY_COL5__UART1_DCD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_KEY_COL5__UART3_CTS (_MX51_PAD_KEY_COL5__UART3_CTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_USBH1_CLK__CSPI_SCLK (_MX51_PAD_USBH1_CLK__CSPI_SCLK | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_USBH1_CLK__GPIO1_25 (_MX51_PAD_USBH1_CLK__GPIO1_25 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_USBH1_CLK__I2C2_SCL (_MX51_PAD_USBH1_CLK__I2C2_SCL | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) +#define MX51_PAD_USBH1_CLK__USBH1_CLK (_MX51_PAD_USBH1_CLK__USBH1_CLK | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL)) +#define MX51_PAD_USBH1_DIR__CSPI_MOSI (_MX51_PAD_USBH1_DIR__CSPI_MOSI | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_USBH1_DIR__GPIO1_26 (_MX51_PAD_USBH1_DIR__GPIO1_26 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_USBH1_DIR__I2C2_SDA (_MX51_PAD_USBH1_DIR__I2C2_SDA | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) +#define MX51_PAD_USBH1_DIR__USBH1_DIR (_MX51_PAD_USBH1_DIR__USBH1_DIR | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL)) +#define MX51_PAD_USBH1_STP__CSPI_RDY (_MX51_PAD_USBH1_STP__CSPI_RDY | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_USBH1_STP__GPIO1_27 (_MX51_PAD_USBH1_STP__GPIO1_27 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_USBH1_STP__UART3_RXD (_MX51_PAD_USBH1_STP__UART3_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_USBH1_STP__USBH1_STP (_MX51_PAD_USBH1_STP__USBH1_STP | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL)) +#define MX51_PAD_USBH1_NXT__CSPI_MISO (_MX51_PAD_USBH1_NXT__CSPI_MISO | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_USBH1_NXT__GPIO1_28 (_MX51_PAD_USBH1_NXT__GPIO1_28 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_USBH1_NXT__UART3_TXD (_MX51_PAD_USBH1_NXT__UART3_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_USBH1_NXT__USBH1_NXT (_MX51_PAD_USBH1_NXT__USBH1_NXT | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL)) +#define MX51_PAD_USBH1_DATA0__GPIO1_11 (_MX51_PAD_USBH1_DATA0__GPIO1_11 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_USBH1_DATA0__UART2_CTS (_MX51_PAD_USBH1_DATA0__UART2_CTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_USBH1_DATA0__USBH1_DATA0 (_MX51_PAD_USBH1_DATA0__USBH1_DATA0 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL)) +#define MX51_PAD_USBH1_DATA1__GPIO1_12 (_MX51_PAD_USBH1_DATA1__GPIO1_12 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_USBH1_DATA1__UART2_RXD (_MX51_PAD_USBH1_DATA1__UART2_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_USBH1_DATA1__USBH1_DATA1 (_MX51_PAD_USBH1_DATA1__USBH1_DATA1 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL)) +#define MX51_PAD_USBH1_DATA2__GPIO1_13 (_MX51_PAD_USBH1_DATA2__GPIO1_13 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_USBH1_DATA2__UART2_TXD (_MX51_PAD_USBH1_DATA2__UART2_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_USBH1_DATA2__USBH1_DATA2 (_MX51_PAD_USBH1_DATA2__USBH1_DATA2 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL)) +#define MX51_PAD_USBH1_DATA3__GPIO1_14 (_MX51_PAD_USBH1_DATA3__GPIO1_14 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_USBH1_DATA3__UART2_RTS (_MX51_PAD_USBH1_DATA3__UART2_RTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_USBH1_DATA3__USBH1_DATA3 (_MX51_PAD_USBH1_DATA3__USBH1_DATA3 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL)) +#define MX51_PAD_USBH1_DATA4__CSPI_SS0 (_MX51_PAD_USBH1_DATA4__CSPI_SS0 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_USBH1_DATA4__GPIO1_15 (_MX51_PAD_USBH1_DATA4__GPIO1_15 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_USBH1_DATA4__USBH1_DATA4 (_MX51_PAD_USBH1_DATA4__USBH1_DATA4 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL)) +#define MX51_PAD_USBH1_DATA5__CSPI_SS1 (_MX51_PAD_USBH1_DATA5__CSPI_SS1 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_USBH1_DATA5__GPIO1_16 (_MX51_PAD_USBH1_DATA5__GPIO1_16 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_USBH1_DATA5__USBH1_DATA5 (_MX51_PAD_USBH1_DATA5__USBH1_DATA5 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL)) +#define MX51_PAD_USBH1_DATA6__CSPI_SS3 (_MX51_PAD_USBH1_DATA6__CSPI_SS3 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_USBH1_DATA6__GPIO1_17 (_MX51_PAD_USBH1_DATA6__GPIO1_17 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_USBH1_DATA6__USBH1_DATA6 (_MX51_PAD_USBH1_DATA6__USBH1_DATA6 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL)) +#define MX51_PAD_USBH1_DATA7__ECSPI1_SS3 (_MX51_PAD_USBH1_DATA7__ECSPI1_SS3 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_USBH1_DATA7__ECSPI2_SS3 (_MX51_PAD_USBH1_DATA7__ECSPI2_SS3 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_USBH1_DATA7__GPIO1_18 (_MX51_PAD_USBH1_DATA7__GPIO1_18 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_USBH1_DATA7__USBH1_DATA7 (_MX51_PAD_USBH1_DATA7__USBH1_DATA7 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL)) +#define MX51_PAD_DI1_PIN11__DI1_PIN11 (_MX51_PAD_DI1_PIN11__DI1_PIN11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DI1_PIN11__ECSPI1_SS2 (_MX51_PAD_DI1_PIN11__ECSPI1_SS2 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_DI1_PIN11__GPIO3_0 (_MX51_PAD_DI1_PIN11__GPIO3_0 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_DI1_PIN12__DI1_PIN12 (_MX51_PAD_DI1_PIN12__DI1_PIN12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DI1_PIN12__GPIO3_1 (_MX51_PAD_DI1_PIN12__GPIO3_1 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_DI1_PIN13__DI1_PIN13 (_MX51_PAD_DI1_PIN13__DI1_PIN13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DI1_PIN13__GPIO3_2 (_MX51_PAD_DI1_PIN13__GPIO3_2 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_DI1_D0_CS__DI1_D0_CS (_MX51_PAD_DI1_D0_CS__DI1_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DI1_D0_CS__GPIO3_3 (_MX51_PAD_DI1_D0_CS__GPIO3_3 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_DI1_D1_CS__DI1_D1_CS (_MX51_PAD_DI1_D1_CS__DI1_D1_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DI1_D1_CS__DISP1_PIN14 (_MX51_PAD_DI1_D1_CS__DISP1_PIN14 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DI1_D1_CS__DISP1_PIN5 (_MX51_PAD_DI1_D1_CS__DISP1_PIN5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DI1_D1_CS__GPIO3_4 (_MX51_PAD_DI1_D1_CS__GPIO3_4 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_DISPB2_SER_DIN__DISP1_PIN1 (_MX51_PAD_DISPB2_SER_DIN__DISP1_PIN1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN (_MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISPB2_SER_DIN__GPIO3_5 (_MX51_PAD_DISPB2_SER_DIN__GPIO3_5 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_DISPB2_SER_DIO__DISP1_PIN6 (_MX51_PAD_DISPB2_SER_DIO__DISP1_PIN6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO (_MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISPB2_SER_DIO__GPIO3_6 (_MX51_PAD_DISPB2_SER_DIO__GPIO3_6 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN17 (_MX51_PAD_DISPB2_SER_CLK__DISP1_PIN17 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN7 (_MX51_PAD_DISPB2_SER_CLK__DISP1_PIN7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK (_MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISPB2_SER_CLK__GPIO3_7 (_MX51_PAD_DISPB2_SER_CLK__GPIO3_7 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_DISPB2_SER_RS__DISP1_EXT_CLK (_MX51_PAD_DISPB2_SER_RS__DISP1_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISPB2_SER_RS__DISP1_PIN16 (_MX51_PAD_DISPB2_SER_RS__DISP1_PIN16 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISPB2_SER_RS__DISP1_PIN8 (_MX51_PAD_DISPB2_SER_RS__DISP1_PIN8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS (_MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS (_MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISPB2_SER_RS__GPIO3_8 (_MX51_PAD_DISPB2_SER_RS__GPIO3_8 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT0__DISP1_DAT0 (_MX51_PAD_DISP1_DAT0__DISP1_DAT0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT1__DISP1_DAT1 (_MX51_PAD_DISP1_DAT1__DISP1_DAT1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT2__DISP1_DAT2 (_MX51_PAD_DISP1_DAT2__DISP1_DAT2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT3__DISP1_DAT3 (_MX51_PAD_DISP1_DAT3__DISP1_DAT3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT4__DISP1_DAT4 (_MX51_PAD_DISP1_DAT4__DISP1_DAT4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT5__DISP1_DAT5 (_MX51_PAD_DISP1_DAT5__DISP1_DAT5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT6__BOOT_USB_SRC (_MX51_PAD_DISP1_DAT6__BOOT_USB_SRC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT6__DISP1_DAT6 (_MX51_PAD_DISP1_DAT6__DISP1_DAT6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT7__BOOT_EEPROM_CFG (_MX51_PAD_DISP1_DAT7__BOOT_EEPROM_CFG | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT7__DISP1_DAT7 (_MX51_PAD_DISP1_DAT7__DISP1_DAT7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT8__BOOT_SRC0 (_MX51_PAD_DISP1_DAT8__BOOT_SRC0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT8__DISP1_DAT8 (_MX51_PAD_DISP1_DAT8__DISP1_DAT8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT9__BOOT_SRC1 (_MX51_PAD_DISP1_DAT9__BOOT_SRC1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT9__DISP1_DAT9 (_MX51_PAD_DISP1_DAT9__DISP1_DAT9 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT10__BOOT_SPARE_SIZE (_MX51_PAD_DISP1_DAT10__BOOT_SPARE_SIZE | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT10__DISP1_DAT10 (_MX51_PAD_DISP1_DAT10__DISP1_DAT10 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT11__BOOT_LPB_FREQ2 (_MX51_PAD_DISP1_DAT11__BOOT_LPB_FREQ2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT11__DISP1_DAT11 (_MX51_PAD_DISP1_DAT11__DISP1_DAT11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT12__BOOT_MLC_SEL (_MX51_PAD_DISP1_DAT12__BOOT_MLC_SEL | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT12__DISP1_DAT12 (_MX51_PAD_DISP1_DAT12__DISP1_DAT12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT13__BOOT_MEM_CTL0 (_MX51_PAD_DISP1_DAT13__BOOT_MEM_CTL0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT13__DISP1_DAT13 (_MX51_PAD_DISP1_DAT13__DISP1_DAT13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT14__BOOT_MEM_CTL1 (_MX51_PAD_DISP1_DAT14__BOOT_MEM_CTL1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT14__DISP1_DAT14 (_MX51_PAD_DISP1_DAT14__DISP1_DAT14 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT15__BOOT_BUS_WIDTH (_MX51_PAD_DISP1_DAT15__BOOT_BUS_WIDTH | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT15__DISP1_DAT15 (_MX51_PAD_DISP1_DAT15__DISP1_DAT15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT16__BOOT_PAGE_SIZE0 (_MX51_PAD_DISP1_DAT16__BOOT_PAGE_SIZE0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT16__DISP1_DAT16 (_MX51_PAD_DISP1_DAT16__DISP1_DAT16 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT17__BOOT_PAGE_SIZE1 (_MX51_PAD_DISP1_DAT17__BOOT_PAGE_SIZE1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT17__DISP1_DAT17 (_MX51_PAD_DISP1_DAT17__DISP1_DAT17 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT18__BOOT_WEIM_MUXED0 (_MX51_PAD_DISP1_DAT18__BOOT_WEIM_MUXED0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT18__DISP1_DAT18 (_MX51_PAD_DISP1_DAT18__DISP1_DAT18 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT18__DISP2_PIN11 (_MX51_PAD_DISP1_DAT18__DISP2_PIN11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT18__DISP2_PIN5 (_MX51_PAD_DISP1_DAT18__DISP2_PIN5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT19__BOOT_WEIM_MUXED1 (_MX51_PAD_DISP1_DAT19__BOOT_WEIM_MUXED1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT19__DISP1_DAT19 (_MX51_PAD_DISP1_DAT19__DISP1_DAT19 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT19__DISP2_PIN12 (_MX51_PAD_DISP1_DAT19__DISP2_PIN12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT19__DISP2_PIN6 (_MX51_PAD_DISP1_DAT19__DISP2_PIN6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT20__BOOT_MEM_TYPE0 (_MX51_PAD_DISP1_DAT20__BOOT_MEM_TYPE0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT20__DISP1_DAT20 (_MX51_PAD_DISP1_DAT20__DISP1_DAT20 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT20__DISP2_PIN13 (_MX51_PAD_DISP1_DAT20__DISP2_PIN13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT20__DISP2_PIN7 (_MX51_PAD_DISP1_DAT20__DISP2_PIN7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT21__BOOT_MEM_TYPE1 (_MX51_PAD_DISP1_DAT21__BOOT_MEM_TYPE1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT21__DISP1_DAT21 (_MX51_PAD_DISP1_DAT21__DISP1_DAT21 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT21__DISP2_PIN14 (_MX51_PAD_DISP1_DAT21__DISP2_PIN14 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT21__DISP2_PIN8 (_MX51_PAD_DISP1_DAT21__DISP2_PIN8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT22__BOOT_LPB_FREQ0 (_MX51_PAD_DISP1_DAT22__BOOT_LPB_FREQ0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT22__DISP1_DAT22 (_MX51_PAD_DISP1_DAT22__DISP1_DAT22 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT22__DISP2_D0_CS (_MX51_PAD_DISP1_DAT22__DISP2_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT22__DISP2_DAT16 (_MX51_PAD_DISP1_DAT22__DISP2_DAT16 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT23__BOOT_LPB_FREQ1 (_MX51_PAD_DISP1_DAT23__BOOT_LPB_FREQ1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT23__DISP1_DAT23 (_MX51_PAD_DISP1_DAT23__DISP1_DAT23 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT23__DISP2_D1_CS (_MX51_PAD_DISP1_DAT23__DISP2_D1_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT23__DISP2_DAT17 (_MX51_PAD_DISP1_DAT23__DISP2_DAT17 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT23__DISP2_SER_CS (_MX51_PAD_DISP1_DAT23__DISP2_SER_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DI1_PIN3__DI1_PIN3 (_MX51_PAD_DI1_PIN3__DI1_PIN3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DI1_PIN2__DI1_PIN2 (_MX51_PAD_DI1_PIN2__DI1_PIN2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DI_GP2__DISP1_SER_CLK (_MX51_PAD_DI_GP2__DISP1_SER_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DI_GP2__DISP2_WAIT (_MX51_PAD_DI_GP2__DISP2_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DI_GP3__CSI1_DATA_EN (_MX51_PAD_DI_GP3__CSI1_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DI_GP3__DISP1_SER_DIO (_MX51_PAD_DI_GP3__DISP1_SER_DIO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DI_GP3__FEC_TX_ER (_MX51_PAD_DI_GP3__FEC_TX_ER | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) +#define MX51_PAD_DI2_PIN4__CSI2_DATA_EN (_MX51_PAD_DI2_PIN4__CSI2_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DI2_PIN4__DI2_PIN4 (_MX51_PAD_DI2_PIN4__DI2_PIN4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DI2_PIN4__FEC_CRS (_MX51_PAD_DI2_PIN4__FEC_CRS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DI2_PIN2__DI2_PIN2 (_MX51_PAD_DI2_PIN2__DI2_PIN2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DI2_PIN2__FEC_MDC (_MX51_PAD_DI2_PIN2__FEC_MDC | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) +#define MX51_PAD_DI2_PIN3__DI2_PIN3 (_MX51_PAD_DI2_PIN3__DI2_PIN3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DI2_PIN3__FEC_MDIO (_MX51_PAD_DI2_PIN3__FEC_MDIO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK (_MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 (_MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DI_GP4__DI2_PIN15 (_MX51_PAD_DI_GP4__DI2_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DI_GP4__DISP1_SER_DIN (_MX51_PAD_DI_GP4__DISP1_SER_DIN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DI_GP4__DISP2_PIN1 (_MX51_PAD_DI_GP4__DISP2_PIN1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DI_GP4__FEC_RDATA2 (_MX51_PAD_DI_GP4__FEC_RDATA2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT0__DISP2_DAT0 (_MX51_PAD_DISP2_DAT0__DISP2_DAT0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT0__FEC_RDATA3 (_MX51_PAD_DISP2_DAT0__FEC_RDATA3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT0__KEY_COL6 (_MX51_PAD_DISP2_DAT0__KEY_COL6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT0__UART3_RXD (_MX51_PAD_DISP2_DAT0__UART3_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT0__USBH3_CLK (_MX51_PAD_DISP2_DAT0__USBH3_CLK | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT1__DISP2_DAT1 (_MX51_PAD_DISP2_DAT1__DISP2_DAT1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT1__FEC_RX_ER (_MX51_PAD_DISP2_DAT1__FEC_RX_ER | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT1__KEY_COL7 (_MX51_PAD_DISP2_DAT1__KEY_COL7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT1__UART3_TXD (_MX51_PAD_DISP2_DAT1__UART3_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT1__USBH3_DIR (_MX51_PAD_DISP2_DAT1__USBH3_DIR | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT2__DISP2_DAT2 (_MX51_PAD_DISP2_DAT2__DISP2_DAT2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT3__DISP2_DAT3 (_MX51_PAD_DISP2_DAT3__DISP2_DAT3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT4__DISP2_DAT4 (_MX51_PAD_DISP2_DAT4__DISP2_DAT4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT5__DISP2_DAT5 (_MX51_PAD_DISP2_DAT5__DISP2_DAT5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT6__DISP2_DAT6 (_MX51_PAD_DISP2_DAT6__DISP2_DAT6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT6__FEC_TDATA1 (_MX51_PAD_DISP2_DAT6__FEC_TDATA1 | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) +#define MX51_PAD_DISP2_DAT6__GPIO1_19 (_MX51_PAD_DISP2_DAT6__GPIO1_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT6__KEY_ROW4 (_MX51_PAD_DISP2_DAT6__KEY_ROW4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT6__USBH3_STP (_MX51_PAD_DISP2_DAT6__USBH3_STP | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT7__DISP2_DAT7 (_MX51_PAD_DISP2_DAT7__DISP2_DAT7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT7__FEC_TDATA2 (_MX51_PAD_DISP2_DAT7__FEC_TDATA2 | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) +#define MX51_PAD_DISP2_DAT7__GPIO1_29 (_MX51_PAD_DISP2_DAT7__GPIO1_29 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT7__KEY_ROW5 (_MX51_PAD_DISP2_DAT7__KEY_ROW5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT7__USBH3_NXT (_MX51_PAD_DISP2_DAT7__USBH3_NXT | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT8__DISP2_DAT8 (_MX51_PAD_DISP2_DAT8__DISP2_DAT8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT8__FEC_TDATA3 (_MX51_PAD_DISP2_DAT8__FEC_TDATA3 | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) +#define MX51_PAD_DISP2_DAT8__GPIO1_30 (_MX51_PAD_DISP2_DAT8__GPIO1_30 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT8__KEY_ROW6 (_MX51_PAD_DISP2_DAT8__KEY_ROW6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT8__USBH3_DATA0 (_MX51_PAD_DISP2_DAT8__USBH3_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT9__AUD6_RXC (_MX51_PAD_DISP2_DAT9__AUD6_RXC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT9__DISP2_DAT9 (_MX51_PAD_DISP2_DAT9__DISP2_DAT9 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT9__FEC_TX_EN (_MX51_PAD_DISP2_DAT9__FEC_TX_EN | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) +#define MX51_PAD_DISP2_DAT9__GPIO1_31 (_MX51_PAD_DISP2_DAT9__GPIO1_31 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT9__USBH3_DATA1 (_MX51_PAD_DISP2_DAT9__USBH3_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT10__DISP2_DAT10 (_MX51_PAD_DISP2_DAT10__DISP2_DAT10 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT10__DISP2_SER_CS (_MX51_PAD_DISP2_DAT10__DISP2_SER_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT10__FEC_COL (_MX51_PAD_DISP2_DAT10__FEC_COL | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT10__KEY_ROW7 (_MX51_PAD_DISP2_DAT10__KEY_ROW7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT10__USBH3_DATA2 (_MX51_PAD_DISP2_DAT10__USBH3_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT11__AUD6_TXD (_MX51_PAD_DISP2_DAT11__AUD6_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT11__DISP2_DAT11 (_MX51_PAD_DISP2_DAT11__DISP2_DAT11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT11__FEC_RX_CLK (_MX51_PAD_DISP2_DAT11__FEC_RX_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT11__GPIO1_10 (_MX51_PAD_DISP2_DAT11__GPIO1_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT11__USBH3_DATA3 (_MX51_PAD_DISP2_DAT11__USBH3_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT12__AUD6_RXD (_MX51_PAD_DISP2_DAT12__AUD6_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT12__DISP2_DAT12 (_MX51_PAD_DISP2_DAT12__DISP2_DAT12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT12__FEC_RX_DV (_MX51_PAD_DISP2_DAT12__FEC_RX_DV | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT12__USBH3_DATA4 (_MX51_PAD_DISP2_DAT12__USBH3_DATA4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT13__AUD6_TXC (_MX51_PAD_DISP2_DAT13__AUD6_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT13__DISP2_DAT13 (_MX51_PAD_DISP2_DAT13__DISP2_DAT13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT13__FEC_TX_CLK (_MX51_PAD_DISP2_DAT13__FEC_TX_CLK | MUX_PAD_CTRL(MX51_PAD_CTRL_4)) +#define MX51_PAD_DISP2_DAT13__USBH3_DATA5 (_MX51_PAD_DISP2_DAT13__USBH3_DATA5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT14__AUD6_TXFS (_MX51_PAD_DISP2_DAT14__AUD6_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT14__DISP2_DAT14 (_MX51_PAD_DISP2_DAT14__DISP2_DAT14 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT14__FEC_RDATA0 (_MX51_PAD_DISP2_DAT14__FEC_RDATA0 | MUX_PAD_CTRL(MX51_PAD_CTRL_4)) +#define MX51_PAD_DISP2_DAT14__USBH3_DATA6 (_MX51_PAD_DISP2_DAT14__USBH3_DATA6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT15__AUD6_RXFS (_MX51_PAD_DISP2_DAT15__AUD6_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT15__DISP1_SER_CS (_MX51_PAD_DISP2_DAT15__DISP1_SER_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT15__DISP2_DAT15 (_MX51_PAD_DISP2_DAT15__DISP2_DAT15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT15__FEC_TDATA0 (_MX51_PAD_DISP2_DAT15__FEC_TDATA0 | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) +#define MX51_PAD_DISP2_DAT15__USBH3_DATA7 (_MX51_PAD_DISP2_DAT15__USBH3_DATA7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_SD1_CMD__AUD5_RXFS (_MX51_PAD_SD1_CMD__AUD5_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_SD1_CMD__CSPI_MOSI (_MX51_PAD_SD1_CMD__CSPI_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_SD1_CMD__SD1_CMD (_MX51_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL)) +#define MX51_PAD_SD1_CLK__AUD5_RXC (_MX51_PAD_SD1_CLK__AUD5_RXC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_SD1_CLK__CSPI_SCLK (_MX51_PAD_SD1_CLK__CSPI_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_SD1_CLK__SD1_CLK (_MX51_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS)) +#define MX51_PAD_SD1_DATA0__AUD5_TXD (_MX51_PAD_SD1_DATA0__AUD5_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_SD1_DATA0__CSPI_MISO (_MX51_PAD_SD1_DATA0__CSPI_MISO | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_SD1_DATA0__SD1_DATA0 (_MX51_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL)) +#define MX51_PAD_EIM_DA0__EIM_DA0 (_MX51_PAD_EIM_DA0__EIM_DA0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_DA1__EIM_DA1 (_MX51_PAD_EIM_DA1__EIM_DA1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_DA2__EIM_DA2 (_MX51_PAD_EIM_DA2__EIM_DA2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_DA3__EIM_DA3 (_MX51_PAD_EIM_DA3__EIM_DA3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_SD1_DATA1__AUD5_RXD (_MX51_PAD_SD1_DATA1__AUD5_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_SD1_DATA1__SD1_DATA1 (_MX51_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL)) +#define MX51_PAD_EIM_DA4__EIM_DA4 (_MX51_PAD_EIM_DA4__EIM_DA4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_DA5__EIM_DA5 (_MX51_PAD_EIM_DA5__EIM_DA5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_DA6__EIM_DA6 (_MX51_PAD_EIM_DA6__EIM_DA6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_DA7__EIM_DA7 (_MX51_PAD_EIM_DA7__EIM_DA7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_SD1_DATA2__AUD5_TXC (_MX51_PAD_SD1_DATA2__AUD5_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_SD1_DATA2__SD1_DATA2 (_MX51_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL)) +#define MX51_PAD_EIM_DA10__EIM_DA10 (_MX51_PAD_EIM_DA10__EIM_DA10 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_DA11__EIM_DA11 (_MX51_PAD_EIM_DA11__EIM_DA11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_DA8__EIM_DA8 (_MX51_PAD_EIM_DA8__EIM_DA8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_DA9__EIM_DA9 (_MX51_PAD_EIM_DA9__EIM_DA9 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_SD1_DATA3__AUD5_TXFS (_MX51_PAD_SD1_DATA3__AUD5_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_SD1_DATA3__CSPI_SS1 (_MX51_PAD_SD1_DATA3__CSPI_SS1 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_SD1_DATA3__SD1_DATA3 (_MX51_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL)) +#define MX51_PAD_GPIO1_0__CSPI_SS2 (_MX51_PAD_GPIO1_0__CSPI_SS2 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_GPIO1_0__GPIO1_0 (_MX51_PAD_GPIO1_0__GPIO1_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_0__SD1_CD (_MX51_PAD_GPIO1_0__SD1_CD | MUX_PAD_CTRL(MX51_ESDHC_PAD_CTRL)) +#define MX51_PAD_GPIO1_1__CSPI_MISO (_MX51_PAD_GPIO1_1__CSPI_MISO | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_GPIO1_1__GPIO1_1 (_MX51_PAD_GPIO1_1__GPIO1_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_1__SD1_WP (_MX51_PAD_GPIO1_1__SD1_WP | MUX_PAD_CTRL(MX51_ESDHC_PAD_CTRL)) +#define MX51_PAD_EIM_DA12__EIM_DA12 (_MX51_PAD_EIM_DA12__EIM_DA12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_DA13__EIM_DA13 (_MX51_PAD_EIM_DA13__EIM_DA13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_DA14__EIM_DA14 (_MX51_PAD_EIM_DA14__EIM_DA14 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_DA15__EIM_DA15 (_MX51_PAD_EIM_DA15__EIM_DA15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_SD2_CMD__CSPI_MOSI (_MX51_PAD_SD2_CMD__CSPI_MOSI | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_SD2_CMD__I2C1_SCL (_MX51_PAD_SD2_CMD__I2C1_SCL | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) +#define MX51_PAD_SD2_CMD__SD2_CMD (_MX51_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL)) +#define MX51_PAD_SD2_CLK__CSPI_SCLK (_MX51_PAD_SD2_CLK__CSPI_SCLK | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_SD2_CLK__I2C1_SDA (_MX51_PAD_SD2_CLK__I2C1_SDA | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) +#define MX51_PAD_SD2_CLK__SD2_CLK (_MX51_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS)) +#define MX51_PAD_SD2_DATA0__CSPI_MISO (_MX51_PAD_SD2_DATA0__CSPI_MISO | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_SD2_DATA0__SD1_DAT4 (_MX51_PAD_SD2_DATA0__SD1_DAT4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_SD2_DATA0__SD2_DATA0 (_MX51_PAD_SD2_DATA0__SD2_DATA0 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL)) +#define MX51_PAD_SD2_DATA1__SD1_DAT5 (_MX51_PAD_SD2_DATA1__SD1_DAT5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_SD2_DATA1__SD2_DATA1 (_MX51_PAD_SD2_DATA1__SD2_DATA1 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL)) +#define MX51_PAD_SD2_DATA1__USBH3_H2_DP (_MX51_PAD_SD2_DATA1__USBH3_H2_DP | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_SD2_DATA2__SD1_DAT6 (_MX51_PAD_SD2_DATA2__SD1_DAT6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_SD2_DATA2__SD2_DATA2 (_MX51_PAD_SD2_DATA2__SD2_DATA2 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL)) +#define MX51_PAD_SD2_DATA2__USBH3_H2_DM (_MX51_PAD_SD2_DATA2__USBH3_H2_DM | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_SD2_DATA3__CSPI_SS2 (_MX51_PAD_SD2_DATA3__CSPI_SS2 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_SD2_DATA3__SD1_DAT7 (_MX51_PAD_SD2_DATA3__SD1_DAT7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_SD2_DATA3__SD2_DATA3 (_MX51_PAD_SD2_DATA3__SD2_DATA3 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL)) +#define MX51_PAD_GPIO1_2__CCM_OUT_2 (_MX51_PAD_GPIO1_2__CCM_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_2__GPIO1_2 (_MX51_PAD_GPIO1_2__GPIO1_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_2__I2C2_SCL (_MX51_PAD_GPIO1_2__I2C2_SCL | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) +#define MX51_PAD_GPIO1_2__PLL1_BYP (_MX51_PAD_GPIO1_2__PLL1_BYP | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_2__PWM1_PWMO (_MX51_PAD_GPIO1_2__PWM1_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_3__GPIO1_3 (_MX51_PAD_GPIO1_3__GPIO1_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_3__I2C2_SDA (_MX51_PAD_GPIO1_3__I2C2_SDA | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) +#define MX51_PAD_GPIO1_3__PLL2_BYP (_MX51_PAD_GPIO1_3__PLL2_BYP | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_3__PWM2_PWMO (_MX51_PAD_GPIO1_3__PWM2_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ (_MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B (_MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_4__DISP2_EXT_CLK (_MX51_PAD_GPIO1_4__DISP2_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_4__EIM_RDY (_MX51_PAD_GPIO1_4__EIM_RDY | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_4__GPIO1_4 (_MX51_PAD_GPIO1_4__GPIO1_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_4__WDOG1_WDOG_B (_MX51_PAD_GPIO1_4__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_5__CSI2_MCLK (_MX51_PAD_GPIO1_5__CSI2_MCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_5__DISP2_PIN16 (_MX51_PAD_GPIO1_5__DISP2_PIN16 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_5__GPIO1_5 (_MX51_PAD_GPIO1_5__GPIO1_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_5__WDOG2_WDOG_B (_MX51_PAD_GPIO1_5__WDOG2_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_6__DISP2_PIN17 (_MX51_PAD_GPIO1_6__DISP2_PIN17 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_6__GPIO1_6 (_MX51_PAD_GPIO1_6__GPIO1_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_6__REF_EN_B (_MX51_PAD_GPIO1_6__REF_EN_B | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_7__CCM_OUT_0 (_MX51_PAD_GPIO1_7__CCM_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_7__GPIO1_7 (_MX51_PAD_GPIO1_7__GPIO1_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_7__SD2_WP (_MX51_PAD_GPIO1_7__SD2_WP | MUX_PAD_CTRL(MX51_ESDHC_PAD_CTRL)) +#define MX51_PAD_GPIO1_7__SPDIF_OUT1 (_MX51_PAD_GPIO1_7__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_8__CSI2_DATA_EN (_MX51_PAD_GPIO1_8__CSI2_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_8__GPIO1_8 (_MX51_PAD_GPIO1_8__GPIO1_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_8__SD2_CD (_MX51_PAD_GPIO1_8__SD2_CD | MUX_PAD_CTRL(MX51_ESDHC_PAD_CTRL)) +#define MX51_PAD_GPIO1_8__USBH3_PWR (_MX51_PAD_GPIO1_8__USBH3_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_9__CCM_OUT_1 (_MX51_PAD_GPIO1_9__CCM_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_9__DISP2_D1_CS (_MX51_PAD_GPIO1_9__DISP2_D1_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_9__DISP2_SER_CS (_MX51_PAD_GPIO1_9__DISP2_SER_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_9__GPIO1_9 (_MX51_PAD_GPIO1_9__GPIO1_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_9__SD2_LCTL (_MX51_PAD_GPIO1_9__SD2_LCTL | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_9__USBH3_OC (_MX51_PAD_GPIO1_9__USBH3_OC | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#endif /* __MACH_IOMUX_MX51_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx53.h b/arch/arm/plat-mxc/include/mach/iomux-mx53.h new file mode 100755 index 00000000..56bade10 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/iomux-mx53.h @@ -0,0 +1,2381 @@ +/* + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc.. + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __MACH_IOMUX_MX53_H__ +#define __MACH_IOMUX_MX53_H__ + +#include <mach/iomux-v3.h> + +/* These 2 defines are for pins that may not have a mux register, but could + * have a pad setting register, and vice-versa. */ +#define NON_PAD_I 0x00 + +#define MX53_UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST | PAD_CTL_HYS) +#define MX53_SDHC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_HIGH | \ + PAD_CTL_SRE_FAST) +#define PAD_CTRL_I2C (PAD_CTL_SRE_FAST | PAD_CTL_ODE | PAD_CTL_PKE | \ + PAD_CTL_PUE | PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP \ + | PAD_CTL_HYS) + +#define _MX53_PAD_GPIO_19__KPP_COL_5 IOMUX_PAD(0x348, 0x20, 0, 0x840, 0, 0) +#define _MX53_PAD_GPIO_19__GPIO4_5 IOMUX_PAD(0x348, 0x20, 1, 0x0, 0, 0) +#define _MX53_PAD_GPIO_19__CCM_CLKO IOMUX_PAD(0x348, 0x20, 2, 0x0, 0, 0) +#define _MX53_PAD_GPIO_19__SPDIF_OUT1 IOMUX_PAD(0x348, 0x20, 3, 0x0, 0, 0) +#define _MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 IOMUX_PAD(0x348, 0x20, 4, 0x0, 0, 0) +#define _MX53_PAD_GPIO_19__ECSPI1_RDY IOMUX_PAD(0x348, 0x20, 5, 0x0, 0, 0) +#define _MX53_PAD_GPIO_19__FEC_TDATA_3 IOMUX_PAD(0x348, 0x20, 6, 0x0, 0, 0) +#define _MX53_PAD_GPIO_19__SRC_INT_BOOT IOMUX_PAD(0x348, 0x20,7, 0x0, 0, 0) +#define _MX53_PAD_KEY_COL0__KPP_COL_0 IOMUX_PAD(0x34C, 0x24, o, 0x0, 0, 0) +#define _MX53_PAD_KEY_COL0__GPIO4_6 IOMUX_PAD(0x34C, 0x24, 1, 0x0, 0, 0) +#define _MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC IOMUX_PAD(0x34C, 0x24, 2, 0x758, 0, 0) +#define _MX53_PAD_KEY_COL0__UART4_TXD_MUX IOMUX_PAD(0x34C, 0x24, 4, 0x890, 0, 0) +#define _MX53_PAD_KEY_COL0__ECSPI1_SCLK IOMUX_PAD(0x34C, 0x24, 5, 0x79C, 0, 0) +#define _MX53_PAD_KEY_COL0__FEC_RDATA_3 IOMUX_PAD(0x34C, 0x24, 6, 0x0, 0, 0) +#define _MX53_PAD_KEY_COL0__SRC_ANY_PU_RST IOMUX_PAD(0x34C, 0x24, 7, 0x0, 0, 0) +#define _MX53_PAD_KEY_ROW0__KPP_ROW_0 IOMUX_PAD(0x350, 0x28, 0, 0x0, 0, 0) +#define _MX53_PAD_KEY_ROW0__GPIO4_7 IOMUX_PAD(0x350, 0x28, 1, 0x0, 0, 0) +#define _MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD IOMUX_PAD(0x350, 0x28, 2, 0x74C, 0, 0) +#define _MX53_PAD_KEY_ROW0__UART4_RXD_MUX IOMUX_PAD(0x350, 0x28, 4, 0x890, 1, 0) +#define _MX53_PAD_KEY_ROW0__ECSPI1_MOSI IOMUX_PAD(0x350, 0x28, 5, 0x7A4, 0, 0) +#define _MX53_PAD_KEY_ROW0__FEC_TX_ER IOMUX_PAD(0x350, 0x28, 6, 0x0, 0, 0) +#define _MX53_PAD_KEY_COL1__KPP_COL_1 IOMUX_PAD(0x354, 0x2C, 0, 0x0, 0, 0) +#define _MX53_PAD_KEY_COL1__GPIO4_8 IOMUX_PAD(0x354, 0x2C, 1, 0x0, 0, 0) +#define _MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS IOMUX_PAD(0x354, 0x2C, 2, 0x75C, 0, 0) +#define _MX53_PAD_KEY_COL1__UART5_TXD_MUX IOMUX_PAD(0x354, 0x2C, 4, 0x898, 0, 0) +#define _MX53_PAD_KEY_COL1__ECSPI1_MISO IOMUX_PAD(0x354, 0x2C, 5, 0x7A0, 0, 0) +#define _MX53_PAD_KEY_COL1__FEC_RX_CLK IOMUX_PAD(0x354, 0x2C, 6, 0x808, 0, 0) +#define _MX53_PAD_KEY_COL1__USBPHY1_TXREADY IOMUX_PAD(0x354, 0x2C, 7, 0x0, 0, 0) +#define _MX53_PAD_KEY_ROW1__KPP_ROW_1 IOMUX_PAD(0x358, 0x30, 0, 0x0, 0, 0) +#define _MX53_PAD_KEY_ROW1__GPIO4_9 IOMUX_PAD(0x358, 0x30, 1, 0x0, 0, 0) +#define _MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD IOMUX_PAD(0x358, 0x30, 2, 0x748, 0, 0) +#define _MX53_PAD_KEY_ROW1__UART5_RXD_MUX IOMUX_PAD(0x358, 0x30, 4, 0x898, 1, 0) +#define _MX53_PAD_KEY_ROW1__ECSPI1_SS0 IOMUX_PAD(0x358, 0x30, 5, 0x7A8, 0, 0) +#define _MX53_PAD_KEY_ROW1__FEC_COL IOMUX_PAD(0x358, 0x30, 6, 0x800, 0, 0) +#define _MX53_PAD_KEY_ROW1__USBPHY1_RXVALID IOMUX_PAD(0x358, 0x30, 7, 0x0, 0, 0) +#define _MX53_PAD_KEY_COL2__KPP_COL_2 IOMUX_PAD(0x35C, 0x34, 0, 0x0, 0, 0) +#define _MX53_PAD_KEY_COL2__GPIO4_10 IOMUX_PAD(0x35C, 0x34, 1, 0x0, 0, 0) +#define _MX53_PAD_KEY_COL2__CAN1_TXCAN IOMUX_PAD(0x35C, 0x34, 2, 0x0, 0, 0) +#define _MX53_PAD_KEY_COL2__FEC_MDIO IOMUX_PAD(0x35C, 0x34, 4, 0x804, 0, 0) +#define _MX53_PAD_KEY_COL2__ECSPI1_SS1 IOMUX_PAD(0x35C, 0x34, 5, 0x7AC, 0, 0) +#define _MX53_PAD_KEY_COL2__FEC_RDATA_2 IOMUX_PAD(0x35C, 0x34, 6, 0x0, 0, 0) +#define _MX53_PAD_KEY_COL2__USBPHY1_RXACTIVE IOMUX_PAD(0x35C, 0x34, 7, 0x0, 0, 0) +#define _MX53_PAD_KEY_ROW2__KPP_ROW_2 IOMUX_PAD(0x360, 0x38, 0, 0x0, 0, 0) +#define _MX53_PAD_KEY_ROW2__GPIO4_11 IOMUX_PAD(0x360, 0x38, 1, 0x0, 0, 0) +#define _MX53_PAD_KEY_ROW2__CAN1_RXCAN IOMUX_PAD(0x360, 0x38, 2, 0x760, 0, 0) +#define _MX53_PAD_KEY_ROW2__FEC_MDC IOMUX_PAD(0x360, 0x38, 4, 0x0, 0, 0) +#define _MX53_PAD_KEY_ROW2__ECSPI1_SS2 IOMUX_PAD(0x360, 0x38, 5, 0x7B0, 0, 0) +#define _MX53_PAD_KEY_ROW2__FEC_TDATA_2 IOMUX_PAD(0x360, 0x38, 6, 0x0, 0, 0) +#define _MX53_PAD_KEY_ROW2__USBPHY1_RXERROR IOMUX_PAD(0x360, 0x38, 7, 0x0, 0, 0) +#define _MX53_PAD_KEY_COL3__KPP_COL_3 IOMUX_PAD(0x364, 0x3C, 0, 0x0, 0, 0) +#define _MX53_PAD_KEY_COL3__GPIO4_12 IOMUX_PAD(0x364, 0x3C, 1, 0x0, 0, 0) +#define _MX53_PAD_KEY_COL3__USBOH3_H2_DP IOMUX_PAD(0x364, 0x3C, 2, 0x0, 0, 0) +#define _MX53_PAD_KEY_COL3__SPDIF_IN1 IOMUX_PAD(0x364, 0x3C, 3, 0x870, 0, 0) +#define _MX53_PAD_KEY_COL3__I2C2_SCL IOMUX_PAD(0x364, 0x3C, 4 | IOMUX_CONFIG_SION, 0x81C, 0, 0) +#define _MX53_PAD_KEY_COL3__ECSPI1_SS3 IOMUX_PAD(0x364, 0x3C, 5, 0x7B4, 0, 0) +#define _MX53_PAD_KEY_COL3__FEC_CRS IOMUX_PAD(0x364, 0x3C, 6, 0x0, 0, 0) +#define _MX53_PAD_KEY_COL3__USBPHY1_SIECLOCK IOMUX_PAD(0x364, 0x3C, 7, 0x0, 0, 0) +#define _MX53_PAD_KEY_ROW3__KPP_ROW_3 IOMUX_PAD(0x368, 0x40, 0, 0x0, 0, 0) +#define _MX53_PAD_KEY_ROW3__GPIO4_13 IOMUX_PAD(0x368, 0x40, 1, 0x0, 0, 0) +#define _MX53_PAD_KEY_ROW3__USBOH3_H2_DM IOMUX_PAD(0x368, 0x40, 2, 0x0, 0, 0) +#define _MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK IOMUX_PAD(0x368, 0x40, 3, 0x768, 0, 0) +#define _MX53_PAD_KEY_ROW3__I2C2_SDA IOMUX_PAD(0x368, 0x40, 4 | IOMUX_CONFIG_SION, 0x820, 0, 0) +#define _MX53_PAD_KEY_ROW3__OSC32K_32K_OUT IOMUX_PAD(0x368, 0x40, 5, 0x0, 0, 0) +#define _MX53_PAD_KEY_ROW3__CCM_PLL4_BYP IOMUX_PAD(0x368, 0x40, 6, 0x77C, 0, 0) +#define _MX53_PAD_KEY_ROW3__USBPHY1_LINESTATE_0 IOMUX_PAD(0x368, 0x40, 7, 0x0, 0, 0) +#define _MX53_PAD_KEY_COL4__KPP_COL_4 IOMUX_PAD(0x36C, 0x44, 0, 0x0, 0, 0) +#define _MX53_PAD_KEY_COL4__GPIO4_14 IOMUX_PAD(0x36C, 0x44, 1, 0x0, 0, 0) +#define _MX53_PAD_KEY_COL4__CAN2_TXCAN IOMUX_PAD(0x36C, 0x44, 2, 0x0, 0, 0) +#define _MX53_PAD_KEY_COL4__IPU_SISG_4 IOMUX_PAD(0x36C, 0x44, 3, 0x0, 0, 0) +#define _MX53_PAD_KEY_COL4__UART5_RTS IOMUX_PAD(0x36C, 0x44, 4, 0x894, 0, 0) +#define _MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC IOMUX_PAD(0x36C, 0x44, 5, 0x89C, 0, 0) +#define _MX53_PAD_KEY_COL4__USBPHY1_LINESTATE_1 IOMUX_PAD(0x36C, 0x44, 7, 0x0, 0, 0) +#define _MX53_PAD_KEY_ROW4__KPP_ROW_4 IOMUX_PAD(0x370, 0x48, 0, 0x0, 0, 0) +#define _MX53_PAD_KEY_ROW4__GPIO4_15 IOMUX_PAD(0x370, 0x48, 1, 0x0, 0, 0) +#define _MX53_PAD_KEY_ROW4__CAN2_RXCAN IOMUX_PAD(0x370, 0x48, 2, 0x764, 0, 0) +#define _MX53_PAD_KEY_ROW4__IPU_SISG_5 IOMUX_PAD(0x370, 0x48, 3, 0x0, 0, 0) +#define _MX53_PAD_KEY_ROW4__UART5_CTS IOMUX_PAD(0x370, 0x48, 4, 0x894, 1, 0) +#define _MX53_PAD_KEY_ROW4__USBOH3_USBOTG_PWR IOMUX_PAD(0x370, 0x48, 5, 0x0, 0, 0) +#define _MX53_PAD_KEY_ROW4__USBPHY1_VBUSVALID IOMUX_PAD(0x370, 0x48, 7, 0x0, 0, 0) +#define _MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK IOMUX_PAD(0x378, 0x4C, 0, 0x0, 0, 0) +#define _MX53_PAD_DI0_DISP_CLK__GPIO4_16 IOMUX_PAD(0x378, 0x4C, 1, 0x0, 0, 0) +#define _MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR IOMUX_PAD(0x378, 0x4C, 2, 0x0, 0, 0) +#define _MX53_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 IOMUX_PAD(0x378, 0x4C, 5, 0x0, 0, 0) +#define _MX53_PAD_DI0_DISP_CLK__EMI_EMI_DEBUG_0 IOMUX_PAD(0x378, 0x4C, 6, 0x0, 0, 0) +#define _MX53_PAD_DI0_DISP_CLK__USBPHY1_AVALID IOMUX_PAD(0x378, 0x4C, 7, 0x0, 0, 0) +#define _MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 IOMUX_PAD(0x37C, 0x50, 0, 0x0, 0, 0) +#define _MX53_PAD_DI0_PIN15__GPIO4_17 IOMUX_PAD(0x37C, 0x50, 1, 0x0, 0, 0) +#define _MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC IOMUX_PAD(0x37C, 0x50, 2, 0x0, 0, 0) +#define _MX53_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 IOMUX_PAD(0x37C, 0x50, 5, 0x0, 0, 0) +#define _MX53_PAD_DI0_PIN15__EMI_EMI_DEBUG_1 IOMUX_PAD(0x37C, 0x50, 6, 0x0, 0, 0) +#define _MX53_PAD_DI0_PIN15__USBPHY1_BVALID IOMUX_PAD(0x37C, 0x50, 7, 0x0, 0, 0) +#define _MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 IOMUX_PAD(0x380, 0x54, 0, 0x0, 0, 0) +#define _MX53_PAD_DI0_PIN2__GPIO4_18 IOMUX_PAD(0x380, 0x54, 1, 0x0, 0, 0) +#define _MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD IOMUX_PAD(0x380, 0x54, 2, 0x0, 0, 0) +#define _MX53_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 IOMUX_PAD(0x380, 0x54, 5, 0x0, 0, 0) +#define _MX53_PAD_DI0_PIN2__EMI_EMI_DEBUG_2 IOMUX_PAD(0x380, 0x54, 6, 0x0, 0, 0) +#define _MX53_PAD_DI0_PIN2__USBPHY1_ENDSESSION IOMUX_PAD(0x380, 0x54, 7, 0x0, 0, 0) +#define _MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 IOMUX_PAD(0x384, 0x58, 0, 0x0, 0, 0) +#define _MX53_PAD_DI0_PIN3__GPIO4_19 IOMUX_PAD(0x384, 0x58, 1, 0x0, 0, 0) +#define _MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS IOMUX_PAD(0x384, 0x58, 2, 0x0, 0, 0) +#define _MX53_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 IOMUX_PAD(0x384, 0x58, 5, 0x0, 0, 0) +#define _MX53_PAD_DI0_PIN3__EMI_EMI_DEBUG_3 IOMUX_PAD(0x384, 0x58, 6, 0x0, 0, 0) +#define _MX53_PAD_DI0_PIN3__USBPHY1_IDDIG IOMUX_PAD(0x384, 0x58, 7, 0x0, 0, 0) +#define _MX53_PAD_DI0_PIN4__IPU_DI0_PIN4 IOMUX_PAD(0x388, 0x5C, 0, 0x0, 0, 0) +#define _MX53_PAD_DI0_PIN4__GPIO4_20 IOMUX_PAD(0x388, 0x5C, 1, 0x0, 0, 0) +#define _MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD IOMUX_PAD(0x388, 0x5C, 2, 0x0, 0, 0) +#define _MX53_PAD_DI0_PIN4__ESDHC1_WP IOMUX_PAD(0x388, 0x5C, 3, 0x7FC, 0, 0) +#define _MX53_PAD_DI0_PIN4__SDMA_DEBUG_YIELD IOMUX_PAD(0x388, 0x5C, 5, 0x0, 0, 0) +#define _MX53_PAD_DI0_PIN4__EMI_EMI_DEBUG_4 IOMUX_PAD(0x388, 0x5C, 6, 0x0, 0, 0) +#define _MX53_PAD_DI0_PIN4__USBPHY1_HOSTDISCONNECT IOMUX_PAD(0x388, 0x5C, 7, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 IOMUX_PAD(0x38C, 0x60, 0, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT0__GPIO4_21 IOMUX_PAD(0x38C, 0x60, 1, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT0__CSPI_SCLK IOMUX_PAD(0x38C, 0x60, 2, 0x780, 0, 0) +#define _MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0 IOMUX_PAD(0x38C, 0x60, 3, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN IOMUX_PAD(0x38C, 0x60, 5, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT0__EMI_EMI_DEBUG_5 IOMUX_PAD(0x38C, 0x60, 6, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT0__USBPHY2_TXREADY IOMUX_PAD(0x38C, 0x60, 7, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 IOMUX_PAD(0x390, 0x64, 0, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT1__GPIO4_22 IOMUX_PAD(0x390, 0x64, 1, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT1__CSPI_MOSI IOMUX_PAD(0x390, 0x64, 2, 0x788, 0, 0) +#define _MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1 IOMUX_PAD(0x390, 0x64, 3, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL IOMUX_PAD(0x390, 0x64, 5, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT1__EMI_EMI_DEBUG_6 IOMUX_PAD(0x390, 0x64, 6, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT1__USBPHY2_RXVALID IOMUX_PAD(0x390, 0x64, 7, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 IOMUX_PAD(0x394, 0x68, 0, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT2__GPIO4_23 IOMUX_PAD(0x394, 0x68, 1, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT2__CSPI_MISO IOMUX_PAD(0x394, 0x68, 2, 0x784, 0, 0) +#define _MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2 IOMUX_PAD(0x394, 0x68, 3, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT2__SDMA_DEBUG_MODE IOMUX_PAD(0x394, 0x68, 5, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT2__EMI_EMI_DEBUG_7 IOMUX_PAD(0x394, 0x68, 6, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT2__USBPHY2_RXACTIVE IOMUX_PAD(0x394, 0x68, 7, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 IOMUX_PAD(0x398, 0x6C, 0, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT3__GPIO4_24 IOMUX_PAD(0x398, 0x6C, 1, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT3__CSPI_SS0 IOMUX_PAD(0x398, 0x6C, 2, 0x78C, 0, 0) +#define _MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3 IOMUX_PAD(0x398, 0x6C, 3, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR IOMUX_PAD(0x398, 0x6C, 5, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT3__EMI_EMI_DEBUG_8 IOMUX_PAD(0x398, 0x6C, 6, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT3__USBPHY2_RXERROR IOMUX_PAD(0x398, 0x6C, 7, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 IOMUX_PAD(0x39C, 0x70, 0, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT4__GPIO4_25 IOMUX_PAD(0x39C, 0x70, 1, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT4__CSPI_SS1 IOMUX_PAD(0x39C, 0x70, 2, 0x790, 0, 0) +#define _MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4 IOMUX_PAD(0x39C, 0x70, 3, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB IOMUX_PAD(0x39C, 0x70, 5, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT4__EMI_EMI_DEBUG_9 IOMUX_PAD(0x39C, 0x70, 6, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT4__USBPHY2_SIECLOCK IOMUX_PAD(0x39C, 0x70, 7, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 IOMUX_PAD(0x3A0, 0x74, 0, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT5__GPIO4_26 IOMUX_PAD(0x3A0, 0x74, 1, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT5__CSPI_SS2 IOMUX_PAD(0x3A0, 0x74, 2, 0x794, 0, 0) +#define _MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5 IOMUX_PAD(0x3A0, 0x74, 3, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS IOMUX_PAD(0x3A0, 0x74, 5, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT5__EMI_EMI_DEBUG_10 IOMUX_PAD(0x3A0, 0x74, 6, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT5__USBPHY2_LINESTATE_0 IOMUX_PAD(0x3A0, 0x74, 7, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 IOMUX_PAD(0x3A4, 0x78, 0, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT6__GPIO4_27 IOMUX_PAD(0x3A4, 0x78, 1, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT6__CSPI_SS3 IOMUX_PAD(0x3A4, 0x78, 2, 0x798, 0, 0) +#define _MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6 IOMUX_PAD(0x3A4, 0x78, 3, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE IOMUX_PAD(0x3A4, 0x78, 5, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT6__EMI_EMI_DEBUG_11 IOMUX_PAD(0x3A4, 0x78, 6, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT6__USBPHY2_LINESTATE_1 IOMUX_PAD(0x3A4, 0x78, 7, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 IOMUX_PAD(0x3A8, 0x7C, 0, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT7__GPIO4_28 IOMUX_PAD(0x3A8, 0x7C, 1, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT7__CSPI_RDY IOMUX_PAD(0x3A8, 0x7C, 2, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7 IOMUX_PAD(0x3A8, 0x7C, 3, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 IOMUX_PAD(0x3A8, 0x7C, 5, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT7__EMI_EMI_DEBUG_12 IOMUX_PAD(0x3A8, 0x7C, 6, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT7__USBPHY2_VBUSVALID IOMUX_PAD(0x3A8, 0x7C, 7, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 IOMUX_PAD(0x3AC, 0x80, 0, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT8__GPIO4_29 IOMUX_PAD(0x3AC, 0x80, 1, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT8__PWM1_PWMO IOMUX_PAD(0x3AC, 0x80, 2, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT8__WDOG1_WDOG_B IOMUX_PAD(0x3AC, 0x80, 3, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 IOMUX_PAD(0x3AC, 0x80, 5, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT8__EMI_EMI_DEBUG_13 IOMUX_PAD(0x3AC, 0x80, 6, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT8__USBPHY2_AVALID IOMUX_PAD(0x3AC, 0x80, 7, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 IOMUX_PAD(0x3B0, 0x84, 0, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT9__GPIO4_30 IOMUX_PAD(0x3B0, 0x84, 1, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT9__PWM2_PWMO IOMUX_PAD(0x3B0, 0x84, 2, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT9__WDOG2_WDOG_B IOMUX_PAD(0x3B0, 0x84, 3, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 IOMUX_PAD(0x3B0, 0x84, 5, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT9__EMI_EMI_DEBUG_14 IOMUX_PAD(0x3B0, 0x84, 6, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT9__USBPHY2_VSTATUS_0 IOMUX_PAD(0x3B0, 0x84, 7, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 IOMUX_PAD(0x3B4, 0x88, 0, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT10__GPIO4_31 IOMUX_PAD(0x3B4, 0x88, 1, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP IOMUX_PAD(0x3B4, 0x88, 2, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 IOMUX_PAD(0x3B4, 0x88, 5, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT10__EMI_EMI_DEBUG_15 IOMUX_PAD(0x3B4, 0x88, 6, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT10__USBPHY2_VSTATUS_1 IOMUX_PAD(0x3B4, 0x88, 7, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 IOMUX_PAD(0x3B8, 0x8C, 0, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT11__GPIO5_5 IOMUX_PAD(0x3B8, 0x8C, 1, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT IOMUX_PAD(0x3B8, 0x8C, 2, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 IOMUX_PAD(0x3B8, 0x8C, 5, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT11__EMI_EMI_DEBUG_16 IOMUX_PAD(0x3B8, 0x8C, 6, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT11__USBPHY2_VSTATUS_2 IOMUX_PAD(0x3B8, 0x8C, 7, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 IOMUX_PAD(0x3BC, 0x90, 0, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT12__GPIO5_6 IOMUX_PAD(0x3BC, 0x90, 1, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK IOMUX_PAD(0x3BC, 0x90, 2, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 IOMUX_PAD(0x3BC, 0x90, 5, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT12__EMI_EMI_DEBUG_17 IOMUX_PAD(0x3BC, 0x90, 6, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT12__USBPHY2_VSTATUS_3 IOMUX_PAD(0x3BC, 0x90, 7, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 IOMUX_PAD(0x3C0, 0x94, 0, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT13__GPIO5_7 IOMUX_PAD(0x3C0, 0x94, 1, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS IOMUX_PAD(0x3C0, 0x94, 3, 0x754, 0, 0) +#define _MX53_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 IOMUX_PAD(0x3C0, 0x94, 5, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT13__EMI_EMI_DEBUG_18 IOMUX_PAD(0x3C0, 0x94, 6, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT13__USBPHY2_VSTATUS_4 IOMUX_PAD(0x3C0, 0x94, 7, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 IOMUX_PAD(0x3C4, 0x98, 0, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT14__GPIO5_8 IOMUX_PAD(0x3C4, 0x98, 1, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC IOMUX_PAD(0x3C4, 0x98, 3, 0x750, 0, 0) +#define _MX53_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 IOMUX_PAD(0x3C4, 0x98, 5, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT14__EMI_EMI_DEBUG_19 IOMUX_PAD(0x3C4, 0x98, 6, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT14__USBPHY2_VSTATUS_5 IOMUX_PAD(0x3C4, 0x98, 7, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 IOMUX_PAD(0x3C8, 0x9C, 0, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT15__GPIO5_9 IOMUX_PAD(0x3C8, 0x9C, 1, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT15__ECSPI1_SS1 IOMUX_PAD(0x3C8, 0x9C, 2, 0x7AC, 1, 0) +#define _MX53_PAD_DISP0_DAT15__ECSPI2_SS1 IOMUX_PAD(0x3C8, 0x9C, 3, 0x7C8, 0, 0) +#define _MX53_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 IOMUX_PAD(0x3C8, 0x9C, 5, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT15__EMI_EMI_DEBUG_20 IOMUX_PAD(0x3C8, 0x9C, 6, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT15__USBPHY2_VSTATUS_6 IOMUX_PAD(0x3C8, 0x9C, 7, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 IOMUX_PAD(0x3CC, 0xA0, 0, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT16__GPIO5_10 IOMUX_PAD(0x3CC, 0xA0, 1, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT16__ECSPI2_MOSI IOMUX_PAD(0x3CC, 0xA0, 2, 0x7C0, 0, 0) +#define _MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC IOMUX_PAD(0x3CC, 0xA0, 3, 0x758, 1, 0) +#define _MX53_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 IOMUX_PAD(0x3CC, 0xA0, 4, 0x868, 0, 0) +#define _MX53_PAD_DISP0_DAT16__SDMA_DEBUG_EVT_CHN_LINES_3 IOMUX_PAD(0x3CC, 0xA0, 5, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT16__EMI_EMI_DEBUG_21 IOMUX_PAD(0x3CC, 0xA0, 6, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT16__USBPHY2_VSTATUS_7 IOMUX_PAD(0x3CC, 0xA0, 7, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 IOMUX_PAD(0x3D0, 0xA4, 0, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT17__GPIO5_11 IOMUX_PAD(0x3D0, 0xA4, 1, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT17__ECSPI2_MISO IOMUX_PAD(0x3D0, 0xA4, 2, 0x7BC, 0, 0) +#define _MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD IOMUX_PAD(0x3D0, 0xA4, 3, 0x74C, 1, 0) +#define _MX53_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 IOMUX_PAD(0x3D0, 0xA4, 4, 0x86C, 0, 0) +#define _MX53_PAD_DISP0_DAT17__SDMA_DEBUG_EVT_CHN_LINES_4 IOMUX_PAD(0x3D0, 0xA4, 5, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT17__EMI_EMI_DEBUG_22 IOMUX_PAD(0x3D0, 0xA4, 6, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 IOMUX_PAD(0x3D4, 0xA8, 0, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT18__GPIO5_12 IOMUX_PAD(0x3D4, 0xA8, 1, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT18__ECSPI2_SS0 IOMUX_PAD(0x3D4, 0xA8, 2, 0x7C4, 0, 0) +#define _MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS IOMUX_PAD(0x3D4, 0xA8, 3, 0x75C, 1, 0) +#define _MX53_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS IOMUX_PAD(0x3D4, 0xA8, 4, 0x73C, 0, 0) +#define _MX53_PAD_DISP0_DAT18__SDMA_DEBUG_EVT_CHN_LINES_5 IOMUX_PAD(0x3D4, 0xA8, 5, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT18__EMI_EMI_DEBUG_23 IOMUX_PAD(0x3D4, 0xA8, 6, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT18__EMI_WEIM_CS_2 IOMUX_PAD(0x3D4, 0xA8, 7, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 IOMUX_PAD(0x3D8, 0xAC, 0, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT19__GPIO5_13 IOMUX_PAD(0x3D8, 0xAC, 1, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT19__ECSPI2_SCLK IOMUX_PAD(0x3D8, 0xAC, 2, 0x7B8, 0, 0) +#define _MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD IOMUX_PAD(0x3D8, 0xAC, 3, 0x748, 1, 0) +#define _MX53_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC IOMUX_PAD(0x3D8, 0xAC, 4, 0x738, 0, 0) +#define _MX53_PAD_DISP0_DAT19__SDMA_DEBUG_EVT_CHN_LINES_6 IOMUX_PAD(0x3D8, 0xAC, 5, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT19__EMI_EMI_DEBUG_24 IOMUX_PAD(0x3D8, 0xAC, 6, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT19__EMI_WEIM_CS_3 IOMUX_PAD(0x3D8, 0xAC, 7, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 IOMUX_PAD(0x3DC, 0xB0, 0, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT20__GPIO5_14 IOMUX_PAD(0x3DC, 0xB0, 1, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT20__ECSPI1_SCLK IOMUX_PAD(0x3DC, 0xB0, 2, 0x79C, 1, 0) +#define _MX53_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC IOMUX_PAD(0x3DC, 0xB0, 3, 0x740, 0, 0) +#define _MX53_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 IOMUX_PAD(0x3DC, 0xB0, 5, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT20__EMI_EMI_DEBUG_25 IOMUX_PAD(0x3DC, 0xB0, 6, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT20__SATA_PHY_TDI IOMUX_PAD(0x3DC, 0xB0, 7, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 IOMUX_PAD(0x3E0, 0xB4, 0, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT21__GPIO5_15 IOMUX_PAD(0x3E0, 0xB4, 1, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT21__ECSPI1_MOSI IOMUX_PAD(0x3E0, 0xB4, 2, 0x7A4, 1, 0) +#define _MX53_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD IOMUX_PAD(0x3E0, 0xB4, 3, 0x734, 0, 0) +#define _MX53_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 IOMUX_PAD(0x3E0, 0xB4, 5, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT21__EMI_EMI_DEBUG_26 IOMUX_PAD(0x3E0, 0xB4, 6, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT21__SATA_PHY_TDO IOMUX_PAD(0x3E0, 0xB4, 7, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 IOMUX_PAD(0x3E4, 0xB8, 0, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT22__GPIO5_16 IOMUX_PAD(0x3E4, 0xB8, 1, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT22__ECSPI1_MISO IOMUX_PAD(0x3E4, 0xB8, 2, 0x7A0, 1, 0) +#define _MX53_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS IOMUX_PAD(0x3E4, 0xB8, 3, 0x744, 0, 0) +#define _MX53_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 IOMUX_PAD(0x3E4, 0xB8, 5, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT22__EMI_EMI_DEBUG_27 IOMUX_PAD(0x3E4, 0xB8, 6, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT22__SATA_PHY_TCK IOMUX_PAD(0x3E4, 0xB8, 7, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 IOMUX_PAD(0x3E8, 0xBC, 0, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT23__GPIO5_17 IOMUX_PAD(0x3E8, 0xBC, 1, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT23__ECSPI1_SS0 IOMUX_PAD(0x3E8, 0xBC, 2, 0x7A8, 1, 0) +#define _MX53_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD IOMUX_PAD(0x3E8, 0xBC, 3, 0x730, 0, 0) +#define _MX53_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 IOMUX_PAD(0x3E8, 0xBC, 5, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT23__EMI_EMI_DEBUG_28 IOMUX_PAD(0x3E8, 0xBC, 6, 0x0, 0, 0) +#define _MX53_PAD_DISP0_DAT23__SATA_PHY_TMS IOMUX_PAD(0x3E8, 0xBC, 7, 0x0, 0, 0) +#define _MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK IOMUX_PAD(0x3EC, 0xC0, 0, 0x0, 0, 0) +#define _MX53_PAD_CSI0_PIXCLK__GPIO5_18 IOMUX_PAD(0x3EC, 0xC0, 1, 0x0, 0, 0) +#define _MX53_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 IOMUX_PAD(0x3EC, 0xC0, 5, 0x0, 0, 0) +#define _MX53_PAD_CSI0_PIXCLK__EMI_EMI_DEBUG_29 IOMUX_PAD(0x3EC, 0xC0, 6, 0x0, 0, 0) +#define _MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC IOMUX_PAD(0x3F0, 0xC4, 0, 0x0, 0, 0) +#define _MX53_PAD_CSI0_MCLK__GPIO5_19 IOMUX_PAD(0x3F0, 0xC4, 1, 0x0, 0, 0) +#define _MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK IOMUX_PAD(0x3F0, 0xC4, 2, 0x0, 0, 0) +#define _MX53_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 IOMUX_PAD(0x3F0, 0xC4, 5, 0x0, 0, 0) +#define _MX53_PAD_CSI0_MCLK__EMI_EMI_DEBUG_30 IOMUX_PAD(0x3F0, 0xC4, 6, 0x0, 0, 0) +#define _MX53_PAD_CSI0_MCLK__TPIU_TRCTL IOMUX_PAD(0x3F0, 0xC4, 7, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN IOMUX_PAD(0x3F4, 0xC8, 0, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DATA_EN__GPIO5_20 IOMUX_PAD(0x3F4, 0xC8, 1, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 IOMUX_PAD(0x3F4, 0xC8, 5, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DATA_EN__EMI_EMI_DEBUG_31 IOMUX_PAD(0x3F4, 0xC8, 6, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DATA_EN__TPIU_TRCLK IOMUX_PAD(0x3F4, 0xC8, 7, 0x0, 0, 0) +#define _MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC IOMUX_PAD(0x3F8, 0xCC, 0, 0x0, 0, 0) +#define _MX53_PAD_CSI0_VSYNC__GPIO5_21 IOMUX_PAD(0x3F8, 0xCC, 1, 0x0, 0, 0) +#define _MX53_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 IOMUX_PAD(0x3F8, 0xCC, 5, 0x0, 0, 0) +#define _MX53_PAD_CSI0_VSYNC__EMI_EMI_DEBUG_32 IOMUX_PAD(0x3F8, 0xCC, 6, 0x0, 0, 0) +#define _MX53_PAD_CSI0_VSYNC__TPIU_TRACE_0 IOMUX_PAD(0x3F8, 0xCC, 7, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 IOMUX_PAD(0x3FC, 0xD0, 0, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT4__GPIO5_22 IOMUX_PAD(0x3FC, 0xD0, 1, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT4__KPP_COL_5 IOMUX_PAD(0x3FC, 0xD0, 2, 0x840, 1, 0) +#define _MX53_PAD_CSI0_DAT4__ECSPI1_SCLK IOMUX_PAD(0x3FC, 0xD0, 3, 0x79C, 2, 0) +#define _MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP IOMUX_PAD(0x3FC, 0xD0, 4, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC IOMUX_PAD(0x3FC, 0xD0, 5, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT4__EMI_EMI_DEBUG_33 IOMUX_PAD(0x3FC, 0xD0, 6, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT4__TPIU_TRACE_1 IOMUX_PAD(0x3FC, 0xD0, 7, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 IOMUX_PAD(0x400, 0xD4, 0, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT5__GPIO5_23 IOMUX_PAD(0x400, 0xD4, 1, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT5__KPP_ROW_5 IOMUX_PAD(0x400, 0xD4, 2, 0x84C, 0, 0) +#define _MX53_PAD_CSI0_DAT5__ECSPI1_MOSI IOMUX_PAD(0x400, 0xD4, 3, 0x7A4, 2, 0) +#define _MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT IOMUX_PAD(0x400, 0xD4, 4, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD IOMUX_PAD(0x400, 0xD4, 5, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT5__EMI_EMI_DEBUG_34 IOMUX_PAD(0x400, 0xD4, 6, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT5__TPIU_TRACE_2 IOMUX_PAD(0x400, 0xD4, 7, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 IOMUX_PAD(0x404, 0xD8, 0, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT6__GPIO5_24 IOMUX_PAD(0x404, 0xD8, 1, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT6__KPP_COL_6 IOMUX_PAD(0x404, 0xD8, 2, 0x844, 0, 0) +#define _MX53_PAD_CSI0_DAT6__ECSPI1_MISO IOMUX_PAD(0x404, 0xD8, 3, 0x7A0, 2, 0) +#define _MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK IOMUX_PAD(0x404, 0xD8, 4, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS IOMUX_PAD(0x404, 0xD8, 5, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT6__EMI_EMI_DEBUG_35 IOMUX_PAD(0x404, 0xD8, 6, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT6__TPIU_TRACE_3 IOMUX_PAD(0x404, 0xD8, 7, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 IOMUX_PAD(0x408, 0xDC, 0, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT7__GPIO5_25 IOMUX_PAD(0x408, 0xDC, 1, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT7__KPP_ROW_6 IOMUX_PAD(0x408, 0xDC, 2, 0x850, 0, 0) +#define _MX53_PAD_CSI0_DAT7__ECSPI1_SS0 IOMUX_PAD(0x408, 0xDC, 3, 0x7A8, 2, 0) +#define _MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR IOMUX_PAD(0x408, 0xDC, 4, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD IOMUX_PAD(0x408, 0xDC, 5, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT7__EMI_EMI_DEBUG_36 IOMUX_PAD(0x408, 0xDC, 6, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT7__TPIU_TRACE_4 IOMUX_PAD(0x408, 0xDC, 7, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 IOMUX_PAD(0x40C, 0xE0, 0, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT8__GPIO5_26 IOMUX_PAD(0x40C, 0xE0, 1, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT8__KPP_COL_7 IOMUX_PAD(0x40C, 0xE0, 2, 0x848, 0, 0) +#define _MX53_PAD_CSI0_DAT8__ECSPI2_SCLK IOMUX_PAD(0x40C, 0xE0, 3, 0x7B8, 1, 0) +#define _MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC IOMUX_PAD(0x40C, 0xE0, 4, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT8__I2C1_SDA IOMUX_PAD(0x40C, 0xE0, 5 | IOMUX_CONFIG_SION, 0x818, 0, 0) +#define _MX53_PAD_CSI0_DAT8__EMI_EMI_DEBUG_37 IOMUX_PAD(0x40C, 0xE0, 6, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT8__TPIU_TRACE_5 IOMUX_PAD(0x40C, 0xE0, 7, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 IOMUX_PAD(0x410, 0xE4, 0, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT9__GPIO5_27 IOMUX_PAD(0x410, 0xE4, 1, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT9__KPP_ROW_7 IOMUX_PAD(0x410, 0xE4, 2, 0x854, 0, 0) +#define _MX53_PAD_CSI0_DAT9__ECSPI2_MOSI IOMUX_PAD(0x410, 0xE4, 3, 0x7C0, 1, 0) +#define _MX53_PAD_CSI0_DAT9__USBOH3_USBH3_PWR IOMUX_PAD(0x410, 0xE4, 4, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT9__I2C1_SCL IOMUX_PAD(0x410, 0xE4, 5 | IOMUX_CONFIG_SION, 0x814, 0, 0) +#define _MX53_PAD_CSI0_DAT9__EMI_EMI_DEBUG_38 IOMUX_PAD(0x410, 0xE4, 6, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT9__TPIU_TRACE_6 IOMUX_PAD(0x410, 0xE4, 7, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 IOMUX_PAD(0x414, 0xE8, 0, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT10__GPIO5_28 IOMUX_PAD(0x414, 0xE8, 1, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT10__UART1_TXD_MUX IOMUX_PAD(0x414, 0xE8, 2, 0x878, 0, 0) +#define _MX53_PAD_CSI0_DAT10__ECSPI2_MISO IOMUX_PAD(0x414, 0xE8, 3, 0x7BC, 1, 0) +#define _MX53_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC IOMUX_PAD(0x414, 0xE8, 4, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 IOMUX_PAD(0x414, 0xE8, 5, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT10__EMI_EMI_DEBUG_39 IOMUX_PAD(0x414, 0xE8, 6, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT10__TPIU_TRACE_7 IOMUX_PAD(0x414, 0xE8, 7, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 IOMUX_PAD(0x418, 0xEC, 0, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT11__GPIO5_29 IOMUX_PAD(0x418, 0xEC, 1, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT11__UART1_RXD_MUX IOMUX_PAD(0x418, 0xEC, 2, 0x878, 1, 0) +#define _MX53_PAD_CSI0_DAT11__ECSPI2_SS0 IOMUX_PAD(0x418, 0xEC, 3, 0x7C4, 1, 0) +#define _MX53_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS IOMUX_PAD(0x418, 0xEC, 4, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 IOMUX_PAD(0x418, 0xEC, 5, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT11__EMI_EMI_DEBUG_40 IOMUX_PAD(0x418, 0xEC, 6, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT11__TPIU_TRACE_8 IOMUX_PAD(0x418, 0xEC, 7, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 IOMUX_PAD(0x41C, 0xF0, 0, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT12__GPIO5_30 IOMUX_PAD(0x41C, 0xF0, 1, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT12__UART4_TXD_MUX IOMUX_PAD(0x41C, 0xF0, 2, 0x890, 2, 0) +#define _MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0 IOMUX_PAD(0x41C, 0xF0, 4, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 IOMUX_PAD(0x41C, 0xF0, 5, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT12__EMI_EMI_DEBUG_41 IOMUX_PAD(0x41C, 0xF0, 6, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT12__TPIU_TRACE_9 IOMUX_PAD(0x41C, 0xF0, 7, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 IOMUX_PAD(0x420, 0xF4, 0, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT13__GPIO5_31 IOMUX_PAD(0x420, 0xF4, 1, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT13__UART4_RXD_MUX IOMUX_PAD(0x420, 0xF4, 2, 0x890, 3, 0) +#define _MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1 IOMUX_PAD(0x420, 0xF4, 4, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 IOMUX_PAD(0x420, 0xF4, 5, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT13__EMI_EMI_DEBUG_42 IOMUX_PAD(0x420, 0xF4, 6, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT13__TPIU_TRACE_10 IOMUX_PAD(0x420, 0xF4, 7, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 IOMUX_PAD(0x424, 0xF8, 0, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT14__GPIO6_0 IOMUX_PAD(0x424, 0xF8, 1, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT14__UART5_TXD_MUX IOMUX_PAD(0x424, 0xF8, 2, 0x898, 2, 0) +#define _MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2 IOMUX_PAD(0x424, 0xF8, 4, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 IOMUX_PAD(0x424, 0xF8, 5, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT14__EMI_EMI_DEBUG_43 IOMUX_PAD(0x424, 0xF8, 6, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT14__TPIU_TRACE_11 IOMUX_PAD(0x424, 0xF8, 7, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 IOMUX_PAD(0x428, 0xFC, 0, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT15__GPIO6_1 IOMUX_PAD(0x428, 0xFC, 1, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT15__UART5_RXD_MUX IOMUX_PAD(0x428, 0xFC, 2, 0x898, 3, 0) +#define _MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3 IOMUX_PAD(0x428, 0xFC, 4, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 IOMUX_PAD(0x428, 0xFC, 5, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT15__EMI_EMI_DEBUG_44 IOMUX_PAD(0x428, 0xFC, 6, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT15__TPIU_TRACE_12 IOMUX_PAD(0x428, 0xFC, 7, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 IOMUX_PAD(0x42C, 0x100, 0, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT16__GPIO6_2 IOMUX_PAD(0x42C, 0x100, 1, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT16__UART4_RTS IOMUX_PAD(0x42C, 0x100, 2, 0x88C, 0, 0) +#define _MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4 IOMUX_PAD(0x42C, 0x100, 4, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 IOMUX_PAD(0x42C, 0x100, 5, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT16__EMI_EMI_DEBUG_45 IOMUX_PAD(0x42C, 0x100, 6, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT16__TPIU_TRACE_13 IOMUX_PAD(0x42C, 0x100, 7, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 IOMUX_PAD(0x430, 0x104, 0, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT17__GPIO6_3 IOMUX_PAD(0x430, 0x104, 1, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT17__UART4_CTS IOMUX_PAD(0x430, 0x104, 2, 0x88C, 1, 0) +#define _MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5 IOMUX_PAD(0x430, 0x104, 4, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 IOMUX_PAD(0x430, 0x104, 5, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT17__EMI_EMI_DEBUG_46 IOMUX_PAD(0x430, 0x104, 6, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT17__TPIU_TRACE_14 IOMUX_PAD(0x430, 0x104, 7, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 IOMUX_PAD(0x434, 0x108, 0, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT18__GPIO6_4 IOMUX_PAD(0x434, 0x108, 1, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT18__UART5_RTS IOMUX_PAD(0x434, 0x108, 2, 0x894, 2, 0) +#define _MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6 IOMUX_PAD(0x434, 0x108, 4, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 IOMUX_PAD(0x434, 0x108, 5, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT18__EMI_EMI_DEBUG_47 IOMUX_PAD(0x434, 0x108, 6, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT18__TPIU_TRACE_15 IOMUX_PAD(0x434, 0x108, 7, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 IOMUX_PAD(0x438, 0x10C, 0, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT19__GPIO6_5 IOMUX_PAD(0x438, 0x10C, 1, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT19__UART5_CTS IOMUX_PAD(0x438, 0x10C, 2, 0x894, 3, 0) +#define _MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7 IOMUX_PAD(0x438, 0x10C, 4, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 IOMUX_PAD(0x438, 0x10C, 5, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT19__EMI_EMI_DEBUG_48 IOMUX_PAD(0x438, 0x10C, 6, 0x0, 0, 0) +#define _MX53_PAD_CSI0_DAT19__USBPHY2_BISTOK IOMUX_PAD(0x438, 0x10C, 7, 0x0, 0, 0) +#define _MX53_PAD_EIM_A25__EMI_WEIM_A_25 IOMUX_PAD(0x458, 0x110, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_A25__GPIO5_2 IOMUX_PAD(0x458, 0x110, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_A25__ECSPI2_RDY IOMUX_PAD(0x458, 0x110, 2, 0x0, 0, 0) +#define _MX53_PAD_EIM_A25__IPU_DI1_PIN12 IOMUX_PAD(0x458, 0x110, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_A25__CSPI_SS1 IOMUX_PAD(0x458, 0x110, 4, 0x790, 1, 0) +#define _MX53_PAD_EIM_A25__IPU_DI0_D1_CS IOMUX_PAD(0x458, 0x110, 6, 0x0, 0, 0) +#define _MX53_PAD_EIM_A25__USBPHY1_BISTOK IOMUX_PAD(0x458, 0x110, 7, 0x0, 0, 0) +#define _MX53_PAD_EIM_EB2__EMI_WEIM_EB_2 IOMUX_PAD(0x45C, 0x114, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_EB2__GPIO2_30 IOMUX_PAD(0x45C, 0x114, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_EB2__CCM_DI1_EXT_CLK IOMUX_PAD(0x45C, 0x114, 2, 0x76C, 0, 0) +#define _MX53_PAD_EIM_EB2__IPU_SER_DISP1_CS IOMUX_PAD(0x45C, 0x114, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_EB2__ECSPI1_SS0 IOMUX_PAD(0x45C, 0x114, 4, 0x7A8, 3, 0) +#define _MX53_PAD_EIM_EB2__I2C2_SCL IOMUX_PAD(0x45C, 0x114, 5 | IOMUX_CONFIG_SION, 0x81C, 1, 0) +#define _MX53_PAD_EIM_D16__EMI_WEIM_D_16 IOMUX_PAD(0x460, 0x118, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_D16__GPIO3_16 IOMUX_PAD(0x460, 0x118, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_D16__IPU_DI0_PIN5 IOMUX_PAD(0x460, 0x118, 2, 0x0, 0, 0) +#define _MX53_PAD_EIM_D16__IPU_DISPB1_SER_CLK IOMUX_PAD(0x460, 0x118, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_D16__ECSPI1_SCLK IOMUX_PAD(0x460, 0x118, 4, 0x79C, 3, 0) +#define _MX53_PAD_EIM_D16__I2C2_SDA IOMUX_PAD(0x460, 0x118, 5, 0x820, 1, 0) +#define _MX53_PAD_EIM_D17__EMI_WEIM_D_17 IOMUX_PAD(0x464, 0x11C, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_D17__GPIO3_17 IOMUX_PAD(0x464, 0x11C, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_D17__IPU_DI0_PIN6 IOMUX_PAD(0x464, 0x11C, 2, 0x0, 0, 0) +#define _MX53_PAD_EIM_D17__IPU_DISPB1_SER_DIN IOMUX_PAD(0x464, 0x11C, 3, 0x830, 0, 0) +#define _MX53_PAD_EIM_D17__ECSPI1_MISO IOMUX_PAD(0x464, 0x11C, 4, 0x7A0, 3, 0) +#define _MX53_PAD_EIM_D17__I2C3_SCL IOMUX_PAD(0x464, 0x11C, 5, 0x824, 0, 0) +#define _MX53_PAD_EIM_D18__EMI_WEIM_D_18 IOMUX_PAD(0x468, 0x120, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_D18__GPIO3_18 IOMUX_PAD(0x468, 0x120, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_D18__IPU_DI0_PIN7 IOMUX_PAD(0x468, 0x120, 2, 0x0, 0, 0) +#define _MX53_PAD_EIM_D18__IPU_DISPB1_SER_DIO IOMUX_PAD(0x468, 0x120, 3, 0x830, 1, 0) +#define _MX53_PAD_EIM_D18__ECSPI1_MOSI IOMUX_PAD(0x468, 0x120, 4, 0x7A4, 3, 0) +#define _MX53_PAD_EIM_D18__I2C3_SDA IOMUX_PAD(0x468, 0x120, 5, 0x828, 0, 0) +#define _MX53_PAD_EIM_D18__IPU_DI1_D0_CS IOMUX_PAD(0x468, 0x120, 6, 0x0, 0, 0) +#define _MX53_PAD_EIM_D19__EMI_WEIM_D_19 IOMUX_PAD(0x46C, 0x124, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_D19__GPIO3_19 IOMUX_PAD(0x46C, 0x124, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_D19__IPU_DI0_PIN8 IOMUX_PAD(0x46C, 0x124, 2, 0x0, 0, 0) +#define _MX53_PAD_EIM_D19__IPU_DISPB1_SER_RS IOMUX_PAD(0x46C, 0x124, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_D19__ECSPI1_SS1 IOMUX_PAD(0x46C, 0x124, 4, 0x7AC, 2, 0) +#define _MX53_PAD_EIM_D19__EPIT1_EPITO IOMUX_PAD(0x46C, 0x124, 5, 0x0, 0, 0) +#define _MX53_PAD_EIM_D19__UART1_CTS IOMUX_PAD(0x46C, 0x124, 6, 0x874, 0, 0) +#define _MX53_PAD_EIM_D19__USBOH3_USBH2_OC IOMUX_PAD(0x46C, 0x124, 7, 0x8A4, 0, 0) +#define _MX53_PAD_EIM_D20__EMI_WEIM_D_20 IOMUX_PAD(0x470, 0x128, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_D20__GPIO3_20 IOMUX_PAD(0x470, 0x128, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_D20__IPU_DI0_PIN16 IOMUX_PAD(0x470, 0x128, 2, 0x0, 0, 0) +#define _MX53_PAD_EIM_D20__IPU_SER_DISP0_CS IOMUX_PAD(0x470, 0x128, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_D20__CSPI_SS0 IOMUX_PAD(0x470, 0x128, 4, 0x78C, 1, 0) +#define _MX53_PAD_EIM_D20__EPIT2_EPITO IOMUX_PAD(0x470, 0x128, 5, 0x0, 0, 0) +#define _MX53_PAD_EIM_D20__UART1_RTS IOMUX_PAD(0x470, 0x128, 6, 0x874, 1, 0) +#define _MX53_PAD_EIM_D20__USBOH3_USBH2_PWR IOMUX_PAD(0x470, 0x128, 7, 0x0, 0, 0) +#define _MX53_PAD_EIM_D21__EMI_WEIM_D_21 IOMUX_PAD(0x474, 0x12C, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_D21__GPIO3_21 IOMUX_PAD(0x474, 0x12C, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_D21__IPU_DI0_PIN17 IOMUX_PAD(0x474, 0x12C, 2, 0x0, 0, 0) +#define _MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK IOMUX_PAD(0x474, 0x12C, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_D21__CSPI_SCLK IOMUX_PAD(0x474, 0x12C, 4, 0x780, 1, 0) +#define _MX53_PAD_EIM_D21__I2C1_SCL IOMUX_PAD(0x474, 0x12C, 5, 0x814, 1, 0) +#define _MX53_PAD_EIM_D21__USBOH3_USBOTG_OC IOMUX_PAD(0x474, 0x12C, 6, 0x89C, 1, 0) +#define _MX53_PAD_EIM_D22__EMI_WEIM_D_22 IOMUX_PAD(0x478, 0x130, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_D22__GPIO3_22 IOMUX_PAD(0x478, 0x130, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_D22__IPU_DI0_PIN1 IOMUX_PAD(0x478, 0x130, 2, 0x0, 0, 0) +#define _MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN IOMUX_PAD(0x478, 0x130, 3, 0x82C, 0, 0) +#define _MX53_PAD_EIM_D22__CSPI_MISO IOMUX_PAD(0x478, 0x130, 4, 0x784, 1, 0) +#define _MX53_PAD_EIM_D22__USBOH3_USBOTG_PWR IOMUX_PAD(0x478, 0x130, 6, 0x0, 0, 0) +#define _MX53_PAD_EIM_D23__EMI_WEIM_D_23 IOMUX_PAD(0x47C, 0x134, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_D23__GPIO3_23 IOMUX_PAD(0x47C, 0x134, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_D23__UART3_CTS IOMUX_PAD(0x47C, 0x134, 2, 0, 0, 0) +#define _MX53_PAD_EIM_D23__UART1_DCD IOMUX_PAD(0x47C, 0x134, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_D23__IPU_DI0_D0_CS IOMUX_PAD(0x47C, 0x134, 4, 0x0, 0, 0) +#define _MX53_PAD_EIM_D23__IPU_DI1_PIN2 IOMUX_PAD(0x47C, 0x134, 5, 0x0, 0, 0) +#define _MX53_PAD_EIM_D23__IPU_CSI1_DATA_EN IOMUX_PAD(0x47C, 0x134, 6, 0x834, 0, 0) +#define _MX53_PAD_EIM_D23__IPU_DI1_PIN14 IOMUX_PAD(0x47C, 0x134, 7, 0x0, 0, 0) +#define _MX53_PAD_EIM_EB3__EMI_WEIM_EB_3 IOMUX_PAD(0x480, 0x138, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_EB3__GPIO2_31 IOMUX_PAD(0x480, 0x138, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_EB3__UART3_RTS IOMUX_PAD(0x480, 0x138, 2, 0x884, 1, 0) +#define _MX53_PAD_EIM_EB3__UART1_RI IOMUX_PAD(0x480, 0x138, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_EB3__IPU_DI1_PIN3 IOMUX_PAD(0x480, 0x138, 5, 0x0, 0, 0) +#define _MX53_PAD_EIM_EB3__IPU_CSI1_HSYNC IOMUX_PAD(0x480, 0x138, 6, 0x838, 0, 0) +#define _MX53_PAD_EIM_EB3__IPU_DI1_PIN16 IOMUX_PAD(0x480, 0x138, 7, 0x0, 0, 0) +#define _MX53_PAD_EIM_D24__EMI_WEIM_D_24 IOMUX_PAD(0x484, 0x13C, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_D24__GPIO3_24 IOMUX_PAD(0x484, 0x13C, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_D24__UART3_TXD_MUX IOMUX_PAD(0x484, 0x13C, 2, 0x888, 0, 0) +#define _MX53_PAD_EIM_D24__ECSPI1_SS2 IOMUX_PAD(0x484, 0x13C, 3, 0x7B0, 1, 0) +#define _MX53_PAD_EIM_D24__CSPI_SS2 IOMUX_PAD(0x484, 0x13C, 4, 0x794, 1, 0) +#define _MX53_PAD_EIM_D24__AUDMUX_AUD5_RXFS IOMUX_PAD(0x484, 0x13C, 5, 0x754, 1, 0) +#define _MX53_PAD_EIM_D24__ECSPI2_SS2 IOMUX_PAD(0x484, 0x13C, 6, 0x0, 0, 0) +#define _MX53_PAD_EIM_D24__UART1_DTR IOMUX_PAD(0x484, 0x13C, 7, 0x0, 0, 0) +#define _MX53_PAD_EIM_D25__EMI_WEIM_D_25 IOMUX_PAD(0x488, 0x140, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_D25__GPIO3_25 IOMUX_PAD(0x488, 0x140, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_D25__UART3_RXD_MUX IOMUX_PAD(0x488, 0x140, 2, 0x888, 1, 0) +#define _MX53_PAD_EIM_D25__ECSPI1_SS3 IOMUX_PAD(0x488, 0x140, 3, 0x7B4, 1, 0) +#define _MX53_PAD_EIM_D25__CSPI_SS3 IOMUX_PAD(0x488, 0x140, 4, 0x798, 1, 0) +#define _MX53_PAD_EIM_D25__AUDMUX_AUD5_RXC IOMUX_PAD(0x488, 0x140, 5, 0x750, 1, 0) +#define _MX53_PAD_EIM_D25__ECSPI2_SS3 IOMUX_PAD(0x488, 0x140, 6, 0x0, 0, 0) +#define _MX53_PAD_EIM_D25__UART1_DSR IOMUX_PAD(0x488, 0x140, 7, 0x0, 0, 0) +#define _MX53_PAD_EIM_D26__EMI_WEIM_D_26 IOMUX_PAD(0x48C, 0x144, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_D26__GPIO3_26 IOMUX_PAD(0x48C, 0x144, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_D26__UART2_TXD_MUX IOMUX_PAD(0x48C, 0x144, 2, 0x880, 0, 0) +#define _MX53_PAD_EIM_D26__FIRI_RXD IOMUX_PAD(0x48C, 0x144, 3, 0x80C, 0, 0) +#define _MX53_PAD_EIM_D26__IPU_CSI0_D_1 IOMUX_PAD(0x48C, 0x144, 4, 0x0, 0, 0) +#define _MX53_PAD_EIM_D26__IPU_DI1_PIN11 IOMUX_PAD(0x48C, 0x144, 5, 0x0, 0, 0) +#define _MX53_PAD_EIM_D26__IPU_SISG_2 IOMUX_PAD(0x48C, 0x144, 6, 0x0, 0, 0) +#define _MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 IOMUX_PAD(0x48C, 0x144, 7, 0x0, 0, 0) +#define _MX53_PAD_EIM_D27__EMI_WEIM_D_27 IOMUX_PAD(0x490, 0x148, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_D27__GPIO3_27 IOMUX_PAD(0x490, 0x148, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_D27__UART2_RXD_MUX IOMUX_PAD(0x490, 0x148, 2, 0x880, 1, 0) +#define _MX53_PAD_EIM_D27__FIRI_TXD IOMUX_PAD(0x490, 0x148, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_D27__IPU_CSI0_D_0 IOMUX_PAD(0x490, 0x148, 4, 0x0, 0, 0) +#define _MX53_PAD_EIM_D27__IPU_DI1_PIN13 IOMUX_PAD(0x490, 0x148, 5, 0x0, 0, 0) +#define _MX53_PAD_EIM_D27__IPU_SISG_3 IOMUX_PAD(0x490, 0x148, 6, 0x0, 0, 0) +#define _MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 IOMUX_PAD(0x490, 0x148, 7, 0x0, 0, 0) +#define _MX53_PAD_EIM_D28__EMI_WEIM_D_28 IOMUX_PAD(0x494, 0x14C, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_D28__GPIO3_28 IOMUX_PAD(0x494, 0x14C, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_D28__UART2_CTS IOMUX_PAD(0x494, 0x14C, 2, 0x87C, 0, 0) +#define _MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO IOMUX_PAD(0x494, 0x14C, 3, 0x82C, 1, 0) +#define _MX53_PAD_EIM_D28__CSPI_MOSI IOMUX_PAD(0x494, 0x14C, 4, 0x788, 1, 0) +#define _MX53_PAD_EIM_D28__I2C1_SDA IOMUX_PAD(0x494, 0x14C, 5, 0x818, 1, 0) +#define _MX53_PAD_EIM_D28__IPU_EXT_TRIG IOMUX_PAD(0x494, 0x14C, 6, 0x0, 0, 0) +#define _MX53_PAD_EIM_D28__IPU_DI0_PIN13 IOMUX_PAD(0x494, 0x14C, 7, 0x0, 0, 0) +#define _MX53_PAD_EIM_D29__EMI_WEIM_D_29 IOMUX_PAD(0x498, 0x150, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_D29__GPIO3_29 IOMUX_PAD(0x498, 0x150, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_D29__UART2_RTS IOMUX_PAD(0x498, 0x150, 2, 0x87C, 1, 0) +#define _MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS IOMUX_PAD(0x498, 0x150, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_D29__CSPI_SS0 IOMUX_PAD(0x498, 0x150, 4, 0x78C, 2, 0) +#define _MX53_PAD_EIM_D29__IPU_DI1_PIN15 IOMUX_PAD(0x498, 0x150, 5, 0x0, 0, 0) +#define _MX53_PAD_EIM_D29__IPU_CSI1_VSYNC IOMUX_PAD(0x498, 0x150, 6, 0x83C, 0, 0) +#define _MX53_PAD_EIM_D29__IPU_DI0_PIN14 IOMUX_PAD(0x498, 0x150, 7, 0x0, 0, 0) +#define _MX53_PAD_EIM_D30__EMI_WEIM_D_30 IOMUX_PAD(0x49C, 0x154, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_D30__GPIO3_30 IOMUX_PAD(0x49C, 0x154, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_D30__UART3_CTS IOMUX_PAD(0x49C, 0x154, 2, 0x884, 2, 0) +#define _MX53_PAD_EIM_D30__IPU_CSI0_D_3 IOMUX_PAD(0x49C, 0x154, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_D30__IPU_DI0_PIN11 IOMUX_PAD(0x49C, 0x154, 4, 0x0, 0, 0) +#define _MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 IOMUX_PAD(0x49C, 0x154, 5, 0x0, 0, 0) +#define _MX53_PAD_EIM_D30__USBOH3_USBH1_OC IOMUX_PAD(0x49C, 0x154, 6, 0x8A0, 0, 0) +#define _MX53_PAD_EIM_D30__USBOH3_USBH2_OC IOMUX_PAD(0x49C, 0x154, 7, 0x8A4, 1, 0) +#define _MX53_PAD_EIM_D31__EMI_WEIM_D_31 IOMUX_PAD(0x4A0, 0x158, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_D31__GPIO3_31 IOMUX_PAD(0x4A0, 0x158, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_D31__UART3_RTS IOMUX_PAD(0x4A0, 0x158, 2, 0x884, 3, 0) +#define _MX53_PAD_EIM_D31__IPU_CSI0_D_2 IOMUX_PAD(0x4A0, 0x158, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_D31__IPU_DI0_PIN12 IOMUX_PAD(0x4A0, 0x158, 4, 0x0, 0, 0) +#define _MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 IOMUX_PAD(0x4A0, 0x158, 5, 0x0, 0, 0) +#define _MX53_PAD_EIM_D31__USBOH3_USBH1_PWR IOMUX_PAD(0x4A0, 0x158, 6, 0x0, 0, 0) +#define _MX53_PAD_EIM_D31__USBOH3_USBH2_PWR IOMUX_PAD(0x4A0, 0x158, 7, 0x0, 0, 0) +#define _MX53_PAD_EIM_A24__EMI_WEIM_A_24 IOMUX_PAD(0x4A8, 0x15C, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_A24__GPIO5_4 IOMUX_PAD(0x4A8, 0x15C, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 IOMUX_PAD(0x4A8, 0x15C, 2, 0x0, 0, 0) +#define _MX53_PAD_EIM_A24__IPU_CSI1_D_19 IOMUX_PAD(0x4A8, 0x15C, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_A24__IPU_SISG_2 IOMUX_PAD(0x4A8, 0x15C, 6, 0x0, 0, 0) +#define _MX53_PAD_EIM_A24__USBPHY2_BVALID IOMUX_PAD(0x4A8, 0x15C, 7, 0x0, 0, 0) +#define _MX53_PAD_EIM_A23__EMI_WEIM_A_23 IOMUX_PAD(0x4AC, 0x160, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_A23__GPIO6_6 IOMUX_PAD(0x4AC, 0x160, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 IOMUX_PAD(0x4AC, 0x160, 2, 0x0, 0, 0) +#define _MX53_PAD_EIM_A23__IPU_CSI1_D_18 IOMUX_PAD(0x4AC, 0x160, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_A23__IPU_SISG_3 IOMUX_PAD(0x4AC, 0x160, 6, 0x0, 0, 0) +#define _MX53_PAD_EIM_A23__USBPHY2_ENDSESSION IOMUX_PAD(0x4AC, 0x160, 7, 0x0, 0, 0) +#define _MX53_PAD_EIM_A22__EMI_WEIM_A_22 IOMUX_PAD(0x4B0, 0x164, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_A22__GPIO2_16 IOMUX_PAD(0x4B0, 0x164, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 IOMUX_PAD(0x4B0, 0x164, 2, 0x0, 0, 0) +#define _MX53_PAD_EIM_A22__IPU_CSI1_D_17 IOMUX_PAD(0x4B0, 0x164, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_A22__SRC_BT_CFG1_7 IOMUX_PAD(0x4B0, 0x164, 7, 0x0, 0, 0) +#define _MX53_PAD_EIM_A21__EMI_WEIM_A_21 IOMUX_PAD(0x4B4, 0x168, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_A21__GPIO2_17 IOMUX_PAD(0x4B4, 0x168, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 IOMUX_PAD(0x4B4, 0x168, 2, 0x0, 0, 0) +#define _MX53_PAD_EIM_A21__IPU_CSI1_D_16 IOMUX_PAD(0x4B4, 0x168, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_A21__SRC_BT_CFG1_6 IOMUX_PAD(0x4B4, 0x168, 7, 0x0, 0, 0) +#define _MX53_PAD_EIM_A20__EMI_WEIM_A_20 IOMUX_PAD(0x4B8, 0x16C, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_A20__GPIO2_18 IOMUX_PAD(0x4B8, 0x16C, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 IOMUX_PAD(0x4B8, 0x16C, 2, 0x0, 0, 0) +#define _MX53_PAD_EIM_A20__IPU_CSI1_D_15 IOMUX_PAD(0x4B8, 0x16C, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_A20__SRC_BT_CFG1_5 IOMUX_PAD(0x4B8, 0x16C, 7, 0x0, 0, 0) +#define _MX53_PAD_EIM_A19__EMI_WEIM_A_19 IOMUX_PAD(0x4BC, 0x170, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_A19__GPIO2_19 IOMUX_PAD(0x4BC, 0x170, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 IOMUX_PAD(0x4BC, 0x170, 2, 0x0, 0, 0) +#define _MX53_PAD_EIM_A19__IPU_CSI1_D_14 IOMUX_PAD(0x4BC, 0x170, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_A19__SRC_BT_CFG1_4 IOMUX_PAD(0x4BC, 0x170, 7, 0x0, 0, 0) +#define _MX53_PAD_EIM_A18__EMI_WEIM_A_18 IOMUX_PAD(0x4C0, 0x174, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_A18__GPIO2_20 IOMUX_PAD(0x4C0, 0x174, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 IOMUX_PAD(0x4C0, 0x174, 2, 0x0, 0, 0) +#define _MX53_PAD_EIM_A18__IPU_CSI1_D_13 IOMUX_PAD(0x4C0, 0x174, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_A18__SRC_BT_CFG1_3 IOMUX_PAD(0x4C0, 0x174, 7, 0x0, 0, 0) +#define _MX53_PAD_EIM_A17__EMI_WEIM_A_17 IOMUX_PAD(0x4C4, 0x178, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_A17__GPIO2_21 IOMUX_PAD(0x4C4, 0x178, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 IOMUX_PAD(0x4C4, 0x178, 2, 0x0, 0, 0) +#define _MX53_PAD_EIM_A17__IPU_CSI1_D_12 IOMUX_PAD(0x4C4, 0x178, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_A17__SRC_BT_CFG1_2 IOMUX_PAD(0x4C4, 0x178, 7, 0x0, 0, 0) +#define _MX53_PAD_EIM_A16__EMI_WEIM_A_16 IOMUX_PAD(0x4C8, 0x17C, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_A16__GPIO2_22 IOMUX_PAD(0x4C8, 0x17C, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK IOMUX_PAD(0x4C8, 0x17C, 2, 0x0, 0, 0) +#define _MX53_PAD_EIM_A16__IPU_CSI1_PIXCLK IOMUX_PAD(0x4C8, 0x17C, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_A16__SRC_BT_CFG1_1 IOMUX_PAD(0x4C8, 0x17C, 7, 0x0, 0, 0) +#define _MX53_PAD_EIM_CS0__EMI_WEIM_CS_0 IOMUX_PAD(0x4CC, 0x180, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_CS0__GPIO2_23 IOMUX_PAD(0x4CC, 0x180, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_CS0__ECSPI2_SCLK IOMUX_PAD(0x4CC, 0x180, 2, 0x7B8, 2, 0) +#define _MX53_PAD_EIM_CS0__IPU_DI1_PIN5 IOMUX_PAD(0x4CC, 0x180, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 IOMUX_PAD(0x4D0, 0x184, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_CS1__GPIO2_24 IOMUX_PAD(0x4D0, 0x184, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_CS1__ECSPI2_MOSI IOMUX_PAD(0x4D0, 0x184, 2, 0x7C0, 2, 0) +#define _MX53_PAD_EIM_CS1__IPU_DI1_PIN6 IOMUX_PAD(0x4D0, 0x184, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_OE__EMI_WEIM_OE IOMUX_PAD(0x4D4, 0x188, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_OE__GPIO2_25 IOMUX_PAD(0x4D4, 0x188, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_OE__ECSPI2_MISO IOMUX_PAD(0x4D4, 0x188, 2, 0x7BC, 2, 0) +#define _MX53_PAD_EIM_OE__IPU_DI1_PIN7 IOMUX_PAD(0x4D4, 0x188, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_OE__USBPHY2_IDDIG IOMUX_PAD(0x4D4, 0x188, 7, 0x0, 0, 0) +#define _MX53_PAD_EIM_RW__EMI_WEIM_RW IOMUX_PAD(0x4D8, 0x18C, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_RW__GPIO2_26 IOMUX_PAD(0x4D8, 0x18C, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_RW__ECSPI2_SS0 IOMUX_PAD(0x4D8, 0x18C, 2, 0x7C4, 2, 0) +#define _MX53_PAD_EIM_RW__IPU_DI1_PIN8 IOMUX_PAD(0x4D8, 0x18C, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_RW__USBPHY2_HOSTDISCONNECT IOMUX_PAD(0x4D8, 0x18C, 7, 0x0, 0, 0) +#define _MX53_PAD_EIM_LBA__EMI_WEIM_LBA IOMUX_PAD(0x4DC, 0x190, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_LBA__GPIO2_27 IOMUX_PAD(0x4DC, 0x190, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_LBA__ECSPI2_SS1 IOMUX_PAD(0x4DC, 0x190, 2, 0x7C8, 1, 0) +#define _MX53_PAD_EIM_LBA__IPU_DI1_PIN17 IOMUX_PAD(0x4DC, 0x190, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_LBA__SRC_BT_CFG1_0 IOMUX_PAD(0x4DC, 0x190, 7, 0x0, 0, 0) +#define _MX53_PAD_EIM_EB0__EMI_WEIM_EB_0 IOMUX_PAD(0x4E4, 0x194, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_EB0__GPIO2_28 IOMUX_PAD(0x4E4, 0x194, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 IOMUX_PAD(0x4E4, 0x194, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_EB0__IPU_CSI1_D_11 IOMUX_PAD(0x4E4, 0x194, 4, 0x0, 0, 0) +#define _MX53_PAD_EIM_EB0__GPC_PMIC_RDY IOMUX_PAD(0x4E4, 0x194, 5, 0x810, 0, 0) +#define _MX53_PAD_EIM_EB0__SRC_BT_CFG2_7 IOMUX_PAD(0x4E4, 0x194, 7, 0x0, 0, 0) +#define _MX53_PAD_EIM_EB1__EMI_WEIM_EB_1 IOMUX_PAD(0x4E8, 0x198, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_EB1__GPIO2_29 IOMUX_PAD(0x4E8, 0x198, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 IOMUX_PAD(0x4E8, 0x198, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_EB1__IPU_CSI1_D_10 IOMUX_PAD(0x4E8, 0x198, 4, 0x0, 0, 0) +#define _MX53_PAD_EIM_EB1__SRC_BT_CFG2_6 IOMUX_PAD(0x4E8, 0x198, 7, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 IOMUX_PAD(0x4EC, 0x19C, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA0__GPIO3_0 IOMUX_PAD(0x4EC, 0x19C, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 IOMUX_PAD(0x4EC, 0x19C, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA0__IPU_CSI1_D_9 IOMUX_PAD(0x4EC, 0x19C, 4, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA0__SRC_BT_CFG2_5 IOMUX_PAD(0x4EC, 0x19C, 7, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 IOMUX_PAD(0x4F0, 0x1A0, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA1__GPIO3_1 IOMUX_PAD(0x4F0, 0x1A0, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 IOMUX_PAD(0x4F0, 0x1A0, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA1__IPU_CSI1_D_8 IOMUX_PAD(0x4F0, 0x1A0, 4, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA1__SRC_BT_CFG2_4 IOMUX_PAD(0x4F0, 0x1A0, 7, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 IOMUX_PAD(0x4F4, 0x1A4, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA2__GPIO3_2 IOMUX_PAD(0x4F4, 0x1A4, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 IOMUX_PAD(0x4F4, 0x1A4, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA2__IPU_CSI1_D_7 IOMUX_PAD(0x4F4, 0x1A4, 4, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA2__SRC_BT_CFG2_3 IOMUX_PAD(0x4F4, 0x1A4, 7, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 IOMUX_PAD(0x4F8, 0x1A8, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA3__GPIO3_3 IOMUX_PAD(0x4F8, 0x1A8, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 IOMUX_PAD(0x4F8, 0x1A8, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA3__IPU_CSI1_D_6 IOMUX_PAD(0x4F8, 0x1A8, 4, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA3__SRC_BT_CFG2_2 IOMUX_PAD(0x4F8, 0x1A8, 7, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 IOMUX_PAD(0x4FC, 0x1AC, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA4__GPIO3_4 IOMUX_PAD(0x4FC, 0x1AC, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 IOMUX_PAD(0x4FC, 0x1AC, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA4__IPU_CSI1_D_5 IOMUX_PAD(0x4FC, 0x1AC, 4, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA4__SRC_BT_CFG3_7 IOMUX_PAD(0x4FC, 0x1AC, 7, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 IOMUX_PAD(0x500, 0x1B0, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA5__GPIO3_5 IOMUX_PAD(0x500, 0x1B0, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 IOMUX_PAD(0x500, 0x1B0, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA5__IPU_CSI1_D_4 IOMUX_PAD(0x500, 0x1B0, 4, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA5__SRC_BT_CFG3_6 IOMUX_PAD(0x500, 0x1B0, 17, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 IOMUX_PAD(0x504, 0x1B4, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA6__GPIO3_6 IOMUX_PAD(0x504, 0x1B4, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 IOMUX_PAD(0x504, 0x1B4, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA6__IPU_CSI1_D_3 IOMUX_PAD(0x504, 0x1B4, 4, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA6__SRC_BT_CFG3_5 IOMUX_PAD(0x504, 0x1B4, 7, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7 IOMUX_PAD(0x508, 0x1B8, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA7__GPIO3_7 IOMUX_PAD(0x508, 0x1B8, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 IOMUX_PAD(0x508, 0x1B8, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA7__IPU_CSI1_D_2 IOMUX_PAD(0x508, 0x1B8, 4, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA7__SRC_BT_CFG3_4 IOMUX_PAD(0x508, 0x1B8, 7, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8 IOMUX_PAD(0x50C, 0x1BC, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA8__GPIO3_8 IOMUX_PAD(0x50C, 0x1BC, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 IOMUX_PAD(0x50C, 0x1BC, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA8__IPU_CSI1_D_1 IOMUX_PAD(0x50C, 0x1BC, 4, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA8__SRC_BT_CFG3_3 IOMUX_PAD(0x50C, 0x1BC, 7, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9 IOMUX_PAD(0x510, 0x1C0, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA9__GPIO3_9 IOMUX_PAD(0x510, 0x1C0, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 IOMUX_PAD(0x510, 0x1C0, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA9__IPU_CSI1_D_0 IOMUX_PAD(0x510, 0x1C0, 4, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA9__SRC_BT_CFG3_2 IOMUX_PAD(0x510, 0x1C0, 7, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10 IOMUX_PAD(0x514, 0x1C4, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA10__GPIO3_10 IOMUX_PAD(0x514, 0x1C4, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA10__IPU_DI1_PIN15 IOMUX_PAD(0x514, 0x1C4, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA10__IPU_CSI1_DATA_EN IOMUX_PAD(0x514, 0x1C4, 4, 0x834, 1, 0) +#define _MX53_PAD_EIM_DA10__SRC_BT_CFG3_1 IOMUX_PAD(0x514, 0x1C4, 7, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11 IOMUX_PAD(0x518, 0x1C8, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA11__GPIO3_11 IOMUX_PAD(0x518, 0x1C8, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA11__IPU_DI1_PIN2 IOMUX_PAD(0x518, 0x1C8, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA11__IPU_CSI1_HSYNC IOMUX_PAD(0x518, 0x1C8, 4, 0x838, 1, 0) +#define _MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12 IOMUX_PAD(0x51C, 0x1CC, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA12__GPIO3_12 IOMUX_PAD(0x51C, 0x1CC, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA12__IPU_DI1_PIN3 IOMUX_PAD(0x51C, 0x1CC, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA12__IPU_CSI1_VSYNC IOMUX_PAD(0x51C, 0x1CC, 4, 0x83C, 1, 0) +#define _MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13 IOMUX_PAD(0x520, 0x1D0, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA13__GPIO3_13 IOMUX_PAD(0x520, 0x1D0, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA13__IPU_DI1_D0_CS IOMUX_PAD(0x520, 0x1D0, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA13__CCM_DI1_EXT_CLK IOMUX_PAD(0x520, 0x1D0, 4, 0x76C, 1, 0) +#define _MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14 IOMUX_PAD(0x524, 0x1D4, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA14__GPIO3_14 IOMUX_PAD(0x524, 0x1D4, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA14__IPU_DI1_D1_CS IOMUX_PAD(0x524, 0x1D4, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA14__CCM_DI0_EXT_CLK IOMUX_PAD(0x524, 0x1D4, 4, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15 IOMUX_PAD(0x528, 0x1D8, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA15__GPIO3_15 IOMUX_PAD(0x528, 0x1D8, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA15__IPU_DI1_PIN1 IOMUX_PAD(0x528, 0x1D8, 3, 0x0, 0, 0) +#define _MX53_PAD_EIM_DA15__IPU_DI1_PIN4 IOMUX_PAD(0x528, 0x1D8, 4, 0x0, 0, 0) +#define _MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B IOMUX_PAD(0x52C, 0x1DC, 0, 0x0, 0, 0) +#define _MX53_PAD_NANDF_WE_B__GPIO6_12 IOMUX_PAD(0x52C, 0x1DC, 1, 0x0, 0, 0) +#define _MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B IOMUX_PAD(0x530, 0x1E0, 0, 0x0, 0, 0) +#define _MX53_PAD_NANDF_RE_B__GPIO6_13 IOMUX_PAD(0x530, 0x1E0, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT IOMUX_PAD(0x534, 0x1E4, 0, 0x0, 0, 0) +#define _MX53_PAD_EIM_WAIT__GPIO5_0 IOMUX_PAD(0x534, 0x1E4, 1, 0x0, 0, 0) +#define _MX53_PAD_EIM_WAIT__EMI_WEIM_DTACK_B IOMUX_PAD(0x534, 0x1E4, 2, 0x0, 0, 0) +#define _MX53_PAD_LVDS1_TX3_P__GPIO6_22 IOMUX_PAD(NON_PAD_I, 0x1EC, 0, 0x0, 0, 0) +#define _MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 IOMUX_PAD(NON_PAD_I, 0x1EC, 1, 0x0, 0, 0) +#define _MX53_PAD_LVDS1_TX2_P__GPIO6_24 IOMUX_PAD(NON_PAD_I, 0x1F0, 0, 0x0, 0, 0) +#define _MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 IOMUX_PAD(NON_PAD_I, 0x1F0, 1, 0x0, 0, 0) +#define _MX53_PAD_LVDS1_CLK_P__GPIO6_26 IOMUX_PAD(NON_PAD_I, 0x1F4, 0, 0x0, 0, 0) +#define _MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK IOMUX_PAD(NON_PAD_I, 0x1F4, 1, 0x0, 0, 0) +#define _MX53_PAD_LVDS1_TX1_P__GPIO6_28 IOMUX_PAD(NON_PAD_I, 0x1F8, 0, 0x0, 0, 0) +#define _MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 IOMUX_PAD(NON_PAD_I, 0x1F8, 1, 0x0, 0, 0) +#define _MX53_PAD_LVDS1_TX0_P__GPIO6_30 IOMUX_PAD(NON_PAD_I, 0x1FC, 0, 0x0, 0, 0) +#define _MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 IOMUX_PAD(NON_PAD_I, 0x1FC, 1, 0x0, 0, 0) +#define _MX53_PAD_LVDS0_TX3_P__GPIO7_22 IOMUX_PAD(NON_PAD_I, 0x200, 0, 0x0, 0, 0) +#define _MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 IOMUX_PAD(NON_PAD_I, 0x200, 1, 0x0, 0, 0) +#define _MX53_PAD_LVDS0_CLK_P__GPIO7_24 IOMUX_PAD(NON_PAD_I, 0x204, 0, 0x0, 0, 0) +#define _MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK IOMUX_PAD(NON_PAD_I, 0x204, 1, 0x0, 0, 0) +#define _MX53_PAD_LVDS0_TX2_P__GPIO7_26 IOMUX_PAD(NON_PAD_I, 0x208, 0, 0x0, 0, 0) +#define _MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 IOMUX_PAD(NON_PAD_I, 0x208, 1, 0x0, 0, 0) +#define _MX53_PAD_LVDS0_TX1_P__GPIO7_28 IOMUX_PAD(NON_PAD_I, 0x20C, 0, 0x0, 0, 0) +#define _MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 IOMUX_PAD(NON_PAD_I, 0x20C, 1, 0x0, 0, 0) +#define _MX53_PAD_LVDS0_TX0_P__GPIO7_30 IOMUX_PAD(NON_PAD_I, 0x210, 0, 0x0, 0, 0) +#define _MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 IOMUX_PAD(NON_PAD_I, 0x210, 1, 0x0, 0, 0) +#define _MX53_PAD_GPIO_10__GPIO4_0 IOMUX_PAD(0x540, 0x214, 0, 0x0, 0, 0) +#define _MX53_PAD_GPIO_10__OSC32k_32K_OUT IOMUX_PAD(0x540, 0x214, 1, 0x0, 0, 0) +#define _MX53_PAD_GPIO_11__GPIO4_1 IOMUX_PAD(0x544, 0x218, 0, 0x0, 0, 0) +#define _MX53_PAD_GPIO_12__GPIO4_2 IOMUX_PAD(0x548, 0x21C, 0, 0x0, 0, 0) +#define _MX53_PAD_GPIO_13__GPIO4_3 IOMUX_PAD(0x54C, 0x220, 0, 0x0, 0, 0) +#define _MX53_PAD_GPIO_14__GPIO4_4 IOMUX_PAD(0x550, 0x224, 0, 0x0, 0, 0) +#define _MX53_PAD_NANDF_CLE__EMI_NANDF_CLE IOMUX_PAD(0x5A0, 0x228, 0, 0x0, 0, 0) +#define _MX53_PAD_NANDF_CLE__GPIO6_7 IOMUX_PAD(0x5A0, 0x228, 1, 0x0, 0, 0) +#define _MX53_PAD_NANDF_CLE__USBPHY1_VSTATUS_0 IOMUX_PAD(0x5A0, 0x228, 7, 0x0, 0, 0) +#define _MX53_PAD_NANDF_ALE__EMI_NANDF_ALE IOMUX_PAD(0x5A4, 0x22C, 0, 0x0, 0, 0) +#define _MX53_PAD_NANDF_ALE__GPIO6_8 IOMUX_PAD(0x5A4, 0x22C, 1, 0x0, 0, 0) +#define _MX53_PAD_NANDF_ALE__USBPHY1_VSTATUS_1 IOMUX_PAD(0x5A4, 0x22C, 7, 0x0, 0, 0) +#define _MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B IOMUX_PAD(0x5A8, 0x230, 0, 0x0, 0, 0) +#define _MX53_PAD_NANDF_WP_B__GPIO6_9 IOMUX_PAD(0x5A8, 0x230, 1, 0x0, 0, 0) +#define _MX53_PAD_NANDF_WP_B__USBPHY1_VSTATUS_2 IOMUX_PAD(0x5A8, 0x230, 7, 0x0, 0, 0) +#define _MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 IOMUX_PAD(0x5AC, 0x234, 0, 0x0, 0, 0) +#define _MX53_PAD_NANDF_RB0__GPIO6_10 IOMUX_PAD(0x5AC, 0x234, 1, 0x0, 0, 0) +#define _MX53_PAD_NANDF_RB0__USBPHY1_VSTATUS_3 IOMUX_PAD(0x5AC, 0x234, 7, 0x0, 0, 0) +#define _MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 IOMUX_PAD(0x5B0, 0x238, 0, 0x0, 0, 0) +#define _MX53_PAD_NANDF_CS0__GPIO6_11 IOMUX_PAD(0x5B0, 0x238, 1, 0x0, 0, 0) +#define _MX53_PAD_NANDF_CS0__USBPHY1_VSTATUS_4 IOMUX_PAD(0x5B0, 0x238, 7, 0x0, 0, 0) +#define _MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1 IOMUX_PAD(0x5B4, 0x23C, 0, 0x0, 0, 0) +#define _MX53_PAD_NANDF_CS1__GPIO6_14 IOMUX_PAD(0x5B4, 0x23C, 1, 0x0, 0, 0) +#define _MX53_PAD_NANDF_CS1__MLB_MLBCLK IOMUX_PAD(0x5B4, 0x23C, 6, 0x858, 0, 0) +#define _MX53_PAD_NANDF_CS1__USBPHY1_VSTATUS_5 IOMUX_PAD(0x5B4, 0x23C, 7, 0x0, 0, 0) +#define _MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2 IOMUX_PAD(0x5B8, 0x240, 0, 0x0, 0, 0) +#define _MX53_PAD_NANDF_CS2__GPIO6_15 IOMUX_PAD(0x5B8, 0x240, 1, 0x0, 0, 0) +#define _MX53_PAD_NANDF_CS2__IPU_SISG_0 IOMUX_PAD(0x5B8, 0x240, 2, 0x0, 0, 0) +#define _MX53_PAD_NANDF_CS2__ESAI1_TX0 IOMUX_PAD(0x5B8, 0x240, 3, 0x7E4, 0, 0) +#define _MX53_PAD_NANDF_CS2__EMI_WEIM_CRE IOMUX_PAD(0x5B8, 0x240, 4, 0x0, 0, 0) +#define _MX53_PAD_NANDF_CS2__CCM_CSI0_MCLK IOMUX_PAD(0x5B8, 0x240, 5, 0x0, 0, 0) +#define _MX53_PAD_NANDF_CS2__MLB_MLBSIG IOMUX_PAD(0x5B8, 0x240, 6, 0x860, 0, 0) +#define _MX53_PAD_NANDF_CS2__USBPHY1_VSTATUS_6 IOMUX_PAD(0x5B8, 0x240, 7, 0x0, 0, 0) +#define _MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3 IOMUX_PAD(0x5BC, 0x244, 0, 0x0, 0, 0) +#define _MX53_PAD_NANDF_CS3__GPIO6_16 IOMUX_PAD(0x5BC, 0x244, 1, 0x0, 0, 0) +#define _MX53_PAD_NANDF_CS3__IPU_SISG_1 IOMUX_PAD(0x5BC, 0x244, 2, 0x0, 0, 0) +#define _MX53_PAD_NANDF_CS3__ESAI1_TX1 IOMUX_PAD(0x5BC, 0x244, 3, 0x7E8, 0, 0) +#define _MX53_PAD_NANDF_CS3__EMI_WEIM_A_26 IOMUX_PAD(0x5BC, 0x244, 4, 0x0, 0, 0) +#define _MX53_PAD_NANDF_CS3__MLB_MLBDAT IOMUX_PAD(0x5BC, 0x244, 6, 0x85C, 0, 0) +#define _MX53_PAD_NANDF_CS3__USBPHY1_VSTATUS_7 IOMUX_PAD(0x5BC, 0x244, 7, 0x0, 0, 0) +#define _MX53_PAD_FEC_MDIO__FEC_MDIO IOMUX_PAD(0x5C4, 0x248, 0, 0x804, 1, 0) +#define _MX53_PAD_FEC_MDIO__GPIO1_22 IOMUX_PAD(0x5C4, 0x248, 1, 0x0, 0, 0) +#define _MX53_PAD_FEC_MDIO__ESAI1_SCKR IOMUX_PAD(0x5C4, 0x248, 2, 0x7DC, 0, 0) +#define _MX53_PAD_FEC_MDIO__FEC_COL IOMUX_PAD(0x5C4, 0x248, 3, 0x800, 1, 0) +#define _MX53_PAD_FEC_MDIO__RTC_CE_RTC_PS2 IOMUX_PAD(0x5C4, 0x248, 4, 0x0, 0, 0) +#define _MX53_PAD_FEC_MDIO__SDMA_DEBUG_BUS_DEVICE_3 IOMUX_PAD(0x5C4, 0x248, 5, 0x0, 0, 0) +#define _MX53_PAD_FEC_MDIO__EMI_EMI_DEBUG_49 IOMUX_PAD(0x5C4, 0x248, 6, 0x0, 0, 0) +#define _MX53_PAD_FEC_REF_CLK__FEC_TX_CLK IOMUX_PAD(0x5C8, 0x24C, 0, 0x0, 0, 0) +#define _MX53_PAD_FEC_REF_CLK__GPIO1_23 IOMUX_PAD(0x5C8, 0x24C, 1, 0x0, 0, 0) +#define _MX53_PAD_FEC_REF_CLK__ESAI1_FSR IOMUX_PAD(0x5C8, 0x24C, 2, 0x7CC, 0, 0) +#define _MX53_PAD_FEC_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 IOMUX_PAD(0x5C8, 0x24C, 5, 0x0, 0, 0) +#define _MX53_PAD_FEC_REF_CLK__EMI_EMI_DEBUG_50 IOMUX_PAD(0x5C8, 0x24C, 6, 0x0, 0, 0) +#define _MX53_PAD_FEC_RX_ER__FEC_RX_ER IOMUX_PAD(0x5CC, 0x250, 0, 0x0, 0, 0) +#define _MX53_PAD_FEC_RX_ER__GPIO1_24 IOMUX_PAD(0x5CC, 0x250, 1, 0x0, 0, 0) +#define _MX53_PAD_FEC_RX_ER__ESAI1_HCKR IOMUX_PAD(0x5CC, 0x250, 2, 0x7D4, 0, 0) +#define _MX53_PAD_FEC_RX_ER__FEC_RX_CLK IOMUX_PAD(0x5CC, 0x250, 3, 0x808, 1, 0) +#define _MX53_PAD_FEC_RX_ER__RTC_CE_RTC_PS3 IOMUX_PAD(0x5CC, 0x250, 4, 0x0, 0, 0) +#define _MX53_PAD_FEC_CRS_DV__FEC_RX_DV IOMUX_PAD(0x5D0, 0x254, 0, 0x0, 0, 0) +#define _MX53_PAD_FEC_CRS_DV__GPIO1_25 IOMUX_PAD(0x5D0, 0x254, 1, 0x0, 0, 0) +#define _MX53_PAD_FEC_CRS_DV__ESAI1_SCKT IOMUX_PAD(0x5D0, 0x254, 2, 0x7E0, 0, 0) +#define _MX53_PAD_FEC_RXD1__FEC_RDATA_1 IOMUX_PAD(0x5D4, 0x258, 0, 0x0, 0, 0) +#define _MX53_PAD_FEC_RXD1__GPIO1_26 IOMUX_PAD(0x5D4, 0x258, 1, 0x0, 0, 0) +#define _MX53_PAD_FEC_RXD1__ESAI1_FST IOMUX_PAD(0x5D4, 0x258, 2, 0x7D0, 0, 0) +#define _MX53_PAD_FEC_RXD1__MLB_MLBSIG IOMUX_PAD(0x5D4, 0x258, 3, 0x860, 1, 0) +#define _MX53_PAD_FEC_RXD1__RTC_CE_RTC_PS1 IOMUX_PAD(0x5D4, 0x258, 4, 0x0, 0, 0) +#define _MX53_PAD_FEC_RXD0__FEC_RDATA_0 IOMUX_PAD(0x5D8, 0x25C, 0, 0x0, 0, 0) +#define _MX53_PAD_FEC_RXD0__GPIO1_27 IOMUX_PAD(0x5D8, 0x25C, 1, 0x0, 0, 0) +#define _MX53_PAD_FEC_RXD0__ESAI1_HCKT IOMUX_PAD(0x5D8, 0x25C, 2, 0x7D8, 0, 0) +#define _MX53_PAD_FEC_RXD0__OSC32k_32K_OUT IOMUX_PAD(0x5D8, 0x25C, 3, 0x0, 0, 0) +#define _MX53_PAD_FEC_TX_EN__FEC_TX_EN IOMUX_PAD(0x5DC, 0x260, 0, 0x0, 0, 0) +#define _MX53_PAD_FEC_TX_EN__GPIO1_28 IOMUX_PAD(0x5DC, 0x260, 1, 0x0, 0, 0) +#define _MX53_PAD_FEC_TX_EN__ESAI1_TX3_RX2 IOMUX_PAD(0x5DC, 0x260, 2, 0x7F0, 0, 0) +#define _MX53_PAD_FEC_TXD1__FEC_TDATA_1 IOMUX_PAD(0x5E0, 0x264, 0, 0x0, 0, 0) +#define _MX53_PAD_FEC_TXD1__GPIO1_29 IOMUX_PAD(0x5E0, 0x264, 1, 0x0, 0, 0) +#define _MX53_PAD_FEC_TXD1__ESAI1_TX2_RX3 IOMUX_PAD(0x5E0, 0x264, 2, 0x7EC, 0, 0) +#define _MX53_PAD_FEC_TXD1__MLB_MLBCLK IOMUX_PAD(0x5E0, 0x264, 3, 0x858, 1, 0) +#define _MX53_PAD_FEC_TXD1__RTC_CE_RTC_PRSC_CLK IOMUX_PAD(0x5E0, 0x264, 4, 0x0, 0, 0) +#define _MX53_PAD_FEC_TXD0__FEC_TDATA_0 IOMUX_PAD(0x5E4, 0x268, 0, 0x0, 0, 0) +#define _MX53_PAD_FEC_TXD0__GPIO1_30 IOMUX_PAD(0x5E4, 0x268, 1, 0x0, 0, 0) +#define _MX53_PAD_FEC_TXD0__ESAI1_TX4_RX1 IOMUX_PAD(0x5E4, 0x268, 2, 0x7F4, 0, 0) +#define _MX53_PAD_FEC_TXD0__USBPHY2_DATAOUT_0 IOMUX_PAD(0x5E4, 0x268, 7, 0x0, 0, 0) +#define _MX53_PAD_FEC_MDC__FEC_MDC IOMUX_PAD(0x5E8, 0x26C, 0, 0x0, 0, 0) +#define _MX53_PAD_FEC_MDC__GPIO1_31 IOMUX_PAD(0x5E8, 0x26C, 1, 0x0, 0, 0) +#define _MX53_PAD_FEC_MDC__ESAI1_TX5_RX0 IOMUX_PAD(0x5E8, 0x26C, 2, 0x7F8, 0, 0) +#define _MX53_PAD_FEC_MDC__MLB_MLBDAT IOMUX_PAD(0x5E8, 0x26C, 3, 0x85C, 1, 0) +#define _MX53_PAD_FEC_MDC__RTC_CE_RTC_ALARM1_TRIG IOMUX_PAD(0x5E8, 0x26C, 4, 0x0, 0, 0) +#define _MX53_PAD_FEC_MDC__USBPHY2_DATAOUT_1 IOMUX_PAD(0x5E8, 0x26C, 7, 0x0, 0, 0) +#define _MX53_PAD_PATA_DIOW__PATA_DIOW IOMUX_PAD(0x5F0, 0x270, 0, 0x0, 0, 0) +#define _MX53_PAD_PATA_DIOW__GPIO6_17 IOMUX_PAD(0x5F0, 0x270, 1, 0x0, 0, 0) +#define _MX53_PAD_PATA_DIOW__UART1_TXD_MUX IOMUX_PAD(0x5F0, 0x270, 3, 0x878, 2, 0) +#define _MX53_PAD_PATA_DIOW__USBPHY2_DATAOUT_2 IOMUX_PAD(0x5F0, 0x270, 7, 0x0, 0, 0) +#define _MX53_PAD_PATA_DMACK__PATA_DMACK IOMUX_PAD(0x5F4, 0x274, 0, 0x0, 0, 0) +#define _MX53_PAD_PATA_DMACK__GPIO6_18 IOMUX_PAD(0x5F4, 0x274, 1, 0x0, 0, 0) +#define _MX53_PAD_PATA_DMACK__UART1_RXD_MUX IOMUX_PAD(0x5F4, 0x274, 3, 0x878, 3, 0) +#define _MX53_PAD_PATA_DMACK__USBPHY2_DATAOUT_3 IOMUX_PAD(0x5F4, 0x274, 7, 0x0, 0, 0) +#define _MX53_PAD_PATA_DMARQ__PATA_DMARQ IOMUX_PAD(0x5F8, 0x278, 0, 0x0, 0, 0) +#define _MX53_PAD_PATA_DMARQ__GPIO7_0 IOMUX_PAD(0x5F8, 0x278, 1, 0x0, 0, 0) +#define _MX53_PAD_PATA_DMARQ__UART2_TXD_MUX IOMUX_PAD(0x5F8, 0x278, 3, 0x880, 2, 0) +#define _MX53_PAD_PATA_DMARQ__CCM_CCM_OUT_0 IOMUX_PAD(0x5F8, 0x278, 5, 0x0, 0, 0) +#define _MX53_PAD_PATA_DMARQ__USBPHY2_DATAOUT_4 IOMUX_PAD(0x5F8, 0x278, 7, 0x0, 0, 0) +#define _MX53_PAD_PATA_BUFFER_EN__PATA_BUFFER_EN IOMUX_PAD(0x5FC, 0x27C, 0, 0x0, 0, 0) +#define _MX53_PAD_PATA_BUFFER_EN__GPIO7_1 IOMUX_PAD(0x5FC, 0x27C, 1, 0x0, 0, 0) +#define _MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX IOMUX_PAD(0x5FC, 0x27C, 3, 0x880, 3, 0) +#define _MX53_PAD_PATA_BUFFER_EN__CCM_CCM_OUT_1 IOMUX_PAD(0x5FC, 0x27C, 5, 0x0, 0, 0) +#define _MX53_PAD_PATA_BUFFER_EN__USBPHY2_DATAOUT_5 IOMUX_PAD(0x5FC, 0x27C, 7, 0x0, 0, 0) +#define _MX53_PAD_PATA_INTRQ__PATA_INTRQ IOMUX_PAD(0x600, 0x280, 0, 0x0, 0, 0) +#define _MX53_PAD_PATA_INTRQ__GPIO7_2 IOMUX_PAD(0x600, 0x280, 1, 0x0, 0, 0) +#define _MX53_PAD_PATA_INTRQ__UART2_CTS IOMUX_PAD(0x600, 0x280, 3, 0x87C, 2, 0) +#define _MX53_PAD_PATA_INTRQ__CAN1_TXCAN IOMUX_PAD(0x600, 0x280, 4, 0x0, 0, 0) +#define _MX53_PAD_PATA_INTRQ__CCM_CCM_OUT_2 IOMUX_PAD(0x600, 0x280, 5, 0x0, 0, 0) +#define _MX53_PAD_PATA_INTRQ__USBPHY2_DATAOUT_6 IOMUX_PAD(0x600, 0x280, 7, 0x0, 0, 0) +#define _MX53_PAD_PATA_DIOR__PATA_DIOR IOMUX_PAD(0x604, 0x284, 0, 0x0, 0, 0) +#define _MX53_PAD_PATA_DIOR__GPIO7_3 IOMUX_PAD(0x604, 0x284, 1, 0x0, 0, 0) +#define _MX53_PAD_PATA_DIOR__UART2_RTS IOMUX_PAD(0x604, 0x284, 3, 0x87C, 3, 0) +#define _MX53_PAD_PATA_DIOR__CAN1_RXCAN IOMUX_PAD(0x604, 0x284, 4, 0x760, 1, 0) +#define _MX53_PAD_PATA_DIOR__USBPHY2_DATAOUT_7 IOMUX_PAD(0x604, 0x284, 7, 0x0, 0, 0) +#define _MX53_PAD_PATA_RESET_B__PATA_PATA_RESET_B IOMUX_PAD(0x608, 0x288, 0, 0x0, 0, 0) +#define _MX53_PAD_PATA_RESET_B__GPIO7_4 IOMUX_PAD(0x608, 0x288, 1, 0x0, 0, 0) +#define _MX53_PAD_PATA_RESET_B__ESDHC3_CMD IOMUX_PAD(0x608, 0x288, 2, 0x0, 0, 0) +#define _MX53_PAD_PATA_RESET_B__UART1_CTS IOMUX_PAD(0x608, 0x288, 3, 0x874, 2, 0) +#define _MX53_PAD_PATA_RESET_B__CAN2_TXCAN IOMUX_PAD(0x608, 0x288, 4, 0x0, 0, 0) +#define _MX53_PAD_PATA_RESET_B__USBPHY1_DATAOUT_0 IOMUX_PAD(0x608, 0x288, 7, 0x0, 0, 0) +#define _MX53_PAD_PATA_IORDY__PATA_IORDY IOMUX_PAD(0x60C, 0x28C, 0, 0x0, 0, 0) +#define _MX53_PAD_PATA_IORDY__GPIO7_5 IOMUX_PAD(0x60C, 0x28C, 1, 0x0, 0, 0) +#define _MX53_PAD_PATA_IORDY__ESDHC3_CLK IOMUX_PAD(0x60C, 0x28C, 2, 0x0, 0, 0) +#define _MX53_PAD_PATA_IORDY__UART1_RTS IOMUX_PAD(0x60C, 0x28C, 3, 0x874, 3, 0) +#define _MX53_PAD_PATA_IORDY__CAN2_RXCAN IOMUX_PAD(0x60C, 0x28C, 4, 0x764, 1, 0) +#define _MX53_PAD_PATA_IORDY__USBPHY1_DATAOUT_1 IOMUX_PAD(0x60C, 0x28C, 7, 0x0, 0, 0) +#define _MX53_PAD_PATA_DA_0__PATA_DA_0 IOMUX_PAD(0x610, 0x290, 0, 0x0, 0, 0) +#define _MX53_PAD_PATA_DA_0__GPIO7_6 IOMUX_PAD(0x610, 0x290, 1, 0x0, 0, 0) +#define _MX53_PAD_PATA_DA_0__ESDHC3_RST IOMUX_PAD(0x610, 0x290, 2, 0x0, 0, 0) +#define _MX53_PAD_PATA_DA_0__OWIRE_LINE IOMUX_PAD(0x610, 0x290, 4, 0x864, 0, 0) +#define _MX53_PAD_PATA_DA_0__USBPHY1_DATAOUT_2 IOMUX_PAD(0x610, 0x290, 7, 0x0, 0, 0) +#define _MX53_PAD_PATA_DA_1__PATA_DA_1 IOMUX_PAD(0x614, 0x294, 0, 0x0, 0, 0) +#define _MX53_PAD_PATA_DA_1__GPIO7_7 IOMUX_PAD(0x614, 0x294, 1, 0x0, 0, 0) +#define _MX53_PAD_PATA_DA_1__ESDHC4_CMD IOMUX_PAD(0x614, 0x294, 2, 0x0, 0, 0) +#define _MX53_PAD_PATA_DA_1__UART3_CTS IOMUX_PAD(0x614, 0x294, 4, 0x884, 4, 0) +#define _MX53_PAD_PATA_DA_1__USBPHY1_DATAOUT_3 IOMUX_PAD(0x614, 0x294, 7, 0x0, 0, 0) +#define _MX53_PAD_PATA_DA_2__PATA_DA_2 IOMUX_PAD(0x618, 0x298, 0, 0x0, 0, 0) +#define _MX53_PAD_PATA_DA_2__GPIO7_8 IOMUX_PAD(0x618, 0x298, 1, 0x0, 0, 0) +#define _MX53_PAD_PATA_DA_2__ESDHC4_CLK IOMUX_PAD(0x618, 0x298, 2, 0x0, 0, 0) +#define _MX53_PAD_PATA_DA_2__UART3_RTS IOMUX_PAD(0x618, 0x298, 4, 0x884, 5, 0) +#define _MX53_PAD_PATA_DA_2__USBPHY1_DATAOUT_4 IOMUX_PAD(0x618, 0x298, 7, 0x0, 0, 0) +#define _MX53_PAD_PATA_CS_0__PATA_CS_0 IOMUX_PAD(0x61C, 0x29C, 0, 0x0, 0, 0) +#define _MX53_PAD_PATA_CS_0__GPIO7_9 IOMUX_PAD(0x61C, 0x29C, 1, 0x0, 0, 0) +#define _MX53_PAD_PATA_CS_0__UART3_TXD_MUX IOMUX_PAD(0x61C, 0x29C, 4, 0x888, 2, 0) +#define _MX53_PAD_PATA_CS_0__USBPHY1_DATAOUT_5 IOMUX_PAD(0x61C, 0x29C, 7, 0x0, 0, 0) +#define _MX53_PAD_PATA_CS_1__PATA_CS_1 IOMUX_PAD(0x620, 0x2A0, 0, 0x0, 0, 0) +#define _MX53_PAD_PATA_CS_1__GPIO7_10 IOMUX_PAD(0x620, 0x2A0, 1, 0x0, 0, 0) +#define _MX53_PAD_PATA_CS_1__UART3_RXD_MUX IOMUX_PAD(0x620, 0x2A0, 4, 0x888, 3, 0) +#define _MX53_PAD_PATA_CS_1__USBPHY1_DATAOUT_6 IOMUX_PAD(0x620, 0x2A0, 7, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA0__PATA_DATA_0 IOMUX_PAD(0x628, 0x2A4, 0, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA0__GPIO2_0 IOMUX_PAD(0x628, 0x2A4, 1, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 IOMUX_PAD(0x628, 0x2A4, 3, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA0__ESDHC3_DAT4 IOMUX_PAD(0x628, 0x2A4, 4, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA0__GPU3d_GPU_DEBUG_OUT_0 IOMUX_PAD(0x628, 0x2A4, 5, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA0__IPU_DIAG_BUS_0 IOMUX_PAD(0x628, 0x2A4, 6, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA0__USBPHY1_DATAOUT_7 IOMUX_PAD(0x628, 0x2A4, 7, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA1__PATA_DATA_1 IOMUX_PAD(0x62C, 0x2A8, 0, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA1__GPIO2_1 IOMUX_PAD(0x62C, 0x2A8, 1, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 IOMUX_PAD(0x62C, 0x2A8, 3, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA1__ESDHC3_DAT5 IOMUX_PAD(0x62C, 0x2A8, 4, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA1__GPU3d_GPU_DEBUG_OUT_1 IOMUX_PAD(0x62C, 0x2A8, 5, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA1__IPU_DIAG_BUS_1 IOMUX_PAD(0x62C, 0x2A8, 6, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA2__PATA_DATA_2 IOMUX_PAD(0x630, 0x2AC, 0, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA2__GPIO2_2 IOMUX_PAD(0x630, 0x2AC, 1, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 IOMUX_PAD(0x630, 0x2AC, 3, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA2__ESDHC3_DAT6 IOMUX_PAD(0x630, 0x2AC, 4, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA2__GPU3d_GPU_DEBUG_OUT_2 IOMUX_PAD(0x630, 0x2AC, 5, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA2__IPU_DIAG_BUS_2 IOMUX_PAD(0x630, 0x2AC, 6, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA3__PATA_DATA_3 IOMUX_PAD(0x634, 0x2B0, 0, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA3__GPIO2_3 IOMUX_PAD(0x634, 0x2B0, 1, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 IOMUX_PAD(0x634, 0x2B0, 3, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA3__ESDHC3_DAT7 IOMUX_PAD(0x634, 0x2B0, 4, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA3__GPU3d_GPU_DEBUG_OUT_3 IOMUX_PAD(0x634, 0x2B0, 5, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA3__IPU_DIAG_BUS_3 IOMUX_PAD(0x634, 0x2B0, 6, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA4__PATA_DATA_4 IOMUX_PAD(0x638, 0x2B4, 0, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA4__GPIO2_4 IOMUX_PAD(0x638, 0x2B4, 1, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 IOMUX_PAD(0x638, 0x2B4, 3, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA4__ESDHC4_DAT4 IOMUX_PAD(0x638, 0x2B4, 4, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA4__GPU3d_GPU_DEBUG_OUT_4 IOMUX_PAD(0x638, 0x2B4, 5, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA4__IPU_DIAG_BUS_4 IOMUX_PAD(0x638, 0x2B4, 6, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA5__PATA_DATA_5 IOMUX_PAD(0x63C, 0x2B8, 0, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA5__GPIO2_5 IOMUX_PAD(0x63C, 0x2B8, 1, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 IOMUX_PAD(0x63C, 0x2B8, 3, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA5__ESDHC4_DAT5 IOMUX_PAD(0x63C, 0x2B8, 4, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5 IOMUX_PAD(0x63C, 0x2B8, 5, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5 IOMUX_PAD(0x63C, 0x2B8, 6, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA6__PATA_DATA_6 IOMUX_PAD(0x640, 0x2BC, 0, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA6__GPIO2_6 IOMUX_PAD(0x640, 0x2BC, 1, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 IOMUX_PAD(0x640, 0x2BC, 3, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA6__ESDHC4_DAT6 IOMUX_PAD(0x640, 0x2BC, 4, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6 IOMUX_PAD(0x640, 0x2BC, 5, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6 IOMUX_PAD(0x640, 0x2BC, 6, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA7__PATA_DATA_7 IOMUX_PAD(0x644, 0x2C0, 0, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA7__GPIO2_7 IOMUX_PAD(0x644, 0x2C0, 1, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 IOMUX_PAD(0x644, 0x2C0, 3, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA7__ESDHC4_DAT7 IOMUX_PAD(0x644, 0x2C0, 4, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA7__GPU3d_GPU_DEBUG_OUT_7 IOMUX_PAD(0x644, 0x2C0, 5, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA7__IPU_DIAG_BUS_7 IOMUX_PAD(0x644, 0x2C0, 6, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA8__PATA_DATA_8 IOMUX_PAD(0x648, 0x2C4, 0, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA8__GPIO2_8 IOMUX_PAD(0x648, 0x2C4, 1, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA8__ESDHC1_DAT4 IOMUX_PAD(0x648, 0x2C4, 2, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA8__EMI_NANDF_D_8 IOMUX_PAD(0x648, 0x2C4, 3, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA8__ESDHC3_DAT0 IOMUX_PAD(0x648, 0x2C4, 4, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA8__GPU3d_GPU_DEBUG_OUT_8 IOMUX_PAD(0x648, 0x2C4, 5, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA8__IPU_DIAG_BUS_8 IOMUX_PAD(0x648, 0x2C4, 6, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA9__PATA_DATA_9 IOMUX_PAD(0x64C, 0x2C8, 0, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA9__GPIO2_9 IOMUX_PAD(0x64C, 0x2C8, 1, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA9__ESDHC1_DAT5 IOMUX_PAD(0x64C, 0x2C8, 2, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA9__EMI_NANDF_D_9 IOMUX_PAD(0x64C, 0x2C8, 3, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA9__ESDHC3_DAT1 IOMUX_PAD(0x64C, 0x2C8, 4, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA9__GPU3d_GPU_DEBUG_OUT_9 IOMUX_PAD(0x64C, 0x2C8, 5, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA9__IPU_DIAG_BUS_9 IOMUX_PAD(0x64C, 0x2C8, 6, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA10__PATA_DATA_10 IOMUX_PAD(0x650, 0x2CC, 0, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA10__GPIO2_10 IOMUX_PAD(0x650, 0x2CC, 1, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA10__ESDHC1_DAT6 IOMUX_PAD(0x650, 0x2CC, 2, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA10__EMI_NANDF_D_10 IOMUX_PAD(0x650, 0x2CC, 3, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA10__ESDHC3_DAT2 IOMUX_PAD(0x650, 0x2CC, 4, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA10__GPU3d_GPU_DEBUG_OUT_10 IOMUX_PAD(0x650, 0x2CC, 5, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA10__IPU_DIAG_BUS_10 IOMUX_PAD(0x650, 0x2CC, 6, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA11__PATA_DATA_11 IOMUX_PAD(0x654, 0x2D0, 0, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA11__GPIO2_11 IOMUX_PAD(0x654, 0x2D0, 1, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA11__ESDHC1_DAT7 IOMUX_PAD(0x654, 0x2D0, 2, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA11__EMI_NANDF_D_11 IOMUX_PAD(0x654, 0x2D0, 3, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA11__ESDHC3_DAT3 IOMUX_PAD(0x654, 0x2D0, 4, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA11__GPU3d_GPU_DEBUG_OUT_11 IOMUX_PAD(0x654, 0x2D0, 5, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA11__IPU_DIAG_BUS_11 IOMUX_PAD(0x654, 0x2D0, 6, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA12__PATA_DATA_12 IOMUX_PAD(0x658, 0x2D4, 0, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA12__GPIO2_12 IOMUX_PAD(0x658, 0x2D4, 1, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA12__ESDHC2_DAT4 IOMUX_PAD(0x658, 0x2D4, 2, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA12__EMI_NANDF_D_12 IOMUX_PAD(0x658, 0x2D4, 3, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA12__ESDHC4_DAT0 IOMUX_PAD(0x658, 0x2D4, 4, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA12__GPU3d_GPU_DEBUG_OUT_12 IOMUX_PAD(0x658, 0x2D4, 5, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA12__IPU_DIAG_BUS_12 IOMUX_PAD(0x658, 0x2D4, 6, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA13__PATA_DATA_13 IOMUX_PAD(0x65C, 0x2D8, 0, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA13__GPIO2_13 IOMUX_PAD(0x65C, 0x2D8, 1, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA13__ESDHC2_DAT5 IOMUX_PAD(0x65C, 0x2D8, 2, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA13__EMI_NANDF_D_13 IOMUX_PAD(0x65C, 0x2D8, 3, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA13__ESDHC4_DAT1 IOMUX_PAD(0x65C, 0x2D8, 4, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA13__GPU3d_GPU_DEBUG_OUT_13 IOMUX_PAD(0x65C, 0x2D8, 5, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA13__IPU_DIAG_BUS_13 IOMUX_PAD(0x65C, 0x2D8, 6, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA14__PATA_DATA_14 IOMUX_PAD(0x660, 0x2DC, 0, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA14__GPIO2_14 IOMUX_PAD(0x660, 0x2DC, 1, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA14__ESDHC2_DAT6 IOMUX_PAD(0x660, 0x2DC, 2, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA14__EMI_NANDF_D_14 IOMUX_PAD(0x660, 0x2DC, 3, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA14__ESDHC4_DAT2 IOMUX_PAD(0x660, 0x2DC, 4, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA14__GPU3d_GPU_DEBUG_OUT_14 IOMUX_PAD(0x660, 0x2DC, 5, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA14__IPU_DIAG_BUS_14 IOMUX_PAD(0x660, 0x2DC, 6, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA15__PATA_DATA_15 IOMUX_PAD(0x664, 0x2E0, 0, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA15__GPIO2_15 IOMUX_PAD(0x664, 0x2E0, 1, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA15__ESDHC2_DAT7 IOMUX_PAD(0x664, 0x2E0, 2, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA15__EMI_NANDF_D_15 IOMUX_PAD(0x664, 0x2E0, 3, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA15__ESDHC4_DAT3 IOMUX_PAD(0x664, 0x2E0, 4, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA15__GPU3d_GPU_DEBUG_OUT_15 IOMUX_PAD(0x664, 0x2E0, 5, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA15__IPU_DIAG_BUS_15 IOMUX_PAD(0x664, 0x2E0, 6, 0x0, 0, 0) +#define _MX53_PAD_SD1_DATA0__ESDHC1_DAT0 IOMUX_PAD(0x66C, 0x2E4, 0, 0x0, 0, 0) +#define _MX53_PAD_SD1_DATA0__GPIO1_16 IOMUX_PAD(0x66C, 0x2E4, 1, 0x0, 0, 0) +#define _MX53_PAD_SD1_DATA0__GPT_CAPIN1 IOMUX_PAD(0x66C, 0x2E4, 3, 0x0, 0, 0) +#define _MX53_PAD_SD1_DATA0__CSPI_MISO IOMUX_PAD(0x66C, 0x2E4, 5, 0x784, 2, 0) +#define _MX53_PAD_SD1_DATA0__CCM_PLL3_BYP IOMUX_PAD(0x66C, 0x2E4, 7, 0x778, 0, 0) +#define _MX53_PAD_SD1_DATA1__ESDHC1_DAT1 IOMUX_PAD(0x670, 0x2E8, 0, 0x0, 0, 0) +#define _MX53_PAD_SD1_DATA1__GPIO1_17 IOMUX_PAD(0x670, 0x2E8, 1, 0x0, 0, 0) +#define _MX53_PAD_SD1_DATA1__GPT_CAPIN2 IOMUX_PAD(0x670, 0x2E8, 3, 0x0, 0, 0) +#define _MX53_PAD_SD1_DATA1__CSPI_SS0 IOMUX_PAD(0x670, 0x2E8, 5, 0x78C, 3, 0) +#define _MX53_PAD_SD1_DATA1__CCM_PLL4_BYP IOMUX_PAD(0x670, 0x2E8, 7, 0x77C, 1, 0) +#define _MX53_PAD_SD1_CMD__ESDHC1_CMD IOMUX_PAD(0x674, 0x2EC, IOMUX_CONFIG_SION, 0x0, 0, 0) +#define _MX53_PAD_SD1_CMD__GPIO1_18 IOMUX_PAD(0x674, 0x2EC, 1, 0x0, 0, 0) +#define _MX53_PAD_SD1_CMD__GPT_CMPOUT1 IOMUX_PAD(0x674, 0x2EC, 3, 0x0, 0, 0) +#define _MX53_PAD_SD1_CMD__CSPI_MOSI IOMUX_PAD(0x674, 0x2EC, 5, 0x788, 2, 0) +#define _MX53_PAD_SD1_CMD__CCM_PLL1_BYP IOMUX_PAD(0x674, 0x2EC, 7, 0x770, 0, 0) +#define _MX53_PAD_SD1_DATA2__ESDHC1_DAT2 IOMUX_PAD(0x678, 0x2F0, 0, 0x0, 0, 0) +#define _MX53_PAD_SD1_DATA2__GPIO1_19 IOMUX_PAD(0x678, 0x2F0, 1, 0x0, 0, 0) +#define _MX53_PAD_SD1_DATA2__GPT_CMPOUT2 IOMUX_PAD(0x678, 0x2F0, 2, 0x0, 0, 0) +#define _MX53_PAD_SD1_DATA2__PWM2_PWMO IOMUX_PAD(0x678, 0x2F0, 3, 0x0, 0, 0) +#define _MX53_PAD_SD1_DATA2__WDOG1_WDOG_B IOMUX_PAD(0x678, 0x2F0, 4, 0x0, 0, 0) +#define _MX53_PAD_SD1_DATA2__CSPI_SS1 IOMUX_PAD(0x678, 0x2F0, 5, 0x790, 2, 0) +#define _MX53_PAD_SD1_DATA2__WDOG1_WDOG_RST_B_DEB IOMUX_PAD(0x678, 0x2F0, 6, 0x0, 0, 0) +#define _MX53_PAD_SD1_DATA2__CCM_PLL2_BYP IOMUX_PAD(0x678, 0x2F0, 7, 0x774, 0, 0) +#define _MX53_PAD_SD1_CLK__ESDHC1_CLK IOMUX_PAD(0x67C, 0x2F4, 0, 0x0, 0, 0) +#define _MX53_PAD_SD1_CLK__GPIO1_20 IOMUX_PAD(0x67C, 0x2F4, 1, 0x0, 0, 0) +#define _MX53_PAD_SD1_CLK__OSC32k_32K_OUT IOMUX_PAD(0x67C, 0x2F4, 2, 0x0, 0, 0) +#define _MX53_PAD_SD1_CLK__GPT_CLKIN IOMUX_PAD(0x67C, 0x2F4, 3, 0x0, 0, 0) +#define _MX53_PAD_SD1_CLK__CSPI_SCLK IOMUX_PAD(0x67C, 0x2F4, 5, 0x780, 2, 0) +#define _MX53_PAD_SD1_CLK__SATA_PHY_DTB_0 IOMUX_PAD(0x67C, 0x2F4, 7, 0x0, 0, 0) +#define _MX53_PAD_SD1_DATA3__ESDHC1_DAT3 IOMUX_PAD(0x680, 0x2F8, 0, 0x0, 0, 0) +#define _MX53_PAD_SD1_DATA3__GPIO1_21 IOMUX_PAD(0x680, 0x2F8, 1, 0x0, 0, 0) +#define _MX53_PAD_SD1_DATA3__GPT_CMPOUT3 IOMUX_PAD(0x680, 0x2F8, 2, 0x0, 0, 0) +#define _MX53_PAD_SD1_DATA3__PWM1_PWMO IOMUX_PAD(0x680, 0x2F8, 3, 0x0, 0, 0) +#define _MX53_PAD_SD1_DATA3__WDOG2_WDOG_B IOMUX_PAD(0x680, 0x2F8, 4, 0x0, 0, 0) +#define _MX53_PAD_SD1_DATA3__CSPI_SS2 IOMUX_PAD(0x680, 0x2F8, 5, 0x794, 2, 0) +#define _MX53_PAD_SD1_DATA3__WDOG2_WDOG_RST_B_DEB IOMUX_PAD(0x680, 0x2F8, 6, 0x0, 0, 0) +#define _MX53_PAD_SD1_DATA3__SATA_PHY_DTB_1 IOMUX_PAD(0x680, 0x2F8, 7, 0x0, 0, 0) +#define _MX53_PAD_SD2_CLK__ESDHC2_CLK IOMUX_PAD(0x688, 0x2FC, 0, 0x0, 0, 0) +#define _MX53_PAD_SD2_CLK__GPIO1_10 IOMUX_PAD(0x688, 0x2FC, 1, 0x0, 0, 0) +#define _MX53_PAD_SD2_CLK__KPP_COL_5 IOMUX_PAD(0x688, 0x2FC, 2, 0x840, 2, 0) +#define _MX53_PAD_SD2_CLK__AUDMUX_AUD4_RXFS IOMUX_PAD(0x688, 0x2FC, 3, 0x73C, 1, 0) +#define _MX53_PAD_SD2_CLK__CSPI_SCLK IOMUX_PAD(0x688, 0x2FC, 5, 0x780, 3, 0) +#define _MX53_PAD_SD2_CLK__SCC_RANDOM_V IOMUX_PAD(0x688, 0x2FC, 7, 0x0, 0, 0) +#define _MX53_PAD_SD2_CMD__ESDHC2_CMD IOMUX_PAD(0x68C, 0x300, 0, 0x0, 0, 0) +#define _MX53_PAD_SD2_CMD__GPIO1_11 IOMUX_PAD(0x68C, 0x300, 1, 0x0, 0, 0) +#define _MX53_PAD_SD2_CMD__KPP_ROW_5 IOMUX_PAD(0x68C, 0x300, 2, 0x84C, 1, 0) +#define _MX53_PAD_SD2_CMD__AUDMUX_AUD4_RXC IOMUX_PAD(0x68C, 0x300, 3, 0x738, 1, 0) +#define _MX53_PAD_SD2_CMD__CSPI_MOSI IOMUX_PAD(0x68C, 0x300, 5, 0x788, 3, 0) +#define _MX53_PAD_SD2_CMD__SCC_RANDOM IOMUX_PAD(0x68C, 0x300, 7, 0x0, 0, 0) +#define _MX53_PAD_SD2_DATA3__ESDHC2_DAT3 IOMUX_PAD(0x690, 0x304, 0, 0x0, 0, 0) +#define _MX53_PAD_SD2_DATA3__GPIO1_12 IOMUX_PAD(0x690, 0x304, 1, 0x0, 0, 0) +#define _MX53_PAD_SD2_DATA3__KPP_COL_6 IOMUX_PAD(0x690, 0x304, 2, 0x844, 1, 0) +#define _MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC IOMUX_PAD(0x690, 0x304, 3, 0x740, 1, 0) +#define _MX53_PAD_SD2_DATA3__CSPI_SS2 IOMUX_PAD(0x690, 0x304, 5, 0x794, 3, 0) +#define _MX53_PAD_SD2_DATA3__SJC_DONE IOMUX_PAD(0x690, 0x304, 7, 0x0, 0, 0) +#define _MX53_PAD_SD2_DATA2__ESDHC2_DAT2 IOMUX_PAD(0x694, 0x308, 0, 0x0, 0, 0) +#define _MX53_PAD_SD2_DATA2__GPIO1_13 IOMUX_PAD(0x694, 0x308, 1, 0x0, 0, 0) +#define _MX53_PAD_SD2_DATA2__KPP_ROW_6 IOMUX_PAD(0x694, 0x308, 2, 0x850, 1, 0) +#define _MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD IOMUX_PAD(0x694, 0x308, 3, 0x734, 1, 0) +#define _MX53_PAD_SD2_DATA2__CSPI_SS1 IOMUX_PAD(0x694, 0x308, 5, 0x790, 3, 0) +#define _MX53_PAD_SD2_DATA2__SJC_FAIL IOMUX_PAD(0x694, 0x308, 7, 0x0, 0, 0) +#define _MX53_PAD_SD2_DATA1__ESDHC2_DAT1 IOMUX_PAD(0x698, 0x30C, 0, 0x0, 0, 0) +#define _MX53_PAD_SD2_DATA1__GPIO1_14 IOMUX_PAD(0x698, 0x30C, 1, 0x0, 0, 0) +#define _MX53_PAD_SD2_DATA1__KPP_COL_7 IOMUX_PAD(0x698, 0x30C, 2, 0x848, 1, 0) +#define _MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS IOMUX_PAD(0x698, 0x30C, 3, 0x744, 0, 0) +#define _MX53_PAD_SD2_DATA1__CSPI_SS0 IOMUX_PAD(0x698, 0x30C, 5, 0x78C, 4, 0) +#define _MX53_PAD_SD2_DATA1__RTIC_SEC_VIO IOMUX_PAD(0x698, 0x30C, 7, 0x0, 0, 0) +#define _MX53_PAD_SD2_DATA0__ESDHC2_DAT0 IOMUX_PAD(0x69C, 0x310, 0, 0x0, 0, 0) +#define _MX53_PAD_SD2_DATA0__GPIO1_15 IOMUX_PAD(0x69C, 0x310, 1, 0x0, 0, 0) +#define _MX53_PAD_SD2_DATA0__KPP_ROW_7 IOMUX_PAD(0x69C, 0x310, 2, 0x854, 1, 0) +#define _MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD IOMUX_PAD(0x69C, 0x310, 3, 0x730, 1, 0) +#define _MX53_PAD_SD2_DATA0__CSPI_MISO IOMUX_PAD(0x69C, 0x310, 5, 0x784, 3, 0) +#define _MX53_PAD_SD2_DATA0__RTIC_DONE_INT IOMUX_PAD(0x69C, 0x310, 7, 0x0, 0, 0) +#define _MX53_PAD_GPIO_0__CCM_CLKO IOMUX_PAD(0x6A4, 0x314, 0, 0x0, 0, 0) +#define _MX53_PAD_GPIO_0__GPIO1_0 IOMUX_PAD(0x6A4, 0x314, 1, 0x0, 0, 0) +#define _MX53_PAD_GPIO_0__KPP_COL_5 IOMUX_PAD(0x6A4, 0x314, 2, 0x840, 3, 0) +#define _MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK IOMUX_PAD(0x6A4, 0x314, 3, 0x0, 0, 0) +#define _MX53_PAD_GPIO_0__EPIT1_EPITO IOMUX_PAD(0x6A4, 0x314, 4, 0x0, 0, 0) +#define _MX53_PAD_GPIO_0__SRTC_ALARM_DEB IOMUX_PAD(0x6A4, 0x314, 5, 0x0, 0, 0) +#define _MX53_PAD_GPIO_0__USBOH3_USBH1_PWR IOMUX_PAD(0x6A4, 0x314, 6, 0x0, 0, 0) +#define _MX53_PAD_GPIO_0__CSU_TD IOMUX_PAD(0x6A4, 0x314, 7, 0x0, 0, 0) +#define _MX53_PAD_GPIO_1__ESAI1_SCKR IOMUX_PAD(0x6A8, 0x318, 0, 0x7DC, 1, 0) +#define _MX53_PAD_GPIO_1__GPIO1_1 IOMUX_PAD(0x6A8, 0x318, 1, 0x0, 0, 0) +#define _MX53_PAD_GPIO_1__KPP_ROW_5 IOMUX_PAD(0x6A8, 0x318, 2, 0x84C, 2, 0) +#define _MX53_PAD_GPIO_1__CCM_SSI_EXT2_CLK IOMUX_PAD(0x6A8, 0x318, 3, 0x0, 0, 0) +#define _MX53_PAD_GPIO_1__PWM2_PWMO IOMUX_PAD(0x6A8, 0x318, 4, 0x0, 0, 0) +#define _MX53_PAD_GPIO_1__WDOG2_WDOG_B IOMUX_PAD(0x6A8, 0x318, 5, 0x0, 0, 0) +#define _MX53_PAD_GPIO_1__ESDHC1_CD IOMUX_PAD(0x6A8, 0x318, 6, 0x0, 0, 0) +#define _MX53_PAD_GPIO_1__SRC_TESTER_ACK IOMUX_PAD(0x6A8, 0x318, 7, 0x0, 0, 0) +#define _MX53_PAD_GPIO_9__ESAI1_FSR IOMUX_PAD(0x6AC, 0x31C, 0, 0x7CC, 1, 0) +#define _MX53_PAD_GPIO_9__GPIO1_9 IOMUX_PAD(0x6AC, 0x31C, 1, 0x0, 0, 0) +#define _MX53_PAD_GPIO_9__KPP_COL_6 IOMUX_PAD(0x6AC, 0x31C, 2, 0x844, 2, 0) +#define _MX53_PAD_GPIO_9__CCM_REF_EN_B IOMUX_PAD(0x6AC, 0x31C, 3, 0x0, 0, 0) +#define _MX53_PAD_GPIO_9__PWM1_PWMO IOMUX_PAD(0x6AC, 0x31C, 4, 0x0, 0, 0) +#define _MX53_PAD_GPIO_9__WDOG1_WDOG_B IOMUX_PAD(0x6AC, 0x31C, 5, 0x0, 0, 0) +#define _MX53_PAD_GPIO_9__ESDHC1_WP IOMUX_PAD(0x6AC, 0x31C, 6, 0x7FC, 1, 0) +#define _MX53_PAD_GPIO_9__SCC_FAIL_STATE IOMUX_PAD(0x6AC, 0x31C, 7, 0x0, 0, 0) +#define _MX53_PAD_GPIO_3__ESAI1_HCKR IOMUX_PAD(0x6B0, 0x320, 0, 0x7D4, 1, 0) +#define _MX53_PAD_GPIO_3__GPIO1_3 IOMUX_PAD(0x6B0, 0x320, 1, 0x0, 0, 0) +#define _MX53_PAD_GPIO_3__I2C3_SCL IOMUX_PAD(0x6B0, 0x320, 2 | IOMUX_CONFIG_SION, 0x824, 1, 0) +#define _MX53_PAD_GPIO_3__DPLLIP1_TOG_EN IOMUX_PAD(0x6B0, 0x320, 3, 0x0, 0, 0) +#define _MX53_PAD_GPIO_3__CCM_CLKO2 IOMUX_PAD(0x6B0, 0x320, 4, 0x0, 0, 0) +#define _MX53_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 IOMUX_PAD(0x6B0, 0x320, 5, 0x0, 0, 0) +#define _MX53_PAD_GPIO_3__USBOH3_USBH1_OC IOMUX_PAD(0x6B0, 0x320, 6, 0x8A0, 1, 0) +#define _MX53_PAD_GPIO_3__MLB_MLBCLK IOMUX_PAD(0x6B0, 0x320, 7, 0x858, 2, 0) +#define _MX53_PAD_GPIO_6__ESAI1_SCKT IOMUX_PAD(0x6B4, 0x324, 0, 0x7E0, 1, 0) +#define _MX53_PAD_GPIO_6__GPIO1_6 IOMUX_PAD(0x6B4, 0x324, 1, 0x0, 0, 0) +#define _MX53_PAD_GPIO_6__I2C3_SDA IOMUX_PAD(0x6B4, 0x324, 2 | IOMUX_CONFIG_SION, 0x828, 1, 0) +#define _MX53_PAD_GPIO_6__CCM_CCM_OUT_0 IOMUX_PAD(0x6B4, 0x324, 3, 0x0, 0, 0) +#define _MX53_PAD_GPIO_6__CSU_CSU_INT_DEB IOMUX_PAD(0x6B4, 0x324, 4, 0x0, 0, 0) +#define _MX53_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 IOMUX_PAD(0x6B4, 0x324, 5, 0x0, 0, 0) +#define _MX53_PAD_GPIO_6__ESDHC2_LCTL IOMUX_PAD(0x6B4, 0x324, 6, 0x0, 0, 0) +#define _MX53_PAD_GPIO_6__MLB_MLBSIG IOMUX_PAD(0x6B4, 0x324, 7, 0x860, 2, 0) +#define _MX53_PAD_GPIO_2__ESAI1_FST IOMUX_PAD(0x6B8, 0x328, 0, 0x7D0, 1, 0) +#define _MX53_PAD_GPIO_2__GPIO1_2 IOMUX_PAD(0x6B8, 0x328, 1, 0x0, 0, 0) +#define _MX53_PAD_GPIO_2__KPP_ROW_6 IOMUX_PAD(0x6B8, 0x328, 2, 0x850, 2, 0) +#define _MX53_PAD_GPIO_2__CCM_CCM_OUT_1 IOMUX_PAD(0x6B8, 0x328, 3, 0x0, 0, 0) +#define _MX53_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 IOMUX_PAD(0x6B8, 0x328, 4, 0x0, 0, 0) +#define _MX53_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 IOMUX_PAD(0x6B8, 0x328, 5, 0x0, 0, 0) +#define _MX53_PAD_GPIO_2__ESDHC2_WP IOMUX_PAD(0x6B8, 0x328, 6, 0x0, 0, 0) +#define _MX53_PAD_GPIO_2__MLB_MLBDAT IOMUX_PAD(0x6B8, 0x328, 7, 0x85C, 2, 0) +#define _MX53_PAD_GPIO_4__ESAI1_HCKT IOMUX_PAD(0x6BC, 0x32C, 0, 0x7D8, 1, 0) +#define _MX53_PAD_GPIO_4__GPIO1_4 IOMUX_PAD(0x6BC, 0x32C, 1, 0x0, 0, 0) +#define _MX53_PAD_GPIO_4__KPP_COL_7 IOMUX_PAD(0x6BC, 0x32C, 2, 0x848, 2, 0) +#define _MX53_PAD_GPIO_4__CCM_CCM_OUT_2 IOMUX_PAD(0x6BC, 0x32C, 3, 0x0, 0, 0) +#define _MX53_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 IOMUX_PAD(0x6BC, 0x32C, 4, 0x0, 0, 0) +#define _MX53_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 IOMUX_PAD(0x6BC, 0x32C, 5, 0x0, 0, 0) +#define _MX53_PAD_GPIO_4__ESDHC2_CD IOMUX_PAD(0x6BC, 0x32C, 6, 0x0, 0, 0) +#define _MX53_PAD_GPIO_4__SCC_SEC_STATE IOMUX_PAD(0x6BC, 0x32C, 7, 0x0, 0, 0) +#define _MX53_PAD_GPIO_5__ESAI1_TX2_RX3 IOMUX_PAD(0x6C0, 0x330, 0, 0x7EC, 1, 0) +#define _MX53_PAD_GPIO_5__GPIO1_5 IOMUX_PAD(0x6C0, 0x330, 1, 0x0, 0, 0) +#define _MX53_PAD_GPIO_5__KPP_ROW_7 IOMUX_PAD(0x6C0, 0x330, 2, 0x854, 2, 0) +#define _MX53_PAD_GPIO_5__CCM_CLKO IOMUX_PAD(0x6C0, 0x330, 3, 0x0, 0, 0) +#define _MX53_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 IOMUX_PAD(0x6C0, 0x330, 4, 0x0, 0, 0) +#define _MX53_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 IOMUX_PAD(0x6C0, 0x330, 5, 0x0, 0, 0) +#define _MX53_PAD_GPIO_5__I2C3_SCL IOMUX_PAD(0x6C0, 0x330, 6, 0x824, 2, 0) +#define _MX53_PAD_GPIO_5__CCM_PLL1_BYP IOMUX_PAD(0x6C0, 0x330, 7, 0x770, 1, 0) +#define _MX53_PAD_GPIO_7__ESAI1_TX4_RX1 IOMUX_PAD(0x6C4, 0x334, 0, 0x7F4, 1, 0) +#define _MX53_PAD_GPIO_7__GPIO1_7 IOMUX_PAD(0x6C4, 0x334, 1, 0x0, 0, 0) +#define _MX53_PAD_GPIO_7__EPIT1_EPITO IOMUX_PAD(0x6C4, 0x334, 2, 0x0, 0, 0) +#define _MX53_PAD_GPIO_7__CAN1_TXCAN IOMUX_PAD(0x6C4, 0x334, 3, 0x0, 0, 0) +#define _MX53_PAD_GPIO_7__UART2_TXD_MUX IOMUX_PAD(0x6C4, 0x334, 4, 0x880, 4, 0) +#define _MX53_PAD_GPIO_7__FIRI_RXD IOMUX_PAD(0x6C4, 0x334, 5, 0x80C, 1, 0) +#define _MX53_PAD_GPIO_7__SPDIF_PLOCK IOMUX_PAD(0x6C4, 0x334, 6, 0x0, 0, 0) +#define _MX53_PAD_GPIO_7__CCM_PLL2_BYP IOMUX_PAD(0x6C4, 0x334, 7, 0x774, 1, 0) +#define _MX53_PAD_GPIO_8__ESAI1_TX5_RX0 IOMUX_PAD(0x6C8, 0x338, 0, 0x7F8, 1, 0) +#define _MX53_PAD_GPIO_8__GPIO1_8 IOMUX_PAD(0x6C8, 0x338, 1, 0x0, 0, 0) +#define _MX53_PAD_GPIO_8__EPIT2_EPITO IOMUX_PAD(0x6C8, 0x338, 2, 0x0, 0, 0) +#define _MX53_PAD_GPIO_8__CAN1_RXCAN IOMUX_PAD(0x6C8, 0x338, 3, 0x760, 3, 0) +#define _MX53_PAD_GPIO_8__UART2_RXD_MUX IOMUX_PAD(0x6C8, 0x338, 4, 0x880, 5, 0) +#define _MX53_PAD_GPIO_8__FIRI_TXD IOMUX_PAD(0x6C8, 0x338, 5, 0x0, 0, 0) +#define _MX53_PAD_GPIO_8__SPDIF_SRCLK IOMUX_PAD(0x6C8, 0x338, 6, 0x0, 0, 0) +#define _MX53_PAD_GPIO_8__CCM_PLL3_BYP IOMUX_PAD(0x6C8, 0x338, 7, 0x778, 1, 0) +#define _MX53_PAD_GPIO_16__ESAI1_TX3_RX2 IOMUX_PAD(0x6CC, 0x33C, 0, 0x7F0, 1, 0) +#define _MX53_PAD_GPIO_16__GPIO7_11 IOMUX_PAD(0x6CC, 0x33C, 1, 0x0, 0, 0) +#define _MX53_PAD_GPIO_16__TZIC_PWRFAIL_INT IOMUX_PAD(0x6CC, 0x33C, 2, 0x0, 0, 0) +#define _MX53_PAD_GPIO_16__RTC_CE_RTC_EXT_TRIG1 IOMUX_PAD(0x6CC, 0x33C, 4, 0x0, 0, 0) +#define _MX53_PAD_GPIO_16__SPDIF_IN1 IOMUX_PAD(0x6CC, 0x33C, 5, 0x870, 1, 0) +#define _MX53_PAD_GPIO_16__I2C3_SDA IOMUX_PAD(0x6CC, 0x33C, 6 | IOMUX_CONFIG_SION, 0x828, 2, 0) +#define _MX53_PAD_GPIO_16__SJC_DE_B IOMUX_PAD(0x6CC, 0x33C, 7, 0x0, 0, 0) +#define _MX53_PAD_GPIO_17__ESAI1_TX0 IOMUX_PAD(0x6D0, 0x340, 0, 0x7E4, 1, 0) +#define _MX53_PAD_GPIO_17__GPIO7_12 IOMUX_PAD(0x6D0, 0x340, 1, 0x0, 0, 0) +#define _MX53_PAD_GPIO_17__SDMA_EXT_EVENT_0 IOMUX_PAD(0x6D0, 0x340, 2, 0x868, 1, 0) +#define _MX53_PAD_GPIO_17__GPC_PMIC_RDY IOMUX_PAD(0x6D0, 0x340, 3, 0x810, 1, 0) +#define _MX53_PAD_GPIO_17__RTC_CE_RTC_FSV_TRIG IOMUX_PAD(0x6D0, 0x340, 4, 0x0, 0, 0) +#define _MX53_PAD_GPIO_17__SPDIF_OUT1 IOMUX_PAD(0x6D0, 0x340, 5, 0x0, 0, 0) +#define _MX53_PAD_GPIO_17__IPU_SNOOP2 IOMUX_PAD(0x6D0, 0x340, 6, 0x0, 0, 0) +#define _MX53_PAD_GPIO_17__SJC_JTAG_ACT IOMUX_PAD(0x6D0, 0x340, 7, 0x0, 0, 0) +#define _MX53_PAD_GPIO_18__ESAI1_TX1 IOMUX_PAD(0x6D4, 0x344, 0, 0x7E8, 1, 0) +#define _MX53_PAD_GPIO_18__GPIO7_13 IOMUX_PAD(0x6D4, 0x344, 1, 0x0, 0, 0) +#define _MX53_PAD_GPIO_18__SDMA_EXT_EVENT_1 IOMUX_PAD(0x6D4, 0x344, 2, 0x86C, 1, 0) +#define _MX53_PAD_GPIO_18__OWIRE_LINE IOMUX_PAD(0x6D4, 0x344, 3, 0x864, 1, 0) +#define _MX53_PAD_GPIO_18__RTC_CE_RTC_ALARM2_TRIG IOMUX_PAD(0x6D4, 0x344, 4, 0x0, 0, 0) +#define _MX53_PAD_GPIO_18__CCM_ASRC_EXT_CLK IOMUX_PAD(0x6D4, 0x344, 5, 0x768, 1, 0) +#define _MX53_PAD_GPIO_18__ESDHC1_LCTL IOMUX_PAD(0x6D4, 0x344, 6, 0x0, 0, 0) +#define _MX53_PAD_GPIO_18__SRC_SYSTEM_RST IOMUX_PAD(0x6D4, 0x344, 7, 0x0, 0, 0) + +#define MX53_PAD_GPIO_19__KPP_COL_5 (_MX53_PAD_GPIO_19__KPP_COL_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_19__GPIO4_5 (_MX53_PAD_GPIO_19__GPIO4_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_19__CCM_CLKO (_MX53_PAD_GPIO_19__CCM_CLKO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_19__SPDIF_OUT1 (_MX53_PAD_GPIO_19__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 (_MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_19__ECSPI1_RDY (_MX53_PAD_GPIO_19__ECSPI1_RDY | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_19__FEC_TDATA_3 (_MX53_PAD_GPIO_19__FEC_TDATA_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_19__SRC_INT_BOOT (_MX53_PAD_GPIO_19__SRC_INT_BOOT | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_COL0__KPP_COL_0 (_MX53_PAD_KEY_COL0__KPP_COL_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_COL0__GPIO4_6 (_MX53_PAD_KEY_COL0__GPIO4_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC (_MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_COL0__UART4_TXD_MUX (_MX53_PAD_KEY_COL0__UART4_TXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_COL0__ECSPI1_SCLK (_MX53_PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_COL0__FEC_RDATA_3 (_MX53_PAD_KEY_COL0__FEC_RDATA_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_COL0__SRC_ANY_PU_RST (_MX53_PAD_KEY_COL0__SRC_ANY_PU_RST | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_ROW0__KPP_ROW_0 (_MX53_PAD_KEY_ROW0__KPP_ROW_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_ROW0__GPIO4_7 (_MX53_PAD_KEY_ROW0__GPIO4_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD (_MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_ROW0__UART4_RXD_MUX (_MX53_PAD_KEY_ROW0__UART4_RXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_ROW0__ECSPI1_MOSI (_MX53_PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_ROW0__FEC_TX_ER (_MX53_PAD_KEY_ROW0__FEC_TX_ER | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_COL1__KPP_COL_1 (_MX53_PAD_KEY_COL1__KPP_COL_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_COL1__GPIO4_8 (_MX53_PAD_KEY_COL1__GPIO4_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS (_MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_COL1__UART5_TXD_MUX (_MX53_PAD_KEY_COL1__UART5_TXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_COL1__ECSPI1_MISO (_MX53_PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_COL1__FEC_RX_CLK (_MX53_PAD_KEY_COL1__FEC_RX_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_COL1__USBPHY1_TXREADY (_MX53_PAD_KEY_COL1__USBPHY1_TXREADY | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_ROW1__KPP_ROW_1 (_MX53_PAD_KEY_ROW1__KPP_ROW_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_ROW1__GPIO4_9 (_MX53_PAD_KEY_ROW1__GPIO4_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD (_MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_ROW1__UART5_RXD_MUX (_MX53_PAD_KEY_ROW1__UART5_RXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_ROW1__ECSPI1_SS0 (_MX53_PAD_KEY_ROW1__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_ROW1__FEC_COL (_MX53_PAD_KEY_ROW1__FEC_COL | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_ROW1__USBPHY1_RXVALID (_MX53_PAD_KEY_ROW1__USBPHY1_RXVALID | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_COL2__KPP_COL_2 (_MX53_PAD_KEY_COL2__KPP_COL_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_COL2__GPIO4_10 (_MX53_PAD_KEY_COL2__GPIO4_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_COL2__CAN1_TXCAN (_MX53_PAD_KEY_COL2__CAN1_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_COL2__FEC_MDIO (_MX53_PAD_KEY_COL2__FEC_MDIO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_COL2__ECSPI1_SS1 (_MX53_PAD_KEY_COL2__ECSPI1_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_COL2__FEC_RDATA_2 (_MX53_PAD_KEY_COL2__FEC_RDATA_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_COL2__USBPHY1_RXACTIVE (_MX53_PAD_KEY_COL2__USBPHY1_RXACTIVE | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_ROW2__KPP_ROW_2 (_MX53_PAD_KEY_ROW2__KPP_ROW_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_ROW2__GPIO4_11 (_MX53_PAD_KEY_ROW2__GPIO4_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_ROW2__CAN1_RXCAN (_MX53_PAD_KEY_ROW2__CAN1_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_ROW2__FEC_MDC (_MX53_PAD_KEY_ROW2__FEC_MDC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_ROW2__ECSPI1_SS2 (_MX53_PAD_KEY_ROW2__ECSPI1_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_ROW2__FEC_TDATA_2 (_MX53_PAD_KEY_ROW2__FEC_TDATA_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_ROW2__USBPHY1_RXERROR (_MX53_PAD_KEY_ROW2__USBPHY1_RXERROR | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_COL3__KPP_COL_3 (_MX53_PAD_KEY_COL3__KPP_COL_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_COL3__GPIO4_12 (_MX53_PAD_KEY_COL3__GPIO4_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_COL3__USBOH3_H2_DP (_MX53_PAD_KEY_COL3__USBOH3_H2_DP | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_COL3__SPDIF_IN1 (_MX53_PAD_KEY_COL3__SPDIF_IN1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_COL3__I2C2_SCL (_MX53_PAD_KEY_COL3__I2C2_SCL | MUX_PAD_CTRL(PAD_CTRL_I2C)) +#define MX53_PAD_KEY_COL3__ECSPI1_SS3 (_MX53_PAD_KEY_COL3__ECSPI1_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_COL3__FEC_CRS (_MX53_PAD_KEY_COL3__FEC_CRS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_COL3__USBPHY1_SIECLOCK (_MX53_PAD_KEY_COL3__USBPHY1_SIECLOCK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_ROW3__KPP_ROW_3 (_MX53_PAD_KEY_ROW3__KPP_ROW_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_ROW3__GPIO4_13 (_MX53_PAD_KEY_ROW3__GPIO4_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_ROW3__USBOH3_H2_DM (_MX53_PAD_KEY_ROW3__USBOH3_H2_DM | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK (_MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_ROW3__I2C2_SDA (_MX53_PAD_KEY_ROW3__I2C2_SDA | MUX_PAD_CTRL(PAD_CTRL_I2C)) +#define MX53_PAD_KEY_ROW3__OSC32K_32K_OUT (_MX53_PAD_KEY_ROW3__OSC32K_32K_OUT | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_ROW3__CCM_PLL4_BYP (_MX53_PAD_KEY_ROW3__CCM_PLL4_BYP | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_ROW3__USBPHY1_LINESTATE_0 (_MX53_PAD_KEY_ROW3__USBPHY1_LINESTATE_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_COL4__KPP_COL_4 (_MX53_PAD_KEY_COL4__KPP_COL_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_COL4__GPIO4_14 (_MX53_PAD_KEY_COL4__GPIO4_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_COL4__CAN2_TXCAN (_MX53_PAD_KEY_COL4__CAN2_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_COL4__IPU_SISG_4 (_MX53_PAD_KEY_COL4__IPU_SISG_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_COL4__UART5_RTS (_MX53_PAD_KEY_COL4__UART5_RTS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC (_MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_COL4__USBPHY1_LINESTATE_1 (_MX53_PAD_KEY_COL4__USBPHY1_LINESTATE_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_ROW4__KPP_ROW_4 (_MX53_PAD_KEY_ROW4__KPP_ROW_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_ROW4__GPIO4_15 (_MX53_PAD_KEY_ROW4__GPIO4_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_ROW4__CAN2_RXCAN (_MX53_PAD_KEY_ROW4__CAN2_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_ROW4__IPU_SISG_5 (_MX53_PAD_KEY_ROW4__IPU_SISG_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_ROW4__UART5_CTS (_MX53_PAD_KEY_ROW4__UART5_CTS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_ROW4__USBOH3_USBOTG_PWR (_MX53_PAD_KEY_ROW4__USBOH3_USBOTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_KEY_ROW4__USBPHY1_VBUSVALID (_MX53_PAD_KEY_ROW4__USBPHY1_VBUSVALID | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK (_MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DI0_DISP_CLK__GPIO4_16 (_MX53_PAD_DI0_DISP_CLK__GPIO4_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR (_MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 (_MX53_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DI0_DISP_CLK__EMI_EMI_DEBUG_0 (_MX53_PAD_DI0_DISP_CLK__EMI_EMI_DEBUG_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DI0_DISP_CLK__USBPHY1_AVALID (_MX53_PAD_DI0_DISP_CLK__USBPHY1_AVALID | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 (_MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DI0_PIN15__GPIO4_17 (_MX53_PAD_DI0_PIN15__GPIO4_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC (_MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 (_MX53_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DI0_PIN15__EMI_EMI_DEBUG_1 (_MX53_PAD_DI0_PIN15__EMI_EMI_DEBUG_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DI0_PIN15__USBPHY1_BVALID (_MX53_PAD_DI0_PIN15__USBPHY1_BVALID | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 (_MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DI0_PIN2__GPIO4_18 (_MX53_PAD_DI0_PIN2__GPIO4_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD (_MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 (_MX53_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DI0_PIN2__EMI_EMI_DEBUG_2 (_MX53_PAD_DI0_PIN2__EMI_EMI_DEBUG_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DI0_PIN2__USBPHY1_ENDSESSION (_MX53_PAD_DI0_PIN2__USBPHY1_ENDSESSION | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 (_MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DI0_PIN3__GPIO4_19 (_MX53_PAD_DI0_PIN3__GPIO4_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS (_MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 (_MX53_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DI0_PIN3__EMI_EMI_DEBUG_3 (_MX53_PAD_DI0_PIN3__EMI_EMI_DEBUG_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DI0_PIN3__USBPHY1_IDDIG (_MX53_PAD_DI0_PIN3__USBPHY1_IDDIG | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DI0_PIN4__IPU_DI0_PIN4 (_MX53_PAD_DI0_PIN4__IPU_DI0_PIN4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DI0_PIN4__GPIO4_20 (_MX53_PAD_DI0_PIN4__GPIO4_20 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD (_MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DI0_PIN4__ESDHC1_WP (_MX53_PAD_DI0_PIN4__ESDHC1_WP | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DI0_PIN4__SDMA_DEBUG_YIELD (_MX53_PAD_DI0_PIN4__SDMA_DEBUG_YIELD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DI0_PIN4__EMI_EMI_DEBUG_4 (_MX53_PAD_DI0_PIN4__EMI_EMI_DEBUG_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DI0_PIN4__USBPHY1_HOSTDISCONNECT (_MX53_PAD_DI0_PIN4__USBPHY1_HOSTDISCONNECT | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 (_MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT0__GPIO4_21 (_MX53_PAD_DISP0_DAT0__GPIO4_21 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT0__CSPI_SCLK (_MX53_PAD_DISP0_DAT0__CSPI_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0 (_MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN (_MX53_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT0__EMI_EMI_DEBUG_5 (_MX53_PAD_DISP0_DAT0__EMI_EMI_DEBUG_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT0__USBPHY2_TXREADY (_MX53_PAD_DISP0_DAT0__USBPHY2_TXREADY | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 (_MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT1__GPIO4_22 (_MX53_PAD_DISP0_DAT1__GPIO4_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT1__CSPI_MOSI (_MX53_PAD_DISP0_DAT1__CSPI_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1 (_MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL (_MX53_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT1__EMI_EMI_DEBUG_6 (_MX53_PAD_DISP0_DAT1__EMI_EMI_DEBUG_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT1__USBPHY2_RXVALID (_MX53_PAD_DISP0_DAT1__USBPHY2_RXVALID | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 (_MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT2__GPIO4_23 (_MX53_PAD_DISP0_DAT2__GPIO4_23 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT2__CSPI_MISO (_MX53_PAD_DISP0_DAT2__CSPI_MISO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2 (_MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT2__SDMA_DEBUG_MODE (_MX53_PAD_DISP0_DAT2__SDMA_DEBUG_MODE | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT2__EMI_EMI_DEBUG_7 (_MX53_PAD_DISP0_DAT2__EMI_EMI_DEBUG_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT2__USBPHY2_RXACTIVE (_MX53_PAD_DISP0_DAT2__USBPHY2_RXACTIVE | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 (_MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT3__GPIO4_24 (_MX53_PAD_DISP0_DAT3__GPIO4_24 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT3__CSPI_SS0 (_MX53_PAD_DISP0_DAT3__CSPI_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3 (_MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR (_MX53_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT3__EMI_EMI_DEBUG_8 (_MX53_PAD_DISP0_DAT3__EMI_EMI_DEBUG_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT3__USBPHY2_RXERROR (_MX53_PAD_DISP0_DAT3__USBPHY2_RXERROR | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 (_MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT4__GPIO4_25 (_MX53_PAD_DISP0_DAT4__GPIO4_25 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT4__CSPI_SS1 (_MX53_PAD_DISP0_DAT4__CSPI_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4 (_MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB (_MX53_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT4__EMI_EMI_DEBUG_9 (_MX53_PAD_DISP0_DAT4__EMI_EMI_DEBUG_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT4__USBPHY2_SIECLOCK (_MX53_PAD_DISP0_DAT4__USBPHY2_SIECLOCK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 (_MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT5__GPIO4_26 (_MX53_PAD_DISP0_DAT5__GPIO4_26 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT5__CSPI_SS2 (_MX53_PAD_DISP0_DAT5__CSPI_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5 (_MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS (_MX53_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT5__EMI_EMI_DEBUG_10 (_MX53_PAD_DISP0_DAT5__EMI_EMI_DEBUG_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT5__USBPHY2_LINESTATE_0 (_MX53_PAD_DISP0_DAT5__USBPHY2_LINESTATE_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 (_MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT6__GPIO4_27 (_MX53_PAD_DISP0_DAT6__GPIO4_27 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT6__CSPI_SS3 (_MX53_PAD_DISP0_DAT6__CSPI_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6 (_MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE (_MX53_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT6__EMI_EMI_DEBUG_11 (_MX53_PAD_DISP0_DAT6__EMI_EMI_DEBUG_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT6__USBPHY2_LINESTATE_1 (_MX53_PAD_DISP0_DAT6__USBPHY2_LINESTATE_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 (_MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT7__GPIO4_28 (_MX53_PAD_DISP0_DAT7__GPIO4_28 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT7__CSPI_RDY (_MX53_PAD_DISP0_DAT7__CSPI_RDY | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7 (_MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 (_MX53_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT7__EMI_EMI_DEBUG_12 (_MX53_PAD_DISP0_DAT7__EMI_EMI_DEBUG_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT7__USBPHY2_VBUSVALID (_MX53_PAD_DISP0_DAT7__USBPHY2_VBUSVALID | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 (_MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT8__GPIO4_29 (_MX53_PAD_DISP0_DAT8__GPIO4_29 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT8__PWM1_PWMO (_MX53_PAD_DISP0_DAT8__PWM1_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT8__WDOG1_WDOG_B (_MX53_PAD_DISP0_DAT8__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 (_MX53_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT8__EMI_EMI_DEBUG_13 (_MX53_PAD_DISP0_DAT8__EMI_EMI_DEBUG_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT8__USBPHY2_AVALID (_MX53_PAD_DISP0_DAT8__USBPHY2_AVALID | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 (_MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT9__GPIO4_30 (_MX53_PAD_DISP0_DAT9__GPIO4_30 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT9__PWM2_PWMO (_MX53_PAD_DISP0_DAT9__PWM2_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT9__WDOG2_WDOG_B (_MX53_PAD_DISP0_DAT9__WDOG2_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 (_MX53_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT9__EMI_EMI_DEBUG_14 (_MX53_PAD_DISP0_DAT9__EMI_EMI_DEBUG_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT9__USBPHY2_VSTATUS_0 (_MX53_PAD_DISP0_DAT9__USBPHY2_VSTATUS_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 (_MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT10__GPIO4_31 (_MX53_PAD_DISP0_DAT10__GPIO4_31 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP (_MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 (_MX53_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT10__EMI_EMI_DEBUG_15 (_MX53_PAD_DISP0_DAT10__EMI_EMI_DEBUG_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT10__USBPHY2_VSTATUS_1 (_MX53_PAD_DISP0_DAT10__USBPHY2_VSTATUS_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 (_MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT11__GPIO5_5 (_MX53_PAD_DISP0_DAT11__GPIO5_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT (_MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 (_MX53_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT11__EMI_EMI_DEBUG_16 (_MX53_PAD_DISP0_DAT11__EMI_EMI_DEBUG_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT11__USBPHY2_VSTATUS_2 (_MX53_PAD_DISP0_DAT11__USBPHY2_VSTATUS_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 (_MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT12__GPIO5_6 (_MX53_PAD_DISP0_DAT12__GPIO5_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK (_MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 (_MX53_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT12__EMI_EMI_DEBUG_17 (_MX53_PAD_DISP0_DAT12__EMI_EMI_DEBUG_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT12__USBPHY2_VSTATUS_3 (_MX53_PAD_DISP0_DAT12__USBPHY2_VSTATUS_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 (_MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT13__GPIO5_7 (_MX53_PAD_DISP0_DAT13__GPIO5_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS (_MX53_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 (_MX53_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT13__EMI_EMI_DEBUG_18 (_MX53_PAD_DISP0_DAT13__EMI_EMI_DEBUG_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT13__USBPHY2_VSTATUS_4 (_MX53_PAD_DISP0_DAT13__USBPHY2_VSTATUS_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 (_MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT14__GPIO5_8 (_MX53_PAD_DISP0_DAT14__GPIO5_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC (_MX53_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 (_MX53_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT14__EMI_EMI_DEBUG_19 (_MX53_PAD_DISP0_DAT14__EMI_EMI_DEBUG_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT14__USBPHY2_VSTATUS_5 (_MX53_PAD_DISP0_DAT14__USBPHY2_VSTATUS_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 (_MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT15__GPIO5_9 (_MX53_PAD_DISP0_DAT15__GPIO5_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT15__ECSPI1_SS1 (_MX53_PAD_DISP0_DAT15__ECSPI1_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT15__ECSPI2_SS1 (_MX53_PAD_DISP0_DAT15__ECSPI2_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 (_MX53_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT15__EMI_EMI_DEBUG_20 (_MX53_PAD_DISP0_DAT15__EMI_EMI_DEBUG_20 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT15__USBPHY2_VSTATUS_6 (_MX53_PAD_DISP0_DAT15__USBPHY2_VSTATUS_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 (_MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT16__GPIO5_10 (_MX53_PAD_DISP0_DAT16__GPIO5_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT16__ECSPI2_MOSI (_MX53_PAD_DISP0_DAT16__ECSPI2_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC (_MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 (_MX53_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT16__SDMA_DEBUG_EVT_CHN_LINES_3 (_MX53_PAD_DISP0_DAT16__SDMA_DEBUG_EVT_CHN_LINES_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT16__EMI_EMI_DEBUG_21 (_MX53_PAD_DISP0_DAT16__EMI_EMI_DEBUG_21 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT16__USBPHY2_VSTATUS_7 (_MX53_PAD_DISP0_DAT16__USBPHY2_VSTATUS_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 (_MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT17__GPIO5_11 (_MX53_PAD_DISP0_DAT17__GPIO5_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT17__ECSPI2_MISO (_MX53_PAD_DISP0_DAT17__ECSPI2_MISO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD (_MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 (_MX53_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT17__SDMA_DEBUG_EVT_CHN_LINES_4 (_MX53_PAD_DISP0_DAT17__SDMA_DEBUG_EVT_CHN_LINES_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT17__EMI_EMI_DEBUG_22 (_MX53_PAD_DISP0_DAT17__EMI_EMI_DEBUG_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 (_MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT18__GPIO5_12 (_MX53_PAD_DISP0_DAT18__GPIO5_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT18__ECSPI2_SS0 (_MX53_PAD_DISP0_DAT18__ECSPI2_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS (_MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS (_MX53_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT18__SDMA_DEBUG_EVT_CHN_LINES_5 (_MX53_PAD_DISP0_DAT18__SDMA_DEBUG_EVT_CHN_LINES_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT18__EMI_EMI_DEBUG_23 (_MX53_PAD_DISP0_DAT18__EMI_EMI_DEBUG_23 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT18__EMI_WEIM_CS_2 (_MX53_PAD_DISP0_DAT18__EMI_WEIM_CS_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 (_MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT19__GPIO5_13 (_MX53_PAD_DISP0_DAT19__GPIO5_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT19__ECSPI2_SCLK (_MX53_PAD_DISP0_DAT19__ECSPI2_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD (_MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC (_MX53_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT19__SDMA_DEBUG_EVT_CHN_LINES_6 (_MX53_PAD_DISP0_DAT19__SDMA_DEBUG_EVT_CHN_LINES_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT19__EMI_EMI_DEBUG_24 (_MX53_PAD_DISP0_DAT19__EMI_EMI_DEBUG_24 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT19__EMI_WEIM_CS_3 (_MX53_PAD_DISP0_DAT19__EMI_WEIM_CS_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 (_MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT20__GPIO5_14 (_MX53_PAD_DISP0_DAT20__GPIO5_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT20__ECSPI1_SCLK (_MX53_PAD_DISP0_DAT20__ECSPI1_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC (_MX53_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 (_MX53_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT20__EMI_EMI_DEBUG_25 (_MX53_PAD_DISP0_DAT20__EMI_EMI_DEBUG_25 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT20__SATA_PHY_TDI (_MX53_PAD_DISP0_DAT20__SATA_PHY_TDI | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 (_MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT21__GPIO5_15 (_MX53_PAD_DISP0_DAT21__GPIO5_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT21__ECSPI1_MOSI (_MX53_PAD_DISP0_DAT21__ECSPI1_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD (_MX53_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 (_MX53_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT21__EMI_EMI_DEBUG_26 (_MX53_PAD_DISP0_DAT21__EMI_EMI_DEBUG_26 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT21__SATA_PHY_TDO (_MX53_PAD_DISP0_DAT21__SATA_PHY_TDO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 (_MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT22__GPIO5_16 (_MX53_PAD_DISP0_DAT22__GPIO5_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT22__ECSPI1_MISO (_MX53_PAD_DISP0_DAT22__ECSPI1_MISO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS (_MX53_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 (_MX53_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT22__EMI_EMI_DEBUG_27 (_MX53_PAD_DISP0_DAT22__EMI_EMI_DEBUG_27 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT22__SATA_PHY_TCK (_MX53_PAD_DISP0_DAT22__SATA_PHY_TCK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 (_MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT23__GPIO5_17 (_MX53_PAD_DISP0_DAT23__GPIO5_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT23__ECSPI1_SS0 (_MX53_PAD_DISP0_DAT23__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD (_MX53_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 (_MX53_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT23__EMI_EMI_DEBUG_28 (_MX53_PAD_DISP0_DAT23__EMI_EMI_DEBUG_28 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_DISP0_DAT23__SATA_PHY_TMS (_MX53_PAD_DISP0_DAT23__SATA_PHY_TMS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK (_MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_PIXCLK__GPIO5_18 (_MX53_PAD_CSI0_PIXCLK__GPIO5_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 (_MX53_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_PIXCLK__EMI_EMI_DEBUG_29 (_MX53_PAD_CSI0_PIXCLK__EMI_EMI_DEBUG_29 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC (_MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_MCLK__GPIO5_19 (_MX53_PAD_CSI0_MCLK__GPIO5_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK (_MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 (_MX53_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_MCLK__EMI_EMI_DEBUG_30 (_MX53_PAD_CSI0_MCLK__EMI_EMI_DEBUG_30 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_MCLK__TPIU_TRCTL (_MX53_PAD_CSI0_MCLK__TPIU_TRCTL | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN (_MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DATA_EN__GPIO5_20 (_MX53_PAD_CSI0_DATA_EN__GPIO5_20 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 (_MX53_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DATA_EN__EMI_EMI_DEBUG_31 (_MX53_PAD_CSI0_DATA_EN__EMI_EMI_DEBUG_31 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DATA_EN__TPIU_TRCLK (_MX53_PAD_CSI0_DATA_EN__TPIU_TRCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC (_MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_VSYNC__GPIO5_21 (_MX53_PAD_CSI0_VSYNC__GPIO5_21 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 (_MX53_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_VSYNC__EMI_EMI_DEBUG_32 (_MX53_PAD_CSI0_VSYNC__EMI_EMI_DEBUG_32 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_VSYNC__TPIU_TRACE_0 (_MX53_PAD_CSI0_VSYNC__TPIU_TRACE_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 (_MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT4__GPIO5_22 (_MX53_PAD_CSI0_DAT4__GPIO5_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT4__KPP_COL_5 (_MX53_PAD_CSI0_DAT4__KPP_COL_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT4__ECSPI1_SCLK (_MX53_PAD_CSI0_DAT4__ECSPI1_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP (_MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC (_MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT4__EMI_EMI_DEBUG_33 (_MX53_PAD_CSI0_DAT4__EMI_EMI_DEBUG_33 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT4__TPIU_TRACE_1 (_MX53_PAD_CSI0_DAT4__TPIU_TRACE_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 (_MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT5__GPIO5_23 (_MX53_PAD_CSI0_DAT5__GPIO5_23 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT5__KPP_ROW_5 (_MX53_PAD_CSI0_DAT5__KPP_ROW_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT5__ECSPI1_MOSI (_MX53_PAD_CSI0_DAT5__ECSPI1_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT (_MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD (_MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT5__EMI_EMI_DEBUG_34 (_MX53_PAD_CSI0_DAT5__EMI_EMI_DEBUG_34 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT5__TPIU_TRACE_2 (_MX53_PAD_CSI0_DAT5__TPIU_TRACE_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 (_MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT6__GPIO5_24 (_MX53_PAD_CSI0_DAT6__GPIO5_24 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT6__KPP_COL_6 (_MX53_PAD_CSI0_DAT6__KPP_COL_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT6__ECSPI1_MISO (_MX53_PAD_CSI0_DAT6__ECSPI1_MISO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK (_MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS (_MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT6__EMI_EMI_DEBUG_35 (_MX53_PAD_CSI0_DAT6__EMI_EMI_DEBUG_35 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT6__TPIU_TRACE_3 (_MX53_PAD_CSI0_DAT6__TPIU_TRACE_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 (_MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT7__GPIO5_25 (_MX53_PAD_CSI0_DAT7__GPIO5_25 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT7__KPP_ROW_6 (_MX53_PAD_CSI0_DAT7__KPP_ROW_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT7__ECSPI1_SS0 (_MX53_PAD_CSI0_DAT7__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR (_MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD (_MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT7__EMI_EMI_DEBUG_36 (_MX53_PAD_CSI0_DAT7__EMI_EMI_DEBUG_36 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT7__TPIU_TRACE_4 (_MX53_PAD_CSI0_DAT7__TPIU_TRACE_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 (_MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT8__GPIO5_26 (_MX53_PAD_CSI0_DAT8__GPIO5_26 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT8__KPP_COL_7 (_MX53_PAD_CSI0_DAT8__KPP_COL_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT8__ECSPI2_SCLK (_MX53_PAD_CSI0_DAT8__ECSPI2_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC (_MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT8__I2C1_SDA (_MX53_PAD_CSI0_DAT8__I2C1_SDA | MUX_PAD_CTRL(PAD_CTRL_I2C)) +#define MX53_PAD_CSI0_DAT8__EMI_EMI_DEBUG_37 (_MX53_PAD_CSI0_DAT8__EMI_EMI_DEBUG_37 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT8__TPIU_TRACE_5 (_MX53_PAD_CSI0_DAT8__TPIU_TRACE_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 (_MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT9__GPIO5_27 (_MX53_PAD_CSI0_DAT9__GPIO5_27 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT9__KPP_ROW_7 (_MX53_PAD_CSI0_DAT9__KPP_ROW_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT9__ECSPI2_MOSI (_MX53_PAD_CSI0_DAT9__ECSPI2_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT9__USBOH3_USBH3_PWR (_MX53_PAD_CSI0_DAT9__USBOH3_USBH3_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT9__I2C1_SCL (_MX53_PAD_CSI0_DAT9__I2C1_SCL | MUX_PAD_CTRL(PAD_CTRL_I2C)) +#define MX53_PAD_CSI0_DAT9__EMI_EMI_DEBUG_38 (_MX53_PAD_CSI0_DAT9__EMI_EMI_DEBUG_38 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT9__TPIU_TRACE_6 (_MX53_PAD_CSI0_DAT9__TPIU_TRACE_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 (_MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT10__GPIO5_28 (_MX53_PAD_CSI0_DAT10__GPIO5_28 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT10__UART1_TXD_MUX (_MX53_PAD_CSI0_DAT10__UART1_TXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT10__ECSPI2_MISO (_MX53_PAD_CSI0_DAT10__ECSPI2_MISO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC (_MX53_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 (_MX53_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT10__EMI_EMI_DEBUG_39 (_MX53_PAD_CSI0_DAT10__EMI_EMI_DEBUG_39 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT10__TPIU_TRACE_7 (_MX53_PAD_CSI0_DAT10__TPIU_TRACE_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 (_MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT11__GPIO5_29 (_MX53_PAD_CSI0_DAT11__GPIO5_29 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT11__UART1_RXD_MUX (_MX53_PAD_CSI0_DAT11__UART1_RXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT11__ECSPI2_SS0 (_MX53_PAD_CSI0_DAT11__ECSPI2_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS (_MX53_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 (_MX53_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT11__EMI_EMI_DEBUG_40 (_MX53_PAD_CSI0_DAT11__EMI_EMI_DEBUG_40 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT11__TPIU_TRACE_8 (_MX53_PAD_CSI0_DAT11__TPIU_TRACE_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 (_MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT12__GPIO5_30 (_MX53_PAD_CSI0_DAT12__GPIO5_30 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT12__UART4_TXD_MUX (_MX53_PAD_CSI0_DAT12__UART4_TXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0 (_MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 (_MX53_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT12__EMI_EMI_DEBUG_41 (_MX53_PAD_CSI0_DAT12__EMI_EMI_DEBUG_41 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT12__TPIU_TRACE_9 (_MX53_PAD_CSI0_DAT12__TPIU_TRACE_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 (_MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT13__GPIO5_31 (_MX53_PAD_CSI0_DAT13__GPIO5_31 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT13__UART4_RXD_MUX (_MX53_PAD_CSI0_DAT13__UART4_RXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1 (_MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 (_MX53_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT13__EMI_EMI_DEBUG_42 (_MX53_PAD_CSI0_DAT13__EMI_EMI_DEBUG_42 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT13__TPIU_TRACE_10 (_MX53_PAD_CSI0_DAT13__TPIU_TRACE_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 (_MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT14__GPIO6_0 (_MX53_PAD_CSI0_DAT14__GPIO6_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT14__UART5_TXD_MUX (_MX53_PAD_CSI0_DAT14__UART5_TXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2 (_MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 (_MX53_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT14__EMI_EMI_DEBUG_43 (_MX53_PAD_CSI0_DAT14__EMI_EMI_DEBUG_43 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT14__TPIU_TRACE_11 (_MX53_PAD_CSI0_DAT14__TPIU_TRACE_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 (_MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT15__GPIO6_1 (_MX53_PAD_CSI0_DAT15__GPIO6_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT15__UART5_RXD_MUX (_MX53_PAD_CSI0_DAT15__UART5_RXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3 (_MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 (_MX53_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT15__EMI_EMI_DEBUG_44 (_MX53_PAD_CSI0_DAT15__EMI_EMI_DEBUG_44 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT15__TPIU_TRACE_12 (_MX53_PAD_CSI0_DAT15__TPIU_TRACE_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 (_MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT16__GPIO6_2 (_MX53_PAD_CSI0_DAT16__GPIO6_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT16__UART4_RTS (_MX53_PAD_CSI0_DAT16__UART4_RTS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4 (_MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 (_MX53_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT16__EMI_EMI_DEBUG_45 (_MX53_PAD_CSI0_DAT16__EMI_EMI_DEBUG_45 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT16__TPIU_TRACE_13 (_MX53_PAD_CSI0_DAT16__TPIU_TRACE_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 (_MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT17__GPIO6_3 (_MX53_PAD_CSI0_DAT17__GPIO6_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT17__UART4_CTS (_MX53_PAD_CSI0_DAT17__UART4_CTS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5 (_MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 (_MX53_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT17__EMI_EMI_DEBUG_46 (_MX53_PAD_CSI0_DAT17__EMI_EMI_DEBUG_46 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT17__TPIU_TRACE_14 (_MX53_PAD_CSI0_DAT17__TPIU_TRACE_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 (_MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT18__GPIO6_4 (_MX53_PAD_CSI0_DAT18__GPIO6_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT18__UART5_RTS (_MX53_PAD_CSI0_DAT18__UART5_RTS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6 (_MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 (_MX53_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT18__EMI_EMI_DEBUG_47 (_MX53_PAD_CSI0_DAT18__EMI_EMI_DEBUG_47 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT18__TPIU_TRACE_15 (_MX53_PAD_CSI0_DAT18__TPIU_TRACE_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 (_MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT19__GPIO6_5 (_MX53_PAD_CSI0_DAT19__GPIO6_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT19__UART5_CTS (_MX53_PAD_CSI0_DAT19__UART5_CTS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7 (_MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 (_MX53_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT19__EMI_EMI_DEBUG_48 (_MX53_PAD_CSI0_DAT19__EMI_EMI_DEBUG_48 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_CSI0_DAT19__USBPHY2_BISTOK (_MX53_PAD_CSI0_DAT19__USBPHY2_BISTOK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A25__EMI_WEIM_A_25 (_MX53_PAD_EIM_A25__EMI_WEIM_A_25 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A25__GPIO5_2 (_MX53_PAD_EIM_A25__GPIO5_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A25__ECSPI2_RDY (_MX53_PAD_EIM_A25__ECSPI2_RDY | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A25__IPU_DI1_PIN12 (_MX53_PAD_EIM_A25__IPU_DI1_PIN12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A25__CSPI_SS1 (_MX53_PAD_EIM_A25__CSPI_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A25__IPU_DI0_D1_CS (_MX53_PAD_EIM_A25__IPU_DI0_D1_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A25__USBPHY1_BISTOK (_MX53_PAD_EIM_A25__USBPHY1_BISTOK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_EB2__EMI_WEIM_EB_2 (_MX53_PAD_EIM_EB2__EMI_WEIM_EB_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_EB2__GPIO2_30 (_MX53_PAD_EIM_EB2__GPIO2_30 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_EB2__CCM_DI1_EXT_CLK (_MX53_PAD_EIM_EB2__CCM_DI1_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_EB2__IPU_SER_DISP1_CS (_MX53_PAD_EIM_EB2__IPU_SER_DISP1_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_EB2__ECSPI1_SS0 (_MX53_PAD_EIM_EB2__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_EB2__I2C2_SCL (_MX53_PAD_EIM_EB2__I2C2_SCL | MUX_PAD_CTRL(PAD_CTRL_I2C)) +#define MX53_PAD_EIM_D16__EMI_WEIM_D_16 (_MX53_PAD_EIM_D16__EMI_WEIM_D_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D16__GPIO3_16 (_MX53_PAD_EIM_D16__GPIO3_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D16__IPU_DI0_PIN5 (_MX53_PAD_EIM_D16__IPU_DI0_PIN5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D16__IPU_DISPB1_SER_CLK (_MX53_PAD_EIM_D16__IPU_DISPB1_SER_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D16__ECSPI1_SCLK (_MX53_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D16__I2C2_SDA (_MX53_PAD_EIM_D16__I2C2_SDA | MUX_PAD_CTRL(PAD_CTRL_I2C)) +#define MX53_PAD_EIM_D17__EMI_WEIM_D_17 (_MX53_PAD_EIM_D17__EMI_WEIM_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D17__GPIO3_17 (_MX53_PAD_EIM_D17__GPIO3_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D17__IPU_DI0_PIN6 (_MX53_PAD_EIM_D17__IPU_DI0_PIN6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D17__IPU_DISPB1_SER_DIN (_MX53_PAD_EIM_D17__IPU_DISPB1_SER_DIN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D17__ECSPI1_MISO (_MX53_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D17__I2C3_SCL (_MX53_PAD_EIM_D17__I2C3_SCL | MUX_PAD_CTRL(PAD_CTRL_I2C)) +#define MX53_PAD_EIM_D18__EMI_WEIM_D_18 (_MX53_PAD_EIM_D18__EMI_WEIM_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D18__GPIO3_18 (_MX53_PAD_EIM_D18__GPIO3_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D18__IPU_DI0_PIN7 (_MX53_PAD_EIM_D18__IPU_DI0_PIN7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D18__IPU_DISPB1_SER_DIO (_MX53_PAD_EIM_D18__IPU_DISPB1_SER_DIO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D18__ECSPI1_MOSI (_MX53_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D18__I2C3_SDA (_MX53_PAD_EIM_D18__I2C3_SDA | MUX_PAD_CTRL(PAD_CTRL_I2C)) +#define MX53_PAD_EIM_D18__IPU_DI1_D0_CS (_MX53_PAD_EIM_D18__IPU_DI1_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D19__EMI_WEIM_D_19 (_MX53_PAD_EIM_D19__EMI_WEIM_D_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D19__GPIO3_19 (_MX53_PAD_EIM_D19__GPIO3_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D19__IPU_DI0_PIN8 (_MX53_PAD_EIM_D19__IPU_DI0_PIN8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D19__IPU_DISPB1_SER_RS (_MX53_PAD_EIM_D19__IPU_DISPB1_SER_RS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D19__ECSPI1_SS1 (_MX53_PAD_EIM_D19__ECSPI1_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D19__EPIT1_EPITO (_MX53_PAD_EIM_D19__EPIT1_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D19__UART1_CTS (_MX53_PAD_EIM_D19__UART1_CTS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D19__USBOH3_USBH2_OC (_MX53_PAD_EIM_D19__USBOH3_USBH2_OC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D20__EMI_WEIM_D_20 (_MX53_PAD_EIM_D20__EMI_WEIM_D_20 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D20__GPIO3_20 (_MX53_PAD_EIM_D20__GPIO3_20 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D20__IPU_DI0_PIN16 (_MX53_PAD_EIM_D20__IPU_DI0_PIN16 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D20__IPU_SER_DISP0_CS (_MX53_PAD_EIM_D20__IPU_SER_DISP0_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D20__CSPI_SS0 (_MX53_PAD_EIM_D20__CSPI_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D20__EPIT2_EPITO (_MX53_PAD_EIM_D20__EPIT2_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D20__UART1_RTS (_MX53_PAD_EIM_D20__UART1_RTS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D20__USBOH3_USBH2_PWR (_MX53_PAD_EIM_D20__USBOH3_USBH2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D21__EMI_WEIM_D_21 (_MX53_PAD_EIM_D21__EMI_WEIM_D_21 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D21__GPIO3_21 (_MX53_PAD_EIM_D21__GPIO3_21 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D21__IPU_DI0_PIN17 (_MX53_PAD_EIM_D21__IPU_DI0_PIN17 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK (_MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D21__CSPI_SCLK (_MX53_PAD_EIM_D21__CSPI_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D21__I2C1_SCL (_MX53_PAD_EIM_D21__I2C1_SCL | MUX_PAD_CTRL(PAD_CTRL_I2C)) +#define MX53_PAD_EIM_D21__USBOH3_USBOTG_OC (_MX53_PAD_EIM_D21__USBOH3_USBOTG_OC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D22__EMI_WEIM_D_22 (_MX53_PAD_EIM_D22__EMI_WEIM_D_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D22__GPIO3_22 (_MX53_PAD_EIM_D22__GPIO3_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D22__IPU_DI0_PIN1 (_MX53_PAD_EIM_D22__IPU_DI0_PIN1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN (_MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D22__CSPI_MISO (_MX53_PAD_EIM_D22__CSPI_MISO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D22__USBOH3_USBOTG_PWR (_MX53_PAD_EIM_D22__USBOH3_USBOTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D23__EMI_WEIM_D_23 (_MX53_PAD_EIM_D23__EMI_WEIM_D_23 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D23__GPIO3_23 (_MX53_PAD_EIM_D23__GPIO3_23 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D23__UART3_CTS (_MX53_PAD_EIM_D23__UART3_CTS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D23__UART1_DCD (_MX53_PAD_EIM_D23__UART1_DCD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D23__IPU_DI0_D0_CS (_MX53_PAD_EIM_D23__IPU_DI0_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D23__IPU_DI1_PIN2 (_MX53_PAD_EIM_D23__IPU_DI1_PIN2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D23__IPU_CSI1_DATA_EN (_MX53_PAD_EIM_D23__IPU_CSI1_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D23__IPU_DI1_PIN14 (_MX53_PAD_EIM_D23__IPU_DI1_PIN14 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_EB3__EMI_WEIM_EB_3 (_MX53_PAD_EIM_EB3__EMI_WEIM_EB_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_EB3__GPIO2_31 (_MX53_PAD_EIM_EB3__GPIO2_31 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_EB3__UART3_RTS (_MX53_PAD_EIM_EB3__UART3_RTS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_EB3__UART1_RI (_MX53_PAD_EIM_EB3__UART1_RI | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_EB3__IPU_DI1_PIN3 (_MX53_PAD_EIM_EB3__IPU_DI1_PIN3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_EB3__IPU_CSI1_HSYNC (_MX53_PAD_EIM_EB3__IPU_CSI1_HSYNC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_EB3__IPU_DI1_PIN16 (_MX53_PAD_EIM_EB3__IPU_DI1_PIN16 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D24__EMI_WEIM_D_24 (_MX53_PAD_EIM_D24__EMI_WEIM_D_24 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D24__GPIO3_24 (_MX53_PAD_EIM_D24__GPIO3_24 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D24__UART3_TXD_MUX (_MX53_PAD_EIM_D24__UART3_TXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D24__ECSPI1_SS2 (_MX53_PAD_EIM_D24__ECSPI1_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D24__CSPI_SS2 (_MX53_PAD_EIM_D24__CSPI_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D24__AUDMUX_AUD5_RXFS (_MX53_PAD_EIM_D24__AUDMUX_AUD5_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D24__ECSPI2_SS2 (_MX53_PAD_EIM_D24__ECSPI2_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D24__UART1_DTR (_MX53_PAD_EIM_D24__UART1_DTR | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D25__EMI_WEIM_D_25 (_MX53_PAD_EIM_D25__EMI_WEIM_D_25 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D25__GPIO3_25 (_MX53_PAD_EIM_D25__GPIO3_25 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D25__UART3_RXD_MUX (_MX53_PAD_EIM_D25__UART3_RXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D25__ECSPI1_SS3 (_MX53_PAD_EIM_D25__ECSPI1_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D25__CSPI_SS3 (_MX53_PAD_EIM_D25__CSPI_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D25__AUDMUX_AUD5_RXC (_MX53_PAD_EIM_D25__AUDMUX_AUD5_RXC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D25__ECSPI2_SS3 (_MX53_PAD_EIM_D25__ECSPI2_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D25__UART1_DSR (_MX53_PAD_EIM_D25__UART1_DSR | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D26__EMI_WEIM_D_26 (_MX53_PAD_EIM_D26__EMI_WEIM_D_26 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D26__GPIO3_26 (_MX53_PAD_EIM_D26__GPIO3_26 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D26__UART2_TXD_MUX (_MX53_PAD_EIM_D26__UART2_TXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D26__FIRI_RXD (_MX53_PAD_EIM_D26__FIRI_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D26__IPU_CSI0_D_1 (_MX53_PAD_EIM_D26__IPU_CSI0_D_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D26__IPU_DI1_PIN11 (_MX53_PAD_EIM_D26__IPU_DI1_PIN11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D26__IPU_SISG_2 (_MX53_PAD_EIM_D26__IPU_SISG_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 (_MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D27__EMI_WEIM_D_27 (_MX53_PAD_EIM_D27__EMI_WEIM_D_27 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D27__GPIO3_27 (_MX53_PAD_EIM_D27__GPIO3_27 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D27__UART2_RXD_MUX (_MX53_PAD_EIM_D27__UART2_RXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D27__FIRI_TXD (_MX53_PAD_EIM_D27__FIRI_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D27__IPU_CSI0_D_0 (_MX53_PAD_EIM_D27__IPU_CSI0_D_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D27__IPU_DI1_PIN13 (_MX53_PAD_EIM_D27__IPU_DI1_PIN13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D27__IPU_SISG_3 (_MX53_PAD_EIM_D27__IPU_SISG_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 (_MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D28__EMI_WEIM_D_28 (_MX53_PAD_EIM_D28__EMI_WEIM_D_28 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D28__GPIO3_28 (_MX53_PAD_EIM_D28__GPIO3_28 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D28__UART2_CTS (_MX53_PAD_EIM_D28__UART2_CTS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO (_MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D28__CSPI_MOSI (_MX53_PAD_EIM_D28__CSPI_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D28__I2C1_SDA (_MX53_PAD_EIM_D28__I2C1_SDA | MUX_PAD_CTRL(PAD_CTRL_I2C)) +#define MX53_PAD_EIM_D28__IPU_EXT_TRIG (_MX53_PAD_EIM_D28__IPU_EXT_TRIG | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D28__IPU_DI0_PIN13 (_MX53_PAD_EIM_D28__IPU_DI0_PIN13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D29__EMI_WEIM_D_29 (_MX53_PAD_EIM_D29__EMI_WEIM_D_29 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D29__GPIO3_29 (_MX53_PAD_EIM_D29__GPIO3_29 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D29__UART2_RTS (_MX53_PAD_EIM_D29__UART2_RTS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS (_MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D29__CSPI_SS0 (_MX53_PAD_EIM_D29__CSPI_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D29__IPU_DI1_PIN15 (_MX53_PAD_EIM_D29__IPU_DI1_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D29__IPU_CSI1_VSYNC (_MX53_PAD_EIM_D29__IPU_CSI1_VSYNC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D29__IPU_DI0_PIN14 (_MX53_PAD_EIM_D29__IPU_DI0_PIN14 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D30__EMI_WEIM_D_30 (_MX53_PAD_EIM_D30__EMI_WEIM_D_30 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D30__GPIO3_30 (_MX53_PAD_EIM_D30__GPIO3_30 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D30__UART3_CTS (_MX53_PAD_EIM_D30__UART3_CTS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D30__IPU_CSI0_D_3 (_MX53_PAD_EIM_D30__IPU_CSI0_D_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D30__IPU_DI0_PIN11 (_MX53_PAD_EIM_D30__IPU_DI0_PIN11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 (_MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D30__USBOH3_USBH1_OC (_MX53_PAD_EIM_D30__USBOH3_USBH1_OC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D30__USBOH3_USBH2_OC (_MX53_PAD_EIM_D30__USBOH3_USBH2_OC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D31__EMI_WEIM_D_31 (_MX53_PAD_EIM_D31__EMI_WEIM_D_31 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D31__GPIO3_31 (_MX53_PAD_EIM_D31__GPIO3_31 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D31__UART3_RTS (_MX53_PAD_EIM_D31__UART3_RTS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D31__IPU_CSI0_D_2 (_MX53_PAD_EIM_D31__IPU_CSI0_D_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D31__IPU_DI0_PIN12 (_MX53_PAD_EIM_D31__IPU_DI0_PIN12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 (_MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D31__USBOH3_USBH1_PWR (_MX53_PAD_EIM_D31__USBOH3_USBH1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_D31__USBOH3_USBH2_PWR (_MX53_PAD_EIM_D31__USBOH3_USBH2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A24__EMI_WEIM_A_24 (_MX53_PAD_EIM_A24__EMI_WEIM_A_24 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A24__GPIO5_4 (_MX53_PAD_EIM_A24__GPIO5_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 (_MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A24__IPU_CSI1_D_19 (_MX53_PAD_EIM_A24__IPU_CSI1_D_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A24__IPU_SISG_2 (_MX53_PAD_EIM_A24__IPU_SISG_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A24__USBPHY2_BVALID (_MX53_PAD_EIM_A24__USBPHY2_BVALID | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A23__EMI_WEIM_A_23 (_MX53_PAD_EIM_A23__EMI_WEIM_A_23 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A23__GPIO6_6 (_MX53_PAD_EIM_A23__GPIO6_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 (_MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A23__IPU_CSI1_D_18 (_MX53_PAD_EIM_A23__IPU_CSI1_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A23__IPU_SISG_3 (_MX53_PAD_EIM_A23__IPU_SISG_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A23__USBPHY2_ENDSESSION (_MX53_PAD_EIM_A23__USBPHY2_ENDSESSION | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A22__EMI_WEIM_A_22 (_MX53_PAD_EIM_A22__EMI_WEIM_A_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A22__GPIO2_16 (_MX53_PAD_EIM_A22__GPIO2_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 (_MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A22__IPU_CSI1_D_17 (_MX53_PAD_EIM_A22__IPU_CSI1_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A22__SRC_BT_CFG1_7 (_MX53_PAD_EIM_A22__SRC_BT_CFG1_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A21__EMI_WEIM_A_21 (_MX53_PAD_EIM_A21__EMI_WEIM_A_21 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A21__GPIO2_17 (_MX53_PAD_EIM_A21__GPIO2_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 (_MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A21__IPU_CSI1_D_16 (_MX53_PAD_EIM_A21__IPU_CSI1_D_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A21__SRC_BT_CFG1_6 (_MX53_PAD_EIM_A21__SRC_BT_CFG1_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A20__EMI_WEIM_A_20 (_MX53_PAD_EIM_A20__EMI_WEIM_A_20 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A20__GPIO2_18 (_MX53_PAD_EIM_A20__GPIO2_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 (_MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A20__IPU_CSI1_D_15 (_MX53_PAD_EIM_A20__IPU_CSI1_D_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A20__SRC_BT_CFG1_5 (_MX53_PAD_EIM_A20__SRC_BT_CFG1_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A19__EMI_WEIM_A_19 (_MX53_PAD_EIM_A19__EMI_WEIM_A_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A19__GPIO2_19 (_MX53_PAD_EIM_A19__GPIO2_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 (_MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A19__IPU_CSI1_D_14 (_MX53_PAD_EIM_A19__IPU_CSI1_D_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A19__SRC_BT_CFG1_4 (_MX53_PAD_EIM_A19__SRC_BT_CFG1_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A18__EMI_WEIM_A_18 (_MX53_PAD_EIM_A18__EMI_WEIM_A_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A18__GPIO2_20 (_MX53_PAD_EIM_A18__GPIO2_20 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 (_MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A18__IPU_CSI1_D_13 (_MX53_PAD_EIM_A18__IPU_CSI1_D_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A18__SRC_BT_CFG1_3 (_MX53_PAD_EIM_A18__SRC_BT_CFG1_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A17__EMI_WEIM_A_17 (_MX53_PAD_EIM_A17__EMI_WEIM_A_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A17__GPIO2_21 (_MX53_PAD_EIM_A17__GPIO2_21 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 (_MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A17__IPU_CSI1_D_12 (_MX53_PAD_EIM_A17__IPU_CSI1_D_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A17__SRC_BT_CFG1_2 (_MX53_PAD_EIM_A17__SRC_BT_CFG1_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A16__EMI_WEIM_A_16 (_MX53_PAD_EIM_A16__EMI_WEIM_A_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A16__GPIO2_22 (_MX53_PAD_EIM_A16__GPIO2_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK (_MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A16__IPU_CSI1_PIXCLK (_MX53_PAD_EIM_A16__IPU_CSI1_PIXCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_A16__SRC_BT_CFG1_1 (_MX53_PAD_EIM_A16__SRC_BT_CFG1_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_CS0__EMI_WEIM_CS_0 (_MX53_PAD_EIM_CS0__EMI_WEIM_CS_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_CS0__GPIO2_23 (_MX53_PAD_EIM_CS0__GPIO2_23 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_CS0__ECSPI2_SCLK (_MX53_PAD_EIM_CS0__ECSPI2_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_CS0__IPU_DI1_PIN5 (_MX53_PAD_EIM_CS0__IPU_DI1_PIN5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 (_MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_CS1__GPIO2_24 (_MX53_PAD_EIM_CS1__GPIO2_24 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_CS1__ECSPI2_MOSI (_MX53_PAD_EIM_CS1__ECSPI2_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_CS1__IPU_DI1_PIN6 (_MX53_PAD_EIM_CS1__IPU_DI1_PIN6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_OE__EMI_WEIM_OE (_MX53_PAD_EIM_OE__EMI_WEIM_OE | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_OE__GPIO2_25 (_MX53_PAD_EIM_OE__GPIO2_25 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_OE__ECSPI2_MISO (_MX53_PAD_EIM_OE__ECSPI2_MISO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_OE__IPU_DI1_PIN7 (_MX53_PAD_EIM_OE__IPU_DI1_PIN7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_OE__USBPHY2_IDDIG (_MX53_PAD_EIM_OE__USBPHY2_IDDIG | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_RW__EMI_WEIM_RW (_MX53_PAD_EIM_RW__EMI_WEIM_RW | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_RW__GPIO2_26 (_MX53_PAD_EIM_RW__GPIO2_26 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_RW__ECSPI2_SS0 (_MX53_PAD_EIM_RW__ECSPI2_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_RW__IPU_DI1_PIN8 (_MX53_PAD_EIM_RW__IPU_DI1_PIN8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_RW__USBPHY2_HOSTDISCONNECT (_MX53_PAD_EIM_RW__USBPHY2_HOSTDISCONNECT | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_LBA__EMI_WEIM_LBA (_MX53_PAD_EIM_LBA__EMI_WEIM_LBA | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_LBA__GPIO2_27 (_MX53_PAD_EIM_LBA__GPIO2_27 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_LBA__ECSPI2_SS1 (_MX53_PAD_EIM_LBA__ECSPI2_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_LBA__IPU_DI1_PIN17 (_MX53_PAD_EIM_LBA__IPU_DI1_PIN17 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_LBA__SRC_BT_CFG1_0 (_MX53_PAD_EIM_LBA__SRC_BT_CFG1_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_EB0__EMI_WEIM_EB_0 (_MX53_PAD_EIM_EB0__EMI_WEIM_EB_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_EB0__GPIO2_28 (_MX53_PAD_EIM_EB0__GPIO2_28 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 (_MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_EB0__IPU_CSI1_D_11 (_MX53_PAD_EIM_EB0__IPU_CSI1_D_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_EB0__GPC_PMIC_RDY (_MX53_PAD_EIM_EB0__GPC_PMIC_RDY | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_EB0__SRC_BT_CFG2_7 (_MX53_PAD_EIM_EB0__SRC_BT_CFG2_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_EB1__EMI_WEIM_EB_1 (_MX53_PAD_EIM_EB1__EMI_WEIM_EB_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_EB1__GPIO2_29 (_MX53_PAD_EIM_EB1__GPIO2_29 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 (_MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_EB1__IPU_CSI1_D_10 (_MX53_PAD_EIM_EB1__IPU_CSI1_D_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_EB1__SRC_BT_CFG2_6 (_MX53_PAD_EIM_EB1__SRC_BT_CFG2_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 (_MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA0__GPIO3_0 (_MX53_PAD_EIM_DA0__GPIO3_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 (_MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA0__IPU_CSI1_D_9 (_MX53_PAD_EIM_DA0__IPU_CSI1_D_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA0__SRC_BT_CFG2_5 (_MX53_PAD_EIM_DA0__SRC_BT_CFG2_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 (_MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA1__GPIO3_1 (_MX53_PAD_EIM_DA1__GPIO3_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 (_MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA1__IPU_CSI1_D_8 (_MX53_PAD_EIM_DA1__IPU_CSI1_D_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA1__SRC_BT_CFG2_4 (_MX53_PAD_EIM_DA1__SRC_BT_CFG2_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 (_MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA2__GPIO3_2 (_MX53_PAD_EIM_DA2__GPIO3_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 (_MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA2__IPU_CSI1_D_7 (_MX53_PAD_EIM_DA2__IPU_CSI1_D_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA2__SRC_BT_CFG2_3 (_MX53_PAD_EIM_DA2__SRC_BT_CFG2_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 (_MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA3__GPIO3_3 (_MX53_PAD_EIM_DA3__GPIO3_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 (_MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA3__IPU_CSI1_D_6 (_MX53_PAD_EIM_DA3__IPU_CSI1_D_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA3__SRC_BT_CFG2_2 (_MX53_PAD_EIM_DA3__SRC_BT_CFG2_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 (_MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA4__GPIO3_4 (_MX53_PAD_EIM_DA4__GPIO3_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 (_MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA4__IPU_CSI1_D_5 (_MX53_PAD_EIM_DA4__IPU_CSI1_D_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA4__SRC_BT_CFG3_7 (_MX53_PAD_EIM_DA4__SRC_BT_CFG3_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 (_MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA5__GPIO3_5 (_MX53_PAD_EIM_DA5__GPIO3_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 (_MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA5__IPU_CSI1_D_4 (_MX53_PAD_EIM_DA5__IPU_CSI1_D_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA5__SRC_BT_CFG3_6 (_MX53_PAD_EIM_DA5__SRC_BT_CFG3_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 (_MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA6__GPIO3_6 (_MX53_PAD_EIM_DA6__GPIO3_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 (_MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA6__IPU_CSI1_D_3 (_MX53_PAD_EIM_DA6__IPU_CSI1_D_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA6__SRC_BT_CFG3_5 (_MX53_PAD_EIM_DA6__SRC_BT_CFG3_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7 (_MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA7__GPIO3_7 (_MX53_PAD_EIM_DA7__GPIO3_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 (_MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA7__IPU_CSI1_D_2 (_MX53_PAD_EIM_DA7__IPU_CSI1_D_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA7__SRC_BT_CFG3_4 (_MX53_PAD_EIM_DA7__SRC_BT_CFG3_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8 (_MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA8__GPIO3_8 (_MX53_PAD_EIM_DA8__GPIO3_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 (_MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA8__IPU_CSI1_D_1 (_MX53_PAD_EIM_DA8__IPU_CSI1_D_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA8__SRC_BT_CFG3_3 (_MX53_PAD_EIM_DA8__SRC_BT_CFG3_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9 (_MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA9__GPIO3_9 (_MX53_PAD_EIM_DA9__GPIO3_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 (_MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA9__IPU_CSI1_D_0 (_MX53_PAD_EIM_DA9__IPU_CSI1_D_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA9__SRC_BT_CFG3_2 (_MX53_PAD_EIM_DA9__SRC_BT_CFG3_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10 (_MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA10__GPIO3_10 (_MX53_PAD_EIM_DA10__GPIO3_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA10__IPU_DI1_PIN15 (_MX53_PAD_EIM_DA10__IPU_DI1_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA10__IPU_CSI1_DATA_EN (_MX53_PAD_EIM_DA10__IPU_CSI1_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA10__SRC_BT_CFG3_1 (_MX53_PAD_EIM_DA10__SRC_BT_CFG3_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11 (_MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA11__GPIO3_11 (_MX53_PAD_EIM_DA11__GPIO3_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA11__IPU_DI1_PIN2 (_MX53_PAD_EIM_DA11__IPU_DI1_PIN2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA11__IPU_CSI1_HSYNC (_MX53_PAD_EIM_DA11__IPU_CSI1_HSYNC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12 (_MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA12__GPIO3_12 (_MX53_PAD_EIM_DA12__GPIO3_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA12__IPU_DI1_PIN3 (_MX53_PAD_EIM_DA12__IPU_DI1_PIN3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA12__IPU_CSI1_VSYNC (_MX53_PAD_EIM_DA12__IPU_CSI1_VSYNC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13 (_MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA13__GPIO3_13 (_MX53_PAD_EIM_DA13__GPIO3_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA13__IPU_DI1_D0_CS (_MX53_PAD_EIM_DA13__IPU_DI1_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA13__CCM_DI1_EXT_CLK (_MX53_PAD_EIM_DA13__CCM_DI1_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14 (_MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA14__GPIO3_14 (_MX53_PAD_EIM_DA14__GPIO3_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA14__IPU_DI1_D1_CS (_MX53_PAD_EIM_DA14__IPU_DI1_D1_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA14__CCM_DI0_EXT_CLK (_MX53_PAD_EIM_DA14__CCM_DI0_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15 (_MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA15__GPIO3_15 (_MX53_PAD_EIM_DA15__GPIO3_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA15__IPU_DI1_PIN1 (_MX53_PAD_EIM_DA15__IPU_DI1_PIN1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_DA15__IPU_DI1_PIN4 (_MX53_PAD_EIM_DA15__IPU_DI1_PIN4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B (_MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_NANDF_WE_B__GPIO6_12 (_MX53_PAD_NANDF_WE_B__GPIO6_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B (_MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_NANDF_RE_B__GPIO6_13 (_MX53_PAD_NANDF_RE_B__GPIO6_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT (_MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_WAIT__GPIO5_0 (_MX53_PAD_EIM_WAIT__GPIO5_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_EIM_WAIT__EMI_WEIM_DTACK_B (_MX53_PAD_EIM_WAIT__EMI_WEIM_DTACK_B | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_LVDS1_TX3_P__GPIO6_22 (_MX53_PAD_LVDS1_TX3_P__GPIO6_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 (_MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_LVDS1_TX2_P__GPIO6_24 (_MX53_PAD_LVDS1_TX2_P__GPIO6_24 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 (_MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_LVDS1_CLK_P__GPIO6_26 (_MX53_PAD_LVDS1_CLK_P__GPIO6_26 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK (_MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_LVDS1_TX1_P__GPIO6_28 (_MX53_PAD_LVDS1_TX1_P__GPIO6_28 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 (_MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_LVDS1_TX0_P__GPIO6_30 (_MX53_PAD_LVDS1_TX0_P__GPIO6_30 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 (_MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_LVDS0_TX3_P__GPIO7_22 (_MX53_PAD_LVDS0_TX3_P__GPIO7_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 (_MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_LVDS0_CLK_P__GPIO7_24 (_MX53_PAD_LVDS0_CLK_P__GPIO7_24 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK (_MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_LVDS0_TX2_P__GPIO7_26 (_MX53_PAD_LVDS0_TX2_P__GPIO7_26 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 (_MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_LVDS0_TX1_P__GPIO7_28 (_MX53_PAD_LVDS0_TX1_P__GPIO7_28 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 (_MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_LVDS0_TX0_P__GPIO7_30 (_MX53_PAD_LVDS0_TX0_P__GPIO7_30 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 (_MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_10__GPIO4_0 (_MX53_PAD_GPIO_10__GPIO4_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_10__OSC32k_32K_OUT (_MX53_PAD_GPIO_10__OSC32k_32K_OUT | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_11__GPIO4_1 (_MX53_PAD_GPIO_11__GPIO4_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_12__GPIO4_2 (_MX53_PAD_GPIO_12__GPIO4_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_13__GPIO4_3 (_MX53_PAD_GPIO_13__GPIO4_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_14__GPIO4_4 (_MX53_PAD_GPIO_14__GPIO4_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_NANDF_CLE__EMI_NANDF_CLE (_MX53_PAD_NANDF_CLE__EMI_NANDF_CLE | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_NANDF_CLE__GPIO6_7 (_MX53_PAD_NANDF_CLE__GPIO6_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_NANDF_CLE__USBPHY1_VSTATUS_0 (_MX53_PAD_NANDF_CLE__USBPHY1_VSTATUS_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_NANDF_ALE__EMI_NANDF_ALE (_MX53_PAD_NANDF_ALE__EMI_NANDF_ALE | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_NANDF_ALE__GPIO6_8 (_MX53_PAD_NANDF_ALE__GPIO6_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_NANDF_ALE__USBPHY1_VSTATUS_1 (_MX53_PAD_NANDF_ALE__USBPHY1_VSTATUS_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B (_MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_NANDF_WP_B__GPIO6_9 (_MX53_PAD_NANDF_WP_B__GPIO6_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_NANDF_WP_B__USBPHY1_VSTATUS_2 (_MX53_PAD_NANDF_WP_B__USBPHY1_VSTATUS_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 (_MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_NANDF_RB0__GPIO6_10 (_MX53_PAD_NANDF_RB0__GPIO6_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_NANDF_RB0__USBPHY1_VSTATUS_3 (_MX53_PAD_NANDF_RB0__USBPHY1_VSTATUS_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 (_MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_NANDF_CS0__GPIO6_11 (_MX53_PAD_NANDF_CS0__GPIO6_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_NANDF_CS0__USBPHY1_VSTATUS_4 (_MX53_PAD_NANDF_CS0__USBPHY1_VSTATUS_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1 (_MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_NANDF_CS1__GPIO6_14 (_MX53_PAD_NANDF_CS1__GPIO6_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_NANDF_CS1__MLB_MLBCLK (_MX53_PAD_NANDF_CS1__MLB_MLBCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_NANDF_CS1__USBPHY1_VSTATUS_5 (_MX53_PAD_NANDF_CS1__USBPHY1_VSTATUS_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2 (_MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_NANDF_CS2__GPIO6_15 (_MX53_PAD_NANDF_CS2__GPIO6_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_NANDF_CS2__IPU_SISG_0 (_MX53_PAD_NANDF_CS2__IPU_SISG_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_NANDF_CS2__ESAI1_TX0 (_MX53_PAD_NANDF_CS2__ESAI1_TX0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_NANDF_CS2__EMI_WEIM_CRE (_MX53_PAD_NANDF_CS2__EMI_WEIM_CRE | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_NANDF_CS2__CCM_CSI0_MCLK (_MX53_PAD_NANDF_CS2__CCM_CSI0_MCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_NANDF_CS2__MLB_MLBSIG (_MX53_PAD_NANDF_CS2__MLB_MLBSIG | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_NANDF_CS2__USBPHY1_VSTATUS_6 (_MX53_PAD_NANDF_CS2__USBPHY1_VSTATUS_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3 (_MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_NANDF_CS3__GPIO6_16 (_MX53_PAD_NANDF_CS3__GPIO6_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_NANDF_CS3__IPU_SISG_1 (_MX53_PAD_NANDF_CS3__IPU_SISG_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_NANDF_CS3__ESAI1_TX1 (_MX53_PAD_NANDF_CS3__ESAI1_TX1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_NANDF_CS3__EMI_WEIM_A_26 (_MX53_PAD_NANDF_CS3__EMI_WEIM_A_26 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_NANDF_CS3__MLB_MLBDAT (_MX53_PAD_NANDF_CS3__MLB_MLBDAT | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_NANDF_CS3__USBPHY1_VSTATUS_7 (_MX53_PAD_NANDF_CS3__USBPHY1_VSTATUS_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_MDIO__FEC_MDIO (_MX53_PAD_FEC_MDIO__FEC_MDIO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_MDIO__GPIO1_22 (_MX53_PAD_FEC_MDIO__GPIO1_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_MDIO__ESAI1_SCKR (_MX53_PAD_FEC_MDIO__ESAI1_SCKR | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_MDIO__FEC_COL (_MX53_PAD_FEC_MDIO__FEC_COL | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_MDIO__RTC_CE_RTC_PS2 (_MX53_PAD_FEC_MDIO__RTC_CE_RTC_PS2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_MDIO__SDMA_DEBUG_BUS_DEVICE_3 (_MX53_PAD_FEC_MDIO__SDMA_DEBUG_BUS_DEVICE_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_MDIO__EMI_EMI_DEBUG_49 (_MX53_PAD_FEC_MDIO__EMI_EMI_DEBUG_49 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_REF_CLK__FEC_TX_CLK (_MX53_PAD_FEC_REF_CLK__FEC_TX_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_REF_CLK__GPIO1_23 (_MX53_PAD_FEC_REF_CLK__GPIO1_23 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_REF_CLK__ESAI1_FSR (_MX53_PAD_FEC_REF_CLK__ESAI1_FSR | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 (_MX53_PAD_FEC_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_REF_CLK__EMI_EMI_DEBUG_50 (_MX53_PAD_FEC_REF_CLK__EMI_EMI_DEBUG_50 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_RX_ER__FEC_RX_ER (_MX53_PAD_FEC_RX_ER__FEC_RX_ER | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_RX_ER__GPIO1_24 (_MX53_PAD_FEC_RX_ER__GPIO1_24 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_RX_ER__ESAI1_HCKR (_MX53_PAD_FEC_RX_ER__ESAI1_HCKR | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_RX_ER__FEC_RX_CLK (_MX53_PAD_FEC_RX_ER__FEC_RX_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_RX_ER__RTC_CE_RTC_PS3 (_MX53_PAD_FEC_RX_ER__RTC_CE_RTC_PS3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_CRS_DV__FEC_RX_DV (_MX53_PAD_FEC_CRS_DV__FEC_RX_DV | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_CRS_DV__GPIO1_25 (_MX53_PAD_FEC_CRS_DV__GPIO1_25 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_CRS_DV__ESAI1_SCKT (_MX53_PAD_FEC_CRS_DV__ESAI1_SCKT | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_RXD1__FEC_RDATA_1 (_MX53_PAD_FEC_RXD1__FEC_RDATA_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_RXD1__GPIO1_26 (_MX53_PAD_FEC_RXD1__GPIO1_26 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_RXD1__ESAI1_FST (_MX53_PAD_FEC_RXD1__ESAI1_FST | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_RXD1__MLB_MLBSIG (_MX53_PAD_FEC_RXD1__MLB_MLBSIG | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_RXD1__RTC_CE_RTC_PS1 (_MX53_PAD_FEC_RXD1__RTC_CE_RTC_PS1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_RXD0__FEC_RDATA_0 (_MX53_PAD_FEC_RXD0__FEC_RDATA_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_RXD0__GPIO1_27 (_MX53_PAD_FEC_RXD0__GPIO1_27 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_RXD0__ESAI1_HCKT (_MX53_PAD_FEC_RXD0__ESAI1_HCKT | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_RXD0__OSC32k_32K_OUT (_MX53_PAD_FEC_RXD0__OSC32k_32K_OUT | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_TX_EN__FEC_TX_EN (_MX53_PAD_FEC_TX_EN__FEC_TX_EN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_TX_EN__GPIO1_28 (_MX53_PAD_FEC_TX_EN__GPIO1_28 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_TX_EN__ESAI1_TX3_RX2 (_MX53_PAD_FEC_TX_EN__ESAI1_TX3_RX2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_TXD1__FEC_TDATA_1 (_MX53_PAD_FEC_TXD1__FEC_TDATA_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_TXD1__GPIO1_29 (_MX53_PAD_FEC_TXD1__GPIO1_29 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_TXD1__ESAI1_TX2_RX3 (_MX53_PAD_FEC_TXD1__ESAI1_TX2_RX3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_TXD1__MLB_MLBCLK (_MX53_PAD_FEC_TXD1__MLB_MLBCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_TXD1__RTC_CE_RTC_PRSC_CLK (_MX53_PAD_FEC_TXD1__RTC_CE_RTC_PRSC_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_TXD0__FEC_TDATA_0 (_MX53_PAD_FEC_TXD0__FEC_TDATA_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_TXD0__GPIO1_30 (_MX53_PAD_FEC_TXD0__GPIO1_30 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_TXD0__ESAI1_TX4_RX1 (_MX53_PAD_FEC_TXD0__ESAI1_TX4_RX1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_TXD0__USBPHY2_DATAOUT_0 (_MX53_PAD_FEC_TXD0__USBPHY2_DATAOUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_MDC__FEC_MDC (_MX53_PAD_FEC_MDC__FEC_MDC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_MDC__GPIO1_31 (_MX53_PAD_FEC_MDC__GPIO1_31 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_MDC__ESAI1_TX5_RX0 (_MX53_PAD_FEC_MDC__ESAI1_TX5_RX0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_MDC__MLB_MLBDAT (_MX53_PAD_FEC_MDC__MLB_MLBDAT | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_MDC__RTC_CE_RTC_ALARM1_TRIG (_MX53_PAD_FEC_MDC__RTC_CE_RTC_ALARM1_TRIG | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_FEC_MDC__USBPHY2_DATAOUT_1 (_MX53_PAD_FEC_MDC__USBPHY2_DATAOUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DIOW__PATA_DIOW (_MX53_PAD_PATA_DIOW__PATA_DIOW | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DIOW__GPIO6_17 (_MX53_PAD_PATA_DIOW__GPIO6_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DIOW__UART1_TXD_MUX (_MX53_PAD_PATA_DIOW__UART1_TXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) +#define MX53_PAD_PATA_DIOW__USBPHY2_DATAOUT_2 (_MX53_PAD_PATA_DIOW__USBPHY2_DATAOUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DMACK__PATA_DMACK (_MX53_PAD_PATA_DMACK__PATA_DMACK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DMACK__GPIO6_18 (_MX53_PAD_PATA_DMACK__GPIO6_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DMACK__UART1_RXD_MUX (_MX53_PAD_PATA_DMACK__UART1_RXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) +#define MX53_PAD_PATA_DMACK__USBPHY2_DATAOUT_3 (_MX53_PAD_PATA_DMACK__USBPHY2_DATAOUT_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DMARQ__PATA_DMARQ (_MX53_PAD_PATA_DMARQ__PATA_DMARQ | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DMARQ__GPIO7_0 (_MX53_PAD_PATA_DMARQ__GPIO7_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DMARQ__UART2_TXD_MUX (_MX53_PAD_PATA_DMARQ__UART2_TXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) +#define MX53_PAD_PATA_DMARQ__CCM_CCM_OUT_0 (_MX53_PAD_PATA_DMARQ__CCM_CCM_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DMARQ__USBPHY2_DATAOUT_4 (_MX53_PAD_PATA_DMARQ__USBPHY2_DATAOUT_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_BUFFER_EN__PATA_BUFFER_EN (_MX53_PAD_PATA_BUFFER_EN__PATA_BUFFER_EN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_BUFFER_EN__GPIO7_1 (_MX53_PAD_PATA_BUFFER_EN__GPIO7_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX (_MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) +#define MX53_PAD_PATA_BUFFER_EN__CCM_CCM_OUT_1 (_MX53_PAD_PATA_BUFFER_EN__CCM_CCM_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_BUFFER_EN__USBPHY2_DATAOUT_5 (_MX53_PAD_PATA_BUFFER_EN__USBPHY2_DATAOUT_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_INTRQ__PATA_INTRQ (_MX53_PAD_PATA_INTRQ__PATA_INTRQ | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_INTRQ__GPIO7_2 (_MX53_PAD_PATA_INTRQ__GPIO7_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_INTRQ__UART2_CTS (_MX53_PAD_PATA_INTRQ__UART2_CTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) +#define MX53_PAD_PATA_INTRQ__CAN1_TXCAN (_MX53_PAD_PATA_INTRQ__CAN1_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_INTRQ__CCM_CCM_OUT_2 (_MX53_PAD_PATA_INTRQ__CCM_CCM_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_INTRQ__USBPHY2_DATAOUT_6 (_MX53_PAD_PATA_INTRQ__USBPHY2_DATAOUT_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DIOR__PATA_DIOR (_MX53_PAD_PATA_DIOR__PATA_DIOR | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DIOR__GPIO7_3 (_MX53_PAD_PATA_DIOR__GPIO7_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DIOR__UART2_RTS (_MX53_PAD_PATA_DIOR__UART2_RTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) +#define MX53_PAD_PATA_DIOR__CAN1_RXCAN (_MX53_PAD_PATA_DIOR__CAN1_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DIOR__USBPHY2_DATAOUT_7 (_MX53_PAD_PATA_DIOR__USBPHY2_DATAOUT_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_RESET_B__PATA_PATA_RESET_B (_MX53_PAD_PATA_RESET_B__PATA_PATA_RESET_B | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_RESET_B__GPIO7_4 (_MX53_PAD_PATA_RESET_B__GPIO7_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_RESET_B__ESDHC3_CMD (_MX53_PAD_PATA_RESET_B__ESDHC3_CMD | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) +#define MX53_PAD_PATA_RESET_B__UART1_CTS (_MX53_PAD_PATA_RESET_B__UART1_CTS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_RESET_B__CAN2_TXCAN (_MX53_PAD_PATA_RESET_B__CAN2_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_RESET_B__USBPHY1_DATAOUT_0 (_MX53_PAD_PATA_RESET_B__USBPHY1_DATAOUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_IORDY__PATA_IORDY (_MX53_PAD_PATA_IORDY__PATA_IORDY | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_IORDY__GPIO7_5 (_MX53_PAD_PATA_IORDY__GPIO7_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_IORDY__ESDHC3_CLK (_MX53_PAD_PATA_IORDY__ESDHC3_CLK | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) +#define MX53_PAD_PATA_IORDY__UART1_RTS (_MX53_PAD_PATA_IORDY__UART1_RTS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_IORDY__CAN2_RXCAN (_MX53_PAD_PATA_IORDY__CAN2_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_IORDY__USBPHY1_DATAOUT_1 (_MX53_PAD_PATA_IORDY__USBPHY1_DATAOUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DA_0__PATA_DA_0 (_MX53_PAD_PATA_DA_0__PATA_DA_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DA_0__GPIO7_6 (_MX53_PAD_PATA_DA_0__GPIO7_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DA_0__ESDHC3_RST (_MX53_PAD_PATA_DA_0__ESDHC3_RST | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DA_0__OWIRE_LINE (_MX53_PAD_PATA_DA_0__OWIRE_LINE | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DA_0__USBPHY1_DATAOUT_2 (_MX53_PAD_PATA_DA_0__USBPHY1_DATAOUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DA_1__PATA_DA_1 (_MX53_PAD_PATA_DA_1__PATA_DA_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DA_1__GPIO7_7 (_MX53_PAD_PATA_DA_1__GPIO7_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DA_1__ESDHC4_CMD (_MX53_PAD_PATA_DA_1__ESDHC4_CMD | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) +#define MX53_PAD_PATA_DA_1__UART3_CTS (_MX53_PAD_PATA_DA_1__UART3_CTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) +#define MX53_PAD_PATA_DA_1__USBPHY1_DATAOUT_3 (_MX53_PAD_PATA_DA_1__USBPHY1_DATAOUT_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DA_2__PATA_DA_2 (_MX53_PAD_PATA_DA_2__PATA_DA_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DA_2__GPIO7_8 (_MX53_PAD_PATA_DA_2__GPIO7_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DA_2__ESDHC4_CLK (_MX53_PAD_PATA_DA_2__ESDHC4_CLK | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) +#define MX53_PAD_PATA_DA_2__UART3_RTS (_MX53_PAD_PATA_DA_2__UART3_RTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) +#define MX53_PAD_PATA_DA_2__USBPHY1_DATAOUT_4 (_MX53_PAD_PATA_DA_2__USBPHY1_DATAOUT_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_CS_0__PATA_CS_0 (_MX53_PAD_PATA_CS_0__PATA_CS_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_CS_0__GPIO7_9 (_MX53_PAD_PATA_CS_0__GPIO7_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_CS_0__UART3_TXD_MUX (_MX53_PAD_PATA_CS_0__UART3_TXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) +#define MX53_PAD_PATA_CS_0__USBPHY1_DATAOUT_5 (_MX53_PAD_PATA_CS_0__USBPHY1_DATAOUT_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_CS_1__PATA_CS_1 (_MX53_PAD_PATA_CS_1__PATA_CS_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_CS_1__GPIO7_10 (_MX53_PAD_PATA_CS_1__GPIO7_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_CS_1__UART3_RXD_MUX (_MX53_PAD_PATA_CS_1__UART3_RXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) +#define MX53_PAD_PATA_CS_1__USBPHY1_DATAOUT_6 (_MX53_PAD_PATA_CS_1__USBPHY1_DATAOUT_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA0__PATA_DATA_0 (_MX53_PAD_PATA_DATA0__PATA_DATA_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA0__GPIO2_0 (_MX53_PAD_PATA_DATA0__GPIO2_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 (_MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA0__ESDHC3_DAT4 (_MX53_PAD_PATA_DATA0__ESDHC3_DAT4 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) +#define MX53_PAD_PATA_DATA0__GPU3d_GPU_DEBUG_OUT_0 (_MX53_PAD_PATA_DATA0__GPU3d_GPU_DEBUG_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA0__IPU_DIAG_BUS_0 (_MX53_PAD_PATA_DATA0__IPU_DIAG_BUS_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA0__USBPHY1_DATAOUT_7 (_MX53_PAD_PATA_DATA0__USBPHY1_DATAOUT_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA1__PATA_DATA_1 (_MX53_PAD_PATA_DATA1__PATA_DATA_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA1__GPIO2_1 (_MX53_PAD_PATA_DATA1__GPIO2_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 (_MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA1__ESDHC3_DAT5 (_MX53_PAD_PATA_DATA1__ESDHC3_DAT5 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) +#define MX53_PAD_PATA_DATA1__GPU3d_GPU_DEBUG_OUT_1 (_MX53_PAD_PATA_DATA1__GPU3d_GPU_DEBUG_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA1__IPU_DIAG_BUS_1 (_MX53_PAD_PATA_DATA1__IPU_DIAG_BUS_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA2__PATA_DATA_2 (_MX53_PAD_PATA_DATA2__PATA_DATA_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA2__GPIO2_2 (_MX53_PAD_PATA_DATA2__GPIO2_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 (_MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA2__ESDHC3_DAT6 (_MX53_PAD_PATA_DATA2__ESDHC3_DAT6 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) +#define MX53_PAD_PATA_DATA2__GPU3d_GPU_DEBUG_OUT_2 (_MX53_PAD_PATA_DATA2__GPU3d_GPU_DEBUG_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA2__IPU_DIAG_BUS_2 (_MX53_PAD_PATA_DATA2__IPU_DIAG_BUS_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA3__PATA_DATA_3 (_MX53_PAD_PATA_DATA3__PATA_DATA_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA3__GPIO2_3 (_MX53_PAD_PATA_DATA3__GPIO2_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 (_MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA3__ESDHC3_DAT7 (_MX53_PAD_PATA_DATA3__ESDHC3_DAT7 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) +#define MX53_PAD_PATA_DATA3__GPU3d_GPU_DEBUG_OUT_3 (_MX53_PAD_PATA_DATA3__GPU3d_GPU_DEBUG_OUT_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA3__IPU_DIAG_BUS_3 (_MX53_PAD_PATA_DATA3__IPU_DIAG_BUS_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA4__PATA_DATA_4 (_MX53_PAD_PATA_DATA4__PATA_DATA_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA4__GPIO2_4 (_MX53_PAD_PATA_DATA4__GPIO2_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 (_MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA4__ESDHC4_DAT4 (_MX53_PAD_PATA_DATA4__ESDHC4_DAT4 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) +#define MX53_PAD_PATA_DATA4__GPU3d_GPU_DEBUG_OUT_4 (_MX53_PAD_PATA_DATA4__GPU3d_GPU_DEBUG_OUT_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA4__IPU_DIAG_BUS_4 (_MX53_PAD_PATA_DATA4__IPU_DIAG_BUS_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA5__PATA_DATA_5 (_MX53_PAD_PATA_DATA5__PATA_DATA_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA5__GPIO2_5 (_MX53_PAD_PATA_DATA5__GPIO2_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 (_MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA5__ESDHC4_DAT5 (_MX53_PAD_PATA_DATA5__ESDHC4_DAT5 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) +#define MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5 (_MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5 (_MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA6__PATA_DATA_6 (_MX53_PAD_PATA_DATA6__PATA_DATA_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA6__GPIO2_6 (_MX53_PAD_PATA_DATA6__GPIO2_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 (_MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA6__ESDHC4_DAT6 (_MX53_PAD_PATA_DATA6__ESDHC4_DAT6 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) +#define MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6 (_MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6 (_MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA7__PATA_DATA_7 (_MX53_PAD_PATA_DATA7__PATA_DATA_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA7__GPIO2_7 (_MX53_PAD_PATA_DATA7__GPIO2_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 (_MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA7__ESDHC4_DAT7 (_MX53_PAD_PATA_DATA7__ESDHC4_DAT7 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) +#define MX53_PAD_PATA_DATA7__GPU3d_GPU_DEBUG_OUT_7 (_MX53_PAD_PATA_DATA7__GPU3d_GPU_DEBUG_OUT_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA7__IPU_DIAG_BUS_7 (_MX53_PAD_PATA_DATA7__IPU_DIAG_BUS_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA8__PATA_DATA_8 (_MX53_PAD_PATA_DATA8__PATA_DATA_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA8__GPIO2_8 (_MX53_PAD_PATA_DATA8__GPIO2_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA8__ESDHC1_DAT4 (_MX53_PAD_PATA_DATA8__ESDHC1_DAT4 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) +#define MX53_PAD_PATA_DATA8__EMI_NANDF_D_8 (_MX53_PAD_PATA_DATA8__EMI_NANDF_D_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA8__ESDHC3_DAT0 (_MX53_PAD_PATA_DATA8__ESDHC3_DAT0 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) +#define MX53_PAD_PATA_DATA8__GPU3d_GPU_DEBUG_OUT_8 (_MX53_PAD_PATA_DATA8__GPU3d_GPU_DEBUG_OUT_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA8__IPU_DIAG_BUS_8 (_MX53_PAD_PATA_DATA8__IPU_DIAG_BUS_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA9__PATA_DATA_9 (_MX53_PAD_PATA_DATA9__PATA_DATA_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA9__GPIO2_9 (_MX53_PAD_PATA_DATA9__GPIO2_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA9__ESDHC1_DAT5 (_MX53_PAD_PATA_DATA9__ESDHC1_DAT5 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) +#define MX53_PAD_PATA_DATA9__EMI_NANDF_D_9 (_MX53_PAD_PATA_DATA9__EMI_NANDF_D_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA9__ESDHC3_DAT1 (_MX53_PAD_PATA_DATA9__ESDHC3_DAT1 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) +#define MX53_PAD_PATA_DATA9__GPU3d_GPU_DEBUG_OUT_9 (_MX53_PAD_PATA_DATA9__GPU3d_GPU_DEBUG_OUT_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA9__IPU_DIAG_BUS_9 (_MX53_PAD_PATA_DATA9__IPU_DIAG_BUS_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA10__PATA_DATA_10 (_MX53_PAD_PATA_DATA10__PATA_DATA_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA10__GPIO2_10 (_MX53_PAD_PATA_DATA10__GPIO2_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA10__ESDHC1_DAT6 (_MX53_PAD_PATA_DATA10__ESDHC1_DAT6 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) +#define MX53_PAD_PATA_DATA10__EMI_NANDF_D_10 (_MX53_PAD_PATA_DATA10__EMI_NANDF_D_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA10__ESDHC3_DAT2 (_MX53_PAD_PATA_DATA10__ESDHC3_DAT2 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) +#define MX53_PAD_PATA_DATA10__GPU3d_GPU_DEBUG_OUT_10 (_MX53_PAD_PATA_DATA10__GPU3d_GPU_DEBUG_OUT_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA10__IPU_DIAG_BUS_10 (_MX53_PAD_PATA_DATA10__IPU_DIAG_BUS_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA11__PATA_DATA_11 (_MX53_PAD_PATA_DATA11__PATA_DATA_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA11__GPIO2_11 (_MX53_PAD_PATA_DATA11__GPIO2_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA11__ESDHC1_DAT7 (_MX53_PAD_PATA_DATA11__ESDHC1_DAT7 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) +#define MX53_PAD_PATA_DATA11__EMI_NANDF_D_11 (_MX53_PAD_PATA_DATA11__EMI_NANDF_D_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA11__ESDHC3_DAT3 (_MX53_PAD_PATA_DATA11__ESDHC3_DAT3 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) +#define MX53_PAD_PATA_DATA11__GPU3d_GPU_DEBUG_OUT_11 (_MX53_PAD_PATA_DATA11__GPU3d_GPU_DEBUG_OUT_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA11__IPU_DIAG_BUS_11 (_MX53_PAD_PATA_DATA11__IPU_DIAG_BUS_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA12__PATA_DATA_12 (_MX53_PAD_PATA_DATA12__PATA_DATA_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA12__GPIO2_12 (_MX53_PAD_PATA_DATA12__GPIO2_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA12__ESDHC2_DAT4 (_MX53_PAD_PATA_DATA12__ESDHC2_DAT4 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) +#define MX53_PAD_PATA_DATA12__EMI_NANDF_D_12 (_MX53_PAD_PATA_DATA12__EMI_NANDF_D_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA12__ESDHC4_DAT0 (_MX53_PAD_PATA_DATA12__ESDHC4_DAT0 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) +#define MX53_PAD_PATA_DATA12__GPU3d_GPU_DEBUG_OUT_12 (_MX53_PAD_PATA_DATA12__GPU3d_GPU_DEBUG_OUT_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA12__IPU_DIAG_BUS_12 (_MX53_PAD_PATA_DATA12__IPU_DIAG_BUS_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA13__PATA_DATA_13 (_MX53_PAD_PATA_DATA13__PATA_DATA_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA13__GPIO2_13 (_MX53_PAD_PATA_DATA13__GPIO2_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA13__ESDHC2_DAT5 (_MX53_PAD_PATA_DATA13__ESDHC2_DAT5 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) +#define MX53_PAD_PATA_DATA13__EMI_NANDF_D_13 (_MX53_PAD_PATA_DATA13__EMI_NANDF_D_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA13__ESDHC4_DAT1 (_MX53_PAD_PATA_DATA13__ESDHC4_DAT1 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) +#define MX53_PAD_PATA_DATA13__GPU3d_GPU_DEBUG_OUT_13 (_MX53_PAD_PATA_DATA13__GPU3d_GPU_DEBUG_OUT_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA13__IPU_DIAG_BUS_13 (_MX53_PAD_PATA_DATA13__IPU_DIAG_BUS_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA14__PATA_DATA_14 (_MX53_PAD_PATA_DATA14__PATA_DATA_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA14__GPIO2_14 (_MX53_PAD_PATA_DATA14__GPIO2_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA14__ESDHC2_DAT6 (_MX53_PAD_PATA_DATA14__ESDHC2_DAT6 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) +#define MX53_PAD_PATA_DATA14__EMI_NANDF_D_14 (_MX53_PAD_PATA_DATA14__EMI_NANDF_D_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA14__ESDHC4_DAT2 (_MX53_PAD_PATA_DATA14__ESDHC4_DAT2 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) +#define MX53_PAD_PATA_DATA14__GPU3d_GPU_DEBUG_OUT_14 (_MX53_PAD_PATA_DATA14__GPU3d_GPU_DEBUG_OUT_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA14__IPU_DIAG_BUS_14 (_MX53_PAD_PATA_DATA14__IPU_DIAG_BUS_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA15__PATA_DATA_15 (_MX53_PAD_PATA_DATA15__PATA_DATA_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA15__GPIO2_15 (_MX53_PAD_PATA_DATA15__GPIO2_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA15__ESDHC2_DAT7 (_MX53_PAD_PATA_DATA15__ESDHC2_DAT7 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) +#define MX53_PAD_PATA_DATA15__EMI_NANDF_D_15 (_MX53_PAD_PATA_DATA15__EMI_NANDF_D_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA15__ESDHC4_DAT3 (_MX53_PAD_PATA_DATA15__ESDHC4_DAT3 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) +#define MX53_PAD_PATA_DATA15__GPU3d_GPU_DEBUG_OUT_15 (_MX53_PAD_PATA_DATA15__GPU3d_GPU_DEBUG_OUT_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_PATA_DATA15__IPU_DIAG_BUS_15 (_MX53_PAD_PATA_DATA15__IPU_DIAG_BUS_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD1_DATA0__ESDHC1_DAT0 (_MX53_PAD_SD1_DATA0__ESDHC1_DAT0 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) +#define MX53_PAD_SD1_DATA0__GPIO1_16 (_MX53_PAD_SD1_DATA0__GPIO1_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD1_DATA0__GPT_CAPIN1 (_MX53_PAD_SD1_DATA0__GPT_CAPIN1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD1_DATA0__CSPI_MISO (_MX53_PAD_SD1_DATA0__CSPI_MISO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD1_DATA0__CCM_PLL3_BYP (_MX53_PAD_SD1_DATA0__CCM_PLL3_BYP | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD1_DATA1__ESDHC1_DAT1 (_MX53_PAD_SD1_DATA1__ESDHC1_DAT1 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) +#define MX53_PAD_SD1_DATA1__GPIO1_17 (_MX53_PAD_SD1_DATA1__GPIO1_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD1_DATA1__GPT_CAPIN2 (_MX53_PAD_SD1_DATA1__GPT_CAPIN2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD1_DATA1__CSPI_SS0 (_MX53_PAD_SD1_DATA1__CSPI_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD1_DATA1__CCM_PLL4_BYP (_MX53_PAD_SD1_DATA1__CCM_PLL4_BYP | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD1_CMD__ESDHC1_CMD (_MX53_PAD_SD1_CMD__ESDHC1_CMD | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) +#define MX53_PAD_SD1_CMD__GPIO1_18 (_MX53_PAD_SD1_CMD__GPIO1_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD1_CMD__GPT_CMPOUT1 (_MX53_PAD_SD1_CMD__GPT_CMPOUT1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD1_CMD__CSPI_MOSI (_MX53_PAD_SD1_CMD__CSPI_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD1_CMD__CCM_PLL1_BYP (_MX53_PAD_SD1_CMD__CCM_PLL1_BYP | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD1_DATA2__ESDHC1_DAT2 (_MX53_PAD_SD1_DATA2__ESDHC1_DAT2 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) +#define MX53_PAD_SD1_DATA2__GPIO1_19 (_MX53_PAD_SD1_DATA2__GPIO1_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD1_DATA2__GPT_CMPOUT2 (_MX53_PAD_SD1_DATA2__GPT_CMPOUT2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD1_DATA2__PWM2_PWMO (_MX53_PAD_SD1_DATA2__PWM2_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD1_DATA2__WDOG1_WDOG_B (_MX53_PAD_SD1_DATA2__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD1_DATA2__CSPI_SS1 (_MX53_PAD_SD1_DATA2__CSPI_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD1_DATA2__WDOG1_WDOG_RST_B_DEB (_MX53_PAD_SD1_DATA2__WDOG1_WDOG_RST_B_DEB | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD1_DATA2__CCM_PLL2_BYP (_MX53_PAD_SD1_DATA2__CCM_PLL2_BYP | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD1_CLK__ESDHC1_CLK (_MX53_PAD_SD1_CLK__ESDHC1_CLK | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) +#define MX53_PAD_SD1_CLK__GPIO1_20 (_MX53_PAD_SD1_CLK__GPIO1_20 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD1_CLK__OSC32k_32K_OUT (_MX53_PAD_SD1_CLK__OSC32k_32K_OUT | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD1_CLK__GPT_CLKIN (_MX53_PAD_SD1_CLK__GPT_CLKIN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD1_CLK__CSPI_SCLK (_MX53_PAD_SD1_CLK__CSPI_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD1_CLK__SATA_PHY_DTB_0 (_MX53_PAD_SD1_CLK__SATA_PHY_DTB_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD1_DATA3__ESDHC1_DAT3 (_MX53_PAD_SD1_DATA3__ESDHC1_DAT3 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) +#define MX53_PAD_SD1_DATA3__GPIO1_21 (_MX53_PAD_SD1_DATA3__GPIO1_21 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD1_DATA3__GPT_CMPOUT3 (_MX53_PAD_SD1_DATA3__GPT_CMPOUT3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD1_DATA3__PWM1_PWMO (_MX53_PAD_SD1_DATA3__PWM1_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD1_DATA3__WDOG2_WDOG_B (_MX53_PAD_SD1_DATA3__WDOG2_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD1_DATA3__CSPI_SS2 (_MX53_PAD_SD1_DATA3__CSPI_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD1_DATA3__WDOG2_WDOG_RST_B_DEB (_MX53_PAD_SD1_DATA3__WDOG2_WDOG_RST_B_DEB | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD1_DATA3__SATA_PHY_DTB_1 (_MX53_PAD_SD1_DATA3__SATA_PHY_DTB_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD2_CLK__ESDHC2_CLK (_MX53_PAD_SD2_CLK__ESDHC2_CLK | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) +#define MX53_PAD_SD2_CLK__GPIO1_10 (_MX53_PAD_SD2_CLK__GPIO1_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD2_CLK__KPP_COL_5 (_MX53_PAD_SD2_CLK__KPP_COL_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD2_CLK__AUDMUX_AUD4_RXFS (_MX53_PAD_SD2_CLK__AUDMUX_AUD4_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD2_CLK__CSPI_SCLK (_MX53_PAD_SD2_CLK__CSPI_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD2_CLK__SCC_RANDOM_V (_MX53_PAD_SD2_CLK__SCC_RANDOM_V | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD2_CMD__ESDHC2_CMD (_MX53_PAD_SD2_CMD__ESDHC2_CMD | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) +#define MX53_PAD_SD2_CMD__GPIO1_11 (_MX53_PAD_SD2_CMD__GPIO1_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD2_CMD__KPP_ROW_5 (_MX53_PAD_SD2_CMD__KPP_ROW_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD2_CMD__AUDMUX_AUD4_RXC (_MX53_PAD_SD2_CMD__AUDMUX_AUD4_RXC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD2_CMD__CSPI_MOSI (_MX53_PAD_SD2_CMD__CSPI_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD2_CMD__SCC_RANDOM (_MX53_PAD_SD2_CMD__SCC_RANDOM | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD2_DATA3__ESDHC2_DAT3 (_MX53_PAD_SD2_DATA3__ESDHC2_DAT3 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) +#define MX53_PAD_SD2_DATA3__GPIO1_12 (_MX53_PAD_SD2_DATA3__GPIO1_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD2_DATA3__KPP_COL_6 (_MX53_PAD_SD2_DATA3__KPP_COL_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC (_MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD2_DATA3__CSPI_SS2 (_MX53_PAD_SD2_DATA3__CSPI_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD2_DATA3__SJC_DONE (_MX53_PAD_SD2_DATA3__SJC_DONE | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD2_DATA2__ESDHC2_DAT2 (_MX53_PAD_SD2_DATA2__ESDHC2_DAT2 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) +#define MX53_PAD_SD2_DATA2__GPIO1_13 (_MX53_PAD_SD2_DATA2__GPIO1_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD2_DATA2__KPP_ROW_6 (_MX53_PAD_SD2_DATA2__KPP_ROW_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD (_MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD2_DATA2__CSPI_SS1 (_MX53_PAD_SD2_DATA2__CSPI_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD2_DATA2__SJC_FAIL (_MX53_PAD_SD2_DATA2__SJC_FAIL | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD2_DATA1__ESDHC2_DAT1 (_MX53_PAD_SD2_DATA1__ESDHC2_DAT1 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) +#define MX53_PAD_SD2_DATA1__GPIO1_14 (_MX53_PAD_SD2_DATA1__GPIO1_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD2_DATA1__KPP_COL_7 (_MX53_PAD_SD2_DATA1__KPP_COL_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS (_MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD2_DATA1__CSPI_SS0 (_MX53_PAD_SD2_DATA1__CSPI_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD2_DATA1__RTIC_SEC_VIO (_MX53_PAD_SD2_DATA1__RTIC_SEC_VIO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD2_DATA0__ESDHC2_DAT0 (_MX53_PAD_SD2_DATA0__ESDHC2_DAT0 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) +#define MX53_PAD_SD2_DATA0__GPIO1_15 (_MX53_PAD_SD2_DATA0__GPIO1_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD2_DATA0__KPP_ROW_7 (_MX53_PAD_SD2_DATA0__KPP_ROW_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD (_MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD2_DATA0__CSPI_MISO (_MX53_PAD_SD2_DATA0__CSPI_MISO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_SD2_DATA0__RTIC_DONE_INT (_MX53_PAD_SD2_DATA0__RTIC_DONE_INT | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_0__CCM_CLKO (_MX53_PAD_GPIO_0__CCM_CLKO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_0__GPIO1_0 (_MX53_PAD_GPIO_0__GPIO1_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_0__KPP_COL_5 (_MX53_PAD_GPIO_0__KPP_COL_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK (_MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_0__EPIT1_EPITO (_MX53_PAD_GPIO_0__EPIT1_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_0__SRTC_ALARM_DEB (_MX53_PAD_GPIO_0__SRTC_ALARM_DEB | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_0__USBOH3_USBH1_PWR (_MX53_PAD_GPIO_0__USBOH3_USBH1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_0__CSU_TD (_MX53_PAD_GPIO_0__CSU_TD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_1__ESAI1_SCKR (_MX53_PAD_GPIO_1__ESAI1_SCKR | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_1__GPIO1_1 (_MX53_PAD_GPIO_1__GPIO1_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_1__KPP_ROW_5 (_MX53_PAD_GPIO_1__KPP_ROW_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_1__CCM_SSI_EXT2_CLK (_MX53_PAD_GPIO_1__CCM_SSI_EXT2_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_1__PWM2_PWMO (_MX53_PAD_GPIO_1__PWM2_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_1__WDOG2_WDOG_B (_MX53_PAD_GPIO_1__WDOG2_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_1__ESDHC1_CD (_MX53_PAD_GPIO_1__ESDHC1_CD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_1__SRC_TESTER_ACK (_MX53_PAD_GPIO_1__SRC_TESTER_ACK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_9__ESAI1_FSR (_MX53_PAD_GPIO_9__ESAI1_FSR | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_9__GPIO1_9 (_MX53_PAD_GPIO_9__GPIO1_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_9__KPP_COL_6 (_MX53_PAD_GPIO_9__KPP_COL_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_9__CCM_REF_EN_B (_MX53_PAD_GPIO_9__CCM_REF_EN_B | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_9__PWM1_PWMO (_MX53_PAD_GPIO_9__PWM1_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_9__WDOG1_WDOG_B (_MX53_PAD_GPIO_9__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_9__ESDHC1_WP (_MX53_PAD_GPIO_9__ESDHC1_WP | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_9__SCC_FAIL_STATE (_MX53_PAD_GPIO_9__SCC_FAIL_STATE | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_3__ESAI1_HCKR (_MX53_PAD_GPIO_3__ESAI1_HCKR | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_3__GPIO1_3 (_MX53_PAD_GPIO_3__GPIO1_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_3__I2C3_SCL (_MX53_PAD_GPIO_3__I2C3_SCL | MUX_PAD_CTRL(PAD_CTRL_I2C)) +#define MX53_PAD_GPIO_3__DPLLIP1_TOG_EN (_MX53_PAD_GPIO_3__DPLLIP1_TOG_EN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_3__CCM_CLKO2 (_MX53_PAD_GPIO_3__CCM_CLKO2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 (_MX53_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_3__USBOH3_USBH1_OC (_MX53_PAD_GPIO_3__USBOH3_USBH1_OC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_3__MLB_MLBCLK (_MX53_PAD_GPIO_3__MLB_MLBCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_6__ESAI1_SCKT (_MX53_PAD_GPIO_6__ESAI1_SCKT | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_6__GPIO1_6 (_MX53_PAD_GPIO_6__GPIO1_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_6__I2C3_SDA (_MX53_PAD_GPIO_6__I2C3_SDA | MUX_PAD_CTRL(PAD_CTRL_I2C)) +#define MX53_PAD_GPIO_6__CCM_CCM_OUT_0 (_MX53_PAD_GPIO_6__CCM_CCM_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_6__CSU_CSU_INT_DEB (_MX53_PAD_GPIO_6__CSU_CSU_INT_DEB | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 (_MX53_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_6__ESDHC2_LCTL (_MX53_PAD_GPIO_6__ESDHC2_LCTL | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_6__MLB_MLBSIG (_MX53_PAD_GPIO_6__MLB_MLBSIG | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_2__ESAI1_FST (_MX53_PAD_GPIO_2__ESAI1_FST | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_2__GPIO1_2 (_MX53_PAD_GPIO_2__GPIO1_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_2__KPP_ROW_6 (_MX53_PAD_GPIO_2__KPP_ROW_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_2__CCM_CCM_OUT_1 (_MX53_PAD_GPIO_2__CCM_CCM_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 (_MX53_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 (_MX53_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_2__ESDHC2_WP (_MX53_PAD_GPIO_2__ESDHC2_WP | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_2__MLB_MLBDAT (_MX53_PAD_GPIO_2__MLB_MLBDAT | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_4__ESAI1_HCKT (_MX53_PAD_GPIO_4__ESAI1_HCKT | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_4__GPIO1_4 (_MX53_PAD_GPIO_4__GPIO1_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_4__KPP_COL_7 (_MX53_PAD_GPIO_4__KPP_COL_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_4__CCM_CCM_OUT_2 (_MX53_PAD_GPIO_4__CCM_CCM_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 (_MX53_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 (_MX53_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_4__ESDHC2_CD (_MX53_PAD_GPIO_4__ESDHC2_CD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_4__SCC_SEC_STATE (_MX53_PAD_GPIO_4__SCC_SEC_STATE | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_5__ESAI1_TX2_RX3 (_MX53_PAD_GPIO_5__ESAI1_TX2_RX3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_5__GPIO1_5 (_MX53_PAD_GPIO_5__GPIO1_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_5__KPP_ROW_7 (_MX53_PAD_GPIO_5__KPP_ROW_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_5__CCM_CLKO (_MX53_PAD_GPIO_5__CCM_CLKO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 (_MX53_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 (_MX53_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_5__I2C3_SCL (_MX53_PAD_GPIO_5__I2C3_SCL | MUX_PAD_CTRL(PAD_CTRL_I2C)) +#define MX53_PAD_GPIO_5__CCM_PLL1_BYP (_MX53_PAD_GPIO_5__CCM_PLL1_BYP | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_7__ESAI1_TX4_RX1 (_MX53_PAD_GPIO_7__ESAI1_TX4_RX1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_7__GPIO1_7 (_MX53_PAD_GPIO_7__GPIO1_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_7__EPIT1_EPITO (_MX53_PAD_GPIO_7__EPIT1_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_7__CAN1_TXCAN (_MX53_PAD_GPIO_7__CAN1_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_7__UART2_TXD_MUX (_MX53_PAD_GPIO_7__UART2_TXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_7__FIRI_RXD (_MX53_PAD_GPIO_7__FIRI_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_7__SPDIF_PLOCK (_MX53_PAD_GPIO_7__SPDIF_PLOCK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_7__CCM_PLL2_BYP (_MX53_PAD_GPIO_7__CCM_PLL2_BYP | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_8__ESAI1_TX5_RX0 (_MX53_PAD_GPIO_8__ESAI1_TX5_RX0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_8__GPIO1_8 (_MX53_PAD_GPIO_8__GPIO1_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_8__EPIT2_EPITO (_MX53_PAD_GPIO_8__EPIT2_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_8__CAN1_RXCAN (_MX53_PAD_GPIO_8__CAN1_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_8__UART2_RXD_MUX (_MX53_PAD_GPIO_8__UART2_RXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_8__FIRI_TXD (_MX53_PAD_GPIO_8__FIRI_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_8__SPDIF_SRCLK (_MX53_PAD_GPIO_8__SPDIF_SRCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_8__CCM_PLL3_BYP (_MX53_PAD_GPIO_8__CCM_PLL3_BYP | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_16__ESAI1_TX3_RX2 (_MX53_PAD_GPIO_16__ESAI1_TX3_RX2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_16__GPIO7_11 (_MX53_PAD_GPIO_16__GPIO7_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_16__TZIC_PWRFAIL_INT (_MX53_PAD_GPIO_16__TZIC_PWRFAIL_INT | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_16__RTC_CE_RTC_EXT_TRIG1 (_MX53_PAD_GPIO_16__RTC_CE_RTC_EXT_TRIG1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_16__SPDIF_IN1 (_MX53_PAD_GPIO_16__SPDIF_IN1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_16__I2C3_SDA (_MX53_PAD_GPIO_16__I2C3_SDA | MUX_PAD_CTRL(PAD_CTRL_I2C)) +#define MX53_PAD_GPIO_16__SJC_DE_B (_MX53_PAD_GPIO_16__SJC_DE_B | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_17__ESAI1_TX0 (_MX53_PAD_GPIO_17__ESAI1_TX0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_17__GPIO7_12 (_MX53_PAD_GPIO_17__GPIO7_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_17__SDMA_EXT_EVENT_0 (_MX53_PAD_GPIO_17__SDMA_EXT_EVENT_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_17__GPC_PMIC_RDY (_MX53_PAD_GPIO_17__GPC_PMIC_RDY | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_17__RTC_CE_RTC_FSV_TRIG (_MX53_PAD_GPIO_17__RTC_CE_RTC_FSV_TRIG | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_17__SPDIF_OUT1 (_MX53_PAD_GPIO_17__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_17__IPU_SNOOP2 (_MX53_PAD_GPIO_17__IPU_SNOOP2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_17__SJC_JTAG_ACT (_MX53_PAD_GPIO_17__SJC_JTAG_ACT | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_18__ESAI1_TX1 (_MX53_PAD_GPIO_18__ESAI1_TX1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_18__GPIO7_13 (_MX53_PAD_GPIO_18__GPIO7_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_18__SDMA_EXT_EVENT_1 (_MX53_PAD_GPIO_18__SDMA_EXT_EVENT_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_18__OWIRE_LINE (_MX53_PAD_GPIO_18__OWIRE_LINE | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_18__RTC_CE_RTC_ALARM2_TRIG (_MX53_PAD_GPIO_18__RTC_CE_RTC_ALARM2_TRIG | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_18__CCM_ASRC_EXT_CLK (_MX53_PAD_GPIO_18__CCM_ASRC_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_18__ESDHC1_LCTL (_MX53_PAD_GPIO_18__ESDHC1_LCTL | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_18__SRC_SYSTEM_RST (_MX53_PAD_GPIO_18__SRC_SYSTEM_RST | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#endif /* __MACH_IOMUX_MX53_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx6dl.h b/arch/arm/plat-mxc/include/mach/iomux-mx6dl.h new file mode 100644 index 00000000..645b0b50 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/iomux-mx6dl.h @@ -0,0 +1,3840 @@ +/* + * Copyright (C) 2012-2013 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Auto Generate file, please don't edit it + * + */ + +#ifndef __MACH_IOMUX_MX6DL_H__ +#define __MACH_IOMUX_MX6DL_H__ + +#include <mach/iomux-v3.h> + +#define MX6DL_HIGH_DRV PAD_CTL_DSE_120ohm +#define MX6DL_DISP_PAD_CLT MX6DL_HIGH_DRV + +#define MX6DL_CCM_CLK0_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define MX6DL_MLB150_PAD_CTRL (PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) \ + +#define MX6DL_UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define MX6DL_USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define MX6DL_USDHC_PAD_CTRL_50MHZ_40OHM (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define MX6DL_USDHC_PAD_CTRL_100MHZ (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define MX6DL_USDHC_PAD_CTRL_200MHZ (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \ + PAD_CTL_DSE_34ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define MX6DL_ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define MX6DL_ENET_REF_CLK_PAD_CTRL (PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define MX6DL_I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | \ + PAD_CTL_HYS | PAD_CTL_ODE) + +#define MX6DL_ESAI_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define MX6DL_USB_HSIC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define MX6DL_ECSPI_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define MX6DL_WEIM_NOR_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_40ohm | \ + PAD_CTL_SPEED_MED | PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP) + +#define MX6DL_ADU_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_DSE_40ohm | PAD_CTL_PUS_100K_DOWN | \ + PAD_CTL_HYS | PAD_CTL_SPEED_MED) + +#define MX6DL_HDMICEC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \ + PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_ODE | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_SLOW) + +#define MX6DL_GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) +#define MX6DL_GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | PAD_CTL_SRE_FAST) +#define MX6DL_GPMI_PAD_CTRL2 (MX6DL_GPMI_PAD_CTRL0 | MX6DL_GPMI_PAD_CTRL1) +#define MX6DL_SPDIF_OUT_PAD_CTRL (PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST) + +#define ENET_IRQ_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_40ohm | \ + PAD_CTL_SPEED_MED) + +#define MX6DL_PAD_CSI0_DAT10__IPU1_CSI0_D_10 \ + IOMUX_PAD(0x0360, 0x004C, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC \ + IOMUX_PAD(0x0360, 0x004C, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT10__ECSPI2_MISO \ + IOMUX_PAD(0x0360, 0x004C, 2, 0x07F8, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT10__UART1_TXD \ + IOMUX_PAD(0x0360, 0x004C, 3, 0x0000, 0, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT10__UART1_RXD \ + IOMUX_PAD(0x0360, 0x004C, 3, 0x08FC, 0, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 \ + IOMUX_PAD(0x0360, 0x004C, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT10__GPIO_5_28 \ + IOMUX_PAD(0x0360, 0x004C, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33 \ + IOMUX_PAD(0x0360, 0x004C, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT10__SIMBA_TRACE_7 \ + IOMUX_PAD(0x0360, 0x004C, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_CSI0_DAT11__IPU1_CSI0_D_11 \ + IOMUX_PAD(0x0364, 0x0050, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS \ + IOMUX_PAD(0x0364, 0x0050, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT11__ECSPI2_SS0 \ + IOMUX_PAD(0x0364, 0x0050, 2, 0x0800, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT11__UART1_TXD \ + IOMUX_PAD(0x0364, 0x0050, 3, 0x0000, 0, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT11__UART1_RXD \ + IOMUX_PAD(0x0364, 0x0050, 3, 0x08FC, 1, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 \ + IOMUX_PAD(0x0364, 0x0050, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT11__GPIO_5_29 \ + IOMUX_PAD(0x0364, 0x0050, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34 \ + IOMUX_PAD(0x0364, 0x0050, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT11__SIMBA_TRACE_8 \ + IOMUX_PAD(0x0364, 0x0050, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_CSI0_DAT12__IPU1_CSI0_D_12 \ + IOMUX_PAD(0x0368, 0x0054, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT12__WEIM_WEIM_D_8 \ + IOMUX_PAD(0x0368, 0x0054, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT12__PCIE_CTRL_DIAG_STATUS_BUS_MUX_16 \ + IOMUX_PAD(0x0368, 0x0054, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT12__UART4_TXD \ + IOMUX_PAD(0x0368, 0x0054, 3, 0x0000, 0, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT12__UART4_RXD \ + IOMUX_PAD(0x0368, 0x0054, 3, 0x0914, 0, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 \ + IOMUX_PAD(0x0368, 0x0054, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT12__GPIO_5_30 \ + IOMUX_PAD(0x0368, 0x0054, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35 \ + IOMUX_PAD(0x0368, 0x0054, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT12__SIMBA_TRACE_9 \ + IOMUX_PAD(0x0368, 0x0054, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_CSI0_DAT13__IPU1_CSI0_D_13 \ + IOMUX_PAD(0x036C, 0x0058, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT13__WEIM_WEIM_D_9 \ + IOMUX_PAD(0x036C, 0x0058, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT13__PCIE_CTRL_DIAG_STATUS_BUS_MUX_17 \ + IOMUX_PAD(0x036C, 0x0058, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT13__UART4_TXD \ + IOMUX_PAD(0x036C, 0x0058, 3, 0x0000, 0, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT13__UART4_RXD \ + IOMUX_PAD(0x036C, 0x0058, 3, 0x0914, 1, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 \ + IOMUX_PAD(0x036C, 0x0058, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT13__GPIO_5_31 \ + IOMUX_PAD(0x036C, 0x0058, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36 \ + IOMUX_PAD(0x036C, 0x0058, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT13__SIMBA_TRACE_10 \ + IOMUX_PAD(0x036C, 0x0058, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_CSI0_DAT14__IPU1_CSI0_D_14 \ + IOMUX_PAD(0x0370, 0x005C, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT14__WEIM_WEIM_D_10 \ + IOMUX_PAD(0x0370, 0x005C, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT14__PCIE_CTRL_DIAG_STATUS_BUS_MUX_18 \ + IOMUX_PAD(0x0370, 0x005C, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT14__UART5_TXD \ + IOMUX_PAD(0x0370, 0x005C, 3, 0x0000, 0, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT14__UART5_RXD \ + IOMUX_PAD(0x0370, 0x005C, 3, 0x091C, 0, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 \ + IOMUX_PAD(0x0370, 0x005C, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT14__GPIO_6_0 \ + IOMUX_PAD(0x0370, 0x005C, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37 \ + IOMUX_PAD(0x0370, 0x005C, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT14__SIMBA_TRACE_11 \ + IOMUX_PAD(0x0370, 0x005C, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_CSI0_DAT15__IPU1_CSI0_D_15 \ + IOMUX_PAD(0x0374, 0x0060, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT15__WEIM_WEIM_D_11 \ + IOMUX_PAD(0x0374, 0x0060, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT15__PCIE_CTRL_DIAG_STATUS_BUS_MUX_19 \ + IOMUX_PAD(0x0374, 0x0060, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT15__UART5_TXD \ + IOMUX_PAD(0x0374, 0x0060, 3, 0x0000, 0, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT15__UART5_RXD \ + IOMUX_PAD(0x0374, 0x0060, 3, 0x091C, 1, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 \ + IOMUX_PAD(0x0374, 0x0060, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT15__GPIO_6_1 \ + IOMUX_PAD(0x0374, 0x0060, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38 \ + IOMUX_PAD(0x0374, 0x0060, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT15__SIMBA_TRACE_12 \ + IOMUX_PAD(0x0374, 0x0060, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_CSI0_DAT16__IPU1_CSI0_D_16 \ + IOMUX_PAD(0x0378, 0x0064, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT16__WEIM_WEIM_D_12 \ + IOMUX_PAD(0x0378, 0x0064, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT16__PCIE_CTRL_DIAG_STATUS_BUS_MUX_20 \ + IOMUX_PAD(0x0378, 0x0064, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT16__UART4_CTS \ + IOMUX_PAD(0x0378, 0x0064, 3, 0x0000, 0, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT16__UART4_RTS \ + IOMUX_PAD(0x0378, 0x0064, 3, 0x0910, 0, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 \ + IOMUX_PAD(0x0378, 0x0064, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT16__GPIO_6_2 \ + IOMUX_PAD(0x0378, 0x0064, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39 \ + IOMUX_PAD(0x0378, 0x0064, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT16__SIMBA_TRACE_13 \ + IOMUX_PAD(0x0378, 0x0064, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_CSI0_DAT17__IPU1_CSI0_D_17 \ + IOMUX_PAD(0x037C, 0x0068, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT17__WEIM_WEIM_D_13 \ + IOMUX_PAD(0x037C, 0x0068, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT17__PCIE_CTRL_DIAG_STATUS_BUS_MUX_21 \ + IOMUX_PAD(0x037C, 0x0068, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT17__UART4_CTS \ + IOMUX_PAD(0x037C, 0x0068, 3, 0x0000, 0, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT17__UART4_RTS \ + IOMUX_PAD(0x037C, 0x0068, 3, 0x0910, 1, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 \ + IOMUX_PAD(0x037C, 0x0068, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT17__GPIO_6_3 \ + IOMUX_PAD(0x037C, 0x0068, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40 \ + IOMUX_PAD(0x037C, 0x0068, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT17__SIMBA_TRACE_14 \ + IOMUX_PAD(0x037C, 0x0068, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_CSI0_DAT18__IPU1_CSI0_D_18 \ + IOMUX_PAD(0x0380, 0x006C, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT18__WEIM_WEIM_D_14 \ + IOMUX_PAD(0x0380, 0x006C, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT18__PCIE_CTRL_DIAG_STATUS_BUS_MUX_22 \ + IOMUX_PAD(0x0380, 0x006C, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT18__UART5_CTS \ + IOMUX_PAD(0x0380, 0x006C, 3, 0x0000, 0, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT18__UART5_RTS \ + IOMUX_PAD(0x0380, 0x006C, 3, 0x0918, 0, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 \ + IOMUX_PAD(0x0380, 0x006C, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT18__GPIO_6_4 \ + IOMUX_PAD(0x0380, 0x006C, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41 \ + IOMUX_PAD(0x0380, 0x006C, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT18__SIMBA_TRACE_15 \ + IOMUX_PAD(0x0380, 0x006C, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_CSI0_DAT19__IPU1_CSI0_D_19 \ + IOMUX_PAD(0x0384, 0x0070, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT19__WEIM_WEIM_D_15 \ + IOMUX_PAD(0x0384, 0x0070, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT19__PCIE_CTRL_DIAG_STATUS_BUS_MUX_23 \ + IOMUX_PAD(0x0384, 0x0070, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT19__UART5_CTS \ + IOMUX_PAD(0x0384, 0x0070, 3, 0x0000, 0, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT19__UART5_RTS \ + IOMUX_PAD(0x0384, 0x0070, 3, 0x0918, 1, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 \ + IOMUX_PAD(0x0384, 0x0070, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT19__GPIO_6_5 \ + IOMUX_PAD(0x0384, 0x0070, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42 \ + IOMUX_PAD(0x0384, 0x0070, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT19__ANATOP_ANATOP_TESTO_9 \ + IOMUX_PAD(0x0384, 0x0070, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_CSI0_DAT4__IPU1_CSI0_D_4 \ + IOMUX_PAD(0x0388, 0x0074, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT4__WEIM_WEIM_D_2 \ + IOMUX_PAD(0x0388, 0x0074, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT4__ECSPI1_SCLK \ + IOMUX_PAD(0x0388, 0x0074, 2, 0x07D8, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT4__KPP_COL_5 \ + IOMUX_PAD(0x0388, 0x0074, 3, 0x08C0, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC \ + IOMUX_PAD(0x0388, 0x0074, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT4__GPIO_5_22 \ + IOMUX_PAD(0x0388, 0x0074, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT4__MMDC_MMDC_DEBUG_43 \ + IOMUX_PAD(0x0388, 0x0074, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT4__SIMBA_TRACE_1 \ + IOMUX_PAD(0x0388, 0x0074, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_CSI0_DAT5__IPU1_CSI0_D_5 \ + IOMUX_PAD(0x038C, 0x0078, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT5__WEIM_WEIM_D_3 \ + IOMUX_PAD(0x038C, 0x0078, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT5__ECSPI1_MOSI \ + IOMUX_PAD(0x038C, 0x0078, 2, 0x07E0, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT5__KPP_ROW_5 \ + IOMUX_PAD(0x038C, 0x0078, 3, 0x08CC, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD \ + IOMUX_PAD(0x038C, 0x0078, 4, 0x0000, 0, MX6DL_ADU_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT5__GPIO_5_23 \ + IOMUX_PAD(0x038C, 0x0078, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44 \ + IOMUX_PAD(0x038C, 0x0078, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT5__SIMBA_TRACE_2 \ + IOMUX_PAD(0x038C, 0x0078, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_CSI0_DAT6__IPU1_CSI0_D_6 \ + IOMUX_PAD(0x0390, 0x007C, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT6__WEIM_WEIM_D_4 \ + IOMUX_PAD(0x0390, 0x007C, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT6__ECSPI1_MISO \ + IOMUX_PAD(0x0390, 0x007C, 2, 0x07DC, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT6__KPP_COL_6 \ + IOMUX_PAD(0x0390, 0x007C, 3, 0x08C4, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS \ + IOMUX_PAD(0x0390, 0x007C, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT6__GPIO_5_24 \ + IOMUX_PAD(0x0390, 0x007C, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45 \ + IOMUX_PAD(0x0390, 0x007C, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT6__SIMBA_TRACE_3 \ + IOMUX_PAD(0x0390, 0x007C, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_CSI0_DAT7__IPU1_CSI0_D_7 \ + IOMUX_PAD(0x0394, 0x0080, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT7__WEIM_WEIM_D_5 \ + IOMUX_PAD(0x0394, 0x0080, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT7__ECSPI1_SS0 \ + IOMUX_PAD(0x0394, 0x0080, 2, 0x07E4, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT7__KPP_ROW_6 \ + IOMUX_PAD(0x0394, 0x0080, 3, 0x08D0, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD \ + IOMUX_PAD(0x0394, 0x0080, 4, 0x0000, 0, MX6DL_ADU_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT7__GPIO_5_25 \ + IOMUX_PAD(0x0394, 0x0080, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46 \ + IOMUX_PAD(0x0394, 0x0080, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT7__SIMBA_TRACE_4 \ + IOMUX_PAD(0x0394, 0x0080, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_CSI0_DAT8__IPU1_CSI0_D_8 \ + IOMUX_PAD(0x0398, 0x0084, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT8__WEIM_WEIM_D_6 \ + IOMUX_PAD(0x0398, 0x0084, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT8__ECSPI2_SCLK \ + IOMUX_PAD(0x0398, 0x0084, 2, 0x07F4, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT8__KPP_COL_7 \ + IOMUX_PAD(0x0398, 0x0084, 3, 0x08C8, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT8__I2C1_SDA \ + IOMUX_PAD(0x0398, 0x0084, 4 | IOMUX_CONFIG_SION, 0x086C, 0, MX6DL_I2C_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT8__GPIO_5_26 \ + IOMUX_PAD(0x0398, 0x0084, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47 \ + IOMUX_PAD(0x0398, 0x0084, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT8__SIMBA_TRACE_5 \ + IOMUX_PAD(0x0398, 0x0084, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_CSI0_DAT9__IPU1_CSI0_D_9 \ + IOMUX_PAD(0x039C, 0x0088, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT9__WEIM_WEIM_D_7 \ + IOMUX_PAD(0x039C, 0x0088, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT9__ECSPI2_MOSI \ + IOMUX_PAD(0x039C, 0x0088, 2, 0x07FC, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT9__KPP_ROW_7 \ + IOMUX_PAD(0x039C, 0x0088, 3, 0x08D4, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT9__I2C1_SCL \ + IOMUX_PAD(0x039C, 0x0088, 4 | IOMUX_CONFIG_SION, 0x0868, 0, MX6DL_I2C_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT9__GPIO_5_27 \ + IOMUX_PAD(0x039C, 0x0088, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48 \ + IOMUX_PAD(0x039C, 0x0088, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DAT9__SIMBA_TRACE_6 \ + IOMUX_PAD(0x039C, 0x0088, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN \ + IOMUX_PAD(0x03A0, 0x008C, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0 \ + IOMUX_PAD(0x03A0, 0x008C, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DATA_EN__PCIE_CTRL_DIAG_STATUS_BUS_MUX_14 \ + IOMUX_PAD(0x03A0, 0x008C, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 \ + IOMUX_PAD(0x03A0, 0x008C, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DATA_EN__GPIO_5_20 \ + IOMUX_PAD(0x03A0, 0x008C, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DATA_EN__MMDC_MMDC_DEBUG_31 \ + IOMUX_PAD(0x03A0, 0x008C, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_DATA_EN__SIMBA_TRCLK \ + IOMUX_PAD(0x03A0, 0x008C, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC \ + IOMUX_PAD(0x03A4, 0x0090, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_MCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_13 \ + IOMUX_PAD(0x03A4, 0x0090, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_MCLK__CCM_CLKO \ + IOMUX_PAD(0x03A4, 0x0090, 3, 0x0000, 0, MX6DL_CCM_CLK0_PAD_CTRL) +#define MX6DL_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 \ + IOMUX_PAD(0x03A4, 0x0090, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_MCLK__GPIO_5_19 \ + IOMUX_PAD(0x03A4, 0x0090, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30 \ + IOMUX_PAD(0x03A4, 0x0090, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_MCLK__SIMBA_TRCTL \ + IOMUX_PAD(0x03A4, 0x0090, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK \ + IOMUX_PAD(0x03A8, 0x0094, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_PIXCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_12 \ + IOMUX_PAD(0x03A8, 0x0094, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 \ + IOMUX_PAD(0x03A8, 0x0094, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_PIXCLK__GPIO_5_18 \ + IOMUX_PAD(0x03A8, 0x0094, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_PIXCLK__MMDC_MMDC_DEBUG_29 \ + IOMUX_PAD(0x03A8, 0x0094, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_PIXCLK__SIMBA_EVENTO \ + IOMUX_PAD(0x03A8, 0x0094, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC \ + IOMUX_PAD(0x03AC, 0x0098, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_VSYNC__WEIM_WEIM_D_1 \ + IOMUX_PAD(0x03AC, 0x0098, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_VSYNC__PCIE_CTRL_DIAG_STATUS_BUS_MUX_15 \ + IOMUX_PAD(0x03AC, 0x0098, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 \ + IOMUX_PAD(0x03AC, 0x0098, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_VSYNC__GPIO_5_21 \ + IOMUX_PAD(0x03AC, 0x0098, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_VSYNC__MMDC_MMDC_DEBUG_32 \ + IOMUX_PAD(0x03AC, 0x0098, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_CSI0_VSYNC__SIMBA_TRACE_0 \ + IOMUX_PAD(0x03AC, 0x0098, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK \ + IOMUX_PAD(0x03B0, 0x009C, 0, 0x0000, 0, MX6DL_DISP_PAD_CLT) +#define MX6DL_PAD_DI0_DISP_CLK__LCDIF_CLK \ + IOMUX_PAD(0x03B0, 0x009C, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DI0_DISP_CLK__MIPI_CORE_DPHY_TEST_OUT_28 \ + IOMUX_PAD(0x03B0, 0x009C, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 \ + IOMUX_PAD(0x03B0, 0x009C, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DI0_DISP_CLK__GPIO_4_16 \ + IOMUX_PAD(0x03B0, 0x009C, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DI0_DISP_CLK__MMDC_MMDC_DEBUG_0 \ + IOMUX_PAD(0x03B0, 0x009C, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DI0_DISP_CLK__TPSMP_HDATA_DIR \ + IOMUX_PAD(0x03B0, 0x009C, 7, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DI0_DISP_CLK__LCDIF_WR_RWN \ + IOMUX_PAD(0x03B0, 0x009C, 8, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DI0_PIN15__IPU1_DI0_PIN15 \ + IOMUX_PAD(0x03B4, 0x00A0, 0, 0x0000, 0, MX6DL_DISP_PAD_CLT) +#define MX6DL_PAD_DI0_PIN15__LCDIF_ENABLE \ + IOMUX_PAD(0x03B4, 0x00A0, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DI0_PIN15__AUDMUX_AUD6_TXC \ + IOMUX_PAD(0x03B4, 0x00A0, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DI0_PIN15__MIPI_CORE_DPHY_TEST_OUT_29 \ + IOMUX_PAD(0x03B4, 0x00A0, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 \ + IOMUX_PAD(0x03B4, 0x00A0, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DI0_PIN15__GPIO_4_17 \ + IOMUX_PAD(0x03B4, 0x00A0, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1 \ + IOMUX_PAD(0x03B4, 0x00A0, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DI0_PIN15__PL301_SIM_MX6DL_PER1_HSIZE_0 \ + IOMUX_PAD(0x03B4, 0x00A0, 7, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DI0_PIN15__LCDIF_RD_E \ + IOMUX_PAD(0x03B4, 0x00A0, 8, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DI0_PIN2__IPU1_DI0_PIN2 \ + IOMUX_PAD(0x03B8, 0x00A4, 0, 0x0000, 0, MX6DL_DISP_PAD_CLT) +#define MX6DL_PAD_DI0_PIN2__LCDIF_HSYNC \ + IOMUX_PAD(0x03B8, 0x00A4, 1, 0x08D8, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DI0_PIN2__AUDMUX_AUD6_TXD \ + IOMUX_PAD(0x03B8, 0x00A4, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DI0_PIN2__MIPI_CORE_DPHY_TEST_OUT_30 \ + IOMUX_PAD(0x03B8, 0x00A4, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 \ + IOMUX_PAD(0x03B8, 0x00A4, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DI0_PIN2__GPIO_4_18 \ + IOMUX_PAD(0x03B8, 0x00A4, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DI0_PIN2__MMDC_MMDC_DEBUG_2 \ + IOMUX_PAD(0x03B8, 0x00A4, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DI0_PIN2__PL301_SIM_MX6DL_PER1_HADDR_9 \ + IOMUX_PAD(0x03B8, 0x00A4, 7, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DI0_PIN2__LCDIF_RS \ + IOMUX_PAD(0x03B8, 0x00A4, 8, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DI0_PIN3__IPU1_DI0_PIN3 \ + IOMUX_PAD(0x03BC, 0x00A8, 0, 0x0000, 0, MX6DL_DISP_PAD_CLT) +#define MX6DL_PAD_DI0_PIN3__LCDIF_VSYNC \ + IOMUX_PAD(0x03BC, 0x00A8, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS \ + IOMUX_PAD(0x03BC, 0x00A8, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DI0_PIN3__MIPI_CORE_DPHY_TEST_OUT_31 \ + IOMUX_PAD(0x03BC, 0x00A8, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 \ + IOMUX_PAD(0x03BC, 0x00A8, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DI0_PIN3__GPIO_4_19 \ + IOMUX_PAD(0x03BC, 0x00A8, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3 \ + IOMUX_PAD(0x03BC, 0x00A8, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DI0_PIN3__PL301_SIM_MX6DL_PER1_HADDR_10 \ + IOMUX_PAD(0x03BC, 0x00A8, 7, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DI0_PIN3__LCDIF_CS \ + IOMUX_PAD(0x03BC, 0x00A8, 8, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DI0_PIN4__IPU1_DI0_PIN4 \ + IOMUX_PAD(0x03C0, 0x00AC, 0, 0x0000, 0, MX6DL_DISP_PAD_CLT) +#define MX6DL_PAD_DI0_PIN4__LCDIF_BUSY \ + IOMUX_PAD(0x03C0, 0x00AC, 1, 0x08D8, 1, NO_PAD_CTRL) +#define MX6DL_PAD_DI0_PIN4__AUDMUX_AUD6_RXD \ + IOMUX_PAD(0x03C0, 0x00AC, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DI0_PIN4__USDHC1_WP \ + IOMUX_PAD(0x03C0, 0x00AC, 3, 0x092C, 0, MX6DL_USDHC_PAD_CTRL) +#define MX6DL_PAD_DI0_PIN4__SDMA_DEBUG_YIELD \ + IOMUX_PAD(0x03C0, 0x00AC, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DI0_PIN4__GPIO_4_20 \ + IOMUX_PAD(0x03C0, 0x00AC, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4 \ + IOMUX_PAD(0x03C0, 0x00AC, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DI0_PIN4__PL301_SIM_MX6DL_PER1_HADDR_11 \ + IOMUX_PAD(0x03C0, 0x00AC, 7, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DI0_PIN4__LCDIF_RESET \ + IOMUX_PAD(0x03C0, 0x00AC, 8, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 \ + IOMUX_PAD(0x03C4, 0x00B0, 0, 0x0000, 0, MX6DL_DISP_PAD_CLT) +#define MX6DL_PAD_DISP0_DAT0__LCDIF_DAT_0 \ + IOMUX_PAD(0x03C4, 0x00B0, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT0__ECSPI3_SCLK \ + IOMUX_PAD(0x03C4, 0x00B0, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT0__USDHC1_USDHC_DEBUG_0 \ + IOMUX_PAD(0x03C4, 0x00B0, 3, 0x0000, 0, MX6DL_USDHC_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN \ + IOMUX_PAD(0x03C4, 0x00B0, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT0__GPIO_4_21 \ + IOMUX_PAD(0x03C4, 0x00B0, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5 \ + IOMUX_PAD(0x03C4, 0x00B0, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT0__PL301_SIM_MX6DL_PER1_HSIZE_1 \ + IOMUX_PAD(0x03C4, 0x00B0, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 \ + IOMUX_PAD(0x03C8, 0x00B4, 0, 0x0000, 0, MX6DL_DISP_PAD_CLT) +#define MX6DL_PAD_DISP0_DAT1__LCDIF_DAT_1 \ + IOMUX_PAD(0x03C8, 0x00B4, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT1__ECSPI3_MOSI \ + IOMUX_PAD(0x03C8, 0x00B4, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT1__USDHC1_USDHC_DEBUG_1 \ + IOMUX_PAD(0x03C8, 0x00B4, 3, 0x0000, 0, MX6DL_USDHC_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL \ + IOMUX_PAD(0x03C8, 0x00B4, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT1__GPIO_4_22 \ + IOMUX_PAD(0x03C8, 0x00B4, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT1__MMDC_MMDC_DEBUG_6 \ + IOMUX_PAD(0x03C8, 0x00B4, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT1__PL301_SIM_MX6DL_PER1_HADDR_12 \ + IOMUX_PAD(0x03C8, 0x00B4, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 \ + IOMUX_PAD(0x03CC, 0x00B8, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT10__LCDIF_DAT_10 \ + IOMUX_PAD(0x03CC, 0x00B8, 1, 0x0000, 0, MX6DL_DISP_PAD_CLT) +#define MX6DL_PAD_DISP0_DAT10__USDHC1_USDHC_DEBUG_6 \ + IOMUX_PAD(0x03CC, 0x00B8, 3, 0x0000, 0, MX6DL_USDHC_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 \ + IOMUX_PAD(0x03CC, 0x00B8, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT10__GPIO_4_31 \ + IOMUX_PAD(0x03CC, 0x00B8, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT10__MMDC_MMDC_DEBUG_15 \ + IOMUX_PAD(0x03CC, 0x00B8, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT10__PL301_SIM_MX6DL_PER1_HADDR_21 \ + IOMUX_PAD(0x03CC, 0x00B8, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 \ + IOMUX_PAD(0x03D0, 0x00BC, 0, 0x0000, 0, MX6DL_DISP_PAD_CLT) +#define MX6DL_PAD_DISP0_DAT11__LCDIF_DAT_11 \ + IOMUX_PAD(0x03D0, 0x00BC, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT11__USDHC1_USDHC_DEBUG_7 \ + IOMUX_PAD(0x03D0, 0x00BC, 3, 0x0000, 0, MX6DL_USDHC_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 \ + IOMUX_PAD(0x03D0, 0x00BC, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT11__GPIO_5_5 \ + IOMUX_PAD(0x03D0, 0x00BC, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT11__MMDC_MMDC_DEBUG_16 \ + IOMUX_PAD(0x03D0, 0x00BC, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT11__PL301_SIM_MX6DL_PER1_HADDR_22 \ + IOMUX_PAD(0x03D0, 0x00BC, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 \ + IOMUX_PAD(0x03D4, 0x00C0, 0, 0x0000, 0, MX6DL_DISP_PAD_CLT) +#define MX6DL_PAD_DISP0_DAT12__LCDIF_DAT_12 \ + IOMUX_PAD(0x03D4, 0x00C0, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 \ + IOMUX_PAD(0x03D4, 0x00C0, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT12__GPIO_5_6 \ + IOMUX_PAD(0x03D4, 0x00C0, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT12__MMDC_MMDC_DEBUG_17 \ + IOMUX_PAD(0x03D4, 0x00C0, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT12__PL301_SIM_MX6DL_PER1_HADDR_23 \ + IOMUX_PAD(0x03D4, 0x00C0, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 \ + IOMUX_PAD(0x03D8, 0x00C4, 0, 0x0000, 0, MX6DL_DISP_PAD_CLT) +#define MX6DL_PAD_DISP0_DAT13__LCDIF_DAT_13 \ + IOMUX_PAD(0x03D8, 0x00C4, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS \ + IOMUX_PAD(0x03D8, 0x00C4, 3, 0x07BC, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 \ + IOMUX_PAD(0x03D8, 0x00C4, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT13__GPIO_5_7 \ + IOMUX_PAD(0x03D8, 0x00C4, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT13__MMDC_MMDC_DEBUG_18 \ + IOMUX_PAD(0x03D8, 0x00C4, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT13__PL301_SIM_MX6DL_PER1_HADDR_24 \ + IOMUX_PAD(0x03D8, 0x00C4, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 \ + IOMUX_PAD(0x03DC, 0x00C8, 0, 0x0000, 0, MX6DL_DISP_PAD_CLT) +#define MX6DL_PAD_DISP0_DAT14__LCDIF_DAT_14 \ + IOMUX_PAD(0x03DC, 0x00C8, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC \ + IOMUX_PAD(0x03DC, 0x00C8, 3, 0x07B8, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 \ + IOMUX_PAD(0x03DC, 0x00C8, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT14__GPIO_5_8 \ + IOMUX_PAD(0x03DC, 0x00C8, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT14__MMDC_MMDC_DEBUG_19 \ + IOMUX_PAD(0x03DC, 0x00C8, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT14__PL301_SIM_MX6DL_PER1_HSIZE_2 \ + IOMUX_PAD(0x03DC, 0x00C8, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 \ + IOMUX_PAD(0x03E0, 0x00CC, 0, 0x0000, 0, MX6DL_DISP_PAD_CLT) +#define MX6DL_PAD_DISP0_DAT15__LCDIF_DAT_15 \ + IOMUX_PAD(0x03E0, 0x00CC, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT15__ECSPI1_SS1 \ + IOMUX_PAD(0x03E0, 0x00CC, 2, 0x07E8, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT15__ECSPI2_SS1 \ + IOMUX_PAD(0x03E0, 0x00CC, 3, 0x0804, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 \ + IOMUX_PAD(0x03E0, 0x00CC, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT15__GPIO_5_9 \ + IOMUX_PAD(0x03E0, 0x00CC, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT15__MMDC_MMDC_DEBUG_20 \ + IOMUX_PAD(0x03E0, 0x00CC, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT15__PL301_SIM_MX6DL_PER1_HADDR_25 \ + IOMUX_PAD(0x03E0, 0x00CC, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 \ + IOMUX_PAD(0x03E4, 0x00D0, 0, 0x0000, 0, MX6DL_DISP_PAD_CLT) +#define MX6DL_PAD_DISP0_DAT16__LCDIF_DAT_16 \ + IOMUX_PAD(0x03E4, 0x00D0, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT16__ECSPI2_MOSI \ + IOMUX_PAD(0x03E4, 0x00D0, 2, 0x07FC, 1, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC \ + IOMUX_PAD(0x03E4, 0x00D0, 3, 0x07C0, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT16__SDMA_SDMA_EXT_EVENT_0 \ + IOMUX_PAD(0x03E4, 0x00D0, 4, 0x08E8, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT16__GPIO_5_10 \ + IOMUX_PAD(0x03E4, 0x00D0, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT16__MMDC_MMDC_DEBUG_21 \ + IOMUX_PAD(0x03E4, 0x00D0, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT16__PL301_SIM_MX6DL_PER1_HADDR_26 \ + IOMUX_PAD(0x03E4, 0x00D0, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 \ + IOMUX_PAD(0x03E8, 0x00D4, 0, 0x0000, 0, MX6DL_DISP_PAD_CLT) +#define MX6DL_PAD_DISP0_DAT17__LCDIF_DAT_17 \ + IOMUX_PAD(0x03E8, 0x00D4, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT17__ECSPI2_MISO \ + IOMUX_PAD(0x03E8, 0x00D4, 2, 0x07F8, 1, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD \ + IOMUX_PAD(0x03E8, 0x00D4, 3, 0x07B4, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT17__SDMA_SDMA_EXT_EVENT_1 \ + IOMUX_PAD(0x03E8, 0x00D4, 4, 0x08EC, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT17__GPIO_5_11 \ + IOMUX_PAD(0x03E8, 0x00D4, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT17__MMDC_MMDC_DEBUG_22 \ + IOMUX_PAD(0x03E8, 0x00D4, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT17__PL301_SIM_MX6DL_PER1_HADDR_27 \ + IOMUX_PAD(0x03E8, 0x00D4, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 \ + IOMUX_PAD(0x03EC, 0x00D8, 0, 0x0000, 0, MX6DL_DISP_PAD_CLT) +#define MX6DL_PAD_DISP0_DAT18__LCDIF_DAT_18 \ + IOMUX_PAD(0x03EC, 0x00D8, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT18__ECSPI2_SS0 \ + IOMUX_PAD(0x03EC, 0x00D8, 2, 0x0800, 1, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS \ + IOMUX_PAD(0x03EC, 0x00D8, 3, 0x07C4, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS \ + IOMUX_PAD(0x03EC, 0x00D8, 4, 0x07A4, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT18__GPIO_5_12 \ + IOMUX_PAD(0x03EC, 0x00D8, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT18__MMDC_MMDC_DEBUG_23 \ + IOMUX_PAD(0x03EC, 0x00D8, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT18__WEIM_WEIM_CS_2 \ + IOMUX_PAD(0x03EC, 0x00D8, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 \ + IOMUX_PAD(0x03F0, 0x00DC, 0, 0x0000, 0, MX6DL_DISP_PAD_CLT) +#define MX6DL_PAD_DISP0_DAT19__LCDIF_DAT_19 \ + IOMUX_PAD(0x03F0, 0x00DC, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT19__ECSPI2_SCLK \ + IOMUX_PAD(0x03F0, 0x00DC, 2, 0x07F4, 1, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD \ + IOMUX_PAD(0x03F0, 0x00DC, 3, 0x07B0, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC \ + IOMUX_PAD(0x03F0, 0x00DC, 4, 0x07A0, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT19__GPIO_5_13 \ + IOMUX_PAD(0x03F0, 0x00DC, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT19__MMDC_MMDC_DEBUG_24 \ + IOMUX_PAD(0x03F0, 0x00DC, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT19__WEIM_WEIM_CS_3 \ + IOMUX_PAD(0x03F0, 0x00DC, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 \ + IOMUX_PAD(0x03F4, 0x00E0, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT2__LCDIF_DAT_2 \ + IOMUX_PAD(0x03F4, 0x00E0, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT2__ECSPI3_MISO \ + IOMUX_PAD(0x03F4, 0x00E0, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT2__USDHC1_USDHC_DEBUG_2 \ + IOMUX_PAD(0x03F4, 0x00E0, 3, 0x0000, 0, MX6DL_USDHC_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT2__SDMA_DEBUG_MODE \ + IOMUX_PAD(0x03F4, 0x00E0, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT2__GPIO_4_23 \ + IOMUX_PAD(0x03F4, 0x00E0, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT2__MMDC_MMDC_DEBUG_7 \ + IOMUX_PAD(0x03F4, 0x00E0, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT2__PL301_SIM_MX6DL_PER1_HADDR_13 \ + IOMUX_PAD(0x03F4, 0x00E0, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 \ + IOMUX_PAD(0x03F8, 0x00E4, 0, 0x0000, 0, MX6DL_DISP_PAD_CLT) +#define MX6DL_PAD_DISP0_DAT20__LCDIF_DAT_20 \ + IOMUX_PAD(0x03F8, 0x00E4, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT20__ECSPI1_SCLK \ + IOMUX_PAD(0x03F8, 0x00E4, 2, 0x07D8, 1, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC \ + IOMUX_PAD(0x03F8, 0x00E4, 3, 0x07A8, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 \ + IOMUX_PAD(0x03F8, 0x00E4, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT20__GPIO_5_14 \ + IOMUX_PAD(0x03F8, 0x00E4, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT20__MMDC_MMDC_DEBUG_25 \ + IOMUX_PAD(0x03F8, 0x00E4, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT20__PL301_SIM_MX6DL_PER1_HADDR_28 \ + IOMUX_PAD(0x03F8, 0x00E4, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 \ + IOMUX_PAD(0x03FC, 0x00E8, 0, 0x0000, 0, MX6DL_DISP_PAD_CLT) +#define MX6DL_PAD_DISP0_DAT21__LCDIF_DAT_21 \ + IOMUX_PAD(0x03FC, 0x00E8, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT21__ECSPI1_MOSI \ + IOMUX_PAD(0x03FC, 0x00E8, 2, 0x07E0, 1, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD \ + IOMUX_PAD(0x03FC, 0x00E8, 3, 0x079C, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 \ + IOMUX_PAD(0x03FC, 0x00E8, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT21__GPIO_5_15 \ + IOMUX_PAD(0x03FC, 0x00E8, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT21__MMDC_MMDC_DEBUG_26 \ + IOMUX_PAD(0x03FC, 0x00E8, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT21__PL301_SIM_MX6DL_PER1_HADDR_29 \ + IOMUX_PAD(0x03FC, 0x00E8, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 \ + IOMUX_PAD(0x0400, 0x00EC, 0, 0x0000, 0, MX6DL_DISP_PAD_CLT) +#define MX6DL_PAD_DISP0_DAT22__LCDIF_DAT_22 \ + IOMUX_PAD(0x0400, 0x00EC, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT22__ECSPI1_MISO \ + IOMUX_PAD(0x0400, 0x00EC, 2, 0x07DC, 1, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS \ + IOMUX_PAD(0x0400, 0x00EC, 3, 0x07AC, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 \ + IOMUX_PAD(0x0400, 0x00EC, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT22__GPIO_5_16 \ + IOMUX_PAD(0x0400, 0x00EC, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT22__MMDC_MMDC_DEBUG_27 \ + IOMUX_PAD(0x0400, 0x00EC, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT22__PL301_SIM_MX6DL_PER1_HADDR_30 \ + IOMUX_PAD(0x0400, 0x00EC, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 \ + IOMUX_PAD(0x0404, 0x00F0, 0, 0x0000, 0, MX6DL_DISP_PAD_CLT) +#define MX6DL_PAD_DISP0_DAT23__LCDIF_DAT_23 \ + IOMUX_PAD(0x0404, 0x00F0, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT23__ECSPI1_SS0 \ + IOMUX_PAD(0x0404, 0x00F0, 2, 0x07E4, 1, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD \ + IOMUX_PAD(0x0404, 0x00F0, 3, 0x0798, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 \ + IOMUX_PAD(0x0404, 0x00F0, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT23__GPIO_5_17 \ + IOMUX_PAD(0x0404, 0x00F0, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT23__MMDC_MMDC_DEBUG_28 \ + IOMUX_PAD(0x0404, 0x00F0, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT23__PL301_SIM_MX6DL_PER1_HADDR_31 \ + IOMUX_PAD(0x0404, 0x00F0, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 \ + IOMUX_PAD(0x0408, 0x00F4, 0, 0x0000, 0, MX6DL_DISP_PAD_CLT) +#define MX6DL_PAD_DISP0_DAT3__LCDIF_DAT_3 \ + IOMUX_PAD(0x0408, 0x00F4, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT3__ECSPI3_SS0 \ + IOMUX_PAD(0x0408, 0x00F4, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT3__USDHC1_USDHC_DEBUG_3 \ + IOMUX_PAD(0x0408, 0x00F4, 3, 0x0000, 0, MX6DL_USDHC_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR \ + IOMUX_PAD(0x0408, 0x00F4, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT3__GPIO_4_24 \ + IOMUX_PAD(0x0408, 0x00F4, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT3__MMDC_MMDC_DEBUG_8 \ + IOMUX_PAD(0x0408, 0x00F4, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT3__PL301_SIM_MX6DL_PER1_HADDR_14 \ + IOMUX_PAD(0x0408, 0x00F4, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 \ + IOMUX_PAD(0x040C, 0x00F8, 0, 0x0000, 0, MX6DL_DISP_PAD_CLT) +#define MX6DL_PAD_DISP0_DAT4__LCDIF_DAT_4 \ + IOMUX_PAD(0x040C, 0x00F8, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT4__ECSPI3_SS1 \ + IOMUX_PAD(0x040C, 0x00F8, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT4__USDHC1_USDHC_DEBUG_4 \ + IOMUX_PAD(0x040C, 0x00F8, 3, 0x0000, 0, MX6DL_USDHC_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB \ + IOMUX_PAD(0x040C, 0x00F8, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT4__GPIO_4_25 \ + IOMUX_PAD(0x040C, 0x00F8, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9 \ + IOMUX_PAD(0x040C, 0x00F8, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT4__PL301_SIM_MX6DL_PER1_HADDR_15 \ + IOMUX_PAD(0x040C, 0x00F8, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 \ + IOMUX_PAD(0x0410, 0x00FC, 0, 0x0000, 0, MX6DL_DISP_PAD_CLT) +#define MX6DL_PAD_DISP0_DAT5__LCDIF_DAT_5 \ + IOMUX_PAD(0x0410, 0x00FC, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT5__ECSPI3_SS2 \ + IOMUX_PAD(0x0410, 0x00FC, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS \ + IOMUX_PAD(0x0410, 0x00FC, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS \ + IOMUX_PAD(0x0410, 0x00FC, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT5__GPIO_4_26 \ + IOMUX_PAD(0x0410, 0x00FC, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT5__MMDC_MMDC_DEBUG_10 \ + IOMUX_PAD(0x0410, 0x00FC, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT5__PL301_SIM_MX6DL_PER1_HADDR_16 \ + IOMUX_PAD(0x0410, 0x00FC, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 \ + IOMUX_PAD(0x0414, 0x0100, 0, 0x0000, 0, MX6DL_DISP_PAD_CLT) +#define MX6DL_PAD_DISP0_DAT6__LCDIF_DAT_6 \ + IOMUX_PAD(0x0414, 0x0100, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT6__ECSPI3_SS3 \ + IOMUX_PAD(0x0414, 0x0100, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC \ + IOMUX_PAD(0x0414, 0x0100, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE \ + IOMUX_PAD(0x0414, 0x0100, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT6__GPIO_4_27 \ + IOMUX_PAD(0x0414, 0x0100, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT6__MMDC_MMDC_DEBUG_11 \ + IOMUX_PAD(0x0414, 0x0100, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT6__PL301_SIM_MX6DL_PER1_HADDR_17 \ + IOMUX_PAD(0x0414, 0x0100, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 \ + IOMUX_PAD(0x0418, 0x0104, 0, 0x0000, 0, MX6DL_DISP_PAD_CLT) +#define MX6DL_PAD_DISP0_DAT7__LCDIF_DAT_7 \ + IOMUX_PAD(0x0418, 0x0104, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT7__ECSPI3_RDY \ + IOMUX_PAD(0x0418, 0x0104, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT7__USDHC1_USDHC_DEBUG_5 \ + IOMUX_PAD(0x0418, 0x0104, 3, 0x0000, 0, MX6DL_USDHC_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 \ + IOMUX_PAD(0x0418, 0x0104, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT7__GPIO_4_28 \ + IOMUX_PAD(0x0418, 0x0104, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT7__MMDC_MMDC_DEBUG_12 \ + IOMUX_PAD(0x0418, 0x0104, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT7__PL301_SIM_MX6DL_PER1_HADDR_18 \ + IOMUX_PAD(0x0418, 0x0104, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 \ + IOMUX_PAD(0x041C, 0x0108, 0, 0x0000, 0, MX6DL_DISP_PAD_CLT) +#define MX6DL_PAD_DISP0_DAT8__LCDIF_DAT_8 \ + IOMUX_PAD(0x041C, 0x0108, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT8__PWM1_PWMO \ + IOMUX_PAD(0x041C, 0x0108, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT8__WDOG1_WDOG_B \ + IOMUX_PAD(0x041C, 0x0108, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 \ + IOMUX_PAD(0x041C, 0x0108, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT8__GPIO_4_29 \ + IOMUX_PAD(0x041C, 0x0108, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT8__MMDC_MMDC_DEBUG_13 \ + IOMUX_PAD(0x041C, 0x0108, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT8__PL301_SIM_MX6DL_PER1_HADDR_19 \ + IOMUX_PAD(0x041C, 0x0108, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 \ + IOMUX_PAD(0x0420, 0x010C, 0, 0x0000, 0, MX6DL_DISP_PAD_CLT) +#define MX6DL_PAD_DISP0_DAT9__LCDIF_DAT_9 \ + IOMUX_PAD(0x0420, 0x010C, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT9__PWM2_PWMO \ + IOMUX_PAD(0x0420, 0x010C, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT9__WDOG2_WDOG_B \ + IOMUX_PAD(0x0420, 0x010C, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 \ + IOMUX_PAD(0x0420, 0x010C, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT9__GPIO_4_30 \ + IOMUX_PAD(0x0420, 0x010C, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT9__MMDC_MMDC_DEBUG_14 \ + IOMUX_PAD(0x0420, 0x010C, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_DISP0_DAT9__PL301_SIM_MX6DL_PER1_HADDR_20 \ + IOMUX_PAD(0x0420, 0x010C, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_A0__MMDC_DRAM_A_0 \ + IOMUX_PAD(0x0424, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_A1__MMDC_DRAM_A_1 \ + IOMUX_PAD(0x0428, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_A10__MMDC_DRAM_A_10 \ + IOMUX_PAD(0x042C, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_A11__MMDC_DRAM_A_11 \ + IOMUX_PAD(0x0430, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_A12__MMDC_DRAM_A_12 \ + IOMUX_PAD(0x0434, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_A13__MMDC_DRAM_A_13 \ + IOMUX_PAD(0x0438, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_A14__MMDC_DRAM_A_14 \ + IOMUX_PAD(0x043C, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_A15__MMDC_DRAM_A_15 \ + IOMUX_PAD(0x0440, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_A2__MMDC_DRAM_A_2 \ + IOMUX_PAD(0x0444, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_A3__MMDC_DRAM_A_3 \ + IOMUX_PAD(0x0448, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_A4__MMDC_DRAM_A_4 \ + IOMUX_PAD(0x044C, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_A5__MMDC_DRAM_A_5 \ + IOMUX_PAD(0x0450, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_A6__MMDC_DRAM_A_6 \ + IOMUX_PAD(0x0454, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_A7__MMDC_DRAM_A_7 \ + IOMUX_PAD(0x0458, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_A8__MMDC_DRAM_A_8 \ + IOMUX_PAD(0x045C, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_A9__MMDC_DRAM_A_9 \ + IOMUX_PAD(0x0460, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_CAS__MMDC_DRAM_CAS \ + IOMUX_PAD(0x0464, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_CS0__MMDC_DRAM_CS_0 \ + IOMUX_PAD(0x0468, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_CS1__MMDC_DRAM_CS_1 \ + IOMUX_PAD(0x046C, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_D0__MMDC_DRAM_D_0 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_D1__MMDC_DRAM_D_1 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_D10__MMDC_DRAM_D_10 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_D11__MMDC_DRAM_D_11 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_D12__MMDC_DRAM_D_12 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_D13__MMDC_DRAM_D_13 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_D14__MMDC_DRAM_D_14 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_D15__MMDC_DRAM_D_15 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_D16__MMDC_DRAM_D_16 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_D17__MMDC_DRAM_D_17 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_D18__MMDC_DRAM_D_18 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_D19__MMDC_DRAM_D_19 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_D2__MMDC_DRAM_D_2 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_D20__MMDC_DRAM_D_20 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_D21__MMDC_DRAM_D_21 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_D22__MMDC_DRAM_D_22 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_D23__MMDC_DRAM_D_23 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_D24__MMDC_DRAM_D_24 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_D25__MMDC_DRAM_D_25 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_D26__MMDC_DRAM_D_26 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_D27__MMDC_DRAM_D_27 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_D28__MMDC_DRAM_D_28 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_D29__MMDC_DRAM_D_29 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_D3__MMDC_DRAM_D_3 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_D30__MMDC_DRAM_D_30 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_D31__MMDC_DRAM_D_31 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_D32__MMDC_DRAM_D_32 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_D33__MMDC_DRAM_D_33 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_D34__MMDC_DRAM_D_34 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_D35__MMDC_DRAM_D_35 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_D36__MMDC_DRAM_D_36 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_D37__MMDC_DRAM_D_37 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_D38__MMDC_DRAM_D_38 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_D39__MMDC_DRAM_D_39 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_D4__MMDC_DRAM_D_4 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_D40__MMDC_DRAM_D_40 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_D41__MMDC_DRAM_D_41 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_D42__MMDC_DRAM_D_42 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_D43__MMDC_DRAM_D_43 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_D44__MMDC_DRAM_D_44 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_D45__MMDC_DRAM_D_45 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_D46__MMDC_DRAM_D_46 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_D47__MMDC_DRAM_D_47 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_D48__MMDC_DRAM_D_48 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_D49__MMDC_DRAM_D_49 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_D5__MMDC_DRAM_D_5 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_D50__MMDC_DRAM_D_50 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_D51__MMDC_DRAM_D_51 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_D52__MMDC_DRAM_D_52 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_D53__MMDC_DRAM_D_53 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_D54__MMDC_DRAM_D_54 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_D55__MMDC_DRAM_D_55 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_D56__MMDC_DRAM_D_56 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_D57__MMDC_DRAM_D_57 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_D58__MMDC_DRAM_D_58 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_D59__MMDC_DRAM_D_59 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_D6__MMDC_DRAM_D_6 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_D60__MMDC_DRAM_D_60 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_D61__MMDC_DRAM_D_61 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_D62__MMDC_DRAM_D_62 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_D63__MMDC_DRAM_D_63 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_D7__MMDC_DRAM_D_7 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_D8__MMDC_DRAM_D_8 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_D9__MMDC_DRAM_D_9 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0 \ + IOMUX_PAD(0x0470, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1 \ + IOMUX_PAD(0x0474, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2 \ + IOMUX_PAD(0x0478, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3 \ + IOMUX_PAD(0x047C, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4 \ + IOMUX_PAD(0x0480, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5 \ + IOMUX_PAD(0x0484, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6 \ + IOMUX_PAD(0x0488, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7 \ + IOMUX_PAD(0x048C, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_RAS__MMDC_DRAM_RAS \ + IOMUX_PAD(0x0490, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_RESET__MMDC_DRAM_RESET \ + IOMUX_PAD(0x0494, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0 \ + IOMUX_PAD(0x0498, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1 \ + IOMUX_PAD(0x049C, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2 \ + IOMUX_PAD(0x04A0, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0 \ + IOMUX_PAD(0x04A4, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1 \ + IOMUX_PAD(0x04A8, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0 \ + IOMUX_PAD(0x04AC, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1 \ + IOMUX_PAD(0x04B0, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0 \ + IOMUX_PAD(0x04B4, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1 \ + IOMUX_PAD(0x04B8, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0 \ + IOMUX_PAD(0x04BC, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1 \ + IOMUX_PAD(0x04C0, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2 \ + IOMUX_PAD(0x04C4, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3 \ + IOMUX_PAD(0x04C8, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4 \ + IOMUX_PAD(0x04CC, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5 \ + IOMUX_PAD(0x04D0, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6 \ + IOMUX_PAD(0x04D4, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7 \ + IOMUX_PAD(0x04D8, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_DRAM_SDWE__MMDC_DRAM_SDWE \ + IOMUX_PAD(0x04DC, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_EIM_A16__WEIM_WEIM_A_16 \ + IOMUX_PAD(0x04E0, 0x0110, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_A16__IPU1_DI1_DISP_CLK \ + IOMUX_PAD(0x04E0, 0x0110, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_A16__IPU1_CSI1_PIXCLK \ + IOMUX_PAD(0x04E0, 0x0110, 2, 0x08B8, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_A16__MIPI_CORE_DPHY_TEST_OUT_23 \ + IOMUX_PAD(0x04E0, 0x0110, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_A16__GPIO_2_22 \ + IOMUX_PAD(0x04E0, 0x0110, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_A16__TPSMP_HDATA_6 \ + IOMUX_PAD(0x04E0, 0x0110, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_A16__SRC_BT_CFG_16 \ + IOMUX_PAD(0x04E0, 0x0110, 7, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_A16__EPDC_SDDO_0 \ + IOMUX_PAD(0x04E0, 0x0110, 8, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_EIM_A17__WEIM_WEIM_A_17 \ + IOMUX_PAD(0x04E4, 0x0114, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_A17__IPU1_DISP1_DAT_12 \ + IOMUX_PAD(0x04E4, 0x0114, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_A17__IPU1_CSI1_D_12 \ + IOMUX_PAD(0x04E4, 0x0114, 2, 0x0890, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_A17__MIPI_CORE_DPHY_TEST_OUT_22 \ + IOMUX_PAD(0x04E4, 0x0114, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_A17__GPIO_2_21 \ + IOMUX_PAD(0x04E4, 0x0114, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_A17__TPSMP_HDATA_5 \ + IOMUX_PAD(0x04E4, 0x0114, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_A17__SRC_BT_CFG_17 \ + IOMUX_PAD(0x04E4, 0x0114, 7, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_A17__EPDC_PWRSTAT \ + IOMUX_PAD(0x04E4, 0x0114, 8, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_EIM_A18__WEIM_WEIM_A_18 \ + IOMUX_PAD(0x04E8, 0x0118, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_A18__IPU1_DISP1_DAT_13 \ + IOMUX_PAD(0x04E8, 0x0118, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_A18__IPU1_CSI1_D_13 \ + IOMUX_PAD(0x04E8, 0x0118, 2, 0x0894, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_A18__MIPI_CORE_DPHY_TEST_OUT_21 \ + IOMUX_PAD(0x04E8, 0x0118, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_A18__GPIO_2_20 \ + IOMUX_PAD(0x04E8, 0x0118, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_A18__TPSMP_HDATA_4 \ + IOMUX_PAD(0x04E8, 0x0118, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_A18__SRC_BT_CFG_18 \ + IOMUX_PAD(0x04E8, 0x0118, 7, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_A18__EPDC_PWRCTRL_0 \ + IOMUX_PAD(0x04E8, 0x0118, 8, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_EIM_A19__WEIM_WEIM_A_19 \ + IOMUX_PAD(0x04EC, 0x011C, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_A19__IPU1_DISP1_DAT_14 \ + IOMUX_PAD(0x04EC, 0x011C, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_A19__IPU1_CSI1_D_14 \ + IOMUX_PAD(0x04EC, 0x011C, 2, 0x0898, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_A19__MIPI_CORE_DPHY_TEST_OUT_20 \ + IOMUX_PAD(0x04EC, 0x011C, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_A19__GPIO_2_19 \ + IOMUX_PAD(0x04EC, 0x011C, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_A19__TPSMP_HDATA_3 \ + IOMUX_PAD(0x04EC, 0x011C, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_A19__SRC_BT_CFG_19 \ + IOMUX_PAD(0x04EC, 0x011C, 7, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_A19__EPDC_PWRCTRL_1 \ + IOMUX_PAD(0x04EC, 0x011C, 8, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_EIM_A20__WEIM_WEIM_A_20 \ + IOMUX_PAD(0x04F0, 0x0120, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_A20__IPU1_DISP1_DAT_15 \ + IOMUX_PAD(0x04F0, 0x0120, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_A20__IPU1_CSI1_D_15 \ + IOMUX_PAD(0x04F0, 0x0120, 2, 0x089C, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_A20__MIPI_CORE_DPHY_TEST_OUT_19 \ + IOMUX_PAD(0x04F0, 0x0120, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_A20__GPIO_2_18 \ + IOMUX_PAD(0x04F0, 0x0120, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_A20__TPSMP_HDATA_2 \ + IOMUX_PAD(0x04F0, 0x0120, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_A20__SRC_BT_CFG_20 \ + IOMUX_PAD(0x04F0, 0x0120, 7, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_A20__EPDC_PWRCTRL_2 \ + IOMUX_PAD(0x04F0, 0x0120, 8, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_EIM_A21__WEIM_WEIM_A_21 \ + IOMUX_PAD(0x04F4, 0x0124, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_A21__IPU1_DISP1_DAT_16 \ + IOMUX_PAD(0x04F4, 0x0124, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_A21__IPU1_CSI1_D_16 \ + IOMUX_PAD(0x04F4, 0x0124, 2, 0x08A0, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_A21__MIPI_CORE_DPHY_TEST_OUT_18 \ + IOMUX_PAD(0x04F4, 0x0124, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_A21__GPIO_2_17 \ + IOMUX_PAD(0x04F4, 0x0124, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_A21__TPSMP_HDATA_1 \ + IOMUX_PAD(0x04F4, 0x0124, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_A21__SRC_BT_CFG_21 \ + IOMUX_PAD(0x04F4, 0x0124, 7, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_A21__EPDC_GDCLK \ + IOMUX_PAD(0x04F4, 0x0124, 8, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_EIM_A22__WEIM_WEIM_A_22 \ + IOMUX_PAD(0x04F8, 0x0128, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_A22__IPU1_DISP1_DAT_17 \ + IOMUX_PAD(0x04F8, 0x0128, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_A22__IPU1_CSI1_D_17 \ + IOMUX_PAD(0x04F8, 0x0128, 2, 0x08A4, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_A22__GPIO_2_16 \ + IOMUX_PAD(0x04F8, 0x0128, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_A22__TPSMP_HDATA_0 \ + IOMUX_PAD(0x04F8, 0x0128, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_A22__SRC_BT_CFG_22 \ + IOMUX_PAD(0x04F8, 0x0128, 7, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_A22__EPDC_GDSP \ + IOMUX_PAD(0x04F8, 0x0128, 8, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_EIM_A23__WEIM_WEIM_A_23 \ + IOMUX_PAD(0x04FC, 0x012C, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_A23__IPU1_DISP1_DAT_18 \ + IOMUX_PAD(0x04FC, 0x012C, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_A23__IPU1_CSI1_D_18 \ + IOMUX_PAD(0x04FC, 0x012C, 2, 0x08A8, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_A23__IPU1_SISG_3 \ + IOMUX_PAD(0x04FC, 0x012C, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_A23__GPIO_6_6 \ + IOMUX_PAD(0x04FC, 0x012C, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_A23__PL301_SIM_MX6DL_PER1_HPROT_3 \ + IOMUX_PAD(0x04FC, 0x012C, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_A23__SRC_BT_CFG_23 \ + IOMUX_PAD(0x04FC, 0x012C, 7, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_A23__EPDC_GDOE \ + IOMUX_PAD(0x04FC, 0x012C, 8, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_EIM_A24__WEIM_WEIM_A_24 \ + IOMUX_PAD(0x0500, 0x0130, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_A24__IPU1_DISP1_DAT_19 \ + IOMUX_PAD(0x0500, 0x0130, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_A24__IPU1_CSI1_D_19 \ + IOMUX_PAD(0x0500, 0x0130, 2, 0x08AC, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_A24__IPU1_SISG_2 \ + IOMUX_PAD(0x0500, 0x0130, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_A24__GPIO_5_4 \ + IOMUX_PAD(0x0500, 0x0130, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_A24__PL301_SIM_MX6DL_PER1_HPROT_2 \ + IOMUX_PAD(0x0500, 0x0130, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_A24__SRC_BT_CFG_24 \ + IOMUX_PAD(0x0500, 0x0130, 7, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_A24__EPDC_GDRL \ + IOMUX_PAD(0x0500, 0x0130, 8, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_EIM_A25__WEIM_WEIM_A_25 \ + IOMUX_PAD(0x0504, 0x0134, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_A25__ECSPI4_SS1 \ + IOMUX_PAD(0x0504, 0x0134, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_A25__ECSPI2_RDY \ + IOMUX_PAD(0x0504, 0x0134, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_A25__IPU1_DI1_PIN12 \ + IOMUX_PAD(0x0504, 0x0134, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_A25__IPU1_DI0_D1_CS \ + IOMUX_PAD(0x0504, 0x0134, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_A25__GPIO_5_2 \ + IOMUX_PAD(0x0504, 0x0134, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_A25__HDMI_TX_CEC_LINE \ + IOMUX_PAD(0x0504, 0x0134, 6, 0x085C, 0, MX6DL_HDMICEC_PAD_CTRL) +#define MX6DL_PAD_EIM_A25__PL301_SIM_MX6DL_PER1_HBURST_0 \ + IOMUX_PAD(0x0504, 0x0134, 7, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_A25__EPDC_SDDO_15 \ + IOMUX_PAD(0x0504, 0x0134, 8, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_A25__WEIM_ACLK_FREERUN \ + IOMUX_PAD(0x0504, 0x0134, 9, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_EIM_BCLK__WEIM_WEIM_BCLK \ + IOMUX_PAD(0x0508, 0x0138, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_BCLK__IPU1_DI1_PIN16 \ + IOMUX_PAD(0x0508, 0x0138, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_BCLK__GPIO_6_31 \ + IOMUX_PAD(0x0508, 0x0138, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_BCLK__TPSMP_HDATA_31 \ + IOMUX_PAD(0x0508, 0x0138, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_BCLK__EPDC_SDCE_9 \ + IOMUX_PAD(0x0508, 0x0138, 8, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_EIM_CS0__WEIM_WEIM_CS_0 \ + IOMUX_PAD(0x050C, 0x013C, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_CS0__IPU1_DI1_PIN5 \ + IOMUX_PAD(0x050C, 0x013C, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_CS0__ECSPI2_SCLK \ + IOMUX_PAD(0x050C, 0x013C, 2, 0x07F4, 2, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_CS0__MIPI_CORE_DPHY_TEST_OUT_24 \ + IOMUX_PAD(0x050C, 0x013C, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_CS0__GPIO_2_23 \ + IOMUX_PAD(0x050C, 0x013C, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_CS0__TPSMP_HDATA_7 \ + IOMUX_PAD(0x050C, 0x013C, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_CS0__EPDC_SDDO_6 \ + IOMUX_PAD(0x050C, 0x013C, 8, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_EIM_CS1__WEIM_WEIM_CS_1 \ + IOMUX_PAD(0x0510, 0x0140, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_CS1__IPU1_DI1_PIN6 \ + IOMUX_PAD(0x0510, 0x0140, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_CS1__ECSPI2_MOSI \ + IOMUX_PAD(0x0510, 0x0140, 2, 0x07FC, 2, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_CS1__MIPI_CORE_DPHY_TEST_OUT_25 \ + IOMUX_PAD(0x0510, 0x0140, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_CS1__GPIO_2_24 \ + IOMUX_PAD(0x0510, 0x0140, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_CS1__TPSMP_HDATA_8 \ + IOMUX_PAD(0x0510, 0x0140, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_CS1__EPDC_SDDO_8 \ + IOMUX_PAD(0x0510, 0x0140, 8, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_EIM_D16__WEIM_WEIM_D_16 \ + IOMUX_PAD(0x0514, 0x0144, 0, 0x0000, 0, MX6DL_WEIM_NOR_PAD_CTRL) +#define MX6DL_PAD_EIM_D16__ECSPI1_SCLK \ + IOMUX_PAD(0x0514, 0x0144, 1, 0x07D8, 2, MX6DL_ECSPI_PAD_CTRL) +#define MX6DL_PAD_EIM_D16__IPU1_DI0_PIN5 \ + IOMUX_PAD(0x0514, 0x0144, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_D16__IPU1_CSI1_D_18 \ + IOMUX_PAD(0x0514, 0x0144, 3, 0x08A8, 1, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_D16__HDMI_TX_DDC_SDA \ + IOMUX_PAD(0x0514, 0x0144, 4, 0x0864, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_D16__GPIO_3_16 \ + IOMUX_PAD(0x0514, 0x0144, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_D16__I2C2_SDA \ + IOMUX_PAD(0x0514, 0x0144, 6 | IOMUX_CONFIG_SION, 0x0874, 0, MX6DL_I2C_PAD_CTRL) +#define MX6DL_PAD_EIM_D16__TPSMP_HTRANS_0 \ + IOMUX_PAD(0x0514, 0x0144, 7, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_D16__EPDC_SDDO_10 \ + IOMUX_PAD(0x0514, 0x0144, 8, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_EIM_D17__WEIM_WEIM_D_17 \ + IOMUX_PAD(0x0518, 0x0148, 0, 0x0000, 0, MX6DL_WEIM_NOR_PAD_CTRL) +#define MX6DL_PAD_EIM_D17__ECSPI1_MISO \ + IOMUX_PAD(0x0518, 0x0148, 1, 0x07DC, 2, MX6DL_ECSPI_PAD_CTRL) +#define MX6DL_PAD_EIM_D17__IPU1_DI0_PIN6 \ + IOMUX_PAD(0x0518, 0x0148, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_D17__IPU1_CSI1_PIXCLK \ + IOMUX_PAD(0x0518, 0x0148, 3, 0x08B8, 1, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_D17__DCIC1_DCIC_OUT \ + IOMUX_PAD(0x0518, 0x0148, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_D17__GPIO_3_17 \ + IOMUX_PAD(0x0518, 0x0148, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_D17__I2C3_SCL \ + IOMUX_PAD(0x0518, 0x0148, 6 | IOMUX_CONFIG_SION, 0x0878, 0, MX6DL_I2C_PAD_CTRL) +#define MX6DL_PAD_EIM_D17__PL301_SIM_MX6DL_PER1_HBURST_1 \ + IOMUX_PAD(0x0518, 0x0148, 7, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_D17__EPDC_VCOM_0 \ + IOMUX_PAD(0x0518, 0x0148, 8, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_EIM_D18__WEIM_WEIM_D_18 \ + IOMUX_PAD(0x051C, 0x014C, 0, 0x0000, 0, MX6DL_WEIM_NOR_PAD_CTRL) +#define MX6DL_PAD_EIM_D18__ECSPI1_MOSI \ + IOMUX_PAD(0x051C, 0x014C, 1, 0x07E0, 2, MX6DL_ECSPI_PAD_CTRL) +#define MX6DL_PAD_EIM_D18__IPU1_DI0_PIN7 \ + IOMUX_PAD(0x051C, 0x014C, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_D18__IPU1_CSI1_D_17 \ + IOMUX_PAD(0x051C, 0x014C, 3, 0x08A4, 1, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_D18__IPU1_DI1_D0_CS \ + IOMUX_PAD(0x051C, 0x014C, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_D18__GPIO_3_18 \ + IOMUX_PAD(0x051C, 0x014C, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_D18__I2C3_SDA \ + IOMUX_PAD(0x051C, 0x014C, 6 | IOMUX_CONFIG_SION, 0x087C, 0, MX6DL_I2C_PAD_CTRL) +#define MX6DL_PAD_EIM_D18__PL301_SIM_MX6DL_PER1_HBURST_2 \ + IOMUX_PAD(0x051C, 0x014C, 7, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_D18__EPDC_VCOM_1 \ + IOMUX_PAD(0x051C, 0x014C, 8, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_EIM_D19__WEIM_WEIM_D_19 \ + IOMUX_PAD(0x0520, 0x0150, 0, 0x0000, 0, MX6DL_WEIM_NOR_PAD_CTRL) +#define MX6DL_PAD_EIM_D19__ECSPI1_SS1 \ + IOMUX_PAD(0x0520, 0x0150, 1, 0x07E8, 1, MX6DL_ECSPI_PAD_CTRL) +#define MX6DL_PAD_EIM_D19__IPU1_DI0_PIN8 \ + IOMUX_PAD(0x0520, 0x0150, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_D19__IPU1_CSI1_D_16 \ + IOMUX_PAD(0x0520, 0x0150, 3, 0x08A0, 1, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_D19__UART1_CTS \ + IOMUX_PAD(0x0520, 0x0150, 4, 0x0000, 0, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_EIM_D19__UART1_RTS \ + IOMUX_PAD(0x0520, 0x0150, 4, 0x08F8, 0, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_EIM_D19__GPIO_3_19 \ + IOMUX_PAD(0x0520, 0x0150, 5, 0x0000, 0, MX6DL_ECSPI_PAD_CTRL) +#define MX6DL_PAD_EIM_D19__EPIT1_EPITO \ + IOMUX_PAD(0x0520, 0x0150, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_D19__PL301_SIM_MX6DL_PER1_HRESP \ + IOMUX_PAD(0x0520, 0x0150, 7, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_D19__EPDC_SDDO_12 \ + IOMUX_PAD(0x0520, 0x0150, 8, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_EIM_D20__WEIM_WEIM_D_20 \ + IOMUX_PAD(0x0524, 0x0154, 0, 0x0000, 0, MX6DL_WEIM_NOR_PAD_CTRL) +#define MX6DL_PAD_EIM_D20__ECSPI4_SS0 \ + IOMUX_PAD(0x0524, 0x0154, 1, 0x0808, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_D20__IPU1_DI0_PIN16 \ + IOMUX_PAD(0x0524, 0x0154, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_D20__IPU1_CSI1_D_15 \ + IOMUX_PAD(0x0524, 0x0154, 3, 0x089C, 1, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_D20__UART1_CTS \ + IOMUX_PAD(0x0524, 0x0154, 4, 0x0000, 0, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_EIM_D20__UART1_RTS \ + IOMUX_PAD(0x0524, 0x0154, 4, 0x08F8, 1, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_EIM_D20__GPIO_3_20 \ + IOMUX_PAD(0x0524, 0x0154, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_D20__EPIT2_EPITO \ + IOMUX_PAD(0x0524, 0x0154, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_D20__TPSMP_HTRANS_1 \ + IOMUX_PAD(0x0524, 0x0154, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_EIM_D21__WEIM_WEIM_D_21 \ + IOMUX_PAD(0x0528, 0x0158, 0, 0x0000, 0, MX6DL_WEIM_NOR_PAD_CTRL) +#define MX6DL_PAD_EIM_D21__ECSPI4_SCLK \ + IOMUX_PAD(0x0528, 0x0158, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_D21__IPU1_DI0_PIN17 \ + IOMUX_PAD(0x0528, 0x0158, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_D21__IPU1_CSI1_D_11 \ + IOMUX_PAD(0x0528, 0x0158, 3, 0x088C, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_D21__USBOH3_USBOTG_OC \ + IOMUX_PAD(0x0528, 0x0158, 4, 0x0920, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_D21__GPIO_3_21 \ + IOMUX_PAD(0x0528, 0x0158, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_D21__I2C1_SCL \ + IOMUX_PAD(0x0528, 0x0158, 6 | IOMUX_CONFIG_SION, 0x0868, 1, MX6DL_I2C_PAD_CTRL) +#define MX6DL_PAD_EIM_D21__SPDIF_IN1 \ + IOMUX_PAD(0x0528, 0x0158, 7, 0x08F0, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_EIM_D22__WEIM_WEIM_D_22 \ + IOMUX_PAD(0x052C, 0x015C, 0, 0x0000, 0, MX6DL_WEIM_NOR_PAD_CTRL) +#define MX6DL_PAD_EIM_D22__ECSPI4_MISO \ + IOMUX_PAD(0x052C, 0x015C, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_D22__IPU1_DI0_PIN1 \ + IOMUX_PAD(0x052C, 0x015C, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_D22__IPU1_CSI1_D_10 \ + IOMUX_PAD(0x052C, 0x015C, 3, 0x0888, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_D22__USBOH3_USBOTG_PWR \ + IOMUX_PAD(0x052C, 0x015C, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_D22__GPIO_3_22 \ + IOMUX_PAD(0x052C, 0x015C, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_D22__SPDIF_OUT1 \ + IOMUX_PAD(0x052C, 0x015C, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_D22__PL301_SIM_MX6DL_PER1_HWRITE \ + IOMUX_PAD(0x052C, 0x015C, 7, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_D22__EPDC_SDCE_6 \ + IOMUX_PAD(0x052C, 0x015C, 8, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_EIM_D23__WEIM_WEIM_D_23 \ + IOMUX_PAD(0x0530, 0x0160, 0, 0x0000, 0, MX6DL_WEIM_NOR_PAD_CTRL) +#define MX6DL_PAD_EIM_D23__IPU1_DI0_D0_CS \ + IOMUX_PAD(0x0530, 0x0160, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_D23__UART3_CTS \ + IOMUX_PAD(0x0530, 0x0160, 2, 0x0000, 0, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_EIM_D23__UART3_RTS \ + IOMUX_PAD(0x0530, 0x0160, 2, 0x0908, 0, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_EIM_D23__UART1_DCD \ + IOMUX_PAD(0x0530, 0x0160, 3, 0x0000, 0, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_EIM_D23__IPU1_CSI1_DATA_EN \ + IOMUX_PAD(0x0530, 0x0160, 4, 0x08B0, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_D23__GPIO_3_23 \ + IOMUX_PAD(0x0530, 0x0160, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_D23__IPU1_DI1_PIN2 \ + IOMUX_PAD(0x0530, 0x0160, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_D23__IPU1_DI1_PIN14 \ + IOMUX_PAD(0x0530, 0x0160, 7, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_D23__EPDC_SDDO_11 \ + IOMUX_PAD(0x0530, 0x0160, 8, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_EIM_D24__WEIM_WEIM_D_24 \ + IOMUX_PAD(0x0534, 0x0164, 0, 0x0000, 0, MX6DL_WEIM_NOR_PAD_CTRL) +#define MX6DL_PAD_EIM_D24__ECSPI4_SS2 \ + IOMUX_PAD(0x0534, 0x0164, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_D24__UART3_TXD \ + IOMUX_PAD(0x0534, 0x0164, 2, 0x0000, 0, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_EIM_D24__UART3_RXD \ + IOMUX_PAD(0x0534, 0x0164, 2, 0x090C, 0, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_EIM_D24__ECSPI1_SS2 \ + IOMUX_PAD(0x0534, 0x0164, 3, 0x07EC, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_D24__ECSPI2_SS2 \ + IOMUX_PAD(0x0534, 0x0164, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_D24__GPIO_3_24 \ + IOMUX_PAD(0x0534, 0x0164, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_D24__AUDMUX_AUD5_RXFS \ + IOMUX_PAD(0x0534, 0x0164, 6, 0x07BC, 1, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_D24__UART1_DTR \ + IOMUX_PAD(0x0534, 0x0164, 7, 0x0000, 0, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_EIM_D24__EPDC_SDCE_7 \ + IOMUX_PAD(0x0534, 0x0164, 8, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_EIM_D25__WEIM_WEIM_D_25 \ + IOMUX_PAD(0x0538, 0x0168, 0, 0x0000, 0, MX6DL_WEIM_NOR_PAD_CTRL) +#define MX6DL_PAD_EIM_D25__ECSPI4_SS3 \ + IOMUX_PAD(0x0538, 0x0168, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_D25__UART3_TXD \ + IOMUX_PAD(0x0538, 0x0168, 2, 0x0000, 0, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_EIM_D25__UART3_RXD \ + IOMUX_PAD(0x0538, 0x0168, 2, 0x090C, 1, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_EIM_D25__ECSPI1_SS3 \ + IOMUX_PAD(0x0538, 0x0168, 3, 0x07F0, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_D25__ECSPI2_SS3 \ + IOMUX_PAD(0x0538, 0x0168, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_D25__GPIO_3_25 \ + IOMUX_PAD(0x0538, 0x0168, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_D25__AUDMUX_AUD5_RXC \ + IOMUX_PAD(0x0538, 0x0168, 6, 0x07B8, 1, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_D25__UART1_DSR \ + IOMUX_PAD(0x0538, 0x0168, 7, 0x0000, 0, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_EIM_D25__EPDC_SDCE_8 \ + IOMUX_PAD(0x0538, 0x0168, 8, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_EIM_D26__WEIM_WEIM_D_26 \ + IOMUX_PAD(0x053C, 0x016C, 0, 0x0000, 0, MX6DL_WEIM_NOR_PAD_CTRL) +#define MX6DL_PAD_EIM_D26__IPU1_DI1_PIN11 \ + IOMUX_PAD(0x053C, 0x016C, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_D26__IPU1_CSI0_D_1 \ + IOMUX_PAD(0x053C, 0x016C, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_D26__IPU1_CSI1_D_14 \ + IOMUX_PAD(0x053C, 0x016C, 3, 0x0898, 1, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_D26__UART2_TXD \ + IOMUX_PAD(0x053C, 0x016C, 4, 0x0000, 0, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_EIM_D26__UART2_RXD \ + IOMUX_PAD(0x053C, 0x016C, 4, 0x0904, 0, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_EIM_D26__GPIO_3_26 \ + IOMUX_PAD(0x053C, 0x016C, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_D26__IPU1_SISG_2 \ + IOMUX_PAD(0x053C, 0x016C, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_D26__IPU1_DISP1_DAT_22 \ + IOMUX_PAD(0x053C, 0x016C, 7, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_D26__EPDC_SDOED \ + IOMUX_PAD(0x053C, 0x016C, 8, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_EIM_D27__WEIM_WEIM_D_27 \ + IOMUX_PAD(0x0540, 0x0170, 0, 0x0000, 0, MX6DL_WEIM_NOR_PAD_CTRL) +#define MX6DL_PAD_EIM_D27__IPU1_DI1_PIN13 \ + IOMUX_PAD(0x0540, 0x0170, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_D27__IPU1_CSI0_D_0 \ + IOMUX_PAD(0x0540, 0x0170, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_D27__IPU1_CSI1_D_13 \ + IOMUX_PAD(0x0540, 0x0170, 3, 0x0894, 1, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_D27__UART2_TXD \ + IOMUX_PAD(0x0540, 0x0170, 4, 0x0000, 0, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_EIM_D27__UART2_RXD \ + IOMUX_PAD(0x0540, 0x0170, 4, 0x0904, 1, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_EIM_D27__GPIO_3_27 \ + IOMUX_PAD(0x0540, 0x0170, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_D27__IPU1_SISG_3 \ + IOMUX_PAD(0x0540, 0x0170, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_D27__IPU1_DISP1_DAT_23 \ + IOMUX_PAD(0x0540, 0x0170, 7, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_D27__EPDC_SDOE \ + IOMUX_PAD(0x0540, 0x0170, 8, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_EIM_D28__WEIM_WEIM_D_28 \ + IOMUX_PAD(0x0544, 0x0174, 0, 0x0000, 0, MX6DL_WEIM_NOR_PAD_CTRL) +#define MX6DL_PAD_EIM_D28__I2C1_SDA \ + IOMUX_PAD(0x0544, 0x0174, 1 | IOMUX_CONFIG_SION, 0x086C, 1, MX6DL_I2C_PAD_CTRL) +#define MX6DL_PAD_EIM_D28__ECSPI4_MOSI \ + IOMUX_PAD(0x0544, 0x0174, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_D28__IPU1_CSI1_D_12 \ + IOMUX_PAD(0x0544, 0x0174, 3, 0x0890, 1, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_D28__UART2_CTS \ + IOMUX_PAD(0x0544, 0x0174, 4, 0x0000, 0, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_EIM_D28__UART2_RTS \ + IOMUX_PAD(0x0544, 0x0174, 4, 0x0900, 0, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_EIM_D28__GPIO_3_28 \ + IOMUX_PAD(0x0544, 0x0174, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_D28__IPU1_EXT_TRIG \ + IOMUX_PAD(0x0544, 0x0174, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_D28__IPU1_DI0_PIN13 \ + IOMUX_PAD(0x0544, 0x0174, 7, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_D28__EPDC_PWRCTRL_3 \ + IOMUX_PAD(0x0544, 0x0174, 8, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_EIM_D29__WEIM_WEIM_D_29 \ + IOMUX_PAD(0x0548, 0x0178, 0, 0x0000, 0, MX6DL_WEIM_NOR_PAD_CTRL) +#define MX6DL_PAD_EIM_D29__IPU1_DI1_PIN15 \ + IOMUX_PAD(0x0548, 0x0178, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_D29__ECSPI4_SS0 \ + IOMUX_PAD(0x0548, 0x0178, 2, 0x0808, 1, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_D29__UART2_CTS \ + IOMUX_PAD(0x0548, 0x0178, 4, 0x0000, 0, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_EIM_D29__UART2_RTS \ + IOMUX_PAD(0x0548, 0x0178, 4, 0x0900, 1, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_EIM_D29__GPIO_3_29 \ + IOMUX_PAD(0x0548, 0x0178, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_D29__IPU1_CSI1_VSYNC \ + IOMUX_PAD(0x0548, 0x0178, 6, 0x08BC, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_D29__IPU1_DI0_PIN14 \ + IOMUX_PAD(0x0548, 0x0178, 7, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_D29__EPDC_PWRWAKE \ + IOMUX_PAD(0x0548, 0x0178, 8, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_EIM_D30__WEIM_WEIM_D_30 \ + IOMUX_PAD(0x054C, 0x017C, 0, 0x0000, 0, MX6DL_WEIM_NOR_PAD_CTRL) +#define MX6DL_PAD_EIM_D30__IPU1_DISP1_DAT_21 \ + IOMUX_PAD(0x054C, 0x017C, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_D30__IPU1_DI0_PIN11 \ + IOMUX_PAD(0x054C, 0x017C, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_D30__IPU1_CSI0_D_3 \ + IOMUX_PAD(0x054C, 0x017C, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_D30__UART3_CTS \ + IOMUX_PAD(0x054C, 0x017C, 4, 0x0000, 0, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_EIM_D30__UART3_RTS \ + IOMUX_PAD(0x054C, 0x017C, 4, 0x0908, 1, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_EIM_D30__GPIO_3_30 \ + IOMUX_PAD(0x054C, 0x017C, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_D30__USBOH3_USBH1_OC \ + IOMUX_PAD(0x054C, 0x017C, 6, 0x0924, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_D30__PL301_SIM_MX6DL_PER1_HPROT_0 \ + IOMUX_PAD(0x054C, 0x017C, 7, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_D30__EPDC_SDOEZ \ + IOMUX_PAD(0x054C, 0x017C, 8, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_EIM_D31__WEIM_WEIM_D_31 \ + IOMUX_PAD(0x0550, 0x0180, 0, 0x0000, 0, MX6DL_WEIM_NOR_PAD_CTRL) +#define MX6DL_PAD_EIM_D31__IPU1_DISP1_DAT_20 \ + IOMUX_PAD(0x0550, 0x0180, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_D31__IPU1_DI0_PIN12 \ + IOMUX_PAD(0x0550, 0x0180, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_D31__IPU1_CSI0_D_2 \ + IOMUX_PAD(0x0550, 0x0180, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_D31__UART3_CTS \ + IOMUX_PAD(0x0550, 0x0180, 4, 0x0000, 0, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_EIM_D31__UART3_RTS \ + IOMUX_PAD(0x0550, 0x0180, 4, 0x0908, 2, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_EIM_D31__GPIO_3_31 \ + IOMUX_PAD(0x0550, 0x0180, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_D31__USBOH3_USBH1_PWR \ + IOMUX_PAD(0x0550, 0x0180, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_D31__PL301_SIM_MX6DL_PER1_HPROT_1 \ + IOMUX_PAD(0x0550, 0x0180, 7, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_D31__EPDC_SDCLK \ + IOMUX_PAD(0x0550, 0x0180, 8, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_D31__WEIM_ACLK_FREERUN \ + IOMUX_PAD(0x0550, 0x0180, 9, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_EIM_DA0__WEIM_WEIM_DA_A_0 \ + IOMUX_PAD(0x0554, 0x0184, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA0__IPU1_DISP1_DAT_9 \ + IOMUX_PAD(0x0554, 0x0184, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA0__IPU1_CSI1_D_9 \ + IOMUX_PAD(0x0554, 0x0184, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA0__MIPI_CORE_DPHY_TEST_OUT_2 \ + IOMUX_PAD(0x0554, 0x0184, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA0__GPIO_3_0 \ + IOMUX_PAD(0x0554, 0x0184, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA0__TPSMP_HDATA_14 \ + IOMUX_PAD(0x0554, 0x0184, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA0__SRC_BT_CFG_0 \ + IOMUX_PAD(0x0554, 0x0184, 7, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA0__EPDC_SDCLKN \ + IOMUX_PAD(0x0554, 0x0184, 8, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_EIM_DA1__WEIM_WEIM_DA_A_1 \ + IOMUX_PAD(0x0558, 0x0188, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA1__IPU1_DISP1_DAT_8 \ + IOMUX_PAD(0x0558, 0x0188, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA1__IPU1_CSI1_D_8 \ + IOMUX_PAD(0x0558, 0x0188, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA1__MIPI_CORE_DPHY_TEST_OUT_3 \ + IOMUX_PAD(0x0558, 0x0188, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA1__ANATOP_USBPHY1_TSTI_TX_LS_MODE \ + IOMUX_PAD(0x0558, 0x0188, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA1__GPIO_3_1 \ + IOMUX_PAD(0x0558, 0x0188, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA1__TPSMP_HDATA_15 \ + IOMUX_PAD(0x0558, 0x0188, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA1__SRC_BT_CFG_1 \ + IOMUX_PAD(0x0558, 0x0188, 7, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA1__EPDC_SDLE \ + IOMUX_PAD(0x0558, 0x0188, 8, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_EIM_DA10__WEIM_WEIM_DA_A_10 \ + IOMUX_PAD(0x055C, 0x018C, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA10__IPU1_DI1_PIN15 \ + IOMUX_PAD(0x055C, 0x018C, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA10__IPU1_CSI1_DATA_EN \ + IOMUX_PAD(0x055C, 0x018C, 2, 0x08B0, 1, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA10__MIPI_CORE_DPHY_TEST_OUT_12 \ + IOMUX_PAD(0x055C, 0x018C, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA10__GPIO_3_10 \ + IOMUX_PAD(0x055C, 0x018C, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA10__TPSMP_HDATA_24 \ + IOMUX_PAD(0x055C, 0x018C, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA10__SRC_BT_CFG_10 \ + IOMUX_PAD(0x055C, 0x018C, 7, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA10__EPDC_SDDO_1 \ + IOMUX_PAD(0x055C, 0x018C, 8, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_EIM_DA11__WEIM_WEIM_DA_A_11 \ + IOMUX_PAD(0x0560, 0x0190, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA11__IPU1_DI1_PIN2 \ + IOMUX_PAD(0x0560, 0x0190, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA11__IPU1_CSI1_HSYNC \ + IOMUX_PAD(0x0560, 0x0190, 2, 0x08B4, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA11__MIPI_CORE_DPHY_TEST_OUT_13 \ + IOMUX_PAD(0x0560, 0x0190, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA11__SDMA_DEBUG_EVT_CHN_LINES_6 \ + IOMUX_PAD(0x0560, 0x0190, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA11__GPIO_3_11 \ + IOMUX_PAD(0x0560, 0x0190, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA11__TPSMP_HDATA_25 \ + IOMUX_PAD(0x0560, 0x0190, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA11__SRC_BT_CFG_11 \ + IOMUX_PAD(0x0560, 0x0190, 7, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA11__EPDC_SDDO_3 \ + IOMUX_PAD(0x0560, 0x0190, 8, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_EIM_DA12__WEIM_WEIM_DA_A_12 \ + IOMUX_PAD(0x0564, 0x0194, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA12__IPU1_DI1_PIN3 \ + IOMUX_PAD(0x0564, 0x0194, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA12__IPU1_CSI1_VSYNC \ + IOMUX_PAD(0x0564, 0x0194, 2, 0x08BC, 1, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA12__MIPI_CORE_DPHY_TEST_OUT_14 \ + IOMUX_PAD(0x0564, 0x0194, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_LINES_3 \ + IOMUX_PAD(0x0564, 0x0194, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA12__GPIO_3_12 \ + IOMUX_PAD(0x0564, 0x0194, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA12__TPSMP_HDATA_26 \ + IOMUX_PAD(0x0564, 0x0194, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA12__SRC_BT_CFG_12 \ + IOMUX_PAD(0x0564, 0x0194, 7, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA12__EPDC_SDDO_2 \ + IOMUX_PAD(0x0564, 0x0194, 8, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_EIM_DA13__WEIM_WEIM_DA_A_13 \ + IOMUX_PAD(0x0568, 0x0198, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA13__IPU1_DI1_D0_CS \ + IOMUX_PAD(0x0568, 0x0198, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA13__CCM_DI1_EXT_CLK \ + IOMUX_PAD(0x0568, 0x0198, 2, 0x07D0, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA13__MIPI_CORE_DPHY_TEST_OUT_15 \ + IOMUX_PAD(0x0568, 0x0198, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_LINES_4 \ + IOMUX_PAD(0x0568, 0x0198, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA13__GPIO_3_13 \ + IOMUX_PAD(0x0568, 0x0198, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA13__TPSMP_HDATA_27 \ + IOMUX_PAD(0x0568, 0x0198, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA13__SRC_BT_CFG_13 \ + IOMUX_PAD(0x0568, 0x0198, 7, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA13__EPDC_SDDO_13 \ + IOMUX_PAD(0x0568, 0x0198, 8, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_EIM_DA14__WEIM_WEIM_DA_A_14 \ + IOMUX_PAD(0x056C, 0x019C, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA14__IPU1_DI1_D1_CS \ + IOMUX_PAD(0x056C, 0x019C, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA14__CCM_DI0_EXT_CLK \ + IOMUX_PAD(0x056C, 0x019C, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA14__MIPI_CORE_DPHY_TEST_OUT_16 \ + IOMUX_PAD(0x056C, 0x019C, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_LINES_5 \ + IOMUX_PAD(0x056C, 0x019C, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA14__GPIO_3_14 \ + IOMUX_PAD(0x056C, 0x019C, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA14__TPSMP_HDATA_28 \ + IOMUX_PAD(0x056C, 0x019C, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA14__SRC_BT_CFG_14 \ + IOMUX_PAD(0x056C, 0x019C, 7, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA14__EPDC_SDDO_14 \ + IOMUX_PAD(0x056C, 0x019C, 8, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_EIM_DA15__WEIM_WEIM_DA_A_15 \ + IOMUX_PAD(0x0570, 0x01A0, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA15__IPU1_DI1_PIN1 \ + IOMUX_PAD(0x0570, 0x01A0, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA15__IPU1_DI1_PIN4 \ + IOMUX_PAD(0x0570, 0x01A0, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA15__MIPI_CORE_DPHY_TEST_OUT_17 \ + IOMUX_PAD(0x0570, 0x01A0, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA15__GPIO_3_15 \ + IOMUX_PAD(0x0570, 0x01A0, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA15__TPSMP_HDATA_29 \ + IOMUX_PAD(0x0570, 0x01A0, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA15__SRC_BT_CFG_15 \ + IOMUX_PAD(0x0570, 0x01A0, 7, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA15__EPDC_SDDO_9 \ + IOMUX_PAD(0x0570, 0x01A0, 8, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_EIM_DA2__WEIM_WEIM_DA_A_2 \ + IOMUX_PAD(0x0574, 0x01A4, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA2__IPU1_DISP1_DAT_7 \ + IOMUX_PAD(0x0574, 0x01A4, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA2__IPU1_CSI1_D_7 \ + IOMUX_PAD(0x0574, 0x01A4, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA2__MIPI_CORE_DPHY_TEST_OUT_4 \ + IOMUX_PAD(0x0574, 0x01A4, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA2__ANATOP_USBPHY1_TSTI_TX_HS_MODE \ + IOMUX_PAD(0x0574, 0x01A4, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA2__GPIO_3_2 \ + IOMUX_PAD(0x0574, 0x01A4, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA2__TPSMP_HDATA_16 \ + IOMUX_PAD(0x0574, 0x01A4, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA2__SRC_BT_CFG_2 \ + IOMUX_PAD(0x0574, 0x01A4, 7, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA2__EPDC_BDR_0 \ + IOMUX_PAD(0x0574, 0x01A4, 8, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_EIM_DA3__WEIM_WEIM_DA_A_3 \ + IOMUX_PAD(0x0578, 0x01A8, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA3__IPU1_DISP1_DAT_6 \ + IOMUX_PAD(0x0578, 0x01A8, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA3__IPU1_CSI1_D_6 \ + IOMUX_PAD(0x0578, 0x01A8, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA3__MIPI_CORE_DPHY_TEST_OUT_5 \ + IOMUX_PAD(0x0578, 0x01A8, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA3__ANATOP_USBPHY1_TSTI_TX_HIZ \ + IOMUX_PAD(0x0578, 0x01A8, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA3__GPIO_3_3 \ + IOMUX_PAD(0x0578, 0x01A8, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA3__TPSMP_HDATA_17 \ + IOMUX_PAD(0x0578, 0x01A8, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA3__SRC_BT_CFG_3 \ + IOMUX_PAD(0x0578, 0x01A8, 7, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA3__EPDC_BDR_1 \ + IOMUX_PAD(0x0578, 0x01A8, 8, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_EIM_DA4__WEIM_WEIM_DA_A_4 \ + IOMUX_PAD(0x057C, 0x01AC, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA4__IPU1_DISP1_DAT_5 \ + IOMUX_PAD(0x057C, 0x01AC, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA4__IPU1_CSI1_D_5 \ + IOMUX_PAD(0x057C, 0x01AC, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA4__MIPI_CORE_DPHY_TEST_OUT_6 \ + IOMUX_PAD(0x057C, 0x01AC, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA4__ANATOP_USBPHY1_TSTI_TX_EN \ + IOMUX_PAD(0x057C, 0x01AC, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA4__GPIO_3_4 \ + IOMUX_PAD(0x057C, 0x01AC, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA4__TPSMP_HDATA_18 \ + IOMUX_PAD(0x057C, 0x01AC, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA4__SRC_BT_CFG_4 \ + IOMUX_PAD(0x057C, 0x01AC, 7, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA4__EPDC_SDCE_0 \ + IOMUX_PAD(0x057C, 0x01AC, 8, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_EIM_DA5__WEIM_WEIM_DA_A_5 \ + IOMUX_PAD(0x0580, 0x01B0, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA5__IPU1_DISP1_DAT_4 \ + IOMUX_PAD(0x0580, 0x01B0, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA5__IPU1_CSI1_D_4 \ + IOMUX_PAD(0x0580, 0x01B0, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA5__MIPI_CORE_DPHY_TEST_OUT_7 \ + IOMUX_PAD(0x0580, 0x01B0, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA5__ANATOP_USBPHY1_TSTI_TX_DP \ + IOMUX_PAD(0x0580, 0x01B0, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA5__GPIO_3_5 \ + IOMUX_PAD(0x0580, 0x01B0, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA5__TPSMP_HDATA_19 \ + IOMUX_PAD(0x0580, 0x01B0, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA5__SRC_BT_CFG_5 \ + IOMUX_PAD(0x0580, 0x01B0, 7, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA5__EPDC_SDCE_1 \ + IOMUX_PAD(0x0580, 0x01B0, 8, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_EIM_DA6__WEIM_WEIM_DA_A_6 \ + IOMUX_PAD(0x0584, 0x01B4, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA6__IPU1_DISP1_DAT_3 \ + IOMUX_PAD(0x0584, 0x01B4, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA6__IPU1_CSI1_D_3 \ + IOMUX_PAD(0x0584, 0x01B4, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA6__MIPI_CORE_DPHY_TEST_OUT_8 \ + IOMUX_PAD(0x0584, 0x01B4, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA6__ANATOP_USBPHY1_TSTI_TX_DN \ + IOMUX_PAD(0x0584, 0x01B4, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA6__GPIO_3_6 \ + IOMUX_PAD(0x0584, 0x01B4, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA6__TPSMP_HDATA_20 \ + IOMUX_PAD(0x0584, 0x01B4, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA6__SRC_BT_CFG_6 \ + IOMUX_PAD(0x0584, 0x01B4, 7, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA6__EPDC_SDCE_2 \ + IOMUX_PAD(0x0584, 0x01B4, 8, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_EIM_DA7__WEIM_WEIM_DA_A_7 \ + IOMUX_PAD(0x0588, 0x01B8, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA7__IPU1_DISP1_DAT_2 \ + IOMUX_PAD(0x0588, 0x01B8, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA7__IPU1_CSI1_D_2 \ + IOMUX_PAD(0x0588, 0x01B8, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA7__MIPI_CORE_DPHY_TEST_OUT_9 \ + IOMUX_PAD(0x0588, 0x01B8, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA7__GPIO_3_7 \ + IOMUX_PAD(0x0588, 0x01B8, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA7__TPSMP_HDATA_21 \ + IOMUX_PAD(0x0588, 0x01B8, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA7__SRC_BT_CFG_7 \ + IOMUX_PAD(0x0588, 0x01B8, 7, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA7__EPDC_SDCE_3 \ + IOMUX_PAD(0x0588, 0x01B8, 8, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_EIM_DA8__WEIM_WEIM_DA_A_8 \ + IOMUX_PAD(0x058C, 0x01BC, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA8__IPU1_DISP1_DAT_1 \ + IOMUX_PAD(0x058C, 0x01BC, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA8__IPU1_CSI1_D_1 \ + IOMUX_PAD(0x058C, 0x01BC, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA8__MIPI_CORE_DPHY_TEST_OUT_10 \ + IOMUX_PAD(0x058C, 0x01BC, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA8__GPIO_3_8 \ + IOMUX_PAD(0x058C, 0x01BC, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA8__TPSMP_HDATA_22 \ + IOMUX_PAD(0x058C, 0x01BC, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA8__SRC_BT_CFG_8 \ + IOMUX_PAD(0x058C, 0x01BC, 7, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA8__EPDC_SDCE_4 \ + IOMUX_PAD(0x058C, 0x01BC, 8, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_EIM_DA9__WEIM_WEIM_DA_A_9 \ + IOMUX_PAD(0x0590, 0x01C0, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA9__IPU1_DISP1_DAT_0 \ + IOMUX_PAD(0x0590, 0x01C0, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA9__IPU1_CSI1_D_0 \ + IOMUX_PAD(0x0590, 0x01C0, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA9__MIPI_CORE_DPHY_TEST_OUT_11 \ + IOMUX_PAD(0x0590, 0x01C0, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA9__GPIO_3_9 \ + IOMUX_PAD(0x0590, 0x01C0, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA9__TPSMP_HDATA_23 \ + IOMUX_PAD(0x0590, 0x01C0, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA9__SRC_BT_CFG_9 \ + IOMUX_PAD(0x0590, 0x01C0, 7, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_DA9__EPDC_SDCE_5 \ + IOMUX_PAD(0x0590, 0x01C0, 8, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_EIM_EB0__WEIM_WEIM_EB_0 \ + IOMUX_PAD(0x0594, 0x01C4, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_EB0__IPU1_DISP1_DAT_11 \ + IOMUX_PAD(0x0594, 0x01C4, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_EB0__IPU1_CSI1_D_11 \ + IOMUX_PAD(0x0594, 0x01C4, 2, 0x088C, 1, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_EB0__MIPI_CORE_DPHY_TEST_OUT_0 \ + IOMUX_PAD(0x0594, 0x01C4, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_EB0__CCM_PMIC_RDY \ + IOMUX_PAD(0x0594, 0x01C4, 4, 0x07D4, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_EB0__GPIO_2_28 \ + IOMUX_PAD(0x0594, 0x01C4, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_EB0__TPSMP_HDATA_12 \ + IOMUX_PAD(0x0594, 0x01C4, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_EB0__SRC_BT_CFG_27 \ + IOMUX_PAD(0x0594, 0x01C4, 7, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_EB0__EPDC_PWRCOM \ + IOMUX_PAD(0x0594, 0x01C4, 8, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_EIM_EB1__WEIM_WEIM_EB_1 \ + IOMUX_PAD(0x0598, 0x01C8, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_EB1__IPU1_DISP1_DAT_10 \ + IOMUX_PAD(0x0598, 0x01C8, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_EB1__IPU1_CSI1_D_10 \ + IOMUX_PAD(0x0598, 0x01C8, 2, 0x0888, 1, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_EB1__MIPI_CORE_DPHY_TEST_OUT_1 \ + IOMUX_PAD(0x0598, 0x01C8, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_EB1__GPIO_2_29 \ + IOMUX_PAD(0x0598, 0x01C8, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_EB1__TPSMP_HDATA_13 \ + IOMUX_PAD(0x0598, 0x01C8, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_EB1__SRC_BT_CFG_28 \ + IOMUX_PAD(0x0598, 0x01C8, 7, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_EB1__EPDC_SDSHR \ + IOMUX_PAD(0x0598, 0x01C8, 8, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_EIM_EB2__WEIM_WEIM_EB_2 \ + IOMUX_PAD(0x059C, 0x01CC, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_EB2__ECSPI1_SS0 \ + IOMUX_PAD(0x059C, 0x01CC, 1, 0x07E4, 2, MX6DL_ECSPI_PAD_CTRL) +#define MX6DL_PAD_EIM_EB2__CCM_DI1_EXT_CLK \ + IOMUX_PAD(0x059C, 0x01CC, 2, 0x07D0, 1, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_EB2__IPU1_CSI1_D_19 \ + IOMUX_PAD(0x059C, 0x01CC, 3, 0x08AC, 1, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_EB2__HDMI_TX_DDC_SCL \ + IOMUX_PAD(0x059C, 0x01CC, 4, 0x0860, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_EB2__GPIO_2_30 \ + IOMUX_PAD(0x059C, 0x01CC, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_EB2__I2C2_SCL \ + IOMUX_PAD(0x059C, 0x01CC, 6 | IOMUX_CONFIG_SION, 0x0870, 0, MX6DL_I2C_PAD_CTRL) +#define MX6DL_PAD_EIM_EB2__SRC_BT_CFG_30 \ + IOMUX_PAD(0x059C, 0x01CC, 7, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_EB2__EPDC_SDDO_5 \ + IOMUX_PAD(0x059C, 0x01CC, 8, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_EIM_EB3__WEIM_WEIM_EB_3 \ + IOMUX_PAD(0x05A0, 0x01D0, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_EB3__ECSPI4_RDY \ + IOMUX_PAD(0x05A0, 0x01D0, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_EB3__UART3_CTS \ + IOMUX_PAD(0x05A0, 0x01D0, 2, 0x0000, 0, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_EIM_EB3__UART3_RTS \ + IOMUX_PAD(0x05A0, 0x01D0, 2, 0x0908, 3, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_EIM_EB3__UART1_RI \ + IOMUX_PAD(0x05A0, 0x01D0, 3, 0x0000, 0, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_EIM_EB3__IPU1_CSI1_HSYNC \ + IOMUX_PAD(0x05A0, 0x01D0, 4, 0x08B4, 1, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_EB3__GPIO_2_31 \ + IOMUX_PAD(0x05A0, 0x01D0, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_EB3__IPU1_DI1_PIN3 \ + IOMUX_PAD(0x05A0, 0x01D0, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_EB3__SRC_BT_CFG_31 \ + IOMUX_PAD(0x05A0, 0x01D0, 7, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_EB3__EPDC_SDCE_0 \ + IOMUX_PAD(0x05A0, 0x01D0, 8, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_EB3__WEIM_ACLK_FREERUN \ + IOMUX_PAD(0x05A0, 0x01D0, 9, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_EIM_LBA__WEIM_WEIM_LBA \ + IOMUX_PAD(0x05A4, 0x01D4, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_LBA__IPU1_DI1_PIN17 \ + IOMUX_PAD(0x05A4, 0x01D4, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_LBA__ECSPI2_SS1 \ + IOMUX_PAD(0x05A4, 0x01D4, 2, 0x0804, 1, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_LBA__GPIO_2_27 \ + IOMUX_PAD(0x05A4, 0x01D4, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_LBA__TPSMP_HDATA_11 \ + IOMUX_PAD(0x05A4, 0x01D4, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_LBA__SRC_BT_CFG_26 \ + IOMUX_PAD(0x05A4, 0x01D4, 7, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_LBA__EPDC_SDDO_4 \ + IOMUX_PAD(0x05A4, 0x01D4, 8, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_EIM_OE__WEIM_WEIM_OE \ + IOMUX_PAD(0x05A8, 0x01D8, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_OE__IPU1_DI1_PIN7 \ + IOMUX_PAD(0x05A8, 0x01D8, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_OE__ECSPI2_MISO \ + IOMUX_PAD(0x05A8, 0x01D8, 2, 0x07F8, 2, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_OE__MIPI_CORE_DPHY_TEST_OUT_26 \ + IOMUX_PAD(0x05A8, 0x01D8, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_OE__GPIO_2_25 \ + IOMUX_PAD(0x05A8, 0x01D8, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_OE__TPSMP_HDATA_9 \ + IOMUX_PAD(0x05A8, 0x01D8, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_OE__EPDC_PWRIRQ \ + IOMUX_PAD(0x05A8, 0x01D8, 8, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_EIM_RW__WEIM_WEIM_RW \ + IOMUX_PAD(0x05AC, 0x01DC, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_RW__IPU1_DI1_PIN8 \ + IOMUX_PAD(0x05AC, 0x01DC, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_RW__ECSPI2_SS0 \ + IOMUX_PAD(0x05AC, 0x01DC, 2, 0x0800, 2, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_RW__MIPI_CORE_DPHY_TEST_OUT_27 \ + IOMUX_PAD(0x05AC, 0x01DC, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_RW__GPIO_2_26 \ + IOMUX_PAD(0x05AC, 0x01DC, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_RW__TPSMP_HDATA_10 \ + IOMUX_PAD(0x05AC, 0x01DC, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_RW__SRC_BT_CFG_29 \ + IOMUX_PAD(0x05AC, 0x01DC, 7, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_RW__EPDC_SDDO_7 \ + IOMUX_PAD(0x05AC, 0x01DC, 8, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_EIM_WAIT__WEIM_WEIM_WAIT \ + IOMUX_PAD(0x05B0, 0x01E0, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B \ + IOMUX_PAD(0x05B0, 0x01E0, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_WAIT__GPIO_5_0 \ + IOMUX_PAD(0x05B0, 0x01E0, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_WAIT__TPSMP_HDATA_30 \ + IOMUX_PAD(0x05B0, 0x01E0, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_EIM_WAIT__SRC_BT_CFG_25 \ + IOMUX_PAD(0x05B0, 0x01E0, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_ENET_CRS_DV__ENET_RX_EN \ + IOMUX_PAD(0x05B4, 0x01E4, 1, 0x0828, 0, NO_PAD_CTRL) +#define MX6DL_PAD_ENET_CRS_DV__ESAI1_SCKT \ + IOMUX_PAD(0x05B4, 0x01E4, 2, 0x0840, 0, MX6DL_ESAI_PAD_CTRL) +#define MX6DL_PAD_ENET_CRS_DV__SPDIF_SPDIF_EXTCLK \ + IOMUX_PAD(0x05B4, 0x01E4, 3, 0x08F4, 0, NO_PAD_CTRL) +#define MX6DL_PAD_ENET_CRS_DV__GPIO_1_25 \ + IOMUX_PAD(0x05B4, 0x01E4, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_ENET_CRS_DV__PHY_TDO \ + IOMUX_PAD(0x05B4, 0x01E4, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_ENET_CRS_DV__ANATOP_USBPHY1_TSTO_RX_FS_RXD \ + IOMUX_PAD(0x05B4, 0x01E4, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_ENET_MDC__MLB_MLBDAT \ + IOMUX_PAD(0x05B8, 0x01E8, 0, 0x08E0, 0, NO_PAD_CTRL) +#define MX6DL_PAD_ENET_MDC__ENET_MDC \ + IOMUX_PAD(0x05B8, 0x01E8, 1, 0x0000, 0, MX6DL_ENET_PAD_CTRL) +#define MX6DL_PAD_ENET_MDC__ESAI1_TX5_RX0 \ + IOMUX_PAD(0x05B8, 0x01E8, 2, 0x0858, 0, MX6DL_ESAI_PAD_CTRL) +#define MX6DL_PAD_ENET_MDC__ENET_1588_EVENT1_IN \ + IOMUX_PAD(0x05B8, 0x01E8, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_ENET_MDC__GPIO_1_31 \ + IOMUX_PAD(0x05B8, 0x01E8, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_ENET_MDC__ANATOP_USBPHY2_TSTO_RX_DISCON_DET \ + IOMUX_PAD(0x05B8, 0x01E8, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_ENET_MDIO__ENET_MDIO \ + IOMUX_PAD(0x05BC, 0x01EC, 1, 0x0810, 0, MX6DL_ENET_PAD_CTRL) +#define MX6DL_PAD_ENET_MDIO__ESAI1_SCKR \ + IOMUX_PAD(0x05BC, 0x01EC, 2, 0x083C, 0, NO_PAD_CTRL) +#define MX6DL_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEVICE_3 \ + IOMUX_PAD(0x05BC, 0x01EC, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT \ + IOMUX_PAD(0x05BC, 0x01EC, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_ENET_MDIO__GPIO_1_22 \ + IOMUX_PAD(0x05BC, 0x01EC, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_ENET_MDIO__SPDIF_PLOCK \ + IOMUX_PAD(0x05BC, 0x01EC, 6, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK \ + IOMUX_PAD(0x05C0, 0x01F0, 1, 0x0000, 0, MX6DL_ENET_REF_CLK_PAD_CTRL) +#define MX6DL_PAD_ENET_REF_CLK__ESAI1_FSR \ + IOMUX_PAD(0x05C0, 0x01F0, 2, 0x082C, 0, NO_PAD_CTRL) +#define MX6DL_PAD_ENET_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 \ + IOMUX_PAD(0x05C0, 0x01F0, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_ENET_REF_CLK__GPIO_1_23 \ + IOMUX_PAD(0x05C0, 0x01F0, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_ENET_REF_CLK__SPDIF_SRCLK \ + IOMUX_PAD(0x05C0, 0x01F0, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_ENET_REF_CLK__ANATOP_USBPHY1_TSTO_RX_SQUELCH \ + IOMUX_PAD(0x05C0, 0x01F0, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_ENET_RX_ER__ANATOP_USBOTG_ID \ + IOMUX_PAD(0x05C4, 0x01F4, 0, 0x0790, 0, NO_PAD_CTRL) +#define MX6DL_PAD_ENET_RX_ER__ENET_RX_ER \ + IOMUX_PAD(0x05C4, 0x01F4, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_ENET_RX_ER__ESAI1_HCKR \ + IOMUX_PAD(0x05C4, 0x01F4, 2, 0x0834, 0, MX6DL_ESAI_PAD_CTRL) +#define MX6DL_PAD_ENET_RX_ER__SPDIF_IN1 \ + IOMUX_PAD(0x05C4, 0x01F4, 3, 0x08F0, 1, NO_PAD_CTRL) +#define MX6DL_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT \ + IOMUX_PAD(0x05C4, 0x01F4, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_ENET_RX_ER__GPIO_1_24 \ + IOMUX_PAD(0x05C4, 0x01F4, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_ENET_RX_ER__PHY_TDI \ + IOMUX_PAD(0x05C4, 0x01F4, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_ENET_RX_ER__ANATOP_USBPHY1_TSTO_RX_HS_RXD \ + IOMUX_PAD(0x05C4, 0x01F4, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_ENET_RXD0__OSC32K_32K_OUT \ + IOMUX_PAD(0x05C8, 0x01F8, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_ENET_RXD0__ENET_RDATA_0 \ + IOMUX_PAD(0x05C8, 0x01F8, 1, 0x0818, 0, NO_PAD_CTRL) +#define MX6DL_PAD_ENET_RXD0__ESAI1_HCKT \ + IOMUX_PAD(0x05C8, 0x01F8, 2, 0x0838, 0, MX6DL_ESAI_PAD_CTRL) +#define MX6DL_PAD_ENET_RXD0__SPDIF_OUT1 \ + IOMUX_PAD(0x05C8, 0x01F8, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_ENET_RXD0__GPIO_1_27 \ + IOMUX_PAD(0x05C8, 0x01F8, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_ENET_RXD0__PHY_TMS \ + IOMUX_PAD(0x05C8, 0x01F8, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_ENET_RXD0__ANATOP_USBPHY1_TSTO_PLL_CLK20DIV \ + IOMUX_PAD(0x05C8, 0x01F8, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_ENET_RXD1__MLB_MLBSIG \ + IOMUX_PAD(0x05CC, 0x01FC, 0, 0x08E4, 0, NO_PAD_CTRL) +#define MX6DL_PAD_ENET_RXD1__ENET_RDATA_1 \ + IOMUX_PAD(0x05CC, 0x01FC, 1, 0x081C, 0, NO_PAD_CTRL) +#define MX6DL_PAD_ENET_RXD1__ESAI1_FST \ + IOMUX_PAD(0x05CC, 0x01FC, 2, 0x0830, 0, MX6DL_ESAI_PAD_CTRL) +#define MX6DL_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT \ + IOMUX_PAD(0x05CC, 0x01FC, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_ENET_RXD1__GPIO_1_26 \ + IOMUX_PAD(0x05CC, 0x01FC, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_ENET_RXD1__PHY_TCK \ + IOMUX_PAD(0x05CC, 0x01FC, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_ENET_RXD1__ANATOP_USBPHY1_TSTO_RX_DISCON_DET \ + IOMUX_PAD(0x05CC, 0x01FC, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_ENET_TX_EN__ENET_TX_EN \ + IOMUX_PAD(0x05D0, 0x0200, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_ENET_TX_EN__ESAI1_TX3_RX2 \ + IOMUX_PAD(0x05D0, 0x0200, 2, 0x0850, 0, MX6DL_ESAI_PAD_CTRL) +#define MX6DL_PAD_ENET_TX_EN__GPIO_1_28 \ + IOMUX_PAD(0x05D0, 0x0200, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_ENET_TX_EN__ANATOP_USBPHY2_TSTO_RX_SQUELCH \ + IOMUX_PAD(0x05D0, 0x0200, 7, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_ENET_TX_EN__I2C4_SCL \ + IOMUX_PAD(0x05D0, 0x0200, 9 | IOMUX_CONFIG_SION, 0x0880, 0, MX6DL_I2C_PAD_CTRL) + +#define MX6DL_PAD_ENET_TXD0__ENET_TDATA_0 \ + IOMUX_PAD(0x05D4, 0x0204, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_ENET_TXD0__ESAI1_TX4_RX1 \ + IOMUX_PAD(0x05D4, 0x0204, 2, 0x0854, 0, MX6DL_ESAI_PAD_CTRL) +#define MX6DL_PAD_ENET_TXD0__GPIO_1_30 \ + IOMUX_PAD(0x05D4, 0x0204, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_ENET_TXD0__ANATOP_USBPHY2_TSTO_RX_FS_RXD \ + IOMUX_PAD(0x05D4, 0x0204, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_ENET_TXD1__MLB_MLBCLK \ + IOMUX_PAD(0x05D8, 0x0208, 0, 0x08DC, 0, NO_PAD_CTRL) +#define MX6DL_PAD_ENET_TXD1__ENET_TDATA_1 \ + IOMUX_PAD(0x05D8, 0x0208, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_ENET_TXD1__ESAI1_TX2_RX3 \ + IOMUX_PAD(0x05D8, 0x0208, 2, 0x084C, 0, MX6DL_ESAI_PAD_CTRL) +#define MX6DL_PAD_ENET_TXD1__ENET_1588_EVENT0_IN \ + IOMUX_PAD(0x05D8, 0x0208, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_ENET_TXD1__GPIO_1_29 \ + IOMUX_PAD(0x05D8, 0x0208, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_ENET_TXD1__ANATOP_USBPHY2_TSTO_RX_HS_RXD \ + IOMUX_PAD(0x05D8, 0x0208, 7, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_ENET_TXD1__I2C4_SDA \ + IOMUX_PAD(0x05D8, 0x0208, 9 | IOMUX_CONFIG_SION, 0x0884, 0, MX6DL_I2C_PAD_CTRL) + +#define MX6DL_PAD_GPIO_0__CCM_CLKO \ + IOMUX_PAD(0x05DC, 0x020C, 0, 0x0000, 0, MX6DL_CCM_CLK0_PAD_CTRL) +#define MX6DL_PAD_GPIO_0__KPP_COL_5 \ + IOMUX_PAD(0x05DC, 0x020C, 2, 0x08C0, 1, NO_PAD_CTRL) +#define MX6DL_PAD_GPIO_0__ASRC_ASRC_EXT_CLK \ + IOMUX_PAD(0x05DC, 0x020C, 3, 0x0794, 0, NO_PAD_CTRL) +#define MX6DL_PAD_GPIO_0__EPIT1_EPITO \ + IOMUX_PAD(0x05DC, 0x020C, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_GPIO_0__GPIO_1_0 \ + IOMUX_PAD(0x05DC, 0x020C, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_GPIO_0__USBOH3_USBH1_PWR \ + IOMUX_PAD(0x05DC, 0x020C, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_GPIO_0__SNVS_HP_WRAPPER_SNVS_VIO_5 \ + IOMUX_PAD(0x05DC, 0x020C, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_GPIO_1__ESAI1_SCKR \ + IOMUX_PAD(0x05E0, 0x0210, 0, 0x083C, 1, NO_PAD_CTRL) +#define MX6DL_PAD_GPIO_1__WDOG2_WDOG_B \ + IOMUX_PAD(0x05E0, 0x0210, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_GPIO_1__KPP_ROW_5 \ + IOMUX_PAD(0x05E0, 0x0210, 2, 0x08CC, 1, NO_PAD_CTRL) +#define MX6DL_PAD_GPIO_1__USBOTG_ID \ + IOMUX_PAD(0x05E0, 0x0210, 3, 0x0790, 1, NO_PAD_CTRL) +#define MX6DL_PAD_GPIO_1__PWM2_PWMO \ + IOMUX_PAD(0x05E0, 0x0210, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_GPIO_1__GPIO_1_1 \ + IOMUX_PAD(0x05E0, 0x0210, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_GPIO_1__USDHC1_CD \ + IOMUX_PAD(0x05E0, 0x0210, 6, 0x0000, 0, MX6DL_USDHC_PAD_CTRL) +#define MX6DL_PAD_GPIO_1__SRC_TESTER_ACK \ + IOMUX_PAD(0x05E0, 0x0210, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_GPIO_16__ESAI1_TX3_RX2 \ + IOMUX_PAD(0x05E4, 0x0214, 0, 0x0850, 1, NO_PAD_CTRL) +#define MX6DL_PAD_GPIO_16__ENET_1588_EVENT2_IN \ + IOMUX_PAD(0x05E4, 0x0214, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT \ + IOMUX_PAD(0x05E4, 0x0214, 0x12, 0x080C, 0, NO_PAD_CTRL) +#define MX6DL_PAD_GPIO_16__USDHC1_LCTL \ + IOMUX_PAD(0x05E4, 0x0214, 3, 0x0000, 0, MX6DL_USDHC_PAD_CTRL) +#define MX6DL_PAD_GPIO_16__SPDIF_IN1 \ + IOMUX_PAD(0x05E4, 0x0214, 4, 0x08F0, 2, NO_PAD_CTRL) +#define MX6DL_PAD_GPIO_16__GPIO_7_11 \ + IOMUX_PAD(0x05E4, 0x0214, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_GPIO_16__I2C3_SDA \ + IOMUX_PAD(0x05E4, 0x0214, 6 | IOMUX_CONFIG_SION, 0x087C, 1, MX6DL_I2C_PAD_CTRL) +#define MX6DL_PAD_GPIO_16__SJC_DE_B \ + IOMUX_PAD(0x05E4, 0x0214, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_GPIO_17__ESAI1_TX0 \ + IOMUX_PAD(0x05E8, 0x0218, 0, 0x0844, 0, MX6DL_ESAI_PAD_CTRL) +#define MX6DL_PAD_GPIO_17__ENET_1588_EVENT3_IN \ + IOMUX_PAD(0x05E8, 0x0218, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_GPIO_17__CCM_PMIC_RDY \ + IOMUX_PAD(0x05E8, 0x0218, 2, 0x07D4, 1, NO_PAD_CTRL) +#define MX6DL_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0 \ + IOMUX_PAD(0x05E8, 0x0218, 3, 0x08E8, 1, NO_PAD_CTRL) +#define MX6DL_PAD_GPIO_17__SPDIF_OUT1 \ + IOMUX_PAD(0x05E8, 0x0218, 4, 0x0000, 0, MX6DL_SPDIF_OUT_PAD_CTRL) +#define MX6DL_PAD_GPIO_17__GPIO_7_12 \ + IOMUX_PAD(0x05E8, 0x0218, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_GPIO_17__SJC_JTAG_ACT \ + IOMUX_PAD(0x05E8, 0x0218, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_GPIO_18__ESAI1_TX1 \ + IOMUX_PAD(0x05EC, 0x021C, 0, 0x0848, 0, NO_PAD_CTRL) +#define MX6DL_PAD_GPIO_18__ENET_RX_CLK \ + IOMUX_PAD(0x05EC, 0x021C, 1, 0x0814, 0, NO_PAD_CTRL) +#define MX6DL_PAD_GPIO_18__USDHC3_VSELECT \ + IOMUX_PAD(0x05EC, 0x021C, 2, 0x0000, 0, MX6DL_USDHC_PAD_CTRL) +#define MX6DL_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1 \ + IOMUX_PAD(0x05EC, 0x021C, 3, 0x08EC, 1, NO_PAD_CTRL) +#define MX6DL_PAD_GPIO_18__ASRC_ASRC_EXT_CLK \ + IOMUX_PAD(0x05EC, 0x021C, 4, 0x0794, 1, NO_PAD_CTRL) +#define MX6DL_PAD_GPIO_18__GPIO_7_13 \ + IOMUX_PAD(0x05EC, 0x021C, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_GPIO_18__SNVS_HP_WRAPPER_SNVS_VIO_5_CTL \ + IOMUX_PAD(0x05EC, 0x021C, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_GPIO_18__SRC_SYSTEM_RST \ + IOMUX_PAD(0x05EC, 0x021C, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_GPIO_19__KPP_COL_5 \ + IOMUX_PAD(0x05F0, 0x0220, 0, 0x08C0, 2, NO_PAD_CTRL) +#define MX6DL_PAD_GPIO_19__ENET_1588_EVENT0_OUT \ + IOMUX_PAD(0x05F0, 0x0220, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_GPIO_19__SPDIF_OUT1 \ + IOMUX_PAD(0x05F0, 0x0220, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_GPIO_19__CCM_CLKO \ + IOMUX_PAD(0x05F0, 0x0220, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_GPIO_19__ECSPI1_RDY \ + IOMUX_PAD(0x05F0, 0x0220, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_GPIO_19__GPIO_4_5 \ + IOMUX_PAD(0x05F0, 0x0220, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_GPIO_19__ENET_TX_ER \ + IOMUX_PAD(0x05F0, 0x0220, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_GPIO_19__SRC_INT_BOOT \ + IOMUX_PAD(0x05F0, 0x0220, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_GPIO_2__ESAI1_FST \ + IOMUX_PAD(0x05F4, 0x0224, 0, 0x0830, 1, NO_PAD_CTRL) +#define MX6DL_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 \ + IOMUX_PAD(0x05F4, 0x0224, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_GPIO_2__KPP_ROW_6 \ + IOMUX_PAD(0x05F4, 0x0224, 2, 0x08D0, 1, NO_PAD_CTRL) +#define MX6DL_PAD_GPIO_2__CCM_CCM_OUT_1 \ + IOMUX_PAD(0x05F4, 0x0224, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 \ + IOMUX_PAD(0x05F4, 0x0224, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_GPIO_2__GPIO_1_2 \ + IOMUX_PAD(0x05F4, 0x0224, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_GPIO_2__USDHC2_WP \ + IOMUX_PAD(0x05F4, 0x0224, 6, 0x0000, 0, MX6DL_USDHC_PAD_CTRL) +#define MX6DL_PAD_GPIO_2__MLB_MLBDAT \ + IOMUX_PAD(0x05F4, 0x0224, 7, 0x08E0, 1, MX6DL_MLB150_PAD_CTRL) + +#define MX6DL_PAD_GPIO_3__ESAI1_HCKR \ + IOMUX_PAD(0x05F8, 0x0228, 0, 0x0834, 1, NO_PAD_CTRL) +#define MX6DL_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 \ + IOMUX_PAD(0x05F8, 0x0228, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_GPIO_3__I2C3_SCL \ + IOMUX_PAD(0x05F8, 0x0228, 2 | IOMUX_CONFIG_SION, 0x0878, 1, MX6DL_I2C_PAD_CTRL) +#define MX6DL_PAD_GPIO_3__ANATOP_ANATOP_24M_OUT \ + IOMUX_PAD(0x05F8, 0x0228, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_GPIO_3__CCM_CLKO2 \ + IOMUX_PAD(0x05F8, 0x0228, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_GPIO_3__GPIO_1_3 \ + IOMUX_PAD(0x05F8, 0x0228, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_GPIO_3__USBOH3_USBH1_OC \ + IOMUX_PAD(0x05F8, 0x0228, 6, 0x0924, 1, NO_PAD_CTRL) +#define MX6DL_PAD_GPIO_3__MLB_MLBCLK \ + IOMUX_PAD(0x05F8, 0x0228, 7, 0x08DC, 1, MX6DL_MLB150_PAD_CTRL) + +#define MX6DL_PAD_GPIO_4__ESAI1_HCKT \ + IOMUX_PAD(0x05FC, 0x022C, 0, 0x0838, 1, NO_PAD_CTRL) +#define MX6DL_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 \ + IOMUX_PAD(0x05FC, 0x022C, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_GPIO_4__KPP_COL_7 \ + IOMUX_PAD(0x05FC, 0x022C, 2, 0x08C8, 1, NO_PAD_CTRL) +#define MX6DL_PAD_GPIO_4__CCM_CCM_OUT_2 \ + IOMUX_PAD(0x05FC, 0x022C, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 \ + IOMUX_PAD(0x05FC, 0x022C, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_GPIO_4__GPIO_1_4 \ + IOMUX_PAD(0x05FC, 0x022C, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_GPIO_4__USDHC2_CD \ + IOMUX_PAD(0x05FC, 0x022C, 6, 0x0000, 0, MX6DL_USDHC_PAD_CTRL) +#define MX6DL_PAD_GPIO_4__OCOTP_CTRL_WRAPPER_FUSE_LATCHED \ + IOMUX_PAD(0x05FC, 0x022C, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_GPIO_5__ESAI1_TX2_RX3 \ + IOMUX_PAD(0x0600, 0x0230, 0, 0x084C, 1, MX6DL_ESAI_PAD_CTRL) +#define MX6DL_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 \ + IOMUX_PAD(0x0600, 0x0230, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_GPIO_5__KPP_ROW_7 \ + IOMUX_PAD(0x0600, 0x0230, 2, 0x08D4, 1, NO_PAD_CTRL) +#define MX6DL_PAD_GPIO_5__CCM_CLKO \ + IOMUX_PAD(0x0600, 0x0230, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 \ + IOMUX_PAD(0x0600, 0x0230, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_GPIO_5__GPIO_1_5 \ + IOMUX_PAD(0x0600, 0x0230, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_GPIO_5__I2C3_SCL \ + IOMUX_PAD(0x0600, 0x0230, 6 | IOMUX_CONFIG_SION, 0x0878, 2, MX6DL_I2C_PAD_CTRL) +#define MX6DL_PAD_GPIO_5__SIMBA_EVENTI \ + IOMUX_PAD(0x0600, 0x0230, 7, 0x0000, 0, NO_PAD_CTRL) + +#ifdef CONFIG_MX6_ENET_IRQ_TO_GPIO +#define MX6DL_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 \ + IOMUX_PAD(0x0604, 0x0234, 1 | IOMUX_CONFIG_SION, 0x0000, 0, ENET_IRQ_PAD_CTRL) +#else +#define MX6DL_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 \ + IOMUX_PAD(0x0604, 0x0234, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_GPIO_6__ESAI1_SCKT \ + IOMUX_PAD(0x0604, 0x0234, 0, 0x0840, 1, NO_PAD_CTRL) +#define MX6DL_PAD_GPIO_6__I2C3_SDA \ + IOMUX_PAD(0x0604, 0x0234, 2 | IOMUX_CONFIG_SION, 0x087C, 2, MX6DL_I2C_PAD_CTRL) +#define MX6DL_PAD_GPIO_6__CCM_CCM_OUT_0 \ + IOMUX_PAD(0x0604, 0x0234, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_GPIO_6__CSU_CSU_INT_DEB \ + IOMUX_PAD(0x0604, 0x0234, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_GPIO_6__GPIO_1_6 \ + IOMUX_PAD(0x0604, 0x0234, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_GPIO_6__USDHC2_LCTL \ + IOMUX_PAD(0x0604, 0x0234, 6, 0x0000, 0, MX6DL_USDHC_PAD_CTRL) +#define MX6DL_PAD_GPIO_6__MLB_MLBSIG \ + IOMUX_PAD(0x0604, 0x0234, 7, 0x08E4, 1, MX6DL_MLB150_PAD_CTRL) +#endif + +#define MX6DL_PAD_GPIO_7__ESAI1_TX4_RX1 \ + IOMUX_PAD(0x0608, 0x0238, 0, 0x0854, 1, NO_PAD_CTRL) +#define MX6DL_PAD_GPIO_7__EPIT1_EPITO \ + IOMUX_PAD(0x0608, 0x0238, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_GPIO_7__CAN1_TXCAN \ + IOMUX_PAD(0x0608, 0x0238, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_GPIO_7__UART2_TXD \ + IOMUX_PAD(0x0608, 0x0238, 4, 0x0000, 0, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_GPIO_7__UART2_RXD \ + IOMUX_PAD(0x0608, 0x0238, 4, 0x0904, 2, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_GPIO_7__GPIO_1_7 \ + IOMUX_PAD(0x0608, 0x0238, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_GPIO_7__SPDIF_PLOCK \ + IOMUX_PAD(0x0608, 0x0238, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_GPIO_7__USBOH3_OTGUSB_HOST_MODE \ + IOMUX_PAD(0x0608, 0x0238, 7, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_GPIO_7__I2C4_SCL \ + IOMUX_PAD(0x0608, 0x0238, 8 | IOMUX_CONFIG_SION, 0x0880, 1, MX6DL_I2C_PAD_CTRL) + +#define MX6DL_PAD_GPIO_8__ESAI1_TX5_RX0 \ + IOMUX_PAD(0x060C, 0x023C, 0, 0x0858, 1, NO_PAD_CTRL) +#define MX6DL_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT \ + IOMUX_PAD(0x060C, 0x023C, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_GPIO_8__EPIT2_EPITO \ + IOMUX_PAD(0x060C, 0x023C, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_GPIO_8__CAN1_RXCAN \ + IOMUX_PAD(0x060C, 0x023C, 3, 0x07C8, 0, NO_PAD_CTRL) +#define MX6DL_PAD_GPIO_8__UART2_TXD \ + IOMUX_PAD(0x060C, 0x023C, 4, 0x0000, 0, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_GPIO_8__UART2_RXD \ + IOMUX_PAD(0x060C, 0x023C, 4, 0x0904, 3, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_GPIO_8__GPIO_1_8 \ + IOMUX_PAD(0x060C, 0x023C, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_GPIO_8__SPDIF_SRCLK \ + IOMUX_PAD(0x060C, 0x023C, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_GPIO_8__USBOH3_OTGUSB_PWRCTL_WAKEUP \ + IOMUX_PAD(0x060C, 0x023C, 7, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_GPIO_8__I2C4_SDA \ + IOMUX_PAD(0x060C, 0x023C, 8 | IOMUX_CONFIG_SION, 0x0884, 1, MX6DL_I2C_PAD_CTRL) + +#define MX6DL_PAD_GPIO_9__ESAI1_FSR \ + IOMUX_PAD(0x0610, 0x0240, 0, 0x082C, 1, MX6DL_ESAI_PAD_CTRL) +#define MX6DL_PAD_GPIO_9__WDOG1_WDOG_B \ + IOMUX_PAD(0x0610, 0x0240, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_GPIO_9__KPP_COL_6 \ + IOMUX_PAD(0x0610, 0x0240, 2, 0x08C4, 1, NO_PAD_CTRL) +#define MX6DL_PAD_GPIO_9__CCM_REF_EN_B \ + IOMUX_PAD(0x0610, 0x0240, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_GPIO_9__PWM1_PWMO \ + IOMUX_PAD(0x0610, 0x0240, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_GPIO_9__GPIO_1_9 \ + IOMUX_PAD(0x0610, 0x0240, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_GPIO_9__USDHC1_WP \ + IOMUX_PAD(0x0610, 0x0240, 6, 0x092C, 1, MX6DL_USDHC_PAD_CTRL) +#define MX6DL_PAD_GPIO_9__SRC_EARLY_RST \ + IOMUX_PAD(0x0610, 0x0240, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_JTAG_MOD__SJC_MOD \ + IOMUX_PAD(0x0614, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_JTAG_TCK__SJC_TCK \ + IOMUX_PAD(0x0618, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_JTAG_TDI__SJC_TDI \ + IOMUX_PAD(0x061C, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_JTAG_TDO__SJC_TDO \ + IOMUX_PAD(0x0620, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_JTAG_TMS__SJC_TMS \ + IOMUX_PAD(0x0624, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_JTAG_TRSTB__SJC_TRSTB \ + IOMUX_PAD(0x0628, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_KEY_COL0__ECSPI1_SCLK \ + IOMUX_PAD(0x062C, 0x0244, 0, 0x07D8, 3, NO_PAD_CTRL) +#define MX6DL_PAD_KEY_COL0__ENET_RDATA_3 \ + IOMUX_PAD(0x062C, 0x0244, 1, 0x0824, 0, NO_PAD_CTRL) +#define MX6DL_PAD_KEY_COL0__AUDMUX_AUD5_TXC \ + IOMUX_PAD(0x062C, 0x0244, 2, 0x07C0, 1, NO_PAD_CTRL) +#define MX6DL_PAD_KEY_COL0__KPP_COL_0 \ + IOMUX_PAD(0x062C, 0x0244, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_KEY_COL0__UART4_TXD \ + IOMUX_PAD(0x062C, 0x0244, 4, 0x0000, 0, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_KEY_COL0__UART4_RXD \ + IOMUX_PAD(0x062C, 0x0244, 4, 0x0914, 2, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_KEY_COL0__GPIO_4_6 \ + IOMUX_PAD(0x062C, 0x0244, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_KEY_COL0__DCIC1_DCIC_OUT \ + IOMUX_PAD(0x062C, 0x0244, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_KEY_COL0__SRC_ANY_PU_RST \ + IOMUX_PAD(0x062C, 0x0244, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_KEY_COL1__ECSPI1_MISO \ + IOMUX_PAD(0x0630, 0x0248, 0, 0x07DC, 3, NO_PAD_CTRL) +#define MX6DL_PAD_KEY_COL1__ENET_MDIO \ + IOMUX_PAD(0x0630, 0x0248, 1, 0x0810, 1, MX6DL_ENET_PAD_CTRL) +#define MX6DL_PAD_KEY_COL1__AUDMUX_AUD5_TXFS \ + IOMUX_PAD(0x0630, 0x0248, 2, 0x07C4, 1, NO_PAD_CTRL) +#define MX6DL_PAD_KEY_COL1__KPP_COL_1 \ + IOMUX_PAD(0x0630, 0x0248, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_KEY_COL1__UART5_TXD \ + IOMUX_PAD(0x0630, 0x0248, 4, 0x0000, 0, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_KEY_COL1__UART5_RXD \ + IOMUX_PAD(0x0630, 0x0248, 4, 0x091C, 2, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_KEY_COL1__GPIO_4_8 \ + IOMUX_PAD(0x0630, 0x0248, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_KEY_COL1__USDHC1_VSELECT \ + IOMUX_PAD(0x0630, 0x0248, 6, 0x0000, 0, MX6DL_USDHC_PAD_CTRL) +#define MX6DL_PAD_KEY_COL1__PL301_SIM_MX6DL_PER1_HADDR_1 \ + IOMUX_PAD(0x0630, 0x0248, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_KEY_COL2__ECSPI1_SS1 \ + IOMUX_PAD(0x0634, 0x024C, 0, 0x07E8, 2, NO_PAD_CTRL) +#define MX6DL_PAD_KEY_COL2__ENET_RDATA_2 \ + IOMUX_PAD(0x0634, 0x024C, 1, 0x0820, 0, NO_PAD_CTRL) +#define MX6DL_PAD_KEY_COL2__CAN1_TXCAN \ + IOMUX_PAD(0x0634, 0x024C, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_KEY_COL2__KPP_COL_2 \ + IOMUX_PAD(0x0634, 0x024C, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_KEY_COL2__ENET_MDC \ + IOMUX_PAD(0x0634, 0x024C, 4, 0x0000, 0, MX6DL_ENET_PAD_CTRL) +#define MX6DL_PAD_KEY_COL2__GPIO_4_10 \ + IOMUX_PAD(0x0634, 0x024C, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_KEY_COL2__USBOH3_H1USB_PWRCTL_WAKEUP \ + IOMUX_PAD(0x0634, 0x024C, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_KEY_COL2__PL301_SIM_MX6DL_PER1_HADDR_3 \ + IOMUX_PAD(0x0634, 0x024C, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_KEY_COL3__ECSPI1_SS3 \ + IOMUX_PAD(0x0638, 0x0250, 0, 0x07F0, 1, NO_PAD_CTRL) +#define MX6DL_PAD_KEY_COL3__ENET_CRS \ + IOMUX_PAD(0x0638, 0x0250, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_KEY_COL3__HDMI_TX_DDC_SCL \ + IOMUX_PAD(0x0638, 0x0250, 2 | IOMUX_CONFIG_SION, 0x0860, 1, \ + MX6DL_I2C_PAD_CTRL) +#define MX6DL_PAD_KEY_COL3__KPP_COL_3 \ + IOMUX_PAD(0x0638, 0x0250, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_KEY_COL3__I2C2_SCL \ + IOMUX_PAD(0x0638, 0x0250, 4 | IOMUX_CONFIG_SION, 0x0870, 1, \ + MX6DL_I2C_PAD_CTRL) +#define MX6DL_PAD_KEY_COL3__GPIO_4_12 \ + IOMUX_PAD(0x0638, 0x0250, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_KEY_COL3__SPDIF_IN1 \ + IOMUX_PAD(0x0638, 0x0250, 6, 0x08F0, 3, NO_PAD_CTRL) +#define MX6DL_PAD_KEY_COL3__PL301_SIM_MX6DL_PER1_HADDR_5 \ + IOMUX_PAD(0x0638, 0x0250, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_KEY_COL4__CAN2_TXCAN \ + IOMUX_PAD(0x063C, 0x0254, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_KEY_COL4__IPU1_SISG_4 \ + IOMUX_PAD(0x063C, 0x0254, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_KEY_COL4__USBOH3_USBOTG_OC \ + IOMUX_PAD(0x063C, 0x0254, 2, 0x0920, 1, NO_PAD_CTRL) +#define MX6DL_PAD_KEY_COL4__KPP_COL_4 \ + IOMUX_PAD(0x063C, 0x0254, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_KEY_COL4__UART5_CTS \ + IOMUX_PAD(0x063C, 0x0254, 4, 0x0000, 0, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_KEY_COL4__UART5_RTS \ + IOMUX_PAD(0x063C, 0x0254, 4, 0x0918, 2, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_KEY_COL4__GPIO_4_14 \ + IOMUX_PAD(0x063C, 0x0254, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_KEY_COL4__MMDC_MMDC_DEBUG_49 \ + IOMUX_PAD(0x063C, 0x0254, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_KEY_COL4__PL301_SIM_MX6DL_PER1_HADDR_7 \ + IOMUX_PAD(0x063C, 0x0254, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_KEY_ROW0__ECSPI1_MOSI \ + IOMUX_PAD(0x0640, 0x0258, 0, 0x07E0, 3, NO_PAD_CTRL) +#define MX6DL_PAD_KEY_ROW0__ENET_TDATA_3 \ + IOMUX_PAD(0x0640, 0x0258, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_KEY_ROW0__AUDMUX_AUD5_TXD \ + IOMUX_PAD(0x0640, 0x0258, 2, 0x07B4, 1, NO_PAD_CTRL) +#define MX6DL_PAD_KEY_ROW0__KPP_ROW_0 \ + IOMUX_PAD(0x0640, 0x0258, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_KEY_ROW0__UART4_TXD \ + IOMUX_PAD(0x0640, 0x0258, 4, 0x0000, 0, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_KEY_ROW0__UART4_RXD \ + IOMUX_PAD(0x0640, 0x0258, 4, 0x0914, 3, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_KEY_ROW0__GPIO_4_7 \ + IOMUX_PAD(0x0640, 0x0258, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_KEY_ROW0__DCIC2_DCIC_OUT \ + IOMUX_PAD(0x0640, 0x0258, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_KEY_ROW0__PL301_SIM_MX6DL_PER1_HADDR_0 \ + IOMUX_PAD(0x0640, 0x0258, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_KEY_ROW1__ECSPI1_SS0 \ + IOMUX_PAD(0x0644, 0x025C, 0, 0x07E4, 3, NO_PAD_CTRL) +#define MX6DL_PAD_KEY_ROW1__ENET_COL \ + IOMUX_PAD(0x0644, 0x025C, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_KEY_ROW1__AUDMUX_AUD5_RXD \ + IOMUX_PAD(0x0644, 0x025C, 2, 0x07B0, 1, NO_PAD_CTRL) +#define MX6DL_PAD_KEY_ROW1__KPP_ROW_1 \ + IOMUX_PAD(0x0644, 0x025C, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_KEY_ROW1__UART5_TXD \ + IOMUX_PAD(0x0644, 0x025C, 4, 0x0000, 0, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_KEY_ROW1__UART5_RXD \ + IOMUX_PAD(0x0644, 0x025C, 4, 0x091C, 3, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_KEY_ROW1__GPIO_4_9 \ + IOMUX_PAD(0x0644, 0x025C, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_KEY_ROW1__USDHC2_VSELECT \ + IOMUX_PAD(0x0644, 0x025C, 6, 0x0000, 0, MX6DL_USDHC_PAD_CTRL) +#define MX6DL_PAD_KEY_ROW1__PL301_SIM_MX6DL_PER1_HADDR_2 \ + IOMUX_PAD(0x0644, 0x025C, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_KEY_ROW2__ECSPI1_SS2 \ + IOMUX_PAD(0x0648, 0x0260, 0, 0x07EC, 1, NO_PAD_CTRL) +#define MX6DL_PAD_KEY_ROW2__ENET_TDATA_2 \ + IOMUX_PAD(0x0648, 0x0260, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_KEY_ROW2__CAN1_RXCAN \ + IOMUX_PAD(0x0648, 0x0260, 2, 0x07C8, 1, NO_PAD_CTRL) +#define MX6DL_PAD_KEY_ROW2__KPP_ROW_2 \ + IOMUX_PAD(0x0648, 0x0260, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_KEY_ROW2__USDHC2_VSELECT \ + IOMUX_PAD(0x0648, 0x0260, 4, 0x0000, 0, MX6DL_USDHC_PAD_CTRL) +#define MX6DL_PAD_KEY_ROW2__GPIO_4_11 \ + IOMUX_PAD(0x0648, 0x0260, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE \ + IOMUX_PAD(0x0648, 0x0260, 6, 0x085C, 1, MX6DL_HDMICEC_PAD_CTRL) +#define MX6DL_PAD_KEY_ROW2__PL301_SIM_MX6DL_PER1_HADDR_4 \ + IOMUX_PAD(0x0648, 0x0260, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_KEY_ROW3__OSC32K_32K_OUT \ + IOMUX_PAD(0x064C, 0x0264, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK \ + IOMUX_PAD(0x064C, 0x0264, 1, 0x0794, 2, NO_PAD_CTRL) +#define MX6DL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA \ + IOMUX_PAD(0x064C, 0x0264, 2 | IOMUX_CONFIG_SION, 0x0864, 1, \ + MX6DL_I2C_PAD_CTRL) +#define MX6DL_PAD_KEY_ROW3__KPP_ROW_3 \ + IOMUX_PAD(0x064C, 0x0264, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_KEY_ROW3__I2C2_SDA \ + IOMUX_PAD(0x064C, 0x0264, 4 | IOMUX_CONFIG_SION, 0x0874, 1, \ + MX6DL_I2C_PAD_CTRL) +#define MX6DL_PAD_KEY_ROW3__GPIO_4_13 \ + IOMUX_PAD(0x064C, 0x0264, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_KEY_ROW3__USDHC1_VSELECT \ + IOMUX_PAD(0x064C, 0x0264, 6, 0x0000, 0, MX6DL_USDHC_PAD_CTRL) +#define MX6DL_PAD_KEY_ROW3__PL301_SIM_MX6DL_PER1_HADDR_6 \ + IOMUX_PAD(0x064C, 0x0264, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_KEY_ROW4__CAN2_RXCAN \ + IOMUX_PAD(0x0650, 0x0268, 0, 0x07CC, 0, NO_PAD_CTRL) +#define MX6DL_PAD_KEY_ROW4__IPU1_SISG_5 \ + IOMUX_PAD(0x0650, 0x0268, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_KEY_ROW4__USBOH3_USBOTG_PWR \ + IOMUX_PAD(0x0650, 0x0268, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_KEY_ROW4__KPP_ROW_4 \ + IOMUX_PAD(0x0650, 0x0268, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_KEY_ROW4__UART5_CTS \ + IOMUX_PAD(0x0650, 0x0268, 4, 0x0000, 0, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_KEY_ROW4__UART5_RTS \ + IOMUX_PAD(0x0650, 0x0268, 4, 0x0918, 3, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_KEY_ROW4__GPIO_4_15 \ + IOMUX_PAD(0x0650, 0x0268, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_KEY_ROW4__MMDC_MMDC_DEBUG_50 \ + IOMUX_PAD(0x0650, 0x0268, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_KEY_ROW4__PL301_SIM_MX6DL_PER1_HADDR_8 \ + IOMUX_PAD(0x0650, 0x0268, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_NANDF_ALE__RAWNAND_ALE \ + IOMUX_PAD(0x0654, 0x026C, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_NANDF_ALE__USDHC4_RST \ + IOMUX_PAD(0x0654, 0x026C, 1, 0x0000, 0, MX6DL_USDHC_PAD_CTRL) +#define MX6DL_PAD_NANDF_ALE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_0 \ + IOMUX_PAD(0x0654, 0x026C, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_NANDF_ALE__USBOH3_UH3_DFD_OUT_12 \ + IOMUX_PAD(0x0654, 0x026C, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_NANDF_ALE__USBOH3_UH2_DFD_OUT_12 \ + IOMUX_PAD(0x0654, 0x026C, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_NANDF_ALE__GPIO_6_8 \ + IOMUX_PAD(0x0654, 0x026C, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_NANDF_ALE__MIPI_CORE_DPHY_TEST_IN_24 \ + IOMUX_PAD(0x0654, 0x026C, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_NANDF_ALE__USDHC3_CLKI \ + IOMUX_PAD(0x0654, 0x026C, 8, 0x0934, 0, MX6DL_USDHC_PAD_CTRL) + +#define MX6DL_PAD_NANDF_CLE__RAWNAND_CLE \ + IOMUX_PAD(0x0658, 0x0270, 0, 0x0000, 0, MX6DL_GPMI_PAD_CTRL2) +#define MX6DL_PAD_NANDF_CLE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_31 \ + IOMUX_PAD(0x0658, 0x0270, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_NANDF_CLE__USBOH3_UH3_DFD_OUT_11 \ + IOMUX_PAD(0x0658, 0x0270, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_NANDF_CLE__USBOH3_UH2_DFD_OUT_11 \ + IOMUX_PAD(0x0658, 0x0270, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_NANDF_CLE__GPIO_6_7 \ + IOMUX_PAD(0x0658, 0x0270, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_NANDF_CLE__MIPI_CORE_DPHY_TEST_IN_23 \ + IOMUX_PAD(0x0658, 0x0270, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_NANDF_CLE__USDHC3_CLKO \ + IOMUX_PAD(0x0658, 0x0270, 8, 0x0000, 0, MX6DL_USDHC_PAD_CTRL) + +#define MX6DL_PAD_NANDF_CS0__RAWNAND_CE0N \ + IOMUX_PAD(0x065C, 0x0274, 0, 0x0000, 0, MX6DL_GPMI_PAD_CTRL2) +#define MX6DL_PAD_NANDF_CS0__USBOH3_UH3_DFD_OUT_15 \ + IOMUX_PAD(0x065C, 0x0274, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_NANDF_CS0__USBOH3_UH2_DFD_OUT_15 \ + IOMUX_PAD(0x065C, 0x0274, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_NANDF_CS0__GPIO_6_11 \ + IOMUX_PAD(0x065C, 0x0274, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_NANDF_CS0__USDHC1_CLKO \ + IOMUX_PAD(0x065C, 0x0274, 8, 0x0000, 0, MX6DL_USDHC_PAD_CTRL) + +#define MX6DL_PAD_NANDF_CS1__RAWNAND_CE1N \ + IOMUX_PAD(0x0660, 0x0278, 0, 0x0000, 0, MX6DL_GPMI_PAD_CTRL2) +#define MX6DL_PAD_NANDF_CS1__USDHC4_VSELECT \ + IOMUX_PAD(0x0660, 0x0278, 1, 0x0000, 0, MX6DL_USDHC_PAD_CTRL) +#define MX6DL_PAD_NANDF_CS1__USDHC3_VSELECT \ + IOMUX_PAD(0x0660, 0x0278, 2, 0x0000, 0, MX6DL_USDHC_PAD_CTRL) +#define MX6DL_PAD_NANDF_CS1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_3 \ + IOMUX_PAD(0x0660, 0x0278, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_NANDF_CS1__GPIO_6_14 \ + IOMUX_PAD(0x0660, 0x0278, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_NANDF_CS1__PL301_SIM_MX6DL_PER1_HREADYOUT \ + IOMUX_PAD(0x0660, 0x0278, 7, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_NANDF_CS1__USDHC1_CLKI \ + IOMUX_PAD(0x0660, 0x0278, 8, 0x0928, 0, MX6DL_USDHC_PAD_CTRL) + +#define MX6DL_PAD_NANDF_CS2__RAWNAND_CE2N \ + IOMUX_PAD(0x0664, 0x027C, 0, 0x0000, 0, MX6DL_GPMI_PAD_CTRL2) +#define MX6DL_PAD_NANDF_CS2__IPU1_SISG_0 \ + IOMUX_PAD(0x0664, 0x027C, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_NANDF_CS2__ESAI1_TX0 \ + IOMUX_PAD(0x0664, 0x027C, 2, 0x0844, 1, MX6DL_ESAI_PAD_CTRL) +#define MX6DL_PAD_NANDF_CS2__WEIM_WEIM_CRE \ + IOMUX_PAD(0x0664, 0x027C, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_NANDF_CS2__CCM_CLKO2 \ + IOMUX_PAD(0x0664, 0x027C, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_NANDF_CS2__GPIO_6_15 \ + IOMUX_PAD(0x0664, 0x027C, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_NANDF_CS2__USDHC2_CLKO \ + IOMUX_PAD(0x0664, 0x027C, 8, 0x0000, 0, MX6DL_USDHC_PAD_CTRL) + +#define MX6DL_PAD_NANDF_CS3__RAWNAND_CE3N \ + IOMUX_PAD(0x0668, 0x0280, 0, 0x0000, 0, MX6DL_GPMI_PAD_CTRL2) +#define MX6DL_PAD_NANDF_CS3__IPU1_SISG_1 \ + IOMUX_PAD(0x0668, 0x0280, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_NANDF_CS3__ESAI1_TX1 \ + IOMUX_PAD(0x0668, 0x0280, 2, 0x0848, 1, MX6DL_ESAI_PAD_CTRL) +#define MX6DL_PAD_NANDF_CS3__WEIM_WEIM_A_26 \ + IOMUX_PAD(0x0668, 0x0280, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_NANDF_CS3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_4 \ + IOMUX_PAD(0x0668, 0x0280, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_NANDF_CS3__GPIO_6_16 \ + IOMUX_PAD(0x0668, 0x0280, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_NANDF_CS3__TPSMP_CLK \ + IOMUX_PAD(0x0668, 0x0280, 7, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_NANDF_CS3__USDHC2_CLKI \ + IOMUX_PAD(0x0668, 0x0280, 8, 0x0930, 0, MX6DL_USDHC_PAD_CTRL) +#define MX6DL_PAD_NANDF_CS3__I2C4_SDA \ + IOMUX_PAD(0x0668, 0x0280, 9 | IOMUX_CONFIG_SION, 0x0884, 2, MX6DL_I2C_PAD_CTRL) + +#define MX6DL_PAD_NANDF_D0__RAWNAND_D0 \ + IOMUX_PAD(0x066C, 0x0284, 0, 0x0000, 0, MX6DL_GPMI_PAD_CTRL2) +#define MX6DL_PAD_NANDF_D0__USDHC1_DAT4 \ + IOMUX_PAD(0x066C, 0x0284, 1, 0x0000, 0, MX6DL_USDHC_PAD_CTRL) +#define MX6DL_PAD_NANDF_D0__GPU3D_GPU_DEBUG_OUT_0 \ + IOMUX_PAD(0x066C, 0x0284, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT_16 \ + IOMUX_PAD(0x066C, 0x0284, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT_16 \ + IOMUX_PAD(0x066C, 0x0284, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_NANDF_D0__GPIO_2_0 \ + IOMUX_PAD(0x066C, 0x0284, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0 \ + IOMUX_PAD(0x066C, 0x0284, 6, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_NANDF_D1__RAWNAND_D1 \ + IOMUX_PAD(0x0670, 0x0288, 0, 0x0000, 0, MX6DL_GPMI_PAD_CTRL2) +#define MX6DL_PAD_NANDF_D1__USDHC1_DAT5 \ + IOMUX_PAD(0x0670, 0x0288, 1, 0x0000, 0, MX6DL_USDHC_PAD_CTRL) +#define MX6DL_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT_1 \ + IOMUX_PAD(0x0670, 0x0288, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT_17 \ + IOMUX_PAD(0x0670, 0x0288, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT_17 \ + IOMUX_PAD(0x0670, 0x0288, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_NANDF_D1__GPIO_2_1 \ + IOMUX_PAD(0x0670, 0x0288, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1 \ + IOMUX_PAD(0x0670, 0x0288, 6, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_NANDF_D2__RAWNAND_D2 \ + IOMUX_PAD(0x0674, 0x028C, 0, 0x0000, 0, MX6DL_GPMI_PAD_CTRL2) +#define MX6DL_PAD_NANDF_D2__USDHC1_DAT6 \ + IOMUX_PAD(0x0674, 0x028C, 1, 0x0000, 0, MX6DL_USDHC_PAD_CTRL) +#define MX6DL_PAD_NANDF_D2__GPU3D_GPU_DEBUG_OUT_2 \ + IOMUX_PAD(0x0674, 0x028C, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT_18 \ + IOMUX_PAD(0x0674, 0x028C, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT_18 \ + IOMUX_PAD(0x0674, 0x028C, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_NANDF_D2__GPIO_2_2 \ + IOMUX_PAD(0x0674, 0x028C, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2 \ + IOMUX_PAD(0x0674, 0x028C, 6, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_NANDF_D3__RAWNAND_D3 \ + IOMUX_PAD(0x0678, 0x0290, 0, 0x0000, 0, MX6DL_GPMI_PAD_CTRL2) +#define MX6DL_PAD_NANDF_D3__USDHC1_DAT7 \ + IOMUX_PAD(0x0678, 0x0290, 1, 0x0000, 0, MX6DL_USDHC_PAD_CTRL) +#define MX6DL_PAD_NANDF_D3__GPU3D_GPU_DEBUG_OUT_3 \ + IOMUX_PAD(0x0678, 0x0290, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT_19 \ + IOMUX_PAD(0x0678, 0x0290, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT_19 \ + IOMUX_PAD(0x0678, 0x0290, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_NANDF_D3__GPIO_2_3 \ + IOMUX_PAD(0x0678, 0x0290, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3 \ + IOMUX_PAD(0x0678, 0x0290, 6, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_NANDF_D4__RAWNAND_D4 \ + IOMUX_PAD(0x067C, 0x0294, 0, 0x0000, 0, MX6DL_GPMI_PAD_CTRL2) +#define MX6DL_PAD_NANDF_D4__USDHC2_DAT4 \ + IOMUX_PAD(0x067C, 0x0294, 1, 0x0000, 0, MX6DL_USDHC_PAD_CTRL) +#define MX6DL_PAD_NANDF_D4__GPU3D_GPU_DEBUG_OUT_4 \ + IOMUX_PAD(0x067C, 0x0294, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT_20 \ + IOMUX_PAD(0x067C, 0x0294, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT_20 \ + IOMUX_PAD(0x067C, 0x0294, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_NANDF_D4__GPIO_2_4 \ + IOMUX_PAD(0x067C, 0x0294, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4 \ + IOMUX_PAD(0x067C, 0x0294, 6, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_NANDF_D5__RAWNAND_D5 \ + IOMUX_PAD(0x0680, 0x0298, 0, 0x0000, 0, MX6DL_GPMI_PAD_CTRL2) +#define MX6DL_PAD_NANDF_D5__USDHC2_DAT5 \ + IOMUX_PAD(0x0680, 0x0298, 1, 0x0000, 0, MX6DL_USDHC_PAD_CTRL) +#define MX6DL_PAD_NANDF_D5__GPU3D_GPU_DEBUG_OUT_5 \ + IOMUX_PAD(0x0680, 0x0298, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT_21 \ + IOMUX_PAD(0x0680, 0x0298, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT_21 \ + IOMUX_PAD(0x0680, 0x0298, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_NANDF_D5__GPIO_2_5 \ + IOMUX_PAD(0x0680, 0x0298, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5 \ + IOMUX_PAD(0x0680, 0x0298, 6, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_NANDF_D6__RAWNAND_D6 \ + IOMUX_PAD(0x0684, 0x029C, 0, 0x0000, 0, MX6DL_GPMI_PAD_CTRL2) +#define MX6DL_PAD_NANDF_D6__USDHC2_DAT6 \ + IOMUX_PAD(0x0684, 0x029C, 1, 0x0000, 0, MX6DL_USDHC_PAD_CTRL) +#define MX6DL_PAD_NANDF_D6__GPU3D_GPU_DEBUG_OUT_6 \ + IOMUX_PAD(0x0684, 0x029C, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT_22 \ + IOMUX_PAD(0x0684, 0x029C, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT_22 \ + IOMUX_PAD(0x0684, 0x029C, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_NANDF_D6__GPIO_2_6 \ + IOMUX_PAD(0x0684, 0x029C, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6 \ + IOMUX_PAD(0x0684, 0x029C, 6, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_NANDF_D7__RAWNAND_D7 \ + IOMUX_PAD(0x0688, 0x02A0, 0, 0x0000, 0, MX6DL_GPMI_PAD_CTRL2) +#define MX6DL_PAD_NANDF_D7__USDHC2_DAT7 \ + IOMUX_PAD(0x0688, 0x02A0, 1, 0x0000, 0, MX6DL_USDHC_PAD_CTRL) +#define MX6DL_PAD_NANDF_D7__GPU3D_GPU_DEBUG_OUT_7 \ + IOMUX_PAD(0x0688, 0x02A0, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT_23 \ + IOMUX_PAD(0x0688, 0x02A0, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT_23 \ + IOMUX_PAD(0x0688, 0x02A0, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_NANDF_D7__GPIO_2_7 \ + IOMUX_PAD(0x0688, 0x02A0, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7 \ + IOMUX_PAD(0x0688, 0x02A0, 6, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_NANDF_RB0__RAWNAND_READY0 \ + IOMUX_PAD(0x068C, 0x02A4, 0, 0x0000, 0, MX6DL_GPMI_PAD_CTRL0) +#define MX6DL_PAD_NANDF_RB0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_2 \ + IOMUX_PAD(0x068C, 0x02A4, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_NANDF_RB0__USBOH3_UH3_DFD_OUT_14 \ + IOMUX_PAD(0x068C, 0x02A4, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_NANDF_RB0__USBOH3_UH2_DFD_OUT_14 \ + IOMUX_PAD(0x068C, 0x02A4, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_NANDF_RB0__GPIO_6_10 \ + IOMUX_PAD(0x068C, 0x02A4, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_NANDF_RB0__MIPI_CORE_DPHY_TEST_OUT_33 \ + IOMUX_PAD(0x068C, 0x02A4, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_NANDF_RB0__USDHC4_CLKI \ + IOMUX_PAD(0x068C, 0x02A4, 8, 0x0938, 0, MX6DL_USDHC_PAD_CTRL) + +#define MX6DL_PAD_NANDF_WP_B__RAWNAND_RESETN \ + IOMUX_PAD(0x0690, 0x02A8, 0, 0x0000, 0, MX6DL_GPMI_PAD_CTRL2) +#define MX6DL_PAD_NANDF_WP_B__PCIE_CTRL_DIAG_STATUS_BUS_MUX_1 \ + IOMUX_PAD(0x0690, 0x02A8, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_NANDF_WP_B__USBOH3_UH3_DFD_OUT_13 \ + IOMUX_PAD(0x0690, 0x02A8, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_NANDF_WP_B__USBOH3_UH2_DFD_OUT_13 \ + IOMUX_PAD(0x0690, 0x02A8, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_NANDF_WP_B__GPIO_6_9 \ + IOMUX_PAD(0x0690, 0x02A8, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_NANDF_WP_B__MIPI_CORE_DPHY_TEST_OUT_32 \ + IOMUX_PAD(0x0690, 0x02A8, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_NANDF_WP_B__USDHC4_CLKO \ + IOMUX_PAD(0x0690, 0x02A8, 8, 0x0000, 0, MX6DL_USDHC_PAD_CTRL) +#define MX6DL_PAD_NANDF_WP_B__I2C4_SCL \ + IOMUX_PAD(0x0690, 0x02A8, 9 | IOMUX_CONFIG_SION, 0x0880, 2, MX6DL_I2C_PAD_CTRL) + +#define MX6DL_PAD_PMIC_ON_REQ__SNVS_LP_WRAPPER_SNVS_WAKEUP_ALARM \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_PMIC_STBY_REQ__CCM_PMIC_VSTBY_REQ \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_POR_B__SRC_POR_B \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_RESET_IN_B__SRC_RESET_B \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_RGMII_RD0__MIPI_HSI_CTRL_RX_READY \ + IOMUX_PAD(0x0694, 0x02AC, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_RGMII_RD0__ENET_RGMII_RD0 \ + IOMUX_PAD(0x0694, 0x02AC, 1, 0x0818, 1, MX6DL_ENET_PAD_CTRL) +#define MX6DL_PAD_RGMII_RD0__GPIO_6_25 \ + IOMUX_PAD(0x0694, 0x02AC, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_RGMII_RD0__MIPI_CORE_DPHY_TEST_IN_6 \ + IOMUX_PAD(0x0694, 0x02AC, 6, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FLAG \ + IOMUX_PAD(0x0698, 0x02B0, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_RGMII_RD1__ENET_RGMII_RD1 \ + IOMUX_PAD(0x0698, 0x02B0, 1, 0x081C, 1, MX6DL_ENET_PAD_CTRL) +#define MX6DL_PAD_RGMII_RD1__GPIO_6_27 \ + IOMUX_PAD(0x0698, 0x02B0, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_RGMII_RD1__MIPI_CORE_DPHY_TEST_IN_8 \ + IOMUX_PAD(0x0698, 0x02B0, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_RGMII_RD1__SJC_FAIL \ + IOMUX_PAD(0x0698, 0x02B0, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_RGMII_RD2__MIPI_HSI_CTRL_TX_DATA \ + IOMUX_PAD(0x069C, 0x02B4, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_RGMII_RD2__ENET_RGMII_RD2 \ + IOMUX_PAD(0x069C, 0x02B4, 1, 0x0820, 1, MX6DL_ENET_PAD_CTRL) +#define MX6DL_PAD_RGMII_RD2__GPIO_6_28 \ + IOMUX_PAD(0x069C, 0x02B4, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_RGMII_RD2__MIPI_CORE_DPHY_TEST_IN_9 \ + IOMUX_PAD(0x069C, 0x02B4, 6, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_RGMII_RD3__MIPI_HSI_CTRL_TX_WAKE \ + IOMUX_PAD(0x06A0, 0x02B8, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_RGMII_RD3__ENET_RGMII_RD3 \ + IOMUX_PAD(0x06A0, 0x02B8, 1, 0x0824, 1, MX6DL_ENET_PAD_CTRL) +#define MX6DL_PAD_RGMII_RD3__GPIO_6_29 \ + IOMUX_PAD(0x06A0, 0x02B8, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_RGMII_RD3__MIPI_CORE_DPHY_TEST_IN_10 \ + IOMUX_PAD(0x06A0, 0x02B8, 6, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_RGMII_RX_CTL__USBOH3_H3_DATA \ + IOMUX_PAD(0x06A4, 0x02BC, 0 | IOMUX_CONFIG_SION, 0x0000, 0, MX6DL_USB_HSIC_PAD_CTRL) +#define MX6DL_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL \ + IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0828, 1, MX6DL_ENET_PAD_CTRL) +#define MX6DL_PAD_RGMII_RX_CTL__GPIO_6_24 \ + IOMUX_PAD(0x06A4, 0x02BC, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_RGMII_RX_CTL__MIPI_CORE_DPHY_TEST_IN_5 \ + IOMUX_PAD(0x06A4, 0x02BC, 6, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_RGMII_RXC__USBOH3_H3_STROBE \ + IOMUX_PAD(0x06A8, 0x02C0, 0 | IOMUX_CONFIG_SION, 0x0000, 0, MX6DL_USB_HSIC_PAD_CTRL) +#define MX6DL_PAD_RGMII_RXC__USBOH3_H3_STROBE_START \ + IOMUX_PAD(0x06A8, 0x02C0, 0 | IOMUX_CONFIG_SION, 0x0000, 0, MX6DL_USB_HSIC_PAD_CTRL | PAD_CTL_PUS_47K_UP) +#define MX6DL_PAD_RGMII_RXC__ENET_RGMII_RXC \ + IOMUX_PAD(0x06A8, 0x02C0, 1, 0x0814, 1, MX6DL_ENET_PAD_CTRL) +#define MX6DL_PAD_RGMII_RXC__GPIO_6_30 \ + IOMUX_PAD(0x06A8, 0x02C0, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_RGMII_RXC__MIPI_CORE_DPHY_TEST_IN_11 \ + IOMUX_PAD(0x06A8, 0x02C0, 6, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_RGMII_TD0__MIPI_HSI_CTRL_TX_READY \ + IOMUX_PAD(0x06AC, 0x02C4, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_RGMII_TD0__ENET_RGMII_TD0 \ + IOMUX_PAD(0x06AC, 0x02C4, 1, 0x0000, 0, MX6DL_ENET_PAD_CTRL) +#define MX6DL_PAD_RGMII_TD0__GPIO_6_20 \ + IOMUX_PAD(0x06AC, 0x02C4, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_RGMII_TD0__MIPI_CORE_DPHY_TEST_IN_1 \ + IOMUX_PAD(0x06AC, 0x02C4, 6, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_RGMII_TD1__MIPI_HSI_CTRL_RX_FLAG \ + IOMUX_PAD(0x06B0, 0x02C8, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_RGMII_TD1__ENET_RGMII_TD1 \ + IOMUX_PAD(0x06B0, 0x02C8, 1, 0x0000, 0, MX6DL_ENET_PAD_CTRL) +#define MX6DL_PAD_RGMII_TD1__GPIO_6_21 \ + IOMUX_PAD(0x06B0, 0x02C8, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_RGMII_TD1__MIPI_CORE_DPHY_TEST_IN_2 \ + IOMUX_PAD(0x06B0, 0x02C8, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_RGMII_TD1__CCM_PLL3_BYP \ + IOMUX_PAD(0x06B0, 0x02C8, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_RGMII_TD2__MIPI_HSI_CTRL_RX_DATA \ + IOMUX_PAD(0x06B4, 0x02CC, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_RGMII_TD2__ENET_RGMII_TD2 \ + IOMUX_PAD(0x06B4, 0x02CC, 1, 0x0000, 0, MX6DL_ENET_PAD_CTRL) +#define MX6DL_PAD_RGMII_TD2__GPIO_6_22 \ + IOMUX_PAD(0x06B4, 0x02CC, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_RGMII_TD2__MIPI_CORE_DPHY_TEST_IN_3 \ + IOMUX_PAD(0x06B4, 0x02CC, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_RGMII_TD2__CCM_PLL2_BYP \ + IOMUX_PAD(0x06B4, 0x02CC, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_RGMII_TD3__MIPI_HSI_CTRL_RX_WAKE \ + IOMUX_PAD(0x06B8, 0x02D0, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_RGMII_TD3__ENET_RGMII_TD3 \ + IOMUX_PAD(0x06B8, 0x02D0, 1, 0x0000, 0, MX6DL_ENET_PAD_CTRL) +#define MX6DL_PAD_RGMII_TD3__GPIO_6_23 \ + IOMUX_PAD(0x06B8, 0x02D0, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_RGMII_TD3__MIPI_CORE_DPHY_TEST_IN_4 \ + IOMUX_PAD(0x06B8, 0x02D0, 6, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE \ + IOMUX_PAD(0x06BC, 0x02D4, 0 | IOMUX_CONFIG_SION, 0x0000, 0, MX6DL_USB_HSIC_PAD_CTRL) +#define MX6DL_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE_START \ + IOMUX_PAD(0x06BC, 0x02D4, 0 | IOMUX_CONFIG_SION, 0x0000, 0, MX6DL_USB_HSIC_PAD_CTRL | PAD_CTL_PUS_47K_UP) +#define MX6DL_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL \ + IOMUX_PAD(0x06BC, 0x02D4, 1, 0x0000, 0, MX6DL_ENET_PAD_CTRL) +#define MX6DL_PAD_RGMII_TX_CTL__GPIO_6_26 \ + IOMUX_PAD(0x06BC, 0x02D4, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_RGMII_TX_CTL__MIPI_CORE_DPHY_TEST_IN_7 \ + IOMUX_PAD(0x06BC, 0x02D4, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_RGMII_TX_CTL__ENET_ANATOP_ETHERNET_REF_OUT \ + IOMUX_PAD(0x06BC, 0x02D4, 7, 0x080C, 1, NO_PAD_CTRL) + +#define MX6DL_PAD_RGMII_TXC__USBOH3_H2_DATA \ + IOMUX_PAD(0x06C0, 0x02D8, 0 | IOMUX_CONFIG_SION, 0x0000, 0, MX6DL_USB_HSIC_PAD_CTRL) +#define MX6DL_PAD_RGMII_TXC__ENET_RGMII_TXC \ + IOMUX_PAD(0x06C0, 0x02D8, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK \ + IOMUX_PAD(0x06C0, 0x02D8, 2, 0x08F4, 1, NO_PAD_CTRL) +#define MX6DL_PAD_RGMII_TXC__GPIO_6_19 \ + IOMUX_PAD(0x06C0, 0x02D8, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_RGMII_TXC__MIPI_CORE_DPHY_TEST_IN_0 \ + IOMUX_PAD(0x06C0, 0x02D8, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_RGMII_TXC__ANATOP_ANATOP_24M_OUT \ + IOMUX_PAD(0x06C0, 0x02D8, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_SD1_CLK__USDHC1_CLK \ + IOMUX_PAD(0x06C4, 0x02DC, 0, 0x0928, 1, MX6DL_USDHC_PAD_CTRL) +#define MX6DL_PAD_SD1_CLK__USDHC1_CLK_50MHZ_40OHM \ + IOMUX_PAD(0x06C4, 0x02DC, 0, 0x0928, 1, MX6DL_USDHC_PAD_CTRL_50MHZ_40OHM) +#define MX6DL_PAD_SD1_CLK__OSC32K_32K_OUT \ + IOMUX_PAD(0x06C4, 0x02DC, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD1_CLK__GPT_CLKIN \ + IOMUX_PAD(0x06C4, 0x02DC, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD1_CLK__GPIO_1_20 \ + IOMUX_PAD(0x06C4, 0x02DC, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD1_CLK__PHY_DTB_0 \ + IOMUX_PAD(0x06C4, 0x02DC, 6, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_SD1_CMD__USDHC1_CMD \ + IOMUX_PAD(0x06C8, 0x02E0, 0 | IOMUX_CONFIG_SION, 0x0000, 0, MX6DL_USDHC_PAD_CTRL) +#define MX6DL_PAD_SD1_CMD__USDHC1_CMD_50MHZ_40OHM \ + IOMUX_PAD(0x06C8, 0x02E0, 0 | IOMUX_CONFIG_SION, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_50MHZ_40OHM) +#define MX6DL_PAD_SD1_CMD__PWM4_PWMO \ + IOMUX_PAD(0x06C8, 0x02E0, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD1_CMD__GPT_CMPOUT1 \ + IOMUX_PAD(0x06C8, 0x02E0, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD1_CMD__GPIO_1_18 \ + IOMUX_PAD(0x06C8, 0x02E0, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD1_CMD__ANATOP_ANATOP_TESTO_5 \ + IOMUX_PAD(0x06C8, 0x02E0, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_SD1_DAT0__USDHC1_DAT0 \ + IOMUX_PAD(0x06CC, 0x02E4, 0, 0x0000, 0, MX6DL_USDHC_PAD_CTRL) +#define MX6DL_PAD_SD1_DAT0__USDHC1_DAT0_50MHZ_40OHM \ + IOMUX_PAD(0x06CC, 0x02E4, 0, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_50MHZ_40OHM) +#define MX6DL_PAD_SD1_DAT0__CAAM_WRAPPER_RNG_OSC_OBS \ + IOMUX_PAD(0x06CC, 0x02E4, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD1_DAT0__GPT_CAPIN1 \ + IOMUX_PAD(0x06CC, 0x02E4, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD1_DAT0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_8 \ + IOMUX_PAD(0x06CC, 0x02E4, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD1_DAT0__GPIO_1_16 \ + IOMUX_PAD(0x06CC, 0x02E4, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1 \ + IOMUX_PAD(0x06CC, 0x02E4, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD1_DAT0__ANATOP_ANATOP_TESTO_7 \ + IOMUX_PAD(0x06CC, 0x02E4, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_SD1_DAT1__USDHC1_DAT1 \ + IOMUX_PAD(0x06D0, 0x02E8, 0, 0x0000, 0, MX6DL_USDHC_PAD_CTRL) +#define MX6DL_PAD_SD1_DAT1__USDHC1_DAT1_50MHZ_40OHM \ + IOMUX_PAD(0x06D0, 0x02E8, 0, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_50MHZ_40OHM) +#define MX6DL_PAD_SD1_DAT1__PWM3_PWMO \ + IOMUX_PAD(0x06D0, 0x02E8, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD1_DAT1__GPT_CAPIN2 \ + IOMUX_PAD(0x06D0, 0x02E8, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD1_DAT1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_7 \ + IOMUX_PAD(0x06D0, 0x02E8, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD1_DAT1__GPIO_1_17 \ + IOMUX_PAD(0x06D0, 0x02E8, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0 \ + IOMUX_PAD(0x06D0, 0x02E8, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD1_DAT1__ANATOP_ANATOP_TESTO_8 \ + IOMUX_PAD(0x06D0, 0x02E8, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_SD1_DAT2__USDHC1_DAT2 \ + IOMUX_PAD(0x06D4, 0x02EC, 0, 0x0000, 0, MX6DL_USDHC_PAD_CTRL) +#define MX6DL_PAD_SD1_DAT2__USDHC1_DAT2_50MHZ_40OHM \ + IOMUX_PAD(0x06D4, 0x02EC, 0, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_50MHZ_40OHM) +#define MX6DL_PAD_SD1_DAT2__GPT_CMPOUT2 \ + IOMUX_PAD(0x06D4, 0x02EC, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD1_DAT2__PWM2_PWMO \ + IOMUX_PAD(0x06D4, 0x02EC, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD1_DAT2__WDOG1_WDOG_B \ + IOMUX_PAD(0x06D4, 0x02EC, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD1_DAT2__GPIO_1_19 \ + IOMUX_PAD(0x06D4, 0x02EC, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB \ + IOMUX_PAD(0x06D4, 0x02EC, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD1_DAT2__ANATOP_ANATOP_TESTO_4 \ + IOMUX_PAD(0x06D4, 0x02EC, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_SD1_DAT3__USDHC1_DAT3 \ + IOMUX_PAD(0x06D8, 0x02F0, 0, 0x0000, 0, MX6DL_USDHC_PAD_CTRL) +#define MX6DL_PAD_SD1_DAT3__USDHC1_DAT3_50MHZ_40OHM \ + IOMUX_PAD(0x06D8, 0x02F0, 0, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_50MHZ_40OHM) +#define MX6DL_PAD_SD1_DAT3__GPT_CMPOUT3 \ + IOMUX_PAD(0x06D8, 0x02F0, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD1_DAT3__PWM1_PWMO \ + IOMUX_PAD(0x06D8, 0x02F0, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD1_DAT3__WDOG2_WDOG_B \ + IOMUX_PAD(0x06D8, 0x02F0, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD1_DAT3__GPIO_1_21 \ + IOMUX_PAD(0x06D8, 0x02F0, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB \ + IOMUX_PAD(0x06D8, 0x02F0, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD1_DAT3__ANATOP_ANATOP_TESTO_6 \ + IOMUX_PAD(0x06D8, 0x02F0, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_SD2_CLK__USDHC2_CLK \ + IOMUX_PAD(0x06DC, 0x02F4, 0, 0x0930, 1, MX6DL_USDHC_PAD_CTRL) +#define MX6DL_PAD_SD2_CLK__KPP_COL_5 \ + IOMUX_PAD(0x06DC, 0x02F4, 2, 0x08C0, 3, NO_PAD_CTRL) +#define MX6DL_PAD_SD2_CLK__AUDMUX_AUD4_RXFS \ + IOMUX_PAD(0x06DC, 0x02F4, 3, 0x07A4, 1, NO_PAD_CTRL) +#define MX6DL_PAD_SD2_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_9 \ + IOMUX_PAD(0x06DC, 0x02F4, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD2_CLK__GPIO_1_10 \ + IOMUX_PAD(0x06DC, 0x02F4, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD2_CLK__PHY_DTB_1 \ + IOMUX_PAD(0x06DC, 0x02F4, 6, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_SD2_CMD__USDHC2_CMD \ + IOMUX_PAD(0x06E0, 0x02F8, 0 | IOMUX_CONFIG_SION, 0x0000, 0, MX6DL_USDHC_PAD_CTRL) +#define MX6DL_PAD_SD2_CMD__KPP_ROW_5 \ + IOMUX_PAD(0x06E0, 0x02F8, 2, 0x08CC, 2, NO_PAD_CTRL) +#define MX6DL_PAD_SD2_CMD__AUDMUX_AUD4_RXC \ + IOMUX_PAD(0x06E0, 0x02F8, 3, 0x07A0, 1, NO_PAD_CTRL) +#define MX6DL_PAD_SD2_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_10 \ + IOMUX_PAD(0x06E0, 0x02F8, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD2_CMD__GPIO_1_11 \ + IOMUX_PAD(0x06E0, 0x02F8, 5, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_SD2_DAT0__USDHC2_DAT0 \ + IOMUX_PAD(0x06E4, 0x02FC, 0, 0x0000, 0, MX6DL_USDHC_PAD_CTRL) +#define MX6DL_PAD_SD2_DAT0__AUDMUX_AUD4_RXD \ + IOMUX_PAD(0x06E4, 0x02FC, 3, 0x0798, 1, NO_PAD_CTRL) +#define MX6DL_PAD_SD2_DAT0__KPP_ROW_7 \ + IOMUX_PAD(0x06E4, 0x02FC, 4, 0x08D4, 2, NO_PAD_CTRL) +#define MX6DL_PAD_SD2_DAT0__GPIO_1_15 \ + IOMUX_PAD(0x06E4, 0x02FC, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD2_DAT0__DCIC2_DCIC_OUT \ + IOMUX_PAD(0x06E4, 0x02FC, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD2_DAT0__ANATOP_ANATOP_TESTO_2 \ + IOMUX_PAD(0x06E4, 0x02FC, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_SD2_DAT1__USDHC2_DAT1 \ + IOMUX_PAD(0x06E8, 0x0300, 0, 0x0000, 0, MX6DL_USDHC_PAD_CTRL) +#define MX6DL_PAD_SD2_DAT1__WEIM_WEIM_CS_2 \ + IOMUX_PAD(0x06E8, 0x0300, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS \ + IOMUX_PAD(0x06E8, 0x0300, 3, 0x07AC, 1, NO_PAD_CTRL) +#define MX6DL_PAD_SD2_DAT1__KPP_COL_7 \ + IOMUX_PAD(0x06E8, 0x0300, 4, 0x08C8, 2, NO_PAD_CTRL) +#define MX6DL_PAD_SD2_DAT1__GPIO_1_14 \ + IOMUX_PAD(0x06E8, 0x0300, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD2_DAT1__CCM_WAIT \ + IOMUX_PAD(0x06E8, 0x0300, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD2_DAT1__ANATOP_ANATOP_TESTO_0 \ + IOMUX_PAD(0x06E8, 0x0300, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_SD2_DAT2__USDHC2_DAT2 \ + IOMUX_PAD(0x06EC, 0x0304, 0, 0x0000, 0, MX6DL_USDHC_PAD_CTRL) +#define MX6DL_PAD_SD2_DAT2__WEIM_WEIM_CS_3 \ + IOMUX_PAD(0x06EC, 0x0304, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD2_DAT2__AUDMUX_AUD4_TXD \ + IOMUX_PAD(0x06EC, 0x0304, 3, 0x079C, 1, NO_PAD_CTRL) +#define MX6DL_PAD_SD2_DAT2__KPP_ROW_6 \ + IOMUX_PAD(0x06EC, 0x0304, 4, 0x08D0, 2, NO_PAD_CTRL) +#define MX6DL_PAD_SD2_DAT2__GPIO_1_13 \ + IOMUX_PAD(0x06EC, 0x0304, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD2_DAT2__CCM_STOP \ + IOMUX_PAD(0x06EC, 0x0304, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD2_DAT2__ANATOP_ANATOP_TESTO_1 \ + IOMUX_PAD(0x06EC, 0x0304, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_SD2_DAT3__USDHC2_DAT3 \ + IOMUX_PAD(0x06F0, 0x0308, 0, 0x0000, 0, MX6DL_USDHC_PAD_CTRL) +#define MX6DL_PAD_SD2_DAT3__KPP_COL_6 \ + IOMUX_PAD(0x06F0, 0x0308, 2, 0x08C4, 2, NO_PAD_CTRL) +#define MX6DL_PAD_SD2_DAT3__AUDMUX_AUD4_TXC \ + IOMUX_PAD(0x06F0, 0x0308, 3, 0x07A8, 1, NO_PAD_CTRL) +#define MX6DL_PAD_SD2_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_11 \ + IOMUX_PAD(0x06F0, 0x0308, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD2_DAT3__GPIO_1_12 \ + IOMUX_PAD(0x06F0, 0x0308, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD2_DAT3__SJC_DONE \ + IOMUX_PAD(0x06F0, 0x0308, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD2_DAT3__ANATOP_ANATOP_TESTO_3 \ + IOMUX_PAD(0x06F0, 0x0308, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_SD3_CLK__USDHC3_CLK_50MHZ \ + IOMUX_PAD(0x06F4, 0x030C, 0, 0x0934, 1, MX6DL_USDHC_PAD_CTRL) +#define MX6DL_PAD_SD3_CLK__USDHC3_CLK_100MHZ \ + IOMUX_PAD(0x06F4, 0x030C, 0, 0x0934, 1, MX6DL_USDHC_PAD_CTRL_100MHZ) +#define MX6DL_PAD_SD3_CLK__USDHC3_CLK_200MHZ \ + IOMUX_PAD(0x06F4, 0x030C, 0, 0x0934, 1, MX6DL_USDHC_PAD_CTRL_200MHZ) +#define MX6DL_PAD_SD3_CLK__UART2_CTS \ + IOMUX_PAD(0x06F4, 0x030C, 1, 0x0000, 0, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_SD3_CLK__UART2_RTS \ + IOMUX_PAD(0x06F4, 0x030C, 1, 0x0900, 2, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_SD3_CLK__CAN1_RXCAN \ + IOMUX_PAD(0x06F4, 0x030C, 2, 0x07C8, 2, NO_PAD_CTRL) +#define MX6DL_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5 \ + IOMUX_PAD(0x06F4, 0x030C, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5 \ + IOMUX_PAD(0x06F4, 0x030C, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD3_CLK__GPIO_7_3 \ + IOMUX_PAD(0x06F4, 0x030C, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD3_CLK__MIPI_CORE_DPHY_TEST_IN_17 \ + IOMUX_PAD(0x06F4, 0x030C, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD3_CLK__ANATOP_ANATOP_TESTO_14 \ + IOMUX_PAD(0x06F4, 0x030C, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_SD3_CMD__USDHC3_CMD_50MHZ \ + IOMUX_PAD(0x06F8, 0x0310, 0 | IOMUX_CONFIG_SION, 0x0000, 0, MX6DL_USDHC_PAD_CTRL) +#define MX6DL_PAD_SD3_CMD__USDHC3_CMD_100MHZ \ + IOMUX_PAD(0x06F8, 0x0310, 0 | IOMUX_CONFIG_SION, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_100MHZ) +#define MX6DL_PAD_SD3_CMD__USDHC3_CMD_200MHZ \ + IOMUX_PAD(0x06F8, 0x0310, 0, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_200MHZ) +#define MX6DL_PAD_SD3_CMD__UART2_CTS \ + IOMUX_PAD(0x06F8, 0x0310, 1, 0x0000, 0, MX6DL_UART_PAD_CTRL) +#define MXSDL_PAD_SD3_CMD__UART2_RTS \ + IOMUX_PAD(0x06F8, 0x0310, 1, 0x0900, 3, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_SD3_CMD__CAN1_TXCAN \ + IOMUX_PAD(0x06F8, 0x0310, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4 \ + IOMUX_PAD(0x06F8, 0x0310, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4 \ + IOMUX_PAD(0x06F8, 0x0310, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD3_CMD__GPIO_7_2 \ + IOMUX_PAD(0x06F8, 0x0310, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD3_CMD__MIPI_CORE_DPHY_TEST_IN_16 \ + IOMUX_PAD(0x06F8, 0x0310, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD3_CMD__ANATOP_ANATOP_TESTO_13 \ + IOMUX_PAD(0x06F8, 0x0310, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_SD3_DAT0__USDHC3_DAT0_50MHZ \ + IOMUX_PAD(0x06FC, 0x0314, 0, 0x0000, 0, MX6DL_USDHC_PAD_CTRL) +#define MX6DL_PAD_SD3_DAT0__USDHC3_DAT0_100MHZ \ + IOMUX_PAD(0x06FC, 0x0314, 0, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_100MHZ) +#define MX6DL_PAD_SD3_DAT0__USDHC3_DAT0_200MHZ \ + IOMUX_PAD(0x06FC, 0x0314, 0, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_200MHZ) +#define MX6DL_PAD_SD3_DAT0__UART1_CTS \ + IOMUX_PAD(0x06FC, 0x0314, 1, 0x0000, 0, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_SD3_DAT0__UART1_RTS \ + IOMUX_PAD(0x06FC, 0x0314, 1, 0x08F8, 2, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_SD3_DAT0__CAN2_TXCAN \ + IOMUX_PAD(0x06FC, 0x0314, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6 \ + IOMUX_PAD(0x06FC, 0x0314, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6 \ + IOMUX_PAD(0x06FC, 0x0314, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD3_DAT0__GPIO_7_4 \ + IOMUX_PAD(0x06FC, 0x0314, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD3_DAT0__MIPI_CORE_DPHY_TEST_IN_18 \ + IOMUX_PAD(0x06FC, 0x0314, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD3_DAT0__ANATOP_ANATOP_TESTO_15 \ + IOMUX_PAD(0x06FC, 0x0314, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_SD3_DAT1__USDHC3_DAT1_50MHZ \ + IOMUX_PAD(0x0700, 0x0318, 0, 0x0000, 0, MX6DL_USDHC_PAD_CTRL) +#define MX6DL_PAD_SD3_DAT1__USDHC3_DAT1_100MHZ \ + IOMUX_PAD(0x0700, 0x0318, 0, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_100MHZ) +#define MX6DL_PAD_SD3_DAT1__USDHC3_DAT1_200MHZ \ + IOMUX_PAD(0x0700, 0x0318, 0, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_200MHZ) +#define MX6DL_PAD_SD3_DAT1__UART1_CTS \ + IOMUX_PAD(0x0700, 0x0318, 1, 0x0000, 0, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_SD3_DAT1__UART1_RTS \ + IOMUX_PAD(0x0700, 0x0318, 1, 0x08F8, 3, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_SD3_DAT1__CAN2_RXCAN \ + IOMUX_PAD(0x0700, 0x0318, 2, 0x07CC, 1, NO_PAD_CTRL) +#define MX6DL_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7 \ + IOMUX_PAD(0x0700, 0x0318, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7 \ + IOMUX_PAD(0x0700, 0x0318, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD3_DAT1__GPIO_7_5 \ + IOMUX_PAD(0x0700, 0x0318, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD3_DAT1__MIPI_CORE_DPHY_TEST_IN_19 \ + IOMUX_PAD(0x0700, 0x0318, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD3_DAT1__ANATOP_ANATOP_TESTI_0 \ + IOMUX_PAD(0x0700, 0x0318, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_SD3_DAT2__USDHC3_DAT2_50MHZ \ + IOMUX_PAD(0x0704, 0x031C, 0, 0x0000, 0, MX6DL_USDHC_PAD_CTRL) +#define MX6DL_PAD_SD3_DAT2__USDHC3_DAT2_100MHZ \ + IOMUX_PAD(0x0704, 0x031C, 0, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_100MHZ) +#define MX6DL_PAD_SD3_DAT2__USDHC3_DAT2_200MHZ \ + IOMUX_PAD(0x0704, 0x031C, 0, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_200MHZ) +#define MX6DL_PAD_SD3_DAT2__PCIE_CTRL_DIAG_STATUS_BUS_MUX_28 \ + IOMUX_PAD(0x0704, 0x031C, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8 \ + IOMUX_PAD(0x0704, 0x031C, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8 \ + IOMUX_PAD(0x0704, 0x031C, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD3_DAT2__GPIO_7_6 \ + IOMUX_PAD(0x0704, 0x031C, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD3_DAT2__MIPI_CORE_DPHY_TEST_IN_20 \ + IOMUX_PAD(0x0704, 0x031C, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD3_DAT2__ANATOP_ANATOP_TESTI_1 \ + IOMUX_PAD(0x0704, 0x031C, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_SD3_DAT3__USDHC3_DAT3_50MHZ \ + IOMUX_PAD(0x0708, 0x0320, 0, 0x0000, 0, MX6DL_USDHC_PAD_CTRL) +#define MX6DL_PAD_SD3_DAT3__USDHC3_DAT3_100MHZ \ + IOMUX_PAD(0x0708, 0x0320, 0, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_100MHZ) +#define MX6DL_PAD_SD3_DAT3__USDHC3_DAT3_200MHZ \ + IOMUX_PAD(0x0708, 0x0320, 0, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_200MHZ) +#define MX6DL_PAD_SD3_DAT3__UART3_CTS \ + IOMUX_PAD(0x0708, 0x0320, 1, 0x0000, 0, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_SD3_DAT3__UART3_RTS \ + IOMUX_PAD(0x0708, 0x0320, 1, 0x0908, 4, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_SD3_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_29 \ + IOMUX_PAD(0x0708, 0x0320, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9 \ + IOMUX_PAD(0x0708, 0x0320, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9 \ + IOMUX_PAD(0x0708, 0x0320, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD3_DAT3__GPIO_7_7 \ + IOMUX_PAD(0x0708, 0x0320, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD3_DAT3__MIPI_CORE_DPHY_TEST_IN_21 \ + IOMUX_PAD(0x0708, 0x0320, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD3_DAT3__ANATOP_ANATOP_TESTI_2 \ + IOMUX_PAD(0x0708, 0x0320, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_SD3_DAT4__USDHC3_DAT4_50MHZ \ + IOMUX_PAD(0x070C, 0x0324, 0, 0x0000, 0, MX6DL_USDHC_PAD_CTRL) +#define MX6DL_PAD_SD3_DAT4__USDHC3_DAT4_100MHZ \ + IOMUX_PAD(0x070C, 0x0324, 0, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_100MHZ) +#define MX6DL_PAD_SD3_DAT4__USDHC3_DAT4_200MHZ \ + IOMUX_PAD(0x070C, 0x0324, 0, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_200MHZ) +#define MX6DL_PAD_SD3_DAT4__UART2_TXD \ + IOMUX_PAD(0x070C, 0x0324, 1, 0x0000, 0, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_SD3_DAT4__UART2_RXD \ + IOMUX_PAD(0x070C, 0x0324, 1, 0x0904, 4, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_SD3_DAT4__PCIE_CTRL_DIAG_STATUS_BUS_MUX_27 \ + IOMUX_PAD(0x070C, 0x0324, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3 \ + IOMUX_PAD(0x070C, 0x0324, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3 \ + IOMUX_PAD(0x070C, 0x0324, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD3_DAT4__GPIO_7_1 \ + IOMUX_PAD(0x070C, 0x0324, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD3_DAT4__MIPI_CORE_DPHY_TEST_IN_15 \ + IOMUX_PAD(0x070C, 0x0324, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD3_DAT4__ANATOP_ANATOP_TESTO_12 \ + IOMUX_PAD(0x070C, 0x0324, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_SD3_DAT5__USDHC3_DAT5_50MHZ \ + IOMUX_PAD(0x0710, 0x0328, 0, 0x0000, 0, MX6DL_USDHC_PAD_CTRL) +#define MX6DL_PAD_SD3_DAT5__USDHC3_DAT5_100MHZ \ + IOMUX_PAD(0x0710, 0x0328, 0, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_100MHZ) +#define MX6DL_PAD_SD3_DAT5__USDHC3_DAT5_200MHZ \ + IOMUX_PAD(0x0710, 0x0328, 0, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_200MHZ) +#define MX6DL_PAD_SD3_DAT5__UART2_TXD \ + IOMUX_PAD(0x0710, 0x0328, 1, 0x0000, 0, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_SD3_DAT5__UART2_RXD \ + IOMUX_PAD(0x0710, 0x0328, 1, 0x0904, 5, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_SD3_DAT5__PCIE_CTRL_DIAG_STATUS_BUS_MUX_26 \ + IOMUX_PAD(0x0710, 0x0328, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2 \ + IOMUX_PAD(0x0710, 0x0328, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2 \ + IOMUX_PAD(0x0710, 0x0328, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD3_DAT5__GPIO_7_0 \ + IOMUX_PAD(0x0710, 0x0328, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD3_DAT5__MIPI_CORE_DPHY_TEST_IN_14 \ + IOMUX_PAD(0x0710, 0x0328, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD3_DAT5__ANATOP_ANATOP_TESTO_11 \ + IOMUX_PAD(0x0710, 0x0328, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_SD3_DAT6__USDHC3_DAT6_50MHZ \ + IOMUX_PAD(0x0714, 0x032C, 0, 0x0000, 0, MX6DL_USDHC_PAD_CTRL) +#define MX6DL_PAD_SD3_DAT6__USDHC3_DAT6_100MHZ \ + IOMUX_PAD(0x0714, 0x032C, 0, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_100MHZ) +#define MX6DL_PAD_SD3_DAT6__USDHC3_DAT6_200MHZ \ + IOMUX_PAD(0x0714, 0x032C, 0, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_200MHZ) +#define MX6DL_PAD_SD3_DAT6__UART1_TXD \ + IOMUX_PAD(0x0714, 0x032C, 1, 0x0000, 0, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_SD3_DAT6__UART1_RXD \ + IOMUX_PAD(0x0714, 0x032C, 1, 0x08FC, 2, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_SD3_DAT6__PCIE_CTRL_DIAG_STATUS_BUS_MUX_25 \ + IOMUX_PAD(0x0714, 0x032C, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1 \ + IOMUX_PAD(0x0714, 0x032C, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1 \ + IOMUX_PAD(0x0714, 0x032C, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD3_DAT6__GPIO_6_18 \ + IOMUX_PAD(0x0714, 0x032C, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD3_DAT6__MIPI_CORE_DPHY_TEST_IN_13 \ + IOMUX_PAD(0x0714, 0x032C, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD3_DAT6__ANATOP_ANATOP_TESTO_10 \ + IOMUX_PAD(0x0714, 0x032C, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_SD3_DAT7__USDHC3_DAT7_50MHZ \ + IOMUX_PAD(0x0718, 0x0330, 0, 0x0000, 0, MX6DL_USDHC_PAD_CTRL) +#define MX6DL_PAD_SD3_DAT7__USDHC3_DAT7_100MHZ \ + IOMUX_PAD(0x0718, 0x0330, 0, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_100MHZ) +#define MX6DL_PAD_SD3_DAT7__USDHC3_DAT7_200MHZ \ + IOMUX_PAD(0x0718, 0x0330, 0, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_200MHZ) +#define MX6DL_PAD_SD3_DAT7__UART1_TXD \ + IOMUX_PAD(0x0718, 0x0330, 1, 0x0000, 0, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_SD3_DAT7__UART1_RXD \ + IOMUX_PAD(0x0718, 0x0330, 1, 0x08FC, 3, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_SD3_DAT7__PCIE_CTRL_DIAG_STATUS_BUS_MUX_24 \ + IOMUX_PAD(0x0718, 0x0330, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0 \ + IOMUX_PAD(0x0718, 0x0330, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0 \ + IOMUX_PAD(0x0718, 0x0330, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD3_DAT7__GPIO_6_17 \ + IOMUX_PAD(0x0718, 0x0330, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD3_DAT7__MIPI_CORE_DPHY_TEST_IN_12 \ + IOMUX_PAD(0x0718, 0x0330, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD3_DAT7__ANATOP_USBPHY2_TSTO_PLL_CLK20DIV \ + IOMUX_PAD(0x0718, 0x0330, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_SD3_RST__USDHC3_RST \ + IOMUX_PAD(0x071C, 0x0334, 0, 0x0000, 0, MX6DL_USDHC_PAD_CTRL) +#define MX6DL_PAD_SD3_RST__UART3_CTS \ + IOMUX_PAD(0x071C, 0x0334, 1, 0x0000, 0, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_SD3_RST__UART3_RTS \ + IOMUX_PAD(0x071C, 0x0334, 1, 0x0908, 5, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_SD3_RST__PCIE_CTRL_DIAG_STATUS_BUS_MUX_30 \ + IOMUX_PAD(0x071C, 0x0334, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10 \ + IOMUX_PAD(0x071C, 0x0334, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10 \ + IOMUX_PAD(0x071C, 0x0334, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD3_RST__GPIO_7_8 \ + IOMUX_PAD(0x071C, 0x0334, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD3_RST__MIPI_CORE_DPHY_TEST_IN_22 \ + IOMUX_PAD(0x071C, 0x0334, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3 \ + IOMUX_PAD(0x071C, 0x0334, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_SD4_CLK__USDHC4_CLK_50MHZ \ + IOMUX_PAD(0x0720, 0x0338, 0, 0x0938, 1, MX6DL_USDHC_PAD_CTRL) +#define MX6DL_PAD_SD4_CLK__USDHC4_CLK_100MHZ \ + IOMUX_PAD(0x0720, 0x0338, 0, 0x0938, 1, MX6DL_USDHC_PAD_CTRL_100MHZ) +#define MX6DL_PAD_SD4_CLK__USDHC4_CLK_200MHZ \ + IOMUX_PAD(0x0720, 0x0338, 0, 0x0938, 1, MX6DL_USDHC_PAD_CTRL_200MHZ) +#define MX6DL_PAD_SD4_CLK__RAWNAND_WRN \ + IOMUX_PAD(0x0720, 0x0338, 1, 0x0000, 0, MX6DL_GPMI_PAD_CTRL2) +#define MX6DL_PAD_SD4_CLK__UART3_TXD \ + IOMUX_PAD(0x0720, 0x0338, 2, 0x0000, 0, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_SD4_CLK__UART3_RXD \ + IOMUX_PAD(0x0720, 0x0338, 2, 0x090C, 2, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_SD4_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_6 \ + IOMUX_PAD(0x0720, 0x0338, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD4_CLK__GPIO_7_10 \ + IOMUX_PAD(0x0720, 0x0338, 5, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_SD4_CMD__USDHC4_CMD_50MHZ \ + IOMUX_PAD(0x0724, 0x033C, 0 | IOMUX_CONFIG_SION, 0x0000, 0, MX6DL_USDHC_PAD_CTRL) +#define MX6DL_PAD_SD4_CMD__USDHC4_CMD_100MHZ \ + IOMUX_PAD(0x0724, 0x033C, 0 | IOMUX_CONFIG_SION, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_100MHZ) +#define MX6DL_PAD_SD4_CMD__USDHC4_CMD_200MHZ \ + IOMUX_PAD(0x0724, 0x033C, 0 | IOMUX_CONFIG_SION, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_200MHZ) +#define MX6DL_PAD_SD4_CMD__RAWNAND_RDN \ + IOMUX_PAD(0x0724, 0x033C, 1, 0x0000, 0, MX6DL_GPMI_PAD_CTRL2) +#define MX6DL_PAD_SD4_CMD__UART3_TXD \ + IOMUX_PAD(0x0724, 0x033C, 2, 0x0000, 0, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_SD4_CMD__UART3_RXD \ + IOMUX_PAD(0x0724, 0x033C, 2, 0x090C, 3, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_SD4_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_5 \ + IOMUX_PAD(0x0724, 0x033C, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD4_CMD__GPIO_7_9 \ + IOMUX_PAD(0x0724, 0x033C, 5, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_SD4_DAT0__RAWNAND_D8 \ + IOMUX_PAD(0x0728, 0x0340, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD4_DAT0__USDHC4_DAT0_50MHZ \ + IOMUX_PAD(0x0728, 0x0340, 1, 0x0000, 0, MX6DL_USDHC_PAD_CTRL) +#define MX6DL_PAD_SD4_DAT0__USDHC4_DAT0_100MHZ \ + IOMUX_PAD(0x0728, 0x0340, 1, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_100MHZ) +#define MX6DL_PAD_SD4_DAT0__USDHC4_DAT0_200MHZ \ + IOMUX_PAD(0x0728, 0x0340, 1, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_200MHZ) +#define MX6DL_PAD_SD4_DAT0__RAWNAND_DQS \ + IOMUX_PAD(0x0728, 0x0340, 2, 0x0000, 0, MX6DL_GPMI_PAD_CTRL1) +#define MX6DL_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT_24 \ + IOMUX_PAD(0x0728, 0x0340, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT_24 \ + IOMUX_PAD(0x0728, 0x0340, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD4_DAT0__GPIO_2_8 \ + IOMUX_PAD(0x0728, 0x0340, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8 \ + IOMUX_PAD(0x0728, 0x0340, 6, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_SD4_DAT1__RAWNAND_D9 \ + IOMUX_PAD(0x072C, 0x0344, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD4_DAT1__USDHC4_DAT1_50MHZ \ + IOMUX_PAD(0x072C, 0x0344, 1, 0x0000, 0, MX6DL_USDHC_PAD_CTRL) +#define MX6DL_PAD_SD4_DAT1__USDHC4_DAT1_100MHZ \ + IOMUX_PAD(0x072C, 0x0344, 1, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_100MHZ) +#define MX6DL_PAD_SD4_DAT1__USDHC4_DAT1_200MHZ \ + IOMUX_PAD(0x072C, 0x0344, 1, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_200MHZ) +#define MX6DL_PAD_SD4_DAT1__PWM3_PWMO \ + IOMUX_PAD(0x072C, 0x0344, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT_25 \ + IOMUX_PAD(0x072C, 0x0344, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT_25 \ + IOMUX_PAD(0x072C, 0x0344, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD4_DAT1__GPIO_2_9 \ + IOMUX_PAD(0x072C, 0x0344, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9 \ + IOMUX_PAD(0x072C, 0x0344, 6, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_SD4_DAT2__RAWNAND_D10 \ + IOMUX_PAD(0x0730, 0x0348, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD4_DAT2__USDHC4_DAT2_50MHZ \ + IOMUX_PAD(0x0730, 0x0348, 1, 0x0000, 0, MX6DL_USDHC_PAD_CTRL) +#define MX6DL_PAD_SD4_DAT2__USDHC4_DAT2_100MHZ \ + IOMUX_PAD(0x0730, 0x0348, 1, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_100MHZ) +#define MX6DL_PAD_SD4_DAT2__USDHC4_DAT2_200MHZ \ + IOMUX_PAD(0x0730, 0x0348, 1, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_200MHZ) +#define MX6DL_PAD_SD4_DAT2__PWM4_PWMO \ + IOMUX_PAD(0x0730, 0x0348, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT_26 \ + IOMUX_PAD(0x0730, 0x0348, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT_26 \ + IOMUX_PAD(0x0730, 0x0348, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD4_DAT2__GPIO_2_10 \ + IOMUX_PAD(0x0730, 0x0348, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10 \ + IOMUX_PAD(0x0730, 0x0348, 6, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_SD4_DAT3__RAWNAND_D11 \ + IOMUX_PAD(0x0734, 0x034C, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD4_DAT3__USDHC4_DAT3_50MHZ \ + IOMUX_PAD(0x0734, 0x034C, 1, 0x0000, 0, MX6DL_USDHC_PAD_CTRL) +#define MX6DL_PAD_SD4_DAT3__USDHC4_DAT3_100MHZ \ + IOMUX_PAD(0x0734, 0x034C, 1, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_100MHZ) +#define MX6DL_PAD_SD4_DAT3__USDHC4_DAT3_200MHZ \ + IOMUX_PAD(0x0734, 0x034C, 1, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_200MHZ) +#define MX6DL_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT_27 \ + IOMUX_PAD(0x0734, 0x034C, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT_27 \ + IOMUX_PAD(0x0734, 0x034C, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD4_DAT3__GPIO_2_11 \ + IOMUX_PAD(0x0734, 0x034C, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11 \ + IOMUX_PAD(0x0734, 0x034C, 6, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_SD4_DAT4__RAWNAND_D12 \ + IOMUX_PAD(0x0738, 0x0350, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD4_DAT4__USDHC4_DAT4_50MHZ \ + IOMUX_PAD(0x0738, 0x0350, 1, 0x0000, 0, MX6DL_USDHC_PAD_CTRL) +#define MX6DL_PAD_SD4_DAT4__USDHC4_DAT4_100MHZ \ + IOMUX_PAD(0x0738, 0x0350, 1, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_100MHZ) +#define MX6DL_PAD_SD4_DAT4__USDHC4_DAT4_200MHZ \ + IOMUX_PAD(0x0738, 0x0350, 1, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_200MHZ) +#define MX6DL_PAD_SD4_DAT4__UART2_TXD \ + IOMUX_PAD(0x0738, 0x0350, 2, 0x0000, 0, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_SD4_DAT4__UART2_RXD \ + IOMUX_PAD(0x0738, 0x0350, 2, 0x0904, 6, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT_28 \ + IOMUX_PAD(0x0738, 0x0350, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT_28 \ + IOMUX_PAD(0x0738, 0x0350, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD4_DAT4__GPIO_2_12 \ + IOMUX_PAD(0x0738, 0x0350, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12 \ + IOMUX_PAD(0x0738, 0x0350, 6, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_SD4_DAT5__RAWNAND_D13 \ + IOMUX_PAD(0x073C, 0x0354, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD4_DAT5__USDHC4_DAT5_50MHZ \ + IOMUX_PAD(0x073C, 0x0354, 1, 0x0000, 0, MX6DL_USDHC_PAD_CTRL) +#define MX6DL_PAD_SD4_DAT5__USDHC4_DAT5_100MHZ \ + IOMUX_PAD(0x073C, 0x0354, 1, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_100MHZ) +#define MX6DL_PAD_SD4_DAT5__USDHC4_DAT5_200MHZ \ + IOMUX_PAD(0x073C, 0x0354, 1, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_200MHZ) +#define MX6DL_PAD_SD4_DAT5__UART2_CTS \ + IOMUX_PAD(0x073C, 0x0354, 2, 0x0000, 0, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_SD4_DAT5__UART2_RTS \ + IOMUX_PAD(0x073C, 0x0354, 2, 0x0900, 4, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT_29 \ + IOMUX_PAD(0x073C, 0x0354, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT_29 \ + IOMUX_PAD(0x073C, 0x0354, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD4_DAT5__GPIO_2_13 \ + IOMUX_PAD(0x073C, 0x0354, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13 \ + IOMUX_PAD(0x073C, 0x0354, 6, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_SD4_DAT6__RAWNAND_D14 \ + IOMUX_PAD(0x0740, 0x0358, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD4_DAT6__USDHC4_DAT6_50MHZ \ + IOMUX_PAD(0x0740, 0x0358, 1, 0x0000, 0, MX6DL_USDHC_PAD_CTRL) +#define MX6DL_PAD_SD4_DAT6__USDHC4_DAT6_100MHZ \ + IOMUX_PAD(0x0740, 0x0358, 1, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_100MHZ) +#define MX6DL_PAD_SD4_DAT6__USDHC4_DAT6_200MHZ \ + IOMUX_PAD(0x0740, 0x0358, 1, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_200MHZ) +#define MX6DL_PAD_SD4_DAT6__UART2_CTS \ + IOMUX_PAD(0x0740, 0x0358, 2, 0x0000, 0, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_SD4_DAT6__UART2_RTS \ + IOMUX_PAD(0x0740, 0x0358, 2, 0x0900, 5, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT_30 \ + IOMUX_PAD(0x0740, 0x0358, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT_30 \ + IOMUX_PAD(0x0740, 0x0358, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD4_DAT6__GPIO_2_14 \ + IOMUX_PAD(0x0740, 0x0358, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14 \ + IOMUX_PAD(0x0740, 0x0358, 6, 0x0000, 0, NO_PAD_CTRL) + +#define MX6DL_PAD_SD4_DAT7__RAWNAND_D15 \ + IOMUX_PAD(0x0744, 0x035C, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD4_DAT7__USDHC4_DAT7_50MHZ \ + IOMUX_PAD(0x0744, 0x035C, 1, 0x0000, 0, MX6DL_USDHC_PAD_CTRL) +#define MX6DL_PAD_SD4_DAT7__USDHC4_DAT7_100MHZ \ + IOMUX_PAD(0x0744, 0x035C, 1, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_100MHZ) +#define MX6DL_PAD_SD4_DAT7__USDHC4_DAT7_200MHZ \ + IOMUX_PAD(0x0744, 0x035C, 1, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_200MHZ) +#define MX6DL_PAD_SD4_DAT7__UART2_TXD \ + IOMUX_PAD(0x0744, 0x035C, 2, 0x0000, 0, MX6DL_UART_PAD_CTRL) +#define MX6DL_PAD_SD4_DAT7__UART2_RXD \ + IOMUX_PAD(0x0744, 0x035C, 2, 0x0904, 7, NO_PAD_CTRL) +#define MX6DL_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT_31 \ + IOMUX_PAD(0x0744, 0x035C, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT_31 \ + IOMUX_PAD(0x0744, 0x035C, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD4_DAT7__GPIO_2_15 \ + IOMUX_PAD(0x0744, 0x035C, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6DL_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15 \ + IOMUX_PAD(0x0744, 0x035C, 6, 0x0000, 0, NO_PAD_CTRL) + +#endif /*__MACH_IOMUX_MX6DL_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx6q.h b/arch/arm/plat-mxc/include/mach/iomux-mx6q.h new file mode 100644 index 00000000..4e85d81c --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/iomux-mx6q.h @@ -0,0 +1,7403 @@ +/* + * Copyright (C) 2013 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Auto Generate file, please don't edit it + * + */ + +#ifndef __MACH_IOMUX_MX6Q_H__ +#define __MACH_IOMUX_MX6Q_H__ + +#include <mach/iomux-v3.h> + +#define MX6Q_CCM_CLK0_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define MX6Q_HIGH_DRV (PAD_CTL_DSE_120ohm) + +#define MX6Q_MLB150_PAD_CTRL (PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) \ + +#define MX6Q_UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define MX6Q_USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define MX6Q_USDHC_PAD_CTRL_50MHZ_40OHM (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define MX6Q_USDHC_PAD_CTRL_100MHZ (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define MX6Q_USDHC_PAD_CTRL_200MHZ (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define MX6Q_ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define MX6Q_ENET_REF_CLK_PAD_CTRL (PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define MX6Q_GPIO_16_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define MX6Q_DISP_PAD_CLT MX6Q_HIGH_DRV + +#define MX6Q_I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_ODE | \ + PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_DSE_40ohm | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_HYS | PAD_CTL_SPEED_MED) + +#define MX6Q_ESAI_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) + +#define MX6Q_GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) +#define MX6Q_GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | PAD_CTL_SRE_FAST) +#define MX6Q_GPMI_PAD_CTRL2 (MX6Q_GPMI_PAD_CTRL0 | MX6Q_GPMI_PAD_CTRL1) + +#define MX6Q_SPDIF_OUT_PAD_CTRL (PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST) +#define MX6Q_USB_HSIC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_DSE_40ohm) + +#define MX6Q_ECSPI_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define MX6Q_HDMICEC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \ + PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_ODE | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_SLOW) + +#define MX6Q_ADU_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_DSE_40ohm | PAD_CTL_PUS_100K_DOWN | \ + PAD_CTL_HYS | PAD_CTL_SPEED_MED) + +#define MX6Q_WEIM_NOR_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_40ohm | \ + PAD_CTL_SPEED_MED | PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP) + +#define ENET_IRQ_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_40ohm | \ + PAD_CTL_SPEED_MED) + +#define _MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 \ + IOMUX_PAD(0x0360, 0x004C, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_SD2_DAT1__ECSPI5_SS0 \ + IOMUX_PAD(0x0360, 0x004C, 1, 0x0834, 0, 0) +#define _MX6Q_PAD_SD2_DAT1__WEIM_WEIM_CS_2 \ + IOMUX_PAD(0x0360, 0x004C, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS \ + IOMUX_PAD(0x0360, 0x004C, 3, 0x07C8, 0, 0) +#define _MX6Q_PAD_SD2_DAT1__KPP_COL_7 \ + IOMUX_PAD(0x0360, 0x004C, 4, 0x08F0, 0, 0) +#define _MX6Q_PAD_SD2_DAT1__GPIO_1_14 \ + IOMUX_PAD(0x0360, 0x004C, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_SD2_DAT1__CCM_WAIT \ + IOMUX_PAD(0x0360, 0x004C, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_SD2_DAT1__ANATOP_ANATOP_TESTO_0 \ + IOMUX_PAD(0x0360, 0x004C, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 \ + IOMUX_PAD(0x0364, 0x0050, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_SD2_DAT2__ECSPI5_SS1 \ + IOMUX_PAD(0x0364, 0x0050, 1, 0x0838, 0, 0) +#define _MX6Q_PAD_SD2_DAT2__WEIM_WEIM_CS_3 \ + IOMUX_PAD(0x0364, 0x0050, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD \ + IOMUX_PAD(0x0364, 0x0050, 3, 0x07B8, 0, 0) +#define _MX6Q_PAD_SD2_DAT2__KPP_ROW_6 \ + IOMUX_PAD(0x0364, 0x0050, 4, 0x08F8, 0, 0) +#define _MX6Q_PAD_SD2_DAT2__GPIO_1_13 \ + IOMUX_PAD(0x0364, 0x0050, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_SD2_DAT2__CCM_STOP \ + IOMUX_PAD(0x0364, 0x0050, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_SD2_DAT2__ANATOP_ANATOP_TESTO_1 \ + IOMUX_PAD(0x0364, 0x0050, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 \ + IOMUX_PAD(0x0368, 0x0054, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_SD2_DAT0__ECSPI5_MISO \ + IOMUX_PAD(0x0368, 0x0054, 1, 0x082C, 0, 0) +#define _MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD \ + IOMUX_PAD(0x0368, 0x0054, 3, 0x07B4, 0, 0) +#define _MX6Q_PAD_SD2_DAT0__KPP_ROW_7 \ + IOMUX_PAD(0x0368, 0x0054, 4, 0x08FC, 0, 0) +#define _MX6Q_PAD_SD2_DAT0__GPIO_1_15 \ + IOMUX_PAD(0x0368, 0x0054, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_SD2_DAT0__DCIC2_DCIC_OUT \ + IOMUX_PAD(0x0368, 0x0054, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_SD2_DAT0__ANATOP_ANATOP_TESTO_2 \ + IOMUX_PAD(0x0368, 0x0054, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_RGMII_TXC__USBOH3_H2_DATA \ + IOMUX_PAD(0x036C, 0x0058, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0) +#define _MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC \ + IOMUX_PAD(0x036C, 0x0058, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK \ + IOMUX_PAD(0x036C, 0x0058, 2, 0x0918, 0, 0) +#define _MX6Q_PAD_RGMII_TXC__GPIO_6_19 \ + IOMUX_PAD(0x036C, 0x0058, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_RGMII_TXC__MIPI_CORE_DPHY_TEST_IN_0 \ + IOMUX_PAD(0x036C, 0x0058, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_RGMII_TXC__ANATOP_ANATOP_24M_OUT \ + IOMUX_PAD(0x036C, 0x0058, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_RGMII_TD0__MIPI_HSI_CTRL_TX_READY \ + IOMUX_PAD(0x0370, 0x005C, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 \ + IOMUX_PAD(0x0370, 0x005C, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_RGMII_TD0__GPIO_6_20 \ + IOMUX_PAD(0x0370, 0x005C, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_RGMII_TD0__MIPI_CORE_DPHY_TEST_IN_1 \ + IOMUX_PAD(0x0370, 0x005C, 6, 0x0000, 0, 0) + +#define _MX6Q_PAD_RGMII_TD1__MIPI_HSI_CTRL_RX_FLAG \ + IOMUX_PAD(0x0374, 0x0060, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 \ + IOMUX_PAD(0x0374, 0x0060, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_RGMII_TD1__GPIO_6_21 \ + IOMUX_PAD(0x0374, 0x0060, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_RGMII_TD1__MIPI_CORE_DPHY_TEST_IN_2 \ + IOMUX_PAD(0x0374, 0x0060, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_RGMII_TD1__CCM_PLL3_BYP \ + IOMUX_PAD(0x0374, 0x0060, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_RGMII_TD2__MIPI_HSI_CTRL_RX_DATA \ + IOMUX_PAD(0x0378, 0x0064, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 \ + IOMUX_PAD(0x0378, 0x0064, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_RGMII_TD2__GPIO_6_22 \ + IOMUX_PAD(0x0378, 0x0064, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_RGMII_TD2__MIPI_CORE_DPHY_TEST_IN_3 \ + IOMUX_PAD(0x0378, 0x0064, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_RGMII_TD2__CCM_PLL2_BYP \ + IOMUX_PAD(0x0378, 0x0064, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_RGMII_TD3__MIPI_HSI_CTRL_RX_WAKE \ + IOMUX_PAD(0x037C, 0x0068, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 \ + IOMUX_PAD(0x037C, 0x0068, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_RGMII_TD3__GPIO_6_23 \ + IOMUX_PAD(0x037C, 0x0068, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_RGMII_TD3__MIPI_CORE_DPHY_TEST_IN_4 \ + IOMUX_PAD(0x037C, 0x0068, 6, 0x0000, 0, 0) + +#define _MX6Q_PAD_RGMII_RX_CTL__USBOH3_H3_DATA \ + IOMUX_PAD(0x0380, 0x006C, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0) +#define _MX6Q_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL \ + IOMUX_PAD(0x0380, 0x006C, 1, 0x0858, 0, 0) +#define _MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24 \ + IOMUX_PAD(0x0380, 0x006C, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_RGMII_RX_CTL__MIPI_CORE_DPHY_TEST_IN_5 \ + IOMUX_PAD(0x0380, 0x006C, 6, 0x0000, 0, 0) + +#define _MX6Q_PAD_RGMII_RD0__MIPI_HSI_CTRL_RX_READY \ + IOMUX_PAD(0x0384, 0x0070, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 \ + IOMUX_PAD(0x0384, 0x0070, 1, 0x0848, 0, 0) +#define _MX6Q_PAD_RGMII_RD0__GPIO_6_25 \ + IOMUX_PAD(0x0384, 0x0070, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_RGMII_RD0__MIPI_CORE_DPHY_TEST_IN_6 \ + IOMUX_PAD(0x0384, 0x0070, 6, 0x0000, 0, 0) + +#define _MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE \ + IOMUX_PAD(0x0388, 0x0074, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0) +#define _MX6Q_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL \ + IOMUX_PAD(0x0388, 0x0074, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_RGMII_TX_CTL__GPIO_6_26 \ + IOMUX_PAD(0x0388, 0x0074, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_RGMII_TX_CTL__MIPI_CORE_DPHY_TEST_IN_7 \ + IOMUX_PAD(0x0388, 0x0074, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_RGMII_TX_CTL__ENET_ANATOP_ETHERNET_REF_OUT \ + IOMUX_PAD(0x0388, 0x0074, 7, 0x083C, 0, 0) + +#define _MX6Q_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FLAG \ + IOMUX_PAD(0x038C, 0x0078, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 \ + IOMUX_PAD(0x038C, 0x0078, 1, 0x084C, 0, 0) +#define _MX6Q_PAD_RGMII_RD1__GPIO_6_27 \ + IOMUX_PAD(0x038C, 0x0078, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_RGMII_RD1__MIPI_CORE_DPHY_TEST_IN_8 \ + IOMUX_PAD(0x038C, 0x0078, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_RGMII_RD1__SJC_FAIL \ + IOMUX_PAD(0x038C, 0x0078, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_RGMII_RD2__MIPI_HSI_CTRL_TX_DATA \ + IOMUX_PAD(0x0390, 0x007C, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 \ + IOMUX_PAD(0x0390, 0x007C, 1, 0x0850, 0, 0) +#define _MX6Q_PAD_RGMII_RD2__GPIO_6_28 \ + IOMUX_PAD(0x0390, 0x007C, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_RGMII_RD2__MIPI_CORE_DPHY_TEST_IN_9 \ + IOMUX_PAD(0x0390, 0x007C, 6, 0x0000, 0, 0) + +#define _MX6Q_PAD_RGMII_RD3__MIPI_HSI_CTRL_TX_WAKE \ + IOMUX_PAD(0x0394, 0x0080, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 \ + IOMUX_PAD(0x0394, 0x0080, 1, 0x0854, 0, 0) +#define _MX6Q_PAD_RGMII_RD3__GPIO_6_29 \ + IOMUX_PAD(0x0394, 0x0080, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_RGMII_RD3__MIPI_CORE_DPHY_TEST_IN_10 \ + IOMUX_PAD(0x0394, 0x0080, 6, 0x0000, 0, 0) + +#define _MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE \ + IOMUX_PAD(0x0398, 0x0084, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0) +#define _MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC \ + IOMUX_PAD(0x0398, 0x0084, 1, 0x0844, 0, 0) +#define _MX6Q_PAD_RGMII_RXC__GPIO_6_30 \ + IOMUX_PAD(0x0398, 0x0084, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_RGMII_RXC__MIPI_CORE_DPHY_TEST_IN_11 \ + IOMUX_PAD(0x0398, 0x0084, 6, 0x0000, 0, 0) + +#define _MX6Q_PAD_EIM_A25__WEIM_WEIM_A_25 \ + IOMUX_PAD(0x039C, 0x0088, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_A25__ECSPI4_SS1 \ + IOMUX_PAD(0x039C, 0x0088, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_A25__ECSPI2_RDY \ + IOMUX_PAD(0x039C, 0x0088, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_A25__IPU1_DI1_PIN12 \ + IOMUX_PAD(0x039C, 0x0088, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_A25__IPU1_DI0_D1_CS \ + IOMUX_PAD(0x039C, 0x0088, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_A25__GPIO_5_2 \ + IOMUX_PAD(0x039C, 0x0088, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE \ + IOMUX_PAD(0x039C, 0x0088, 6, 0x088C, 0, 0) +#define _MX6Q_PAD_EIM_A25__PL301_MX6QPER1_HBURST_0 \ + IOMUX_PAD(0x039C, 0x0088, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_EIM_EB2__WEIM_WEIM_EB_2 \ + IOMUX_PAD(0x03A0, 0x008C, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_EB2__ECSPI1_SS0 \ + IOMUX_PAD(0x03A0, 0x008C, 1, 0x0800, 0, 0) +#define _MX6Q_PAD_EIM_EB2__CCM_DI1_EXT_CLK \ + IOMUX_PAD(0x03A0, 0x008C, 2, 0x07EC, 0, 0) +#define _MX6Q_PAD_EIM_EB2__IPU2_CSI1_D_19 \ + IOMUX_PAD(0x03A0, 0x008C, 3, 0x08D4, 0, 0) +#define _MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL \ + IOMUX_PAD(0x03A0, 0x008C, 4, 0x0890, 0, 0) +#define _MX6Q_PAD_EIM_EB2__GPIO_2_30 \ + IOMUX_PAD(0x03A0, 0x008C, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_EB2__I2C2_SCL \ + IOMUX_PAD(0x03A0, 0x008C, 6 | IOMUX_CONFIG_SION, 0x08A0, 0, 0) +#define _MX6Q_PAD_EIM_EB2__SRC_BT_CFG_30 \ + IOMUX_PAD(0x03A0, 0x008C, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16 \ + IOMUX_PAD(0x03A4, 0x0090, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_D16__ECSPI1_SCLK \ + IOMUX_PAD(0x03A4, 0x0090, 1, 0x07F4, 0, 0) +#define _MX6Q_PAD_EIM_D16__IPU1_DI0_PIN5 \ + IOMUX_PAD(0x03A4, 0x0090, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_D16__IPU2_CSI1_D_18 \ + IOMUX_PAD(0x03A4, 0x0090, 3, 0x08D0, 0, 0) +#define _MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA \ + IOMUX_PAD(0x03A4, 0x0090, 4, 0x0894, 0, 0) +#define _MX6Q_PAD_EIM_D16__GPIO_3_16 \ + IOMUX_PAD(0x03A4, 0x0090, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_D16__I2C2_SDA \ + IOMUX_PAD(0x03A4, 0x0090, 6 | IOMUX_CONFIG_SION, 0x08A4, 0, 0) + +#define _MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17 \ + IOMUX_PAD(0x03A8, 0x0094, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_D17__ECSPI1_MISO \ + IOMUX_PAD(0x03A8, 0x0094, 1, 0x07F8, 0, 0) +#define _MX6Q_PAD_EIM_D17__IPU1_DI0_PIN6 \ + IOMUX_PAD(0x03A8, 0x0094, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK \ + IOMUX_PAD(0x03A8, 0x0094, 3, 0x08E0, 0, 0) +#define _MX6Q_PAD_EIM_D17__DCIC1_DCIC_OUT \ + IOMUX_PAD(0x03A8, 0x0094, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_D17__GPIO_3_17 \ + IOMUX_PAD(0x03A8, 0x0094, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_D17__I2C3_SCL \ + IOMUX_PAD(0x03A8, 0x0094, 6 | IOMUX_CONFIG_SION, 0x08A8, 0, 0) +#define _MX6Q_PAD_EIM_D17__PL301_MX6QPER1_HBURST_1 \ + IOMUX_PAD(0x03A8, 0x0094, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18 \ + IOMUX_PAD(0x03AC, 0x0098, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_D18__ECSPI1_MOSI \ + IOMUX_PAD(0x03AC, 0x0098, 1, 0x07FC, 0, 0) +#define _MX6Q_PAD_EIM_D18__IPU1_DI0_PIN7 \ + IOMUX_PAD(0x03AC, 0x0098, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_D18__IPU2_CSI1_D_17 \ + IOMUX_PAD(0x03AC, 0x0098, 3, 0x08CC, 0, 0) +#define _MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS \ + IOMUX_PAD(0x03AC, 0x0098, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_D18__GPIO_3_18 \ + IOMUX_PAD(0x03AC, 0x0098, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_D18__I2C3_SDA \ + IOMUX_PAD(0x03AC, 0x0098, 6 | IOMUX_CONFIG_SION, 0x08AC, 0, 0) +#define _MX6Q_PAD_EIM_D18__PL301_MX6QPER1_HBURST_2 \ + IOMUX_PAD(0x03AC, 0x0098, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19 \ + IOMUX_PAD(0x03B0, 0x009C, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_D19__ECSPI1_SS1 \ + IOMUX_PAD(0x03B0, 0x009C, 1, 0x0804, 0, 0) +#define _MX6Q_PAD_EIM_D19__IPU1_DI0_PIN8 \ + IOMUX_PAD(0x03B0, 0x009C, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_D19__IPU2_CSI1_D_16 \ + IOMUX_PAD(0x03B0, 0x009C, 3, 0x08C8, 0, 0) +#define _MX6Q_PAD_EIM_D19__UART1_CTS \ + IOMUX_PAD(0x03B0, 0x009C, 4, 0x091C, 0, 0) +#define _MX6Q_PAD_EIM_D19__GPIO_3_19 \ + IOMUX_PAD(0x03B0, 0x009C, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_D19__EPIT1_EPITO \ + IOMUX_PAD(0x03B0, 0x009C, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_D19__PL301_MX6QPER1_HRESP \ + IOMUX_PAD(0x03B0, 0x009C, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20 \ + IOMUX_PAD(0x03B4, 0x00A0, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_D20__ECSPI4_SS0 \ + IOMUX_PAD(0x03B4, 0x00A0, 1, 0x0824, 0, 0) +#define _MX6Q_PAD_EIM_D20__IPU1_DI0_PIN16 \ + IOMUX_PAD(0x03B4, 0x00A0, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_D20__IPU2_CSI1_D_15 \ + IOMUX_PAD(0x03B4, 0x00A0, 3, 0x08C4, 0, 0) +#define _MX6Q_PAD_EIM_D20__UART1_CTS \ + IOMUX_PAD(0x03B4, 0x00A0, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_D20__UART1_RTS \ + IOMUX_PAD(0x03B4, 0x00A0, 4, 0x091C, 1, 0) +#define _MX6Q_PAD_EIM_D20__GPIO_3_20 \ + IOMUX_PAD(0x03B4, 0x00A0, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_D20__EPIT2_EPITO \ + IOMUX_PAD(0x03B4, 0x00A0, 6, 0x0000, 0, 0) + +#define _MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21 \ + IOMUX_PAD(0x03B8, 0x00A4, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_D21__ECSPI4_SCLK \ + IOMUX_PAD(0x03B8, 0x00A4, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_D21__IPU1_DI0_PIN17 \ + IOMUX_PAD(0x03B8, 0x00A4, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_D21__IPU2_CSI1_D_11 \ + IOMUX_PAD(0x03B8, 0x00A4, 3, 0x08B4, 0, 0) +#define _MX6Q_PAD_EIM_D21__USBOH3_USBOTG_OC \ + IOMUX_PAD(0x03B8, 0x00A4, 4, 0x0944, 0, 0) +#define _MX6Q_PAD_EIM_D21__GPIO_3_21 \ + IOMUX_PAD(0x03B8, 0x00A4, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_D21__I2C1_SCL \ + IOMUX_PAD(0x03B8, 0x00A4, 6 | IOMUX_CONFIG_SION, 0x0898, 0, 0) +#define _MX6Q_PAD_EIM_D21__SPDIF_IN1 \ + IOMUX_PAD(0x03B8, 0x00A4, 7, 0x0914, 0, 0) + +#define _MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22 \ + IOMUX_PAD(0x03BC, 0x00A8, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_D22__ECSPI4_MISO \ + IOMUX_PAD(0x03BC, 0x00A8, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_D22__IPU1_DI0_PIN1 \ + IOMUX_PAD(0x03BC, 0x00A8, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_D22__IPU2_CSI1_D_10 \ + IOMUX_PAD(0x03BC, 0x00A8, 3, 0x08B0, 0, 0) +#define _MX6Q_PAD_EIM_D22__USBOH3_USBOTG_PWR \ + IOMUX_PAD(0x03BC, 0x00A8, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_D22__GPIO_3_22 \ + IOMUX_PAD(0x03BC, 0x00A8, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_D22__SPDIF_OUT1 \ + IOMUX_PAD(0x03BC, 0x00A8, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_D22__PL301_MX6QPER1_HWRITE \ + IOMUX_PAD(0x03BC, 0x00A8, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23 \ + IOMUX_PAD(0x03C0, 0x00AC, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS \ + IOMUX_PAD(0x03C0, 0x00AC, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_D23__UART3_CTS \ + IOMUX_PAD(0x03C0, 0x00AC, 2, 0x092C, 0, 0) +#define _MX6Q_PAD_EIM_D23__UART1_DCD \ + IOMUX_PAD(0x03C0, 0x00AC, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_D23__IPU2_CSI1_DATA_EN \ + IOMUX_PAD(0x03C0, 0x00AC, 4, 0x08D8, 0, 0) +#define _MX6Q_PAD_EIM_D23__GPIO_3_23 \ + IOMUX_PAD(0x03C0, 0x00AC, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_D23__IPU1_DI1_PIN2 \ + IOMUX_PAD(0x03C0, 0x00AC, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_D23__IPU1_DI1_PIN14 \ + IOMUX_PAD(0x03C0, 0x00AC, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_EIM_EB3__WEIM_WEIM_EB_3 \ + IOMUX_PAD(0x03C4, 0x00B0, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_EB3__ECSPI4_RDY \ + IOMUX_PAD(0x03C4, 0x00B0, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_EB3__UART3_CTS \ + IOMUX_PAD(0x03C4, 0x00B0, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_EB3__UART3_RTS \ + IOMUX_PAD(0x03C4, 0x00B0, 2, 0x092C, 1, 0) +#define _MX6Q_PAD_EIM_EB3__UART1_RI \ + IOMUX_PAD(0x03C4, 0x00B0, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_EB3__IPU2_CSI1_HSYNC \ + IOMUX_PAD(0x03C4, 0x00B0, 4, 0x08DC, 0, 0) +#define _MX6Q_PAD_EIM_EB3__GPIO_2_31 \ + IOMUX_PAD(0x03C4, 0x00B0, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_EB3__IPU1_DI1_PIN3 \ + IOMUX_PAD(0x03C4, 0x00B0, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_EB3__SRC_BT_CFG_31 \ + IOMUX_PAD(0x03C4, 0x00B0, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24 \ + IOMUX_PAD(0x03C8, 0x00B4, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_D24__ECSPI4_SS2 \ + IOMUX_PAD(0x03C8, 0x00B4, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_D24__UART3_TXD \ + IOMUX_PAD(0x03C8, 0x00B4, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_D24__UART3_RXD \ + IOMUX_PAD(0x03C8, 0x00B4, 2, 0x0930, 0, 0) +#define _MX6Q_PAD_EIM_D24__ECSPI1_SS2 \ + IOMUX_PAD(0x03C8, 0x00B4, 3, 0x0808, 0, 0) +#define _MX6Q_PAD_EIM_D24__ECSPI2_SS2 \ + IOMUX_PAD(0x03C8, 0x00B4, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_D24__GPIO_3_24 \ + IOMUX_PAD(0x03C8, 0x00B4, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_D24__AUDMUX_AUD5_RXFS \ + IOMUX_PAD(0x03C8, 0x00B4, 6, 0x07D8, 0, 0) +#define _MX6Q_PAD_EIM_D24__UART1_DTR \ + IOMUX_PAD(0x03C8, 0x00B4, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25 \ + IOMUX_PAD(0x03CC, 0x00B8, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_D25__ECSPI4_SS3 \ + IOMUX_PAD(0x03CC, 0x00B8, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_D25__UART3_TXD \ + IOMUX_PAD(0x03CC, 0x00B8, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_D25__UART3_RXD \ + IOMUX_PAD(0x03CC, 0x00B8, 2, 0x0930, 1, 0) +#define _MX6Q_PAD_EIM_D25__ECSPI1_SS3 \ + IOMUX_PAD(0x03CC, 0x00B8, 3, 0x080C, 0, 0) +#define _MX6Q_PAD_EIM_D25__ECSPI2_SS3 \ + IOMUX_PAD(0x03CC, 0x00B8, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_D25__GPIO_3_25 \ + IOMUX_PAD(0x03CC, 0x00B8, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_D25__AUDMUX_AUD5_RXC \ + IOMUX_PAD(0x03CC, 0x00B8, 6, 0x07D4, 0, 0) +#define _MX6Q_PAD_EIM_D25__UART1_DSR \ + IOMUX_PAD(0x03CC, 0x00B8, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_EIM_D26__WEIM_WEIM_D_26 \ + IOMUX_PAD(0x03D0, 0x00BC, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11 \ + IOMUX_PAD(0x03D0, 0x00BC, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_D26__IPU1_CSI0_D_1 \ + IOMUX_PAD(0x03D0, 0x00BC, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_D26__IPU2_CSI1_D_14 \ + IOMUX_PAD(0x03D0, 0x00BC, 3, 0x08C0, 0, 0) +#define _MX6Q_PAD_EIM_D26__UART2_TXD \ + IOMUX_PAD(0x03D0, 0x00BC, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_D26__UART2_RXD \ + IOMUX_PAD(0x03D0, 0x00BC, 4, 0x0928, 0, 0) +#define _MX6Q_PAD_EIM_D26__GPIO_3_26 \ + IOMUX_PAD(0x03D0, 0x00BC, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_D26__IPU1_SISG_2 \ + IOMUX_PAD(0x03D0, 0x00BC, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_D26__IPU1_DISP1_DAT_22 \ + IOMUX_PAD(0x03D0, 0x00BC, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_EIM_D27__WEIM_WEIM_D_27 \ + IOMUX_PAD(0x03D4, 0x00C0, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13 \ + IOMUX_PAD(0x03D4, 0x00C0, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_D27__IPU1_CSI0_D_0 \ + IOMUX_PAD(0x03D4, 0x00C0, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_D27__IPU2_CSI1_D_13 \ + IOMUX_PAD(0x03D4, 0x00C0, 3, 0x08BC, 0, 0) +#define _MX6Q_PAD_EIM_D27__UART2_TXD \ + IOMUX_PAD(0x03D4, 0x00C0, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_D27__UART2_RXD \ + IOMUX_PAD(0x03D4, 0x00C0, 4, 0x0928, 1, 0) +#define _MX6Q_PAD_EIM_D27__GPIO_3_27 \ + IOMUX_PAD(0x03D4, 0x00C0, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_D27__IPU1_SISG_3 \ + IOMUX_PAD(0x03D4, 0x00C0, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_D27__IPU1_DISP1_DAT_23 \ + IOMUX_PAD(0x03D4, 0x00C0, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28 \ + IOMUX_PAD(0x03D8, 0x00C4, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_D28__I2C1_SDA \ + IOMUX_PAD(0x03D8, 0x00C4, 1 | IOMUX_CONFIG_SION, 0x089C, 0, 0) +#define _MX6Q_PAD_EIM_D28__ECSPI4_MOSI \ + IOMUX_PAD(0x03D8, 0x00C4, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_D28__IPU2_CSI1_D_12 \ + IOMUX_PAD(0x03D8, 0x00C4, 3, 0x08B8, 0, 0) +#define _MX6Q_PAD_EIM_D28__UART2_CTS \ + IOMUX_PAD(0x03D8, 0x00C4, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_D28__UART2_RTS \ + IOMUX_PAD(0x03D8, 0x00C4, 4, 0x0924, 0, 0) +#define _MX6Q_PAD_EIM_D28__GPIO_3_28 \ + IOMUX_PAD(0x03D8, 0x00C4, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_D28__IPU1_EXT_TRIG \ + IOMUX_PAD(0x03D8, 0x00C4, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_D28__IPU1_DI0_PIN13 \ + IOMUX_PAD(0x03D8, 0x00C4, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_EIM_D29__WEIM_WEIM_D_29 \ + IOMUX_PAD(0x03DC, 0x00C8, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15 \ + IOMUX_PAD(0x03DC, 0x00C8, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_D29__ECSPI4_SS0 \ + IOMUX_PAD(0x03DC, 0x00C8, 2, 0x0824, 1, 0) +#define _MX6Q_PAD_EIM_D29__UART2_CTS \ + IOMUX_PAD(0x03DC, 0x00C8, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_D29__UART2_RTS \ + IOMUX_PAD(0x03DC, 0x00C8, 4, 0x0924, 1, 0) +#define _MX6Q_PAD_EIM_D29__GPIO_3_29 \ + IOMUX_PAD(0x03DC, 0x00C8, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_D29__IPU2_CSI1_VSYNC \ + IOMUX_PAD(0x03DC, 0x00C8, 6, 0x08E4, 0, 0) +#define _MX6Q_PAD_EIM_D29__IPU1_DI0_PIN14 \ + IOMUX_PAD(0x03DC, 0x00C8, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_EIM_D30__WEIM_WEIM_D_30 \ + IOMUX_PAD(0x03E0, 0x00CC, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_D30__IPU1_DISP1_DAT_21 \ + IOMUX_PAD(0x03E0, 0x00CC, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_D30__IPU1_DI0_PIN11 \ + IOMUX_PAD(0x03E0, 0x00CC, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_D30__IPU1_CSI0_D_3 \ + IOMUX_PAD(0x03E0, 0x00CC, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_D30__UART3_CTS \ + IOMUX_PAD(0x03E0, 0x00CC, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_D30__GPIO_3_30 \ + IOMUX_PAD(0x03E0, 0x00CC, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_D30__USBOH3_USBH1_OC \ + IOMUX_PAD(0x03E0, 0x00CC, 6, 0x0948, 0, 0) +#define _MX6Q_PAD_EIM_D30__PL301_MX6QPER1_HPROT_0 \ + IOMUX_PAD(0x03E0, 0x00CC, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_EIM_D31__WEIM_WEIM_D_31 \ + IOMUX_PAD(0x03E4, 0x00D0, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_D31__IPU1_DISP1_DAT_20 \ + IOMUX_PAD(0x03E4, 0x00D0, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_D31__IPU1_DI0_PIN12 \ + IOMUX_PAD(0x03E4, 0x00D0, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_D31__IPU1_CSI0_D_2 \ + IOMUX_PAD(0x03E4, 0x00D0, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_D31__UART3_CTS \ + IOMUX_PAD(0x03E4, 0x00D0, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_D31__UART3_RTS \ + IOMUX_PAD(0x03E4, 0x00D0, 4, 0x092C, 3, 0) +#define _MX6Q_PAD_EIM_D31__GPIO_3_31 \ + IOMUX_PAD(0x03E4, 0x00D0, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_D31__USBOH3_USBH1_PWR \ + IOMUX_PAD(0x03E4, 0x00D0, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_D31__PL301_MX6QPER1_HPROT_1 \ + IOMUX_PAD(0x03E4, 0x00D0, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_EIM_A24__WEIM_WEIM_A_24 \ + IOMUX_PAD(0x03E8, 0x00D4, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_A24__IPU1_DISP1_DAT_19 \ + IOMUX_PAD(0x03E8, 0x00D4, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_A24__IPU2_CSI1_D_19 \ + IOMUX_PAD(0x03E8, 0x00D4, 2, 0x08D4, 1, 0) +#define _MX6Q_PAD_EIM_A24__IPU2_SISG_2 \ + IOMUX_PAD(0x03E8, 0x00D4, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_A24__IPU1_SISG_2 \ + IOMUX_PAD(0x03E8, 0x00D4, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_A24__GPIO_5_4 \ + IOMUX_PAD(0x03E8, 0x00D4, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_A24__PL301_MX6QPER1_HPROT_2 \ + IOMUX_PAD(0x03E8, 0x00D4, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_A24__SRC_BT_CFG_24 \ + IOMUX_PAD(0x03E8, 0x00D4, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_EIM_A23__WEIM_WEIM_A_23 \ + IOMUX_PAD(0x03EC, 0x00D8, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_A23__IPU1_DISP1_DAT_18 \ + IOMUX_PAD(0x03EC, 0x00D8, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_A23__IPU2_CSI1_D_18 \ + IOMUX_PAD(0x03EC, 0x00D8, 2, 0x08D0, 1, 0) +#define _MX6Q_PAD_EIM_A23__IPU2_SISG_3 \ + IOMUX_PAD(0x03EC, 0x00D8, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_A23__IPU1_SISG_3 \ + IOMUX_PAD(0x03EC, 0x00D8, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_A23__GPIO_6_6 \ + IOMUX_PAD(0x03EC, 0x00D8, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_A23__PL301_MX6QPER1_HPROT_3 \ + IOMUX_PAD(0x03EC, 0x00D8, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_A23__SRC_BT_CFG_23 \ + IOMUX_PAD(0x03EC, 0x00D8, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_EIM_A22__WEIM_WEIM_A_22 \ + IOMUX_PAD(0x03F0, 0x00DC, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_A22__IPU1_DISP1_DAT_17 \ + IOMUX_PAD(0x03F0, 0x00DC, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_A22__IPU2_CSI1_D_17 \ + IOMUX_PAD(0x03F0, 0x00DC, 2, 0x08CC, 1, 0) +#define _MX6Q_PAD_EIM_A22__GPIO_2_16 \ + IOMUX_PAD(0x03F0, 0x00DC, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_A22__TPSMP_HDATA_0 \ + IOMUX_PAD(0x03F0, 0x00DC, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_A22__SRC_BT_CFG_22 \ + IOMUX_PAD(0x03F0, 0x00DC, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_EIM_A21__WEIM_WEIM_A_21 \ + IOMUX_PAD(0x03F4, 0x00E0, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_A21__IPU1_DISP1_DAT_16 \ + IOMUX_PAD(0x03F4, 0x00E0, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_A21__IPU2_CSI1_D_16 \ + IOMUX_PAD(0x03F4, 0x00E0, 2, 0x08C8, 1, 0) +#define _MX6Q_PAD_EIM_A21__RESERVED_RESERVED \ + IOMUX_PAD(0x03F4, 0x00E0, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_A21__MIPI_CORE_DPHY_TEST_OUT_18 \ + IOMUX_PAD(0x03F4, 0x00E0, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_A21__GPIO_2_17 \ + IOMUX_PAD(0x03F4, 0x00E0, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_A21__TPSMP_HDATA_1 \ + IOMUX_PAD(0x03F4, 0x00E0, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_A21__SRC_BT_CFG_21 \ + IOMUX_PAD(0x03F4, 0x00E0, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_EIM_A20__WEIM_WEIM_A_20 \ + IOMUX_PAD(0x03F8, 0x00E4, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_A20__IPU1_DISP1_DAT_15 \ + IOMUX_PAD(0x03F8, 0x00E4, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_A20__IPU2_CSI1_D_15 \ + IOMUX_PAD(0x03F8, 0x00E4, 2, 0x08C4, 1, 0) +#define _MX6Q_PAD_EIM_A20__RESERVED_RESERVED \ + IOMUX_PAD(0x03F8, 0x00E4, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_A20__MIPI_CORE_DPHY_TEST_OUT_19 \ + IOMUX_PAD(0x03F8, 0x00E4, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_A20__GPIO_2_18 \ + IOMUX_PAD(0x03F8, 0x00E4, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_A20__TPSMP_HDATA_2 \ + IOMUX_PAD(0x03F8, 0x00E4, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_A20__SRC_BT_CFG_20 \ + IOMUX_PAD(0x03F8, 0x00E4, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_EIM_A19__WEIM_WEIM_A_19 \ + IOMUX_PAD(0x03FC, 0x00E8, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_A19__IPU1_DISP1_DAT_14 \ + IOMUX_PAD(0x03FC, 0x00E8, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_A19__IPU2_CSI1_D_14 \ + IOMUX_PAD(0x03FC, 0x00E8, 2, 0x08C0, 1, 0) +#define _MX6Q_PAD_EIM_A19__RESERVED_RESERVED \ + IOMUX_PAD(0x03FC, 0x00E8, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_A19__MIPI_CORE_DPHY_TEST_OUT_20 \ + IOMUX_PAD(0x03FC, 0x00E8, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_A19__GPIO_2_19 \ + IOMUX_PAD(0x03FC, 0x00E8, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_A19__TPSMP_HDATA_3 \ + IOMUX_PAD(0x03FC, 0x00E8, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_A19__SRC_BT_CFG_19 \ + IOMUX_PAD(0x03FC, 0x00E8, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_EIM_A18__WEIM_WEIM_A_18 \ + IOMUX_PAD(0x0400, 0x00EC, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_A18__IPU1_DISP1_DAT_13 \ + IOMUX_PAD(0x0400, 0x00EC, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_A18__IPU2_CSI1_D_13 \ + IOMUX_PAD(0x0400, 0x00EC, 2, 0x08BC, 1, 0) +#define _MX6Q_PAD_EIM_A18__RESERVED_RESERVED \ + IOMUX_PAD(0x0400, 0x00EC, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_A18__MIPI_CORE_DPHY_TEST_OUT_21 \ + IOMUX_PAD(0x0400, 0x00EC, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_A18__GPIO_2_20 \ + IOMUX_PAD(0x0400, 0x00EC, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_A18__TPSMP_HDATA_4 \ + IOMUX_PAD(0x0400, 0x00EC, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_A18__SRC_BT_CFG_18 \ + IOMUX_PAD(0x0400, 0x00EC, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_EIM_A17__WEIM_WEIM_A_17 \ + IOMUX_PAD(0x0404, 0x00F0, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_A17__IPU1_DISP1_DAT_12 \ + IOMUX_PAD(0x0404, 0x00F0, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_A17__IPU2_CSI1_D_12 \ + IOMUX_PAD(0x0404, 0x00F0, 2, 0x08B8, 1, 0) +#define _MX6Q_PAD_EIM_A17__RESERVED_RESERVED \ + IOMUX_PAD(0x0404, 0x00F0, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_A17__MIPI_CORE_DPHY_TEST_OUT_22 \ + IOMUX_PAD(0x0404, 0x00F0, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_A17__GPIO_2_21 \ + IOMUX_PAD(0x0404, 0x00F0, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_A17__TPSMP_HDATA_5 \ + IOMUX_PAD(0x0404, 0x00F0, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_A17__SRC_BT_CFG_17 \ + IOMUX_PAD(0x0404, 0x00F0, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_EIM_A16__WEIM_WEIM_A_16 \ + IOMUX_PAD(0x0408, 0x00F4, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_A16__IPU1_DI1_DISP_CLK \ + IOMUX_PAD(0x0408, 0x00F4, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK \ + IOMUX_PAD(0x0408, 0x00F4, 2, 0x08E0, 1, 0) +#define _MX6Q_PAD_EIM_A16__MIPI_CORE_DPHY_TEST_OUT_23 \ + IOMUX_PAD(0x0408, 0x00F4, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_A16__GPIO_2_22 \ + IOMUX_PAD(0x0408, 0x00F4, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_A16__TPSMP_HDATA_6 \ + IOMUX_PAD(0x0408, 0x00F4, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_A16__SRC_BT_CFG_16 \ + IOMUX_PAD(0x0408, 0x00F4, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0 \ + IOMUX_PAD(0x040C, 0x00F8, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_CS0__IPU1_DI1_PIN5 \ + IOMUX_PAD(0x040C, 0x00F8, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_CS0__ECSPI2_SCLK \ + IOMUX_PAD(0x040C, 0x00F8, 2, 0x0810, 0, 0) +#define _MX6Q_PAD_EIM_CS0__MIPI_CORE_DPHY_TEST_OUT_24 \ + IOMUX_PAD(0x040C, 0x00F8, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_CS0__GPIO_2_23 \ + IOMUX_PAD(0x040C, 0x00F8, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_CS0__TPSMP_HDATA_7 \ + IOMUX_PAD(0x040C, 0x00F8, 6, 0x0000, 0, 0) + +#define _MX6Q_PAD_EIM_CS1__WEIM_WEIM_CS_1 \ + IOMUX_PAD(0x0410, 0x00FC, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_CS1__IPU1_DI1_PIN6 \ + IOMUX_PAD(0x0410, 0x00FC, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_CS1__ECSPI2_MOSI \ + IOMUX_PAD(0x0410, 0x00FC, 2, 0x0818, 0, 0) +#define _MX6Q_PAD_EIM_CS1__MIPI_CORE_DPHY_TEST_OUT_25 \ + IOMUX_PAD(0x0410, 0x00FC, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_CS1__GPIO_2_24 \ + IOMUX_PAD(0x0410, 0x00FC, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_CS1__TPSMP_HDATA_8 \ + IOMUX_PAD(0x0410, 0x00FC, 6, 0x0000, 0, 0) + +#define _MX6Q_PAD_EIM_OE__WEIM_WEIM_OE \ + IOMUX_PAD(0x0414, 0x0100, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_OE__IPU1_DI1_PIN7 \ + IOMUX_PAD(0x0414, 0x0100, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_OE__ECSPI2_MISO \ + IOMUX_PAD(0x0414, 0x0100, 2, 0x0814, 0, 0) +#define _MX6Q_PAD_EIM_OE__MIPI_CORE_DPHY_TEST_OUT_26 \ + IOMUX_PAD(0x0414, 0x0100, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_OE__GPIO_2_25 \ + IOMUX_PAD(0x0414, 0x0100, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_OE__TPSMP_HDATA_9 \ + IOMUX_PAD(0x0414, 0x0100, 6, 0x0000, 0, 0) + +#define _MX6Q_PAD_EIM_RW__WEIM_WEIM_RW \ + IOMUX_PAD(0x0418, 0x0104, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_RW__IPU1_DI1_PIN8 \ + IOMUX_PAD(0x0418, 0x0104, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_RW__ECSPI2_SS0 \ + IOMUX_PAD(0x0418, 0x0104, 2, 0x081C, 0, 0) +#define _MX6Q_PAD_EIM_RW__MIPI_CORE_DPHY_TEST_OUT_27 \ + IOMUX_PAD(0x0418, 0x0104, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_RW__GPIO_2_26 \ + IOMUX_PAD(0x0418, 0x0104, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_RW__TPSMP_HDATA_10 \ + IOMUX_PAD(0x0418, 0x0104, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_RW__SRC_BT_CFG_29 \ + IOMUX_PAD(0x0418, 0x0104, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_EIM_LBA__WEIM_WEIM_LBA \ + IOMUX_PAD(0x041C, 0x0108, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_LBA__IPU1_DI1_PIN17 \ + IOMUX_PAD(0x041C, 0x0108, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_LBA__ECSPI2_SS1 \ + IOMUX_PAD(0x041C, 0x0108, 2, 0x0820, 0, 0) +#define _MX6Q_PAD_EIM_LBA__GPIO_2_27 \ + IOMUX_PAD(0x041C, 0x0108, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_LBA__TPSMP_HDATA_11 \ + IOMUX_PAD(0x041C, 0x0108, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_LBA__SRC_BT_CFG_26 \ + IOMUX_PAD(0x041C, 0x0108, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_EIM_EB0__WEIM_WEIM_EB_0 \ + IOMUX_PAD(0x0420, 0x010C, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_EB0__IPU1_DISP1_DAT_11 \ + IOMUX_PAD(0x0420, 0x010C, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_EB0__IPU2_CSI1_D_11 \ + IOMUX_PAD(0x0420, 0x010C, 2, 0x08B4, 1, 0) +#define _MX6Q_PAD_EIM_EB0__MIPI_CORE_DPHY_TEST_OUT_0 \ + IOMUX_PAD(0x0420, 0x010C, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_EB0__CCM_PMIC_RDY \ + IOMUX_PAD(0x0420, 0x010C, 4, 0x07F0, 0, 0) +#define _MX6Q_PAD_EIM_EB0__GPIO_2_28 \ + IOMUX_PAD(0x0420, 0x010C, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_EB0__TPSMP_HDATA_12 \ + IOMUX_PAD(0x0420, 0x010C, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_EB0__SRC_BT_CFG_27 \ + IOMUX_PAD(0x0420, 0x010C, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_EIM_EB1__WEIM_WEIM_EB_1 \ + IOMUX_PAD(0x0424, 0x0110, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_EB1__IPU1_DISP1_DAT_10 \ + IOMUX_PAD(0x0424, 0x0110, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_EB1__IPU2_CSI1_D_10 \ + IOMUX_PAD(0x0424, 0x0110, 2, 0x08B0, 1, 0) +#define _MX6Q_PAD_EIM_EB1__MIPI_CORE_DPHY_TEST_OUT_1 \ + IOMUX_PAD(0x0424, 0x0110, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_EB1__GPIO_2_29 \ + IOMUX_PAD(0x0424, 0x0110, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_EB1__TPSMP_HDATA_13 \ + IOMUX_PAD(0x0424, 0x0110, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_EB1__SRC_BT_CFG_28 \ + IOMUX_PAD(0x0424, 0x0110, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_EIM_DA0__WEIM_WEIM_DA_A_0 \ + IOMUX_PAD(0x0428, 0x0114, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA0__IPU1_DISP1_DAT_9 \ + IOMUX_PAD(0x0428, 0x0114, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA0__IPU2_CSI1_D_9 \ + IOMUX_PAD(0x0428, 0x0114, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA0__MIPI_CORE_DPHY_TEST_OUT_2 \ + IOMUX_PAD(0x0428, 0x0114, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA0__GPIO_3_0 \ + IOMUX_PAD(0x0428, 0x0114, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA0__TPSMP_HDATA_14 \ + IOMUX_PAD(0x0428, 0x0114, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA0__SRC_BT_CFG_0 \ + IOMUX_PAD(0x0428, 0x0114, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_EIM_DA1__WEIM_WEIM_DA_A_1 \ + IOMUX_PAD(0x042C, 0x0118, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA1__IPU1_DISP1_DAT_8 \ + IOMUX_PAD(0x042C, 0x0118, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA1__IPU2_CSI1_D_8 \ + IOMUX_PAD(0x042C, 0x0118, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA1__MIPI_CORE_DPHY_TEST_OUT_3 \ + IOMUX_PAD(0x042C, 0x0118, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA1__ANATOP_USBPHY1_TSTI_TX_LS_MODE \ + IOMUX_PAD(0x042C, 0x0118, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA1__GPIO_3_1 \ + IOMUX_PAD(0x042C, 0x0118, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA1__TPSMP_HDATA_15 \ + IOMUX_PAD(0x042C, 0x0118, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA1__SRC_BT_CFG_1 \ + IOMUX_PAD(0x042C, 0x0118, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_EIM_DA2__WEIM_WEIM_DA_A_2 \ + IOMUX_PAD(0x0430, 0x011C, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA2__IPU1_DISP1_DAT_7 \ + IOMUX_PAD(0x0430, 0x011C, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA2__IPU2_CSI1_D_7 \ + IOMUX_PAD(0x0430, 0x011C, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA2__MIPI_CORE_DPHY_TEST_OUT_4 \ + IOMUX_PAD(0x0430, 0x011C, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA2__ANATOP_USBPHY1_TSTI_TX_HS_MODE \ + IOMUX_PAD(0x0430, 0x011C, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA2__GPIO_3_2 \ + IOMUX_PAD(0x0430, 0x011C, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA2__TPSMP_HDATA_16 \ + IOMUX_PAD(0x0430, 0x011C, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA2__SRC_BT_CFG_2 \ + IOMUX_PAD(0x0430, 0x011C, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_EIM_DA3__WEIM_WEIM_DA_A_3 \ + IOMUX_PAD(0x0434, 0x0120, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA3__IPU1_DISP1_DAT_6 \ + IOMUX_PAD(0x0434, 0x0120, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA3__IPU2_CSI1_D_6 \ + IOMUX_PAD(0x0434, 0x0120, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA3__MIPI_CORE_DPHY_TEST_OUT_5 \ + IOMUX_PAD(0x0434, 0x0120, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA3__ANATOP_USBPHY1_TSTI_TX_HIZ \ + IOMUX_PAD(0x0434, 0x0120, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA3__GPIO_3_3 \ + IOMUX_PAD(0x0434, 0x0120, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA3__TPSMP_HDATA_17 \ + IOMUX_PAD(0x0434, 0x0120, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA3__SRC_BT_CFG_3 \ + IOMUX_PAD(0x0434, 0x0120, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_EIM_DA4__WEIM_WEIM_DA_A_4 \ + IOMUX_PAD(0x0438, 0x0124, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA4__IPU1_DISP1_DAT_5 \ + IOMUX_PAD(0x0438, 0x0124, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA4__IPU2_CSI1_D_5 \ + IOMUX_PAD(0x0438, 0x0124, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA4__MIPI_CORE_DPHY_TEST_OUT_6 \ + IOMUX_PAD(0x0438, 0x0124, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA4__ANATOP_USBPHY1_TSTI_TX_EN \ + IOMUX_PAD(0x0438, 0x0124, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA4__GPIO_3_4 \ + IOMUX_PAD(0x0438, 0x0124, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA4__TPSMP_HDATA_18 \ + IOMUX_PAD(0x0438, 0x0124, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA4__SRC_BT_CFG_4 \ + IOMUX_PAD(0x0438, 0x0124, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_EIM_DA5__WEIM_WEIM_DA_A_5 \ + IOMUX_PAD(0x043C, 0x0128, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA5__IPU1_DISP1_DAT_4 \ + IOMUX_PAD(0x043C, 0x0128, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA5__IPU2_CSI1_D_4 \ + IOMUX_PAD(0x043C, 0x0128, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA5__MIPI_CORE_DPHY_TEST_OUT_7 \ + IOMUX_PAD(0x043C, 0x0128, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA5__ANATOP_USBPHY1_TSTI_TX_DP \ + IOMUX_PAD(0x043C, 0x0128, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA5__GPIO_3_5 \ + IOMUX_PAD(0x043C, 0x0128, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA5__TPSMP_HDATA_19 \ + IOMUX_PAD(0x043C, 0x0128, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA5__SRC_BT_CFG_5 \ + IOMUX_PAD(0x043C, 0x0128, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_EIM_DA6__WEIM_WEIM_DA_A_6 \ + IOMUX_PAD(0x0440, 0x012C, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA6__IPU1_DISP1_DAT_3 \ + IOMUX_PAD(0x0440, 0x012C, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA6__IPU2_CSI1_D_3 \ + IOMUX_PAD(0x0440, 0x012C, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA6__MIPI_CORE_DPHY_TEST_OUT_8 \ + IOMUX_PAD(0x0440, 0x012C, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA6__ANATOP_USBPHY1_TSTI_TX_DN \ + IOMUX_PAD(0x0440, 0x012C, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA6__GPIO_3_6 \ + IOMUX_PAD(0x0440, 0x012C, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA6__TPSMP_HDATA_20 \ + IOMUX_PAD(0x0440, 0x012C, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA6__SRC_BT_CFG_6 \ + IOMUX_PAD(0x0440, 0x012C, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_EIM_DA7__WEIM_WEIM_DA_A_7 \ + IOMUX_PAD(0x0444, 0x0130, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA7__IPU1_DISP1_DAT_2 \ + IOMUX_PAD(0x0444, 0x0130, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA7__IPU2_CSI1_D_2 \ + IOMUX_PAD(0x0444, 0x0130, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA7__MIPI_CORE_DPHY_TEST_OUT_9 \ + IOMUX_PAD(0x0444, 0x0130, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA7__GPIO_3_7 \ + IOMUX_PAD(0x0444, 0x0130, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA7__TPSMP_HDATA_21 \ + IOMUX_PAD(0x0444, 0x0130, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA7__SRC_BT_CFG_7 \ + IOMUX_PAD(0x0444, 0x0130, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_EIM_DA8__WEIM_WEIM_DA_A_8 \ + IOMUX_PAD(0x0448, 0x0134, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA8__IPU1_DISP1_DAT_1 \ + IOMUX_PAD(0x0448, 0x0134, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA8__IPU2_CSI1_D_1 \ + IOMUX_PAD(0x0448, 0x0134, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA8__MIPI_CORE_DPHY_TEST_OUT_10 \ + IOMUX_PAD(0x0448, 0x0134, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA8__GPIO_3_8 \ + IOMUX_PAD(0x0448, 0x0134, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA8__TPSMP_HDATA_22 \ + IOMUX_PAD(0x0448, 0x0134, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA8__SRC_BT_CFG_8 \ + IOMUX_PAD(0x0448, 0x0134, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_EIM_DA9__WEIM_WEIM_DA_A_9 \ + IOMUX_PAD(0x044C, 0x0138, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA9__IPU1_DISP1_DAT_0 \ + IOMUX_PAD(0x044C, 0x0138, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA9__IPU2_CSI1_D_0 \ + IOMUX_PAD(0x044C, 0x0138, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA9__MIPI_CORE_DPHY_TEST_OUT_11 \ + IOMUX_PAD(0x044C, 0x0138, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA9__GPIO_3_9 \ + IOMUX_PAD(0x044C, 0x0138, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA9__TPSMP_HDATA_23 \ + IOMUX_PAD(0x044C, 0x0138, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA9__SRC_BT_CFG_9 \ + IOMUX_PAD(0x044C, 0x0138, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_EIM_DA10__WEIM_WEIM_DA_A_10 \ + IOMUX_PAD(0x0450, 0x013C, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA10__IPU1_DI1_PIN15 \ + IOMUX_PAD(0x0450, 0x013C, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA10__IPU2_CSI1_DATA_EN \ + IOMUX_PAD(0x0450, 0x013C, 2, 0x08D8, 1, 0) +#define _MX6Q_PAD_EIM_DA10__MIPI_CORE_DPHY_TEST_OUT_12 \ + IOMUX_PAD(0x0450, 0x013C, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA10__GPIO_3_10 \ + IOMUX_PAD(0x0450, 0x013C, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA10__TPSMP_HDATA_24 \ + IOMUX_PAD(0x0450, 0x013C, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA10__SRC_BT_CFG_10 \ + IOMUX_PAD(0x0450, 0x013C, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_EIM_DA11__WEIM_WEIM_DA_A_11 \ + IOMUX_PAD(0x0454, 0x0140, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA11__IPU1_DI1_PIN2 \ + IOMUX_PAD(0x0454, 0x0140, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA11__IPU2_CSI1_HSYNC \ + IOMUX_PAD(0x0454, 0x0140, 2, 0x08DC, 1, 0) +#define _MX6Q_PAD_EIM_DA11__MIPI_CORE_DPHY_TEST_OUT_13 \ + IOMUX_PAD(0x0454, 0x0140, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA11__SDMA_DEBUG_EVT_CHN_LINES_6 \ + IOMUX_PAD(0x0454, 0x0140, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA11__GPIO_3_11 \ + IOMUX_PAD(0x0454, 0x0140, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA11__TPSMP_HDATA_25 \ + IOMUX_PAD(0x0454, 0x0140, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA11__SRC_BT_CFG_11 \ + IOMUX_PAD(0x0454, 0x0140, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_EIM_DA12__WEIM_WEIM_DA_A_12 \ + IOMUX_PAD(0x0458, 0x0144, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA12__IPU1_DI1_PIN3 \ + IOMUX_PAD(0x0458, 0x0144, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA12__IPU2_CSI1_VSYNC \ + IOMUX_PAD(0x0458, 0x0144, 2, 0x08E4, 1, 0) +#define _MX6Q_PAD_EIM_DA12__MIPI_CORE_DPHY_TEST_OUT_14 \ + IOMUX_PAD(0x0458, 0x0144, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_LINES_3 \ + IOMUX_PAD(0x0458, 0x0144, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA12__GPIO_3_12 \ + IOMUX_PAD(0x0458, 0x0144, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA12__TPSMP_HDATA_26 \ + IOMUX_PAD(0x0458, 0x0144, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA12__SRC_BT_CFG_12 \ + IOMUX_PAD(0x0458, 0x0144, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_EIM_DA13__WEIM_WEIM_DA_A_13 \ + IOMUX_PAD(0x045C, 0x0148, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA13__IPU1_DI1_D0_CS \ + IOMUX_PAD(0x045C, 0x0148, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA13__CCM_DI1_EXT_CLK \ + IOMUX_PAD(0x045C, 0x0148, 2, 0x07EC, 1, 0) +#define _MX6Q_PAD_EIM_DA13__MIPI_CORE_DPHY_TEST_OUT_15 \ + IOMUX_PAD(0x045C, 0x0148, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_LINES_4 \ + IOMUX_PAD(0x045C, 0x0148, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA13__GPIO_3_13 \ + IOMUX_PAD(0x045C, 0x0148, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA13__TPSMP_HDATA_27 \ + IOMUX_PAD(0x045C, 0x0148, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA13__SRC_BT_CFG_13 \ + IOMUX_PAD(0x045C, 0x0148, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_EIM_DA14__WEIM_WEIM_DA_A_14 \ + IOMUX_PAD(0x0460, 0x014C, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA14__IPU1_DI1_D1_CS \ + IOMUX_PAD(0x0460, 0x014C, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA14__CCM_DI0_EXT_CLK \ + IOMUX_PAD(0x0460, 0x014C, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA14__MIPI_CORE_DPHY_TEST_OUT_16 \ + IOMUX_PAD(0x0460, 0x014C, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_LINES_5 \ + IOMUX_PAD(0x0460, 0x014C, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA14__GPIO_3_14 \ + IOMUX_PAD(0x0460, 0x014C, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA14__TPSMP_HDATA_28 \ + IOMUX_PAD(0x0460, 0x014C, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA14__SRC_BT_CFG_14 \ + IOMUX_PAD(0x0460, 0x014C, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_EIM_DA15__WEIM_WEIM_DA_A_15 \ + IOMUX_PAD(0x0464, 0x0150, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN1 \ + IOMUX_PAD(0x0464, 0x0150, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN4 \ + IOMUX_PAD(0x0464, 0x0150, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA15__MIPI_CORE_DPHY_TEST_OUT_17 \ + IOMUX_PAD(0x0464, 0x0150, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA15__GPIO_3_15 \ + IOMUX_PAD(0x0464, 0x0150, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA15__TPSMP_HDATA_29 \ + IOMUX_PAD(0x0464, 0x0150, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_DA15__SRC_BT_CFG_15 \ + IOMUX_PAD(0x0464, 0x0150, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_EIM_WAIT__WEIM_WEIM_WAIT \ + IOMUX_PAD(0x0468, 0x0154, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B \ + IOMUX_PAD(0x0468, 0x0154, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_WAIT__GPIO_5_0 \ + IOMUX_PAD(0x0468, 0x0154, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_WAIT__TPSMP_HDATA_30 \ + IOMUX_PAD(0x0468, 0x0154, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_WAIT__SRC_BT_CFG_25 \ + IOMUX_PAD(0x0468, 0x0154, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_EIM_BCLK__WEIM_WEIM_BCLK \ + IOMUX_PAD(0x046C, 0x0158, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16 \ + IOMUX_PAD(0x046C, 0x0158, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_BCLK__GPIO_6_31 \ + IOMUX_PAD(0x046C, 0x0158, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_EIM_BCLK__TPSMP_HDATA_31 \ + IOMUX_PAD(0x046C, 0x0158, 6, 0x0000, 0, 0) + +#define _MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK \ + IOMUX_PAD(0x0470, 0x015C, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK \ + IOMUX_PAD(0x0470, 0x015C, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_DI0_DISP_CLK__MIPI_CORE_DPHY_TEST_OUT_28 \ + IOMUX_PAD(0x0470, 0x015C, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 \ + IOMUX_PAD(0x0470, 0x015C, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_DI0_DISP_CLK__GPIO_4_16 \ + IOMUX_PAD(0x0470, 0x015C, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_DI0_DISP_CLK__MMDC_MMDC_DEBUG_0 \ + IOMUX_PAD(0x0470, 0x015C, 6, 0x0000, 0, 0) + +#define _MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15 \ + IOMUX_PAD(0x0474, 0x0160, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15 \ + IOMUX_PAD(0x0474, 0x0160, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_DI0_PIN15__AUDMUX_AUD6_TXC \ + IOMUX_PAD(0x0474, 0x0160, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_DI0_PIN15__MIPI_CORE_DPHY_TEST_OUT_29 \ + IOMUX_PAD(0x0474, 0x0160, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 \ + IOMUX_PAD(0x0474, 0x0160, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_DI0_PIN15__GPIO_4_17 \ + IOMUX_PAD(0x0474, 0x0160, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1 \ + IOMUX_PAD(0x0474, 0x0160, 6, 0x0000, 0, 0) + +#define _MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2 \ + IOMUX_PAD(0x0478, 0x0164, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN2 \ + IOMUX_PAD(0x0478, 0x0164, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_DI0_PIN2__AUDMUX_AUD6_TXD \ + IOMUX_PAD(0x0478, 0x0164, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_DI0_PIN2__MIPI_CORE_DPHY_TEST_OUT_30 \ + IOMUX_PAD(0x0478, 0x0164, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 \ + IOMUX_PAD(0x0478, 0x0164, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_DI0_PIN2__GPIO_4_18 \ + IOMUX_PAD(0x0478, 0x0164, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_DI0_PIN2__MMDC_MMDC_DEBUG_2 \ + IOMUX_PAD(0x0478, 0x0164, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_DI0_PIN2__PL301_MX6QPER1_HADDR_9 \ + IOMUX_PAD(0x0478, 0x0164, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3 \ + IOMUX_PAD(0x047C, 0x0168, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN3 \ + IOMUX_PAD(0x047C, 0x0168, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS \ + IOMUX_PAD(0x047C, 0x0168, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_DI0_PIN3__MIPI_CORE_DPHY_TEST_OUT_31 \ + IOMUX_PAD(0x047C, 0x0168, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 \ + IOMUX_PAD(0x047C, 0x0168, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_DI0_PIN3__GPIO_4_19 \ + IOMUX_PAD(0x047C, 0x0168, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3 \ + IOMUX_PAD(0x047C, 0x0168, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_DI0_PIN3__PL301_MX6QPER1_HADDR_10 \ + IOMUX_PAD(0x047C, 0x0168, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN4 \ + IOMUX_PAD(0x0480, 0x016C, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_DI0_PIN4__IPU2_DI0_PIN4 \ + IOMUX_PAD(0x0480, 0x016C, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_DI0_PIN4__AUDMUX_AUD6_RXD \ + IOMUX_PAD(0x0480, 0x016C, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_DI0_PIN4__USDHC1_WP \ + IOMUX_PAD(0x0480, 0x016C, 3, 0x094C, 0, 0) +#define _MX6Q_PAD_DI0_PIN4__SDMA_DEBUG_YIELD \ + IOMUX_PAD(0x0480, 0x016C, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_DI0_PIN4__GPIO_4_20 \ + IOMUX_PAD(0x0480, 0x016C, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4 \ + IOMUX_PAD(0x0480, 0x016C, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_DI0_PIN4__PL301_MX6QPER1_HADDR_11 \ + IOMUX_PAD(0x0480, 0x016C, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 \ + IOMUX_PAD(0x0484, 0x0170, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0 \ + IOMUX_PAD(0x0484, 0x0170, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK \ + IOMUX_PAD(0x0484, 0x0170, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT0__USDHC1_USDHC_DEBUG_0 \ + IOMUX_PAD(0x0484, 0x0170, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN \ + IOMUX_PAD(0x0484, 0x0170, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT0__GPIO_4_21 \ + IOMUX_PAD(0x0484, 0x0170, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5 \ + IOMUX_PAD(0x0484, 0x0170, 6, 0x0000, 0, 0) + +#define _MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 \ + IOMUX_PAD(0x0488, 0x0174, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1 \ + IOMUX_PAD(0x0488, 0x0174, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI \ + IOMUX_PAD(0x0488, 0x0174, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT1__USDHC1_USDHC_DEBUG_1 \ + IOMUX_PAD(0x0488, 0x0174, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL \ + IOMUX_PAD(0x0488, 0x0174, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT1__GPIO_4_22 \ + IOMUX_PAD(0x0488, 0x0174, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT1__MMDC_MMDC_DEBUG_6 \ + IOMUX_PAD(0x0488, 0x0174, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT1__PL301_MX6QPER1_HADDR_12 \ + IOMUX_PAD(0x0488, 0x0174, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 \ + IOMUX_PAD(0x048C, 0x0178, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2 \ + IOMUX_PAD(0x048C, 0x0178, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO \ + IOMUX_PAD(0x048C, 0x0178, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT2__USDHC1_USDHC_DEBUG_2 \ + IOMUX_PAD(0x048C, 0x0178, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT2__SDMA_DEBUG_MODE \ + IOMUX_PAD(0x048C, 0x0178, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT2__GPIO_4_23 \ + IOMUX_PAD(0x048C, 0x0178, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT2__MMDC_MMDC_DEBUG_7 \ + IOMUX_PAD(0x048C, 0x0178, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT2__PL301_MX6QPER1_HADDR_13 \ + IOMUX_PAD(0x048C, 0x0178, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 \ + IOMUX_PAD(0x0490, 0x017C, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3 \ + IOMUX_PAD(0x0490, 0x017C, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0 \ + IOMUX_PAD(0x0490, 0x017C, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT3__USDHC1_USDHC_DEBUG_3 \ + IOMUX_PAD(0x0490, 0x017C, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR \ + IOMUX_PAD(0x0490, 0x017C, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT3__GPIO_4_24 \ + IOMUX_PAD(0x0490, 0x017C, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT3__MMDC_MMDC_DEBUG_8 \ + IOMUX_PAD(0x0490, 0x017C, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT3__PL301_MX6QPER1_HADDR_14 \ + IOMUX_PAD(0x0490, 0x017C, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 \ + IOMUX_PAD(0x0494, 0x0180, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4 \ + IOMUX_PAD(0x0494, 0x0180, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1 \ + IOMUX_PAD(0x0494, 0x0180, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT4__USDHC1_USDHC_DEBUG_4 \ + IOMUX_PAD(0x0494, 0x0180, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB \ + IOMUX_PAD(0x0494, 0x0180, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT4__GPIO_4_25 \ + IOMUX_PAD(0x0494, 0x0180, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9 \ + IOMUX_PAD(0x0494, 0x0180, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT4__PL301_MX6QPER1_HADDR_15 \ + IOMUX_PAD(0x0494, 0x0180, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 \ + IOMUX_PAD(0x0498, 0x0184, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5 \ + IOMUX_PAD(0x0498, 0x0184, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2 \ + IOMUX_PAD(0x0498, 0x0184, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS \ + IOMUX_PAD(0x0498, 0x0184, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS \ + IOMUX_PAD(0x0498, 0x0184, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT5__GPIO_4_26 \ + IOMUX_PAD(0x0498, 0x0184, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT5__MMDC_MMDC_DEBUG_10 \ + IOMUX_PAD(0x0498, 0x0184, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT5__PL301_MX6QPER1_HADDR_16 \ + IOMUX_PAD(0x0498, 0x0184, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 \ + IOMUX_PAD(0x049C, 0x0188, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6 \ + IOMUX_PAD(0x049C, 0x0188, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3 \ + IOMUX_PAD(0x049C, 0x0188, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC \ + IOMUX_PAD(0x049C, 0x0188, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE \ + IOMUX_PAD(0x049C, 0x0188, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT6__GPIO_4_27 \ + IOMUX_PAD(0x049C, 0x0188, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT6__MMDC_MMDC_DEBUG_11 \ + IOMUX_PAD(0x049C, 0x0188, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT6__PL301_MX6QPER1_HADDR_17 \ + IOMUX_PAD(0x049C, 0x0188, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 \ + IOMUX_PAD(0x04A0, 0x018C, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7 \ + IOMUX_PAD(0x04A0, 0x018C, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY \ + IOMUX_PAD(0x04A0, 0x018C, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT7__USDHC1_USDHC_DEBUG_5 \ + IOMUX_PAD(0x04A0, 0x018C, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 \ + IOMUX_PAD(0x04A0, 0x018C, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT7__GPIO_4_28 \ + IOMUX_PAD(0x04A0, 0x018C, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT7__MMDC_MMDC_DEBUG_12 \ + IOMUX_PAD(0x04A0, 0x018C, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT7__PL301_MX6QPER1_HADDR_18 \ + IOMUX_PAD(0x04A0, 0x018C, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 \ + IOMUX_PAD(0x04A4, 0x0190, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8 \ + IOMUX_PAD(0x04A4, 0x0190, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT8__PWM1_PWMO \ + IOMUX_PAD(0x04A4, 0x0190, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT8__WDOG1_WDOG_B \ + IOMUX_PAD(0x04A4, 0x0190, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 \ + IOMUX_PAD(0x04A4, 0x0190, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT8__GPIO_4_29 \ + IOMUX_PAD(0x04A4, 0x0190, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT8__MMDC_MMDC_DEBUG_13 \ + IOMUX_PAD(0x04A4, 0x0190, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT8__PL301_MX6QPER1_HADDR_19 \ + IOMUX_PAD(0x04A4, 0x0190, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 \ + IOMUX_PAD(0x04A8, 0x0194, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9 \ + IOMUX_PAD(0x04A8, 0x0194, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT9__PWM2_PWMO \ + IOMUX_PAD(0x04A8, 0x0194, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT9__WDOG2_WDOG_B \ + IOMUX_PAD(0x04A8, 0x0194, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 \ + IOMUX_PAD(0x04A8, 0x0194, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT9__GPIO_4_30 \ + IOMUX_PAD(0x04A8, 0x0194, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT9__MMDC_MMDC_DEBUG_14 \ + IOMUX_PAD(0x04A8, 0x0194, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT9__PL301_MX6QPER1_HADDR_20 \ + IOMUX_PAD(0x04A8, 0x0194, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 \ + IOMUX_PAD(0x04AC, 0x0198, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10 \ + IOMUX_PAD(0x04AC, 0x0198, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT10__USDHC1_USDHC_DEBUG_6 \ + IOMUX_PAD(0x04AC, 0x0198, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 \ + IOMUX_PAD(0x04AC, 0x0198, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT10__GPIO_4_31 \ + IOMUX_PAD(0x04AC, 0x0198, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT10__MMDC_MMDC_DEBUG_15 \ + IOMUX_PAD(0x04AC, 0x0198, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT10__PL301_MX6QPER1_HADDR_21 \ + IOMUX_PAD(0x04AC, 0x0198, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 \ + IOMUX_PAD(0x04B0, 0x019C, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11 \ + IOMUX_PAD(0x04B0, 0x019C, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT11__USDHC1_USDHC_DEBUG_7 \ + IOMUX_PAD(0x04B0, 0x019C, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 \ + IOMUX_PAD(0x04B0, 0x019C, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT11__GPIO_5_5 \ + IOMUX_PAD(0x04B0, 0x019C, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT11__MMDC_MMDC_DEBUG_16 \ + IOMUX_PAD(0x04B0, 0x019C, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT11__PL301_MX6QPER1_HADDR_22 \ + IOMUX_PAD(0x04B0, 0x019C, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 \ + IOMUX_PAD(0x04B4, 0x01A0, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12 \ + IOMUX_PAD(0x04B4, 0x01A0, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT12__RESERVED_RESERVED \ + IOMUX_PAD(0x04B4, 0x01A0, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 \ + IOMUX_PAD(0x04B4, 0x01A0, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT12__GPIO_5_6 \ + IOMUX_PAD(0x04B4, 0x01A0, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT12__MMDC_MMDC_DEBUG_17 \ + IOMUX_PAD(0x04B4, 0x01A0, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT12__PL301_MX6QPER1_HADDR_23 \ + IOMUX_PAD(0x04B4, 0x01A0, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 \ + IOMUX_PAD(0x04B8, 0x01A4, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13 \ + IOMUX_PAD(0x04B8, 0x01A4, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS \ + IOMUX_PAD(0x04B8, 0x01A4, 3, 0x07D8, 1, 0) +#define _MX6Q_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 \ + IOMUX_PAD(0x04B8, 0x01A4, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT13__GPIO_5_7 \ + IOMUX_PAD(0x04B8, 0x01A4, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT13__MMDC_MMDC_DEBUG_18 \ + IOMUX_PAD(0x04B8, 0x01A4, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT13__PL301_MX6QPER1_HADDR_24 \ + IOMUX_PAD(0x04B8, 0x01A4, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 \ + IOMUX_PAD(0x04BC, 0x01A8, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14 \ + IOMUX_PAD(0x04BC, 0x01A8, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC \ + IOMUX_PAD(0x04BC, 0x01A8, 3, 0x07D4, 1, 0) +#define _MX6Q_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 \ + IOMUX_PAD(0x04BC, 0x01A8, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT14__GPIO_5_8 \ + IOMUX_PAD(0x04BC, 0x01A8, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT14__MMDC_MMDC_DEBUG_19 \ + IOMUX_PAD(0x04BC, 0x01A8, 6, 0x0000, 0, 0) + +#define _MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 \ + IOMUX_PAD(0x04C0, 0x01AC, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15 \ + IOMUX_PAD(0x04C0, 0x01AC, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1 \ + IOMUX_PAD(0x04C0, 0x01AC, 2, 0x0804, 1, 0) +#define _MX6Q_PAD_DISP0_DAT15__ECSPI2_SS1 \ + IOMUX_PAD(0x04C0, 0x01AC, 3, 0x0820, 1, 0) +#define _MX6Q_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 \ + IOMUX_PAD(0x04C0, 0x01AC, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT15__GPIO_5_9 \ + IOMUX_PAD(0x04C0, 0x01AC, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT15__MMDC_MMDC_DEBUG_20 \ + IOMUX_PAD(0x04C0, 0x01AC, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT15__PL301_MX6QPER1_HADDR_25 \ + IOMUX_PAD(0x04C0, 0x01AC, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 \ + IOMUX_PAD(0x04C4, 0x01B0, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16 \ + IOMUX_PAD(0x04C4, 0x01B0, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI \ + IOMUX_PAD(0x04C4, 0x01B0, 2, 0x0818, 1, 0) +#define _MX6Q_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC \ + IOMUX_PAD(0x04C4, 0x01B0, 3, 0x07DC, 0, 0) +#define _MX6Q_PAD_DISP0_DAT16__SDMA_SDMA_EXT_EVENT_0 \ + IOMUX_PAD(0x04C4, 0x01B0, 4, 0x090C, 0, 0) +#define _MX6Q_PAD_DISP0_DAT16__GPIO_5_10 \ + IOMUX_PAD(0x04C4, 0x01B0, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT16__MMDC_MMDC_DEBUG_21 \ + IOMUX_PAD(0x04C4, 0x01B0, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT16__PL301_MX6QPER1_HADDR_26 \ + IOMUX_PAD(0x04C4, 0x01B0, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 \ + IOMUX_PAD(0x04C8, 0x01B4, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17 \ + IOMUX_PAD(0x04C8, 0x01B4, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO \ + IOMUX_PAD(0x04C8, 0x01B4, 2, 0x0814, 1, 0) +#define _MX6Q_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD \ + IOMUX_PAD(0x04C8, 0x01B4, 3, 0x07D0, 0, 0) +#define _MX6Q_PAD_DISP0_DAT17__SDMA_SDMA_EXT_EVENT_1 \ + IOMUX_PAD(0x04C8, 0x01B4, 4, 0x0910, 0, 0) +#define _MX6Q_PAD_DISP0_DAT17__GPIO_5_11 \ + IOMUX_PAD(0x04C8, 0x01B4, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT17__MMDC_MMDC_DEBUG_22 \ + IOMUX_PAD(0x04C8, 0x01B4, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT17__PL301_MX6QPER1_HADDR_27 \ + IOMUX_PAD(0x04C8, 0x01B4, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 \ + IOMUX_PAD(0x04CC, 0x01B8, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18 \ + IOMUX_PAD(0x04CC, 0x01B8, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0 \ + IOMUX_PAD(0x04CC, 0x01B8, 2, 0x081C, 1, 0) +#define _MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS \ + IOMUX_PAD(0x04CC, 0x01B8, 3, 0x07E0, 0, 0) +#define _MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS \ + IOMUX_PAD(0x04CC, 0x01B8, 4, 0x07C0, 0, 0) +#define _MX6Q_PAD_DISP0_DAT18__GPIO_5_12 \ + IOMUX_PAD(0x04CC, 0x01B8, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT18__MMDC_MMDC_DEBUG_23 \ + IOMUX_PAD(0x04CC, 0x01B8, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT18__WEIM_WEIM_CS_2 \ + IOMUX_PAD(0x04CC, 0x01B8, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 \ + IOMUX_PAD(0x04D0, 0x01BC, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19 \ + IOMUX_PAD(0x04D0, 0x01BC, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK \ + IOMUX_PAD(0x04D0, 0x01BC, 2, 0x0810, 1, 0) +#define _MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD \ + IOMUX_PAD(0x04D0, 0x01BC, 3, 0x07CC, 0, 0) +#define _MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC \ + IOMUX_PAD(0x04D0, 0x01BC, 4, 0x07BC, 0, 0) +#define _MX6Q_PAD_DISP0_DAT19__GPIO_5_13 \ + IOMUX_PAD(0x04D0, 0x01BC, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT19__MMDC_MMDC_DEBUG_24 \ + IOMUX_PAD(0x04D0, 0x01BC, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT19__WEIM_WEIM_CS_3 \ + IOMUX_PAD(0x04D0, 0x01BC, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 \ + IOMUX_PAD(0x04D4, 0x01C0, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20 \ + IOMUX_PAD(0x04D4, 0x01C0, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK \ + IOMUX_PAD(0x04D4, 0x01C0, 2, 0x07F4, 1, 0) +#define _MX6Q_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC \ + IOMUX_PAD(0x04D4, 0x01C0, 3, 0x07C4, 0, 0) +#define _MX6Q_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 \ + IOMUX_PAD(0x04D4, 0x01C0, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT20__GPIO_5_14 \ + IOMUX_PAD(0x04D4, 0x01C0, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT20__MMDC_MMDC_DEBUG_25 \ + IOMUX_PAD(0x04D4, 0x01C0, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT20__PL301_MX6QPER1_HADDR_28 \ + IOMUX_PAD(0x04D4, 0x01C0, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 \ + IOMUX_PAD(0x04D8, 0x01C4, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21 \ + IOMUX_PAD(0x04D8, 0x01C4, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI \ + IOMUX_PAD(0x04D8, 0x01C4, 2, 0x07FC, 1, 0) +#define _MX6Q_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD \ + IOMUX_PAD(0x04D8, 0x01C4, 3, 0x07B8, 1, 0) +#define _MX6Q_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 \ + IOMUX_PAD(0x04D8, 0x01C4, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT21__GPIO_5_15 \ + IOMUX_PAD(0x04D8, 0x01C4, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT21__MMDC_MMDC_DEBUG_26 \ + IOMUX_PAD(0x04D8, 0x01C4, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT21__PL301_MX6QPER1_HADDR_29 \ + IOMUX_PAD(0x04D8, 0x01C4, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 \ + IOMUX_PAD(0x04DC, 0x01C8, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22 \ + IOMUX_PAD(0x04DC, 0x01C8, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO \ + IOMUX_PAD(0x04DC, 0x01C8, 2, 0x07F8, 1, 0) +#define _MX6Q_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS \ + IOMUX_PAD(0x04DC, 0x01C8, 3, 0x07C8, 1, 0) +#define _MX6Q_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 \ + IOMUX_PAD(0x04DC, 0x01C8, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT22__GPIO_5_16 \ + IOMUX_PAD(0x04DC, 0x01C8, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT22__MMDC_MMDC_DEBUG_27 \ + IOMUX_PAD(0x04DC, 0x01C8, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT22__PL301_MX6QPER1_HADDR_30 \ + IOMUX_PAD(0x04DC, 0x01C8, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 \ + IOMUX_PAD(0x04E0, 0x01CC, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23 \ + IOMUX_PAD(0x04E0, 0x01CC, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0 \ + IOMUX_PAD(0x04E0, 0x01CC, 2, 0x0800, 1, 0) +#define _MX6Q_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD \ + IOMUX_PAD(0x04E0, 0x01CC, 3, 0x07B4, 1, 0) +#define _MX6Q_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 \ + IOMUX_PAD(0x04E0, 0x01CC, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT23__GPIO_5_17 \ + IOMUX_PAD(0x04E0, 0x01CC, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT23__MMDC_MMDC_DEBUG_28 \ + IOMUX_PAD(0x04E0, 0x01CC, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_DISP0_DAT23__PL301_MX6QPER1_HADDR_31 \ + IOMUX_PAD(0x04E0, 0x01CC, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_ENET_MDIO__RESERVED_RESERVED \ + IOMUX_PAD(0x04E4, 0x01D0, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_ENET_MDIO__ENET_MDIO \ + IOMUX_PAD(0x04E4, 0x01D0, 1, 0x0840, 0, 0) +#define _MX6Q_PAD_ENET_MDIO__ESAI1_SCKR \ + IOMUX_PAD(0x04E4, 0x01D0, 2, 0x086C, 0, 0) +#define _MX6Q_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEVICE_3 \ + IOMUX_PAD(0x04E4, 0x01D0, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT \ + IOMUX_PAD(0x04E4, 0x01D0, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_ENET_MDIO__GPIO_1_22 \ + IOMUX_PAD(0x04E4, 0x01D0, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_ENET_MDIO__SPDIF_PLOCK \ + IOMUX_PAD(0x04E4, 0x01D0, 6, 0x0000, 0, 0) + +#define _MX6Q_PAD_ENET_REF_CLK__RESERVED_RESERVED \ + IOMUX_PAD(0x04E8, 0x01D4, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK \ + IOMUX_PAD(0x04E8, 0x01D4, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_ENET_REF_CLK__ESAI1_FSR \ + IOMUX_PAD(0x04E8, 0x01D4, 2, 0x085C, 0, 0) +#define _MX6Q_PAD_ENET_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 \ + IOMUX_PAD(0x04E8, 0x01D4, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_ENET_REF_CLK__GPIO_1_23 \ + IOMUX_PAD(0x04E8, 0x01D4, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_ENET_REF_CLK__SPDIF_SRCLK \ + IOMUX_PAD(0x04E8, 0x01D4, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_ENET_REF_CLK__ANATOP_USBPHY1_TSTO_RX_SQUELCH \ + IOMUX_PAD(0x04E8, 0x01D4, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_ENET_RX_ER__ANATOP_USBOTG_ID \ + IOMUX_PAD(0x04EC, 0x01D8, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_ENET_RX_ER__ENET_RX_ER \ + IOMUX_PAD(0x04EC, 0x01D8, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_ENET_RX_ER__ESAI1_HCKR \ + IOMUX_PAD(0x04EC, 0x01D8, 2, 0x0864, 0, 0) +#define _MX6Q_PAD_ENET_RX_ER__SPDIF_IN1 \ + IOMUX_PAD(0x04EC, 0x01D8, 3, 0x0914, 1, 0) +#define _MX6Q_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT \ + IOMUX_PAD(0x04EC, 0x01D8, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_ENET_RX_ER__GPIO_1_24 \ + IOMUX_PAD(0x04EC, 0x01D8, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_ENET_RX_ER__PHY_TDI \ + IOMUX_PAD(0x04EC, 0x01D8, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_ENET_RX_ER__ANATOP_USBPHY1_TSTO_RX_HS_RXD \ + IOMUX_PAD(0x04EC, 0x01D8, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_ENET_CRS_DV__RESERVED_RESERVED \ + IOMUX_PAD(0x04F0, 0x01DC, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN \ + IOMUX_PAD(0x04F0, 0x01DC, 1, 0x0858, 1, 0) +#define _MX6Q_PAD_ENET_CRS_DV__ESAI1_SCKT \ + IOMUX_PAD(0x04F0, 0x01DC, 2, 0x0870, 0, 0) +#define _MX6Q_PAD_ENET_CRS_DV__SPDIF_SPDIF_EXTCLK \ + IOMUX_PAD(0x04F0, 0x01DC, 3, 0x0918, 1, 0) +#define _MX6Q_PAD_ENET_CRS_DV__GPIO_1_25 \ + IOMUX_PAD(0x04F0, 0x01DC, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_ENET_CRS_DV__PHY_TDO \ + IOMUX_PAD(0x04F0, 0x01DC, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_ENET_CRS_DV__ANATOP_USBPHY1_TSTO_RX_FS_RXD \ + IOMUX_PAD(0x04F0, 0x01DC, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_ENET_RXD1__MLB_MLBSIG \ + IOMUX_PAD(0x04F4, 0x01E0, 0, 0x0908, 0, 0) +#define _MX6Q_PAD_ENET_RXD1__ENET_RDATA_1 \ + IOMUX_PAD(0x04F4, 0x01E0, 1, 0x084C, 1, 0) +#define _MX6Q_PAD_ENET_RXD1__ESAI1_FST \ + IOMUX_PAD(0x04F4, 0x01E0, 2, 0x0860, 0, 0) +#define _MX6Q_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT \ + IOMUX_PAD(0x04F4, 0x01E0, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_ENET_RXD1__GPIO_1_26 \ + IOMUX_PAD(0x04F4, 0x01E0, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_ENET_RXD1__PHY_TCK \ + IOMUX_PAD(0x04F4, 0x01E0, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_ENET_RXD1__ANATOP_USBPHY1_TSTO_RX_DISCON_DET \ + IOMUX_PAD(0x04F4, 0x01E0, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_ENET_RXD0__OSC32K_32K_OUT \ + IOMUX_PAD(0x04F8, 0x01E4, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_ENET_RXD0__ENET_RDATA_0 \ + IOMUX_PAD(0x04F8, 0x01E4, 1, 0x0848, 1, 0) +#define _MX6Q_PAD_ENET_RXD0__ESAI1_HCKT \ + IOMUX_PAD(0x04F8, 0x01E4, 2, 0x0868, 0, 0) +#define _MX6Q_PAD_ENET_RXD0__SPDIF_OUT1 \ + IOMUX_PAD(0x04F8, 0x01E4, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_ENET_RXD0__GPIO_1_27 \ + IOMUX_PAD(0x04F8, 0x01E4, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_ENET_RXD0__PHY_TMS \ + IOMUX_PAD(0x04F8, 0x01E4, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_ENET_RXD0__ANATOP_USBPHY1_TSTO_PLL_CLK20DIV \ + IOMUX_PAD(0x04F8, 0x01E4, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_ENET_TX_EN__RESERVED_RESERVED \ + IOMUX_PAD(0x04FC, 0x01E8, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_ENET_TX_EN__ENET_TX_EN \ + IOMUX_PAD(0x04FC, 0x01E8, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_ENET_TX_EN__ESAI1_TX3_RX2 \ + IOMUX_PAD(0x04FC, 0x01E8, 2, 0x0880, 0, 0) +#define _MX6Q_PAD_ENET_TX_EN__GPIO_1_28 \ + IOMUX_PAD(0x04FC, 0x01E8, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_ENET_TX_EN__SATA_PHY_TDI \ + IOMUX_PAD(0x04FC, 0x01E8, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_ENET_TX_EN__ANATOP_USBPHY2_TSTO_RX_SQUELCH \ + IOMUX_PAD(0x04FC, 0x01E8, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_ENET_TXD1__MLB_MLBCLK \ + IOMUX_PAD(0x0500, 0x01EC, 0, 0x0900, 0, 0) +#define _MX6Q_PAD_ENET_TXD1__ENET_TDATA_1 \ + IOMUX_PAD(0x0500, 0x01EC, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_ENET_TXD1__ESAI1_TX2_RX3 \ + IOMUX_PAD(0x0500, 0x01EC, 2, 0x087C, 0, 0) +#define _MX6Q_PAD_ENET_TXD1__ENET_1588_EVENT0_IN \ + IOMUX_PAD(0x0500, 0x01EC, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_ENET_TXD1__GPIO_1_29 \ + IOMUX_PAD(0x0500, 0x01EC, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_ENET_TXD1__SATA_PHY_TDO \ + IOMUX_PAD(0x0500, 0x01EC, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_ENET_TXD1__ANATOP_USBPHY2_TSTO_RX_HS_RXD \ + IOMUX_PAD(0x0500, 0x01EC, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_ENET_TXD0__RESERVED_RESERVED \ + IOMUX_PAD(0x0504, 0x01F0, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_ENET_TXD0__ENET_TDATA_0 \ + IOMUX_PAD(0x0504, 0x01F0, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_ENET_TXD0__ESAI1_TX4_RX1 \ + IOMUX_PAD(0x0504, 0x01F0, 2, 0x0884, 0, 0) +#define _MX6Q_PAD_ENET_TXD0__GPIO_1_30 \ + IOMUX_PAD(0x0504, 0x01F0, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_ENET_TXD0__SATA_PHY_TCK \ + IOMUX_PAD(0x0504, 0x01F0, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_ENET_TXD0__ANATOP_USBPHY2_TSTO_RX_FS_RXD \ + IOMUX_PAD(0x0504, 0x01F0, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_ENET_MDC__MLB_MLBDAT \ + IOMUX_PAD(0x0508, 0x01F4, 0, 0x0904, 0, 0) +#define _MX6Q_PAD_ENET_MDC__ENET_MDC \ + IOMUX_PAD(0x0508, 0x01F4, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_ENET_MDC__ESAI1_TX5_RX0 \ + IOMUX_PAD(0x0508, 0x01F4, 2, 0x0888, 0, 0) +#define _MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN \ + IOMUX_PAD(0x0508, 0x01F4, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_ENET_MDC__GPIO_1_31 \ + IOMUX_PAD(0x0508, 0x01F4, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_ENET_MDC__SATA_PHY_TMS \ + IOMUX_PAD(0x0508, 0x01F4, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_ENET_MDC__ANATOP_USBPHY2_TSTO_RX_DISCON_DET \ + IOMUX_PAD(0x0508, 0x01F4, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_D40__MMDC_DRAM_D_40 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_D41__MMDC_DRAM_D_41 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_D42__MMDC_DRAM_D_42 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_D43__MMDC_DRAM_D_43 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_D44__MMDC_DRAM_D_44 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_D45__MMDC_DRAM_D_45 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_D46__MMDC_DRAM_D_46 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_D47__MMDC_DRAM_D_47 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5 \ + IOMUX_PAD(0x050C, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5 \ + IOMUX_PAD(0x0510, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_D32__MMDC_DRAM_D_32 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_D33__MMDC_DRAM_D_33 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_D34__MMDC_DRAM_D_34 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_D35__MMDC_DRAM_D_35 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_D36__MMDC_DRAM_D_36 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_D37__MMDC_DRAM_D_37 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_D38__MMDC_DRAM_D_38 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_D39__MMDC_DRAM_D_39 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4 \ + IOMUX_PAD(0x0514, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4 \ + IOMUX_PAD(0x0518, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_D24__MMDC_DRAM_D_24 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_D25__MMDC_DRAM_D_25 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_D26__MMDC_DRAM_D_26 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_D27__MMDC_DRAM_D_27 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_D28__MMDC_DRAM_D_28 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_D29__MMDC_DRAM_D_29 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3 \ + IOMUX_PAD(0x051C, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_D30__MMDC_DRAM_D_30 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_D31__MMDC_DRAM_D_31 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3 \ + IOMUX_PAD(0x0520, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_D16__MMDC_DRAM_D_16 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_D17__MMDC_DRAM_D_17 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_D18__MMDC_DRAM_D_18 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_D19__MMDC_DRAM_D_19 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_D20__MMDC_DRAM_D_20 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_D21__MMDC_DRAM_D_21 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_D22__MMDC_DRAM_D_22 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2 \ + IOMUX_PAD(0x0524, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_D23__MMDC_DRAM_D_23 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2 \ + IOMUX_PAD(0x0528, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_A0__MMDC_DRAM_A_0 \ + IOMUX_PAD(0x052C, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_A1__MMDC_DRAM_A_1 \ + IOMUX_PAD(0x0530, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_A2__MMDC_DRAM_A_2 \ + IOMUX_PAD(0x0534, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_A3__MMDC_DRAM_A_3 \ + IOMUX_PAD(0x0538, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_A4__MMDC_DRAM_A_4 \ + IOMUX_PAD(0x053C, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_A5__MMDC_DRAM_A_5 \ + IOMUX_PAD(0x0540, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_A6__MMDC_DRAM_A_6 \ + IOMUX_PAD(0x0544, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_A7__MMDC_DRAM_A_7 \ + IOMUX_PAD(0x0548, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_A8__MMDC_DRAM_A_8 \ + IOMUX_PAD(0x054C, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_A9__MMDC_DRAM_A_9 \ + IOMUX_PAD(0x0550, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_A10__MMDC_DRAM_A_10 \ + IOMUX_PAD(0x0554, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_A11__MMDC_DRAM_A_11 \ + IOMUX_PAD(0x0558, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_A12__MMDC_DRAM_A_12 \ + IOMUX_PAD(0x055C, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_A13__MMDC_DRAM_A_13 \ + IOMUX_PAD(0x0560, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_A14__MMDC_DRAM_A_14 \ + IOMUX_PAD(0x0564, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_A15__MMDC_DRAM_A_15 \ + IOMUX_PAD(0x0568, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_CAS__MMDC_DRAM_CAS \ + IOMUX_PAD(0x056C, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_CS0__MMDC_DRAM_CS_0 \ + IOMUX_PAD(0x0570, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_CS1__MMDC_DRAM_CS_1 \ + IOMUX_PAD(0x0574, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_RAS__MMDC_DRAM_RAS \ + IOMUX_PAD(0x0578, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_RESET__MMDC_DRAM_RESET \ + IOMUX_PAD(0x057C, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0 \ + IOMUX_PAD(0x0580, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1 \ + IOMUX_PAD(0x0584, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0 \ + IOMUX_PAD(0x0588, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2 \ + IOMUX_PAD(0x058C, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0 \ + IOMUX_PAD(0x0590, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1 \ + IOMUX_PAD(0x0594, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1 \ + IOMUX_PAD(0x0598, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0 \ + IOMUX_PAD(0x059C, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1 \ + IOMUX_PAD(0x05A0, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_SDWE__MMDC_DRAM_SDWE \ + IOMUX_PAD(0x05A4, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_D0__MMDC_DRAM_D_0 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_D1__MMDC_DRAM_D_1 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_D2__MMDC_DRAM_D_2 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_D3__MMDC_DRAM_D_3 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_D4__MMDC_DRAM_D_4 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_D5__MMDC_DRAM_D_5 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0 \ + IOMUX_PAD(0x05A8, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_D6__MMDC_DRAM_D_6 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_D7__MMDC_DRAM_D_7 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0 \ + IOMUX_PAD(0x05AC, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_D8__MMDC_DRAM_D_8 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_D9__MMDC_DRAM_D_9 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_D10__MMDC_DRAM_D_10 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_D11__MMDC_DRAM_D_11 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_D12__MMDC_DRAM_D_12 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_D13__MMDC_DRAM_D_13 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_D14__MMDC_DRAM_D_14 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1 \ + IOMUX_PAD(0x05B0, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_D15__MMDC_DRAM_D_15 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1 \ + IOMUX_PAD(0x05B4, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_D48__MMDC_DRAM_D_48 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_D49__MMDC_DRAM_D_49 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_D50__MMDC_DRAM_D_50 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_D51__MMDC_DRAM_D_51 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_D52__MMDC_DRAM_D_52 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_D53__MMDC_DRAM_D_53 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_D54__MMDC_DRAM_D_54 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_D55__MMDC_DRAM_D_55 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6 \ + IOMUX_PAD(0x05B8, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6 \ + IOMUX_PAD(0x05BC, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_D56__MMDC_DRAM_D_56 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7 \ + IOMUX_PAD(0x05C0, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_D57__MMDC_DRAM_D_57 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_D58__MMDC_DRAM_D_58 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_D59__MMDC_DRAM_D_59 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_D60__MMDC_DRAM_D_60 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7 \ + IOMUX_PAD(0x05C4, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_D61__MMDC_DRAM_D_61 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_D62__MMDC_DRAM_D_62 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_DRAM_D63__MMDC_DRAM_D_63 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_KEY_COL0__ECSPI1_SCLK \ + IOMUX_PAD(0x05C8, 0x01F8, 0, 0x07F4, 2, 0) +#define _MX6Q_PAD_KEY_COL0__ENET_RDATA_3 \ + IOMUX_PAD(0x05C8, 0x01F8, 1, 0x0854, 1, 0) +#define _MX6Q_PAD_KEY_COL0__AUDMUX_AUD5_TXC \ + IOMUX_PAD(0x05C8, 0x01F8, 2, 0x07DC, 1, 0) +#define _MX6Q_PAD_KEY_COL0__KPP_COL_0 \ + IOMUX_PAD(0x05C8, 0x01F8, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_KEY_COL0__UART4_TXD \ + IOMUX_PAD(0x05C8, 0x01F8, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_KEY_COL0__UART4_RXD \ + IOMUX_PAD(0x05C8, 0x01F8, 4, 0x0938, 0, 0) +#define _MX6Q_PAD_KEY_COL0__GPIO_4_6 \ + IOMUX_PAD(0x05C8, 0x01F8, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_KEY_COL0__DCIC1_DCIC_OUT \ + IOMUX_PAD(0x05C8, 0x01F8, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_KEY_COL0__SRC_ANY_PU_RST \ + IOMUX_PAD(0x05C8, 0x01F8, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI \ + IOMUX_PAD(0x05CC, 0x01FC, 0, 0x07FC, 2, 0) +#define _MX6Q_PAD_KEY_ROW0__ENET_TDATA_3 \ + IOMUX_PAD(0x05CC, 0x01FC, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_KEY_ROW0__AUDMUX_AUD5_TXD \ + IOMUX_PAD(0x05CC, 0x01FC, 2, 0x07D0, 1, 0) +#define _MX6Q_PAD_KEY_ROW0__KPP_ROW_0 \ + IOMUX_PAD(0x05CC, 0x01FC, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_KEY_ROW0__UART4_TXD \ + IOMUX_PAD(0x05CC, 0x01FC, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_KEY_ROW0__UART4_RXD \ + IOMUX_PAD(0x05CC, 0x01FC, 4, 0x0938, 1, 0) +#define _MX6Q_PAD_KEY_ROW0__GPIO_4_7 \ + IOMUX_PAD(0x05CC, 0x01FC, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_KEY_ROW0__DCIC2_DCIC_OUT \ + IOMUX_PAD(0x05CC, 0x01FC, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_KEY_ROW0__PL301_MX6QPER1_HADDR_0 \ + IOMUX_PAD(0x05CC, 0x01FC, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_KEY_COL1__ECSPI1_MISO \ + IOMUX_PAD(0x05D0, 0x0200, 0, 0x07F8, 2, 0) +#define _MX6Q_PAD_KEY_COL1__ENET_MDIO \ + IOMUX_PAD(0x05D0, 0x0200, 1, 0x0840, 1, 0) +#define _MX6Q_PAD_KEY_COL1__AUDMUX_AUD5_TXFS \ + IOMUX_PAD(0x05D0, 0x0200, 2, 0x07E0, 1, 0) +#define _MX6Q_PAD_KEY_COL1__KPP_COL_1 \ + IOMUX_PAD(0x05D0, 0x0200, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_KEY_COL1__UART5_TXD \ + IOMUX_PAD(0x05D0, 0x0200, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_KEY_COL1__UART5_RXD \ + IOMUX_PAD(0x05D0, 0x0200, 4, 0x0940, 0, 0) +#define _MX6Q_PAD_KEY_COL1__GPIO_4_8 \ + IOMUX_PAD(0x05D0, 0x0200, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_KEY_COL1__USDHC1_VSELECT \ + IOMUX_PAD(0x05D0, 0x0200, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_KEY_COL1__PL301_MX6QPER1_HADDR_1 \ + IOMUX_PAD(0x05D0, 0x0200, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_KEY_ROW1__ECSPI1_SS0 \ + IOMUX_PAD(0x05D4, 0x0204, 0, 0x0800, 2, 0) +#define _MX6Q_PAD_KEY_ROW1__ENET_COL \ + IOMUX_PAD(0x05D4, 0x0204, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_KEY_ROW1__AUDMUX_AUD5_RXD \ + IOMUX_PAD(0x05D4, 0x0204, 2, 0x07CC, 1, 0) +#define _MX6Q_PAD_KEY_ROW1__KPP_ROW_1 \ + IOMUX_PAD(0x05D4, 0x0204, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_KEY_ROW1__UART5_TXD \ + IOMUX_PAD(0x05D4, 0x0204, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_KEY_ROW1__UART5_RXD \ + IOMUX_PAD(0x05D4, 0x0204, 4, 0x0940, 1, 0) +#define _MX6Q_PAD_KEY_ROW1__GPIO_4_9 \ + IOMUX_PAD(0x05D4, 0x0204, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_KEY_ROW1__USDHC2_VSELECT \ + IOMUX_PAD(0x05D4, 0x0204, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_KEY_ROW1__PL301_MX6QPER1_HADDR_2 \ + IOMUX_PAD(0x05D4, 0x0204, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_KEY_COL2__ECSPI1_SS1 \ + IOMUX_PAD(0x05D8, 0x0208, 0, 0x0804, 2, 0) +#define _MX6Q_PAD_KEY_COL2__ENET_RDATA_2 \ + IOMUX_PAD(0x05D8, 0x0208, 1, 0x0850, 1, 0) +#define _MX6Q_PAD_KEY_COL2__CAN1_TXCAN \ + IOMUX_PAD(0x05D8, 0x0208, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_KEY_COL2__KPP_COL_2 \ + IOMUX_PAD(0x05D8, 0x0208, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_KEY_COL2__ENET_MDC \ + IOMUX_PAD(0x05D8, 0x0208, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_KEY_COL2__GPIO_4_10 \ + IOMUX_PAD(0x05D8, 0x0208, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_KEY_COL2__USBOH3_H1USB_PWRCTL_WAKEUP \ + IOMUX_PAD(0x05D8, 0x0208, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_KEY_COL2__PL301_MX6QPER1_HADDR_3 \ + IOMUX_PAD(0x05D8, 0x0208, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_KEY_ROW2__ECSPI1_SS2 \ + IOMUX_PAD(0x05DC, 0x020C, 0, 0x0808, 1, 0) +#define _MX6Q_PAD_KEY_ROW2__ENET_TDATA_2 \ + IOMUX_PAD(0x05DC, 0x020C, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_KEY_ROW2__CAN1_RXCAN \ + IOMUX_PAD(0x05DC, 0x020C, 2, 0x07E4, 0, 0) +#define _MX6Q_PAD_KEY_ROW2__KPP_ROW_2 \ + IOMUX_PAD(0x05DC, 0x020C, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_KEY_ROW2__USDHC2_VSELECT \ + IOMUX_PAD(0x05DC, 0x020C, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_KEY_ROW2__GPIO_4_11 \ + IOMUX_PAD(0x05DC, 0x020C, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE \ + IOMUX_PAD(0x05DC, 0x020C, 6, 0x088C, 1, 0) +#define _MX6Q_PAD_KEY_ROW2__PL301_MX6QPER1_HADDR_4 \ + IOMUX_PAD(0x05DC, 0x020C, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_KEY_COL3__ECSPI1_SS3 \ + IOMUX_PAD(0x05E0, 0x0210, 0, 0x080C, 1, 0) +#define _MX6Q_PAD_KEY_COL3__ENET_CRS \ + IOMUX_PAD(0x05E0, 0x0210, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL \ + IOMUX_PAD(0x05E0, 0x0210, 2 | IOMUX_CONFIG_SION, 0x0890, 1, 0) +#define _MX6Q_PAD_KEY_COL3__KPP_COL_3 \ + IOMUX_PAD(0x05E0, 0x0210, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_KEY_COL3__I2C2_SCL \ + IOMUX_PAD(0x05E0, 0x0210, 4 | IOMUX_CONFIG_SION, 0x08A0, 1, 0) +#define _MX6Q_PAD_KEY_COL3__GPIO_4_12 \ + IOMUX_PAD(0x05E0, 0x0210, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_KEY_COL3__SPDIF_IN1 \ + IOMUX_PAD(0x05E0, 0x0210, 6, 0x0914, 2, 0) +#define _MX6Q_PAD_KEY_COL3__PL301_MX6QPER1_HADDR_5 \ + IOMUX_PAD(0x05E0, 0x0210, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_KEY_ROW3__OSC32K_32K_OUT \ + IOMUX_PAD(0x05E4, 0x0214, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK \ + IOMUX_PAD(0x05E4, 0x0214, 1, 0x07B0, 0, 0) +#define _MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA \ + IOMUX_PAD(0x05E4, 0x0214, 2 | IOMUX_CONFIG_SION, 0x0894, 1, 0) +#define _MX6Q_PAD_KEY_ROW3__KPP_ROW_3 \ + IOMUX_PAD(0x05E4, 0x0214, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_KEY_ROW3__I2C2_SDA \ + IOMUX_PAD(0x05E4, 0x0214, 4 | IOMUX_CONFIG_SION, 0x08A4, 1, 0) +#define _MX6Q_PAD_KEY_ROW3__GPIO_4_13 \ + IOMUX_PAD(0x05E4, 0x0214, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_KEY_ROW3__USDHC1_VSELECT \ + IOMUX_PAD(0x05E4, 0x0214, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_KEY_ROW3__PL301_MX6QPER1_HADDR_6 \ + IOMUX_PAD(0x05E4, 0x0214, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_KEY_COL4__CAN2_TXCAN \ + IOMUX_PAD(0x05E8, 0x0218, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_KEY_COL4__IPU1_SISG_4 \ + IOMUX_PAD(0x05E8, 0x0218, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_KEY_COL4__USBOH3_USBOTG_OC \ + IOMUX_PAD(0x05E8, 0x0218, 2, 0x0944, 1, 0) +#define _MX6Q_PAD_KEY_COL4__KPP_COL_4 \ + IOMUX_PAD(0x05E8, 0x0218, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_KEY_COL4__UART5_CTS \ + IOMUX_PAD(0x05E8, 0x0218, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_KEY_COL4__UART5_RTS \ + IOMUX_PAD(0x05E8, 0x0218, 4, 0x093C, 0, 0) +#define _MX6Q_PAD_KEY_COL4__GPIO_4_14 \ + IOMUX_PAD(0x05E8, 0x0218, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_KEY_COL4__MMDC_MMDC_DEBUG_49 \ + IOMUX_PAD(0x05E8, 0x0218, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_KEY_COL4__PL301_MX6QPER1_HADDR_7 \ + IOMUX_PAD(0x05E8, 0x0218, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_KEY_ROW4__CAN2_RXCAN \ + IOMUX_PAD(0x05EC, 0x021C, 0, 0x07E8, 0, 0) +#define _MX6Q_PAD_KEY_ROW4__IPU1_SISG_5 \ + IOMUX_PAD(0x05EC, 0x021C, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_KEY_ROW4__USBOH3_USBOTG_PWR \ + IOMUX_PAD(0x05EC, 0x021C, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_KEY_ROW4__KPP_ROW_4 \ + IOMUX_PAD(0x05EC, 0x021C, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_KEY_ROW4__UART5_CTS \ + IOMUX_PAD(0x05EC, 0x021C, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_KEY_ROW4__GPIO_4_15 \ + IOMUX_PAD(0x05EC, 0x021C, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_KEY_ROW4__MMDC_MMDC_DEBUG_50 \ + IOMUX_PAD(0x05EC, 0x021C, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_KEY_ROW4__PL301_MX6QPER1_HADDR_8 \ + IOMUX_PAD(0x05EC, 0x021C, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_GPIO_0__CCM_CLKO \ + IOMUX_PAD(0x05F0, 0x0220, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_GPIO_0__KPP_COL_5 \ + IOMUX_PAD(0x05F0, 0x0220, 2, 0x08E8, 0, 0) +#define _MX6Q_PAD_GPIO_0__ASRC_ASRC_EXT_CLK \ + IOMUX_PAD(0x05F0, 0x0220, 3, 0x07B0, 1, 0) +#define _MX6Q_PAD_GPIO_0__EPIT1_EPITO \ + IOMUX_PAD(0x05F0, 0x0220, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_GPIO_0__GPIO_1_0 \ + IOMUX_PAD(0x05F0, 0x0220, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_GPIO_0__USBOH3_USBH1_PWR \ + IOMUX_PAD(0x05F0, 0x0220, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_GPIO_0__SNVS_HP_WRAPPER_SNVS_VIO_5 \ + IOMUX_PAD(0x05F0, 0x0220, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_GPIO_1__ESAI1_SCKR \ + IOMUX_PAD(0x05F4, 0x0224, 0, 0x086C, 1, 0) +#define _MX6Q_PAD_GPIO_1__WDOG2_WDOG_B \ + IOMUX_PAD(0x05F4, 0x0224, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_GPIO_1__KPP_ROW_5 \ + IOMUX_PAD(0x05F4, 0x0224, 2, 0x08F4, 0, 0) +#define MX6Q_PAD_GPIO_1__USBOTG_ID \ + IOMUX_PAD(0x05F4, 0x0224, 3, 0x0000, 0, MX6Q_USDHC_PAD_CTRL) +#define _MX6Q_PAD_GPIO_1__PWM2_PWMO \ + IOMUX_PAD(0x05F4, 0x0224, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_GPIO_1__GPIO_1_1 \ + IOMUX_PAD(0x05F4, 0x0224, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_GPIO_1__USDHC1_CD \ + IOMUX_PAD(0x05F4, 0x0224, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_GPIO_1__SRC_TESTER_ACK \ + IOMUX_PAD(0x05F4, 0x0224, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_GPIO_9__ESAI1_FSR \ + IOMUX_PAD(0x05F8, 0x0228, 0, 0x085C, 1, 0) +#define _MX6Q_PAD_GPIO_9__WDOG1_WDOG_B \ + IOMUX_PAD(0x05F8, 0x0228, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_GPIO_9__KPP_COL_6 \ + IOMUX_PAD(0x05F8, 0x0228, 2, 0x08EC, 0, 0) +#define _MX6Q_PAD_GPIO_9__CCM_REF_EN_B \ + IOMUX_PAD(0x05F8, 0x0228, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_GPIO_9__PWM1_PWMO \ + IOMUX_PAD(0x05F8, 0x0228, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_GPIO_9__GPIO_1_9 \ + IOMUX_PAD(0x05F8, 0x0228, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_GPIO_9__USDHC1_WP \ + IOMUX_PAD(0x05F8, 0x0228, 6, 0x094C, 1, 0) +#define _MX6Q_PAD_GPIO_9__SRC_EARLY_RST \ + IOMUX_PAD(0x05F8, 0x0228, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_GPIO_3__ESAI1_HCKR \ + IOMUX_PAD(0x05FC, 0x022C, 0, 0x0864, 1, 0) +#define _MX6Q_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 \ + IOMUX_PAD(0x05FC, 0x022C, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_GPIO_3__I2C3_SCL \ + IOMUX_PAD(0x05FC, 0x022C, 2 | IOMUX_CONFIG_SION, 0x08A8, 1, 0) +#define _MX6Q_PAD_GPIO_3__ANATOP_ANATOP_24M_OUT \ + IOMUX_PAD(0x05FC, 0x022C, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_GPIO_3__CCM_CLKO2 \ + IOMUX_PAD(0x05FC, 0x022C, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_GPIO_3__GPIO_1_3 \ + IOMUX_PAD(0x05FC, 0x022C, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_GPIO_3__USBOH3_USBH1_OC \ + IOMUX_PAD(0x05FC, 0x022C, 6, 0x0948, 1, 0) +#define _MX6Q_PAD_GPIO_3__MLB_MLBCLK \ + IOMUX_PAD(0x05FC, 0x022C, 7, 0x0900, 1, 0) + +#define _MX6Q_PAD_GPIO_6__ESAI1_SCKT \ + IOMUX_PAD(0x0600, 0x0230, 0, 0x0870, 1, 0) +#ifdef CONFIG_MX6_ENET_IRQ_TO_GPIO +#define _MX6Q_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 \ + IOMUX_PAD(0x0600, 0x0230, 1 | IOMUX_CONFIG_SION, 0x0000, 0, 0) +#else +#define _MX6Q_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 \ + IOMUX_PAD(0x0600, 0x0230, 1, 0x0000, 0, 0) +#endif +#define _MX6Q_PAD_GPIO_6__I2C3_SDA \ + IOMUX_PAD(0x0600, 0x0230, 2 | IOMUX_CONFIG_SION, 0x08AC, 1, 0) +#define _MX6Q_PAD_GPIO_6__CCM_CCM_OUT_0 \ + IOMUX_PAD(0x0600, 0x0230, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_GPIO_6__CSU_CSU_INT_DEB \ + IOMUX_PAD(0x0600, 0x0230, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_GPIO_6__GPIO_1_6 \ + IOMUX_PAD(0x0600, 0x0230, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_GPIO_6__USDHC2_LCTL \ + IOMUX_PAD(0x0600, 0x0230, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_GPIO_6__MLB_MLBSIG \ + IOMUX_PAD(0x0600, 0x0230, 7, 0x0908, 1, 0) + +#define _MX6Q_PAD_GPIO_2__ESAI1_FST \ + IOMUX_PAD(0x0604, 0x0234, 0, 0x0860, 1, 0) +#define _MX6Q_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 \ + IOMUX_PAD(0x0604, 0x0234, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_GPIO_2__KPP_ROW_6 \ + IOMUX_PAD(0x0604, 0x0234, 2, 0x08F8, 1, 0) +#define _MX6Q_PAD_GPIO_2__CCM_CCM_OUT_1 \ + IOMUX_PAD(0x0604, 0x0234, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 \ + IOMUX_PAD(0x0604, 0x0234, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_GPIO_2__GPIO_1_2 \ + IOMUX_PAD(0x0604, 0x0234, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_GPIO_2__USDHC2_WP \ + IOMUX_PAD(0x0604, 0x0234, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_GPIO_2__MLB_MLBDAT \ + IOMUX_PAD(0x0604, 0x0234, 7, 0x0904, 1, 0) + +#define _MX6Q_PAD_GPIO_4__ESAI1_HCKT \ + IOMUX_PAD(0x0608, 0x0238, 0, 0x0868, 1, 0) +#define _MX6Q_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 \ + IOMUX_PAD(0x0608, 0x0238, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_GPIO_4__KPP_COL_7 \ + IOMUX_PAD(0x0608, 0x0238, 2, 0x08F0, 1, 0) +#define _MX6Q_PAD_GPIO_4__CCM_CCM_OUT_2 \ + IOMUX_PAD(0x0608, 0x0238, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 \ + IOMUX_PAD(0x0608, 0x0238, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_GPIO_4__GPIO_1_4 \ + IOMUX_PAD(0x0608, 0x0238, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_GPIO_4__USDHC2_CD \ + IOMUX_PAD(0x0608, 0x0238, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_GPIO_4__OCOTP_CTRL_WRAPPER_FUSE_LATCHED \ + IOMUX_PAD(0x0608, 0x0238, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_GPIO_5__ESAI1_TX2_RX3 \ + IOMUX_PAD(0x060C, 0x023C, 0, 0x087C, 1, 0) +#define _MX6Q_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 \ + IOMUX_PAD(0x060C, 0x023C, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_GPIO_5__KPP_ROW_7 \ + IOMUX_PAD(0x060C, 0x023C, 2, 0x08FC, 1, 0) +#define _MX6Q_PAD_GPIO_5__CCM_CLKO \ + IOMUX_PAD(0x060C, 0x023C, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 \ + IOMUX_PAD(0x060C, 0x023C, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_GPIO_5__GPIO_1_5 \ + IOMUX_PAD(0x060C, 0x023C, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_GPIO_5__I2C3_SCL \ + IOMUX_PAD(0x060C, 0x023C, 6 | IOMUX_CONFIG_SION, 0x08A8, 2, 0) +#define _MX6Q_PAD_GPIO_5__CHEETAH_EVENTI \ + IOMUX_PAD(0x060C, 0x023C, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_GPIO_7__ESAI1_TX4_RX1 \ + IOMUX_PAD(0x0610, 0x0240, 0, 0x0884, 1, 0) +#define _MX6Q_PAD_GPIO_7__ECSPI5_RDY \ + IOMUX_PAD(0x0610, 0x0240, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_GPIO_7__EPIT1_EPITO \ + IOMUX_PAD(0x0610, 0x0240, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_GPIO_7__CAN1_TXCAN \ + IOMUX_PAD(0x0610, 0x0240, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_GPIO_7__UART2_TXD \ + IOMUX_PAD(0x0610, 0x0240, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_GPIO_7__UART2_RXD \ + IOMUX_PAD(0x0610, 0x0240, 4, 0x0928, 2, 0) +#define _MX6Q_PAD_GPIO_7__GPIO_1_7 \ + IOMUX_PAD(0x0610, 0x0240, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_GPIO_7__SPDIF_PLOCK \ + IOMUX_PAD(0x0610, 0x0240, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_GPIO_7__USBOH3_OTGUSB_HOST_MODE \ + IOMUX_PAD(0x0610, 0x0240, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_GPIO_8__ESAI1_TX5_RX0 \ + IOMUX_PAD(0x0614, 0x0244, 0, 0x0888, 1, 0) +#define _MX6Q_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT \ + IOMUX_PAD(0x0614, 0x0244, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_GPIO_8__EPIT2_EPITO \ + IOMUX_PAD(0x0614, 0x0244, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_GPIO_8__CAN1_RXCAN \ + IOMUX_PAD(0x0614, 0x0244, 3, 0x07E4, 1, 0) +#define _MX6Q_PAD_GPIO_8__UART2_TXD \ + IOMUX_PAD(0x0614, 0x0244, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_GPIO_8__UART2_RXD \ + IOMUX_PAD(0x0614, 0x0244, 4, 0x0928, 3, 0) +#define _MX6Q_PAD_GPIO_8__GPIO_1_8 \ + IOMUX_PAD(0x0614, 0x0244, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_GPIO_8__SPDIF_SRCLK \ + IOMUX_PAD(0x0614, 0x0244, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_GPIO_8__USBOH3_OTGUSB_PWRCTL_WAKEUP \ + IOMUX_PAD(0x0614, 0x0244, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_GPIO_16__ESAI1_TX3_RX2 \ + IOMUX_PAD(0x0618, 0x0248, 0, 0x0880, 1, 0) +#define _MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN \ + IOMUX_PAD(0x0618, 0x0248, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT \ + IOMUX_PAD(0x0618, 0x0248, 0x12, 0x083C, 1, 0) +#define _MX6Q_PAD_GPIO_16__USDHC1_LCTL \ + IOMUX_PAD(0x0618, 0x0248, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_GPIO_16__SPDIF_IN1 \ + IOMUX_PAD(0x0618, 0x0248, 4, 0x0914, 3, 0) +#define _MX6Q_PAD_GPIO_16__GPIO_7_11 \ + IOMUX_PAD(0x0618, 0x0248, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_GPIO_16__I2C3_SDA \ + IOMUX_PAD(0x0618, 0x0248, 6 | IOMUX_CONFIG_SION, 0x08AC, 2, 0) +#define _MX6Q_PAD_GPIO_16__SJC_DE_B \ + IOMUX_PAD(0x0618, 0x0248, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_GPIO_17__ESAI1_TX0 \ + IOMUX_PAD(0x061C, 0x024C, 0, 0x0874, 0, 0) +#define _MX6Q_PAD_GPIO_17__ENET_1588_EVENT3_IN \ + IOMUX_PAD(0x061C, 0x024C, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_GPIO_17__CCM_PMIC_RDY \ + IOMUX_PAD(0x061C, 0x024C, 2, 0x07F0, 1, 0) +#define _MX6Q_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0 \ + IOMUX_PAD(0x061C, 0x024C, 3, 0x090C, 1, 0) +#define _MX6Q_PAD_GPIO_17__SPDIF_OUT1 \ + IOMUX_PAD(0x061C, 0x024C, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_GPIO_17__GPIO_7_12 \ + IOMUX_PAD(0x061C, 0x024C, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_GPIO_17__SJC_JTAG_ACT \ + IOMUX_PAD(0x061C, 0x024C, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_GPIO_18__ESAI1_TX1 \ + IOMUX_PAD(0x0620, 0x0250, 0, 0x0878, 0, 0) +#define _MX6Q_PAD_GPIO_18__ENET_RX_CLK \ + IOMUX_PAD(0x0620, 0x0250, 1, 0x0844, 1, 0) +#define _MX6Q_PAD_GPIO_18__USDHC3_VSELECT \ + IOMUX_PAD(0x0620, 0x0250, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1 \ + IOMUX_PAD(0x0620, 0x0250, 3, 0x0910, 1, 0) +#define _MX6Q_PAD_GPIO_18__ASRC_ASRC_EXT_CLK \ + IOMUX_PAD(0x0620, 0x0250, 4, 0x07B0, 2, 0) +#define _MX6Q_PAD_GPIO_18__GPIO_7_13 \ + IOMUX_PAD(0x0620, 0x0250, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_GPIO_18__SNVS_HP_WRAPPER_SNVS_VIO_5_CTL \ + IOMUX_PAD(0x0620, 0x0250, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_GPIO_18__SRC_SYSTEM_RST \ + IOMUX_PAD(0x0620, 0x0250, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_GPIO_19__KPP_COL_5 \ + IOMUX_PAD(0x0624, 0x0254, 0, 0x08E8, 1, 0) +#define _MX6Q_PAD_GPIO_19__ENET_1588_EVENT0_OUT \ + IOMUX_PAD(0x0624, 0x0254, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_GPIO_19__SPDIF_OUT1 \ + IOMUX_PAD(0x0624, 0x0254, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_GPIO_19__CCM_CLKO \ + IOMUX_PAD(0x0624, 0x0254, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_GPIO_19__ECSPI1_RDY \ + IOMUX_PAD(0x0624, 0x0254, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_GPIO_19__GPIO_4_5 \ + IOMUX_PAD(0x0624, 0x0254, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_GPIO_19__ENET_TX_ER \ + IOMUX_PAD(0x0624, 0x0254, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_GPIO_19__SRC_INT_BOOT \ + IOMUX_PAD(0x0624, 0x0254, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK \ + IOMUX_PAD(0x0628, 0x0258, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_PIXCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_12 \ + IOMUX_PAD(0x0628, 0x0258, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 \ + IOMUX_PAD(0x0628, 0x0258, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_PIXCLK__GPIO_5_18 \ + IOMUX_PAD(0x0628, 0x0258, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_PIXCLK__MMDC_MMDC_DEBUG_29 \ + IOMUX_PAD(0x0628, 0x0258, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_PIXCLK__CHEETAH_EVENTO \ + IOMUX_PAD(0x0628, 0x0258, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC \ + IOMUX_PAD(0x062C, 0x025C, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_MCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_13 \ + IOMUX_PAD(0x062C, 0x025C, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_MCLK__CCM_CLKO \ + IOMUX_PAD(0x062C, 0x025C, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 \ + IOMUX_PAD(0x062C, 0x025C, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_MCLK__GPIO_5_19 \ + IOMUX_PAD(0x062C, 0x025C, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30 \ + IOMUX_PAD(0x062C, 0x025C, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_MCLK__CHEETAH_TRCTL \ + IOMUX_PAD(0x062C, 0x025C, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN \ + IOMUX_PAD(0x0630, 0x0260, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0 \ + IOMUX_PAD(0x0630, 0x0260, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DATA_EN__PCIE_CTRL_DIAG_STATUS_BUS_MUX_14 \ + IOMUX_PAD(0x0630, 0x0260, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 \ + IOMUX_PAD(0x0630, 0x0260, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DATA_EN__GPIO_5_20 \ + IOMUX_PAD(0x0630, 0x0260, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DATA_EN__MMDC_MMDC_DEBUG_31 \ + IOMUX_PAD(0x0630, 0x0260, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DATA_EN__CHEETAH_TRCLK \ + IOMUX_PAD(0x0630, 0x0260, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC \ + IOMUX_PAD(0x0634, 0x0264, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_VSYNC__WEIM_WEIM_D_1 \ + IOMUX_PAD(0x0634, 0x0264, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_VSYNC__PCIE_CTRL_DIAG_STATUS_BUS_MUX_15 \ + IOMUX_PAD(0x0634, 0x0264, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 \ + IOMUX_PAD(0x0634, 0x0264, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_VSYNC__GPIO_5_21 \ + IOMUX_PAD(0x0634, 0x0264, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_VSYNC__MMDC_MMDC_DEBUG_32 \ + IOMUX_PAD(0x0634, 0x0264, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_VSYNC__CHEETAH_TRACE_0 \ + IOMUX_PAD(0x0634, 0x0264, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_CSI0_DAT4__IPU1_CSI0_D_4 \ + IOMUX_PAD(0x0638, 0x0268, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT4__WEIM_WEIM_D_2 \ + IOMUX_PAD(0x0638, 0x0268, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT4__ECSPI1_SCLK \ + IOMUX_PAD(0x0638, 0x0268, 2, 0x07F4, 3, 0) +#define _MX6Q_PAD_CSI0_DAT4__KPP_COL_5 \ + IOMUX_PAD(0x0638, 0x0268, 3, 0x08E8, 2, 0) +#define _MX6Q_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC \ + IOMUX_PAD(0x0638, 0x0268, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT4__GPIO_5_22 \ + IOMUX_PAD(0x0638, 0x0268, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT4__MMDC_MMDC_DEBUG_43 \ + IOMUX_PAD(0x0638, 0x0268, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT4__CHEETAH_TRACE_1 \ + IOMUX_PAD(0x0638, 0x0268, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_CSI0_DAT5__IPU1_CSI0_D_5 \ + IOMUX_PAD(0x063C, 0x026C, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT5__WEIM_WEIM_D_3 \ + IOMUX_PAD(0x063C, 0x026C, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT5__ECSPI1_MOSI \ + IOMUX_PAD(0x063C, 0x026C, 2, 0x07FC, 3, 0) +#define _MX6Q_PAD_CSI0_DAT5__KPP_ROW_5 \ + IOMUX_PAD(0x063C, 0x026C, 3, 0x08F4, 1, 0) +#define _MX6Q_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD \ + IOMUX_PAD(0x063C, 0x026C, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT5__GPIO_5_23 \ + IOMUX_PAD(0x063C, 0x026C, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44 \ + IOMUX_PAD(0x063C, 0x026C, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT5__CHEETAH_TRACE_2 \ + IOMUX_PAD(0x063C, 0x026C, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_CSI0_DAT6__IPU1_CSI0_D_6 \ + IOMUX_PAD(0x0640, 0x0270, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT6__WEIM_WEIM_D_4 \ + IOMUX_PAD(0x0640, 0x0270, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT6__ECSPI1_MISO \ + IOMUX_PAD(0x0640, 0x0270, 2, 0x07F8, 3, 0) +#define _MX6Q_PAD_CSI0_DAT6__KPP_COL_6 \ + IOMUX_PAD(0x0640, 0x0270, 3, 0x08EC, 1, 0) +#define _MX6Q_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS \ + IOMUX_PAD(0x0640, 0x0270, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT6__GPIO_5_24 \ + IOMUX_PAD(0x0640, 0x0270, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45 \ + IOMUX_PAD(0x0640, 0x0270, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT6__CHEETAH_TRACE_3 \ + IOMUX_PAD(0x0640, 0x0270, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_CSI0_DAT7__IPU1_CSI0_D_7 \ + IOMUX_PAD(0x0644, 0x0274, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT7__WEIM_WEIM_D_5 \ + IOMUX_PAD(0x0644, 0x0274, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT7__ECSPI1_SS0 \ + IOMUX_PAD(0x0644, 0x0274, 2, 0x0800, 3, 0) +#define _MX6Q_PAD_CSI0_DAT7__KPP_ROW_6 \ + IOMUX_PAD(0x0644, 0x0274, 3, 0x08F8, 2, 0) +#define _MX6Q_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD \ + IOMUX_PAD(0x0644, 0x0274, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT7__GPIO_5_25 \ + IOMUX_PAD(0x0644, 0x0274, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46 \ + IOMUX_PAD(0x0644, 0x0274, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT7__CHEETAH_TRACE_4 \ + IOMUX_PAD(0x0644, 0x0274, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_CSI0_DAT8__IPU1_CSI0_D_8 \ + IOMUX_PAD(0x0648, 0x0278, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT8__WEIM_WEIM_D_6 \ + IOMUX_PAD(0x0648, 0x0278, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT8__ECSPI2_SCLK \ + IOMUX_PAD(0x0648, 0x0278, 2, 0x0810, 2, 0) +#define _MX6Q_PAD_CSI0_DAT8__KPP_COL_7 \ + IOMUX_PAD(0x0648, 0x0278, 3, 0x08F0, 2, 0) +#define _MX6Q_PAD_CSI0_DAT8__I2C1_SDA \ + IOMUX_PAD(0x0648, 0x0278, 4 | IOMUX_CONFIG_SION, 0x089C, 1, 0) +#define _MX6Q_PAD_CSI0_DAT8__GPIO_5_26 \ + IOMUX_PAD(0x0648, 0x0278, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47 \ + IOMUX_PAD(0x0648, 0x0278, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT8__CHEETAH_TRACE_5 \ + IOMUX_PAD(0x0648, 0x0278, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_CSI0_DAT9__IPU1_CSI0_D_9 \ + IOMUX_PAD(0x064C, 0x027C, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT9__WEIM_WEIM_D_7 \ + IOMUX_PAD(0x064C, 0x027C, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT9__ECSPI2_MOSI \ + IOMUX_PAD(0x064C, 0x027C, 2, 0x0818, 2, 0) +#define _MX6Q_PAD_CSI0_DAT9__KPP_ROW_7 \ + IOMUX_PAD(0x064C, 0x027C, 3, 0x08FC, 2, 0) +#define _MX6Q_PAD_CSI0_DAT9__I2C1_SCL \ + IOMUX_PAD(0x064C, 0x027C, 4 | IOMUX_CONFIG_SION, 0x0898, 1, 0) +#define _MX6Q_PAD_CSI0_DAT9__GPIO_5_27 \ + IOMUX_PAD(0x064C, 0x027C, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48 \ + IOMUX_PAD(0x064C, 0x027C, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT9__CHEETAH_TRACE_6 \ + IOMUX_PAD(0x064C, 0x027C, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_D_10 \ + IOMUX_PAD(0x0650, 0x0280, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC \ + IOMUX_PAD(0x0650, 0x0280, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT10__ECSPI2_MISO \ + IOMUX_PAD(0x0650, 0x0280, 2, 0x0814, 2, 0) +#define _MX6Q_PAD_CSI0_DAT10__UART1_TXD \ + IOMUX_PAD(0x0650, 0x0280, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT10__UART1_RXD \ + IOMUX_PAD(0x0650, 0x0280, 3, 0x0920, 0, 0) +#define _MX6Q_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 \ + IOMUX_PAD(0x0650, 0x0280, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT10__GPIO_5_28 \ + IOMUX_PAD(0x0650, 0x0280, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33 \ + IOMUX_PAD(0x0650, 0x0280, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT10__CHEETAH_TRACE_7 \ + IOMUX_PAD(0x0650, 0x0280, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_D_11 \ + IOMUX_PAD(0x0654, 0x0284, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS \ + IOMUX_PAD(0x0654, 0x0284, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT11__ECSPI2_SS0 \ + IOMUX_PAD(0x0654, 0x0284, 2, 0x081C, 2, 0) +#define _MX6Q_PAD_CSI0_DAT11__UART1_TXD \ + IOMUX_PAD(0x0654, 0x0284, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT11__UART1_RXD \ + IOMUX_PAD(0x0654, 0x0284, 3, 0x0920, 1, 0) +#define _MX6Q_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 \ + IOMUX_PAD(0x0654, 0x0284, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT11__GPIO_5_29 \ + IOMUX_PAD(0x0654, 0x0284, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34 \ + IOMUX_PAD(0x0654, 0x0284, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT11__CHEETAH_TRACE_8 \ + IOMUX_PAD(0x0654, 0x0284, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_D_12 \ + IOMUX_PAD(0x0658, 0x0288, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT12__WEIM_WEIM_D_8 \ + IOMUX_PAD(0x0658, 0x0288, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT12__PCIE_CTRL_DIAG_STATUS_BUS_MUX_16 \ + IOMUX_PAD(0x0658, 0x0288, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT12__UART4_TXD \ + IOMUX_PAD(0x0658, 0x0288, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT12__UART4_RXD \ + IOMUX_PAD(0x0658, 0x0288, 3, 0x0938, 2, 0) +#define _MX6Q_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 \ + IOMUX_PAD(0x0658, 0x0288, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT12__GPIO_5_30 \ + IOMUX_PAD(0x0658, 0x0288, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35 \ + IOMUX_PAD(0x0658, 0x0288, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT12__CHEETAH_TRACE_9 \ + IOMUX_PAD(0x0658, 0x0288, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_D_13 \ + IOMUX_PAD(0x065C, 0x028C, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT13__WEIM_WEIM_D_9 \ + IOMUX_PAD(0x065C, 0x028C, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT13__PCIE_CTRL_DIAG_STATUS_BUS_MUX_17 \ + IOMUX_PAD(0x065C, 0x028C, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT13__UART4_TXD \ + IOMUX_PAD(0x065C, 0x028C, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT13__UART4_RXD \ + IOMUX_PAD(0x065C, 0x028C, 3, 0x0938, 3, 0) +#define _MX6Q_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 \ + IOMUX_PAD(0x065C, 0x028C, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT13__GPIO_5_31 \ + IOMUX_PAD(0x065C, 0x028C, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36 \ + IOMUX_PAD(0x065C, 0x028C, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT13__CHEETAH_TRACE_10 \ + IOMUX_PAD(0x065C, 0x028C, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_D_14 \ + IOMUX_PAD(0x0660, 0x0290, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT14__WEIM_WEIM_D_10 \ + IOMUX_PAD(0x0660, 0x0290, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT14__PCIE_CTRL_DIAG_STATUS_BUS_MUX_18 \ + IOMUX_PAD(0x0660, 0x0290, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT14__UART5_TXD \ + IOMUX_PAD(0x0660, 0x0290, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT14__UART5_RXD \ + IOMUX_PAD(0x0660, 0x0290, 3, 0x0940, 2, 0) +#define _MX6Q_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 \ + IOMUX_PAD(0x0660, 0x0290, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT14__GPIO_6_0 \ + IOMUX_PAD(0x0660, 0x0290, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37 \ + IOMUX_PAD(0x0660, 0x0290, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT14__CHEETAH_TRACE_11 \ + IOMUX_PAD(0x0660, 0x0290, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_D_15 \ + IOMUX_PAD(0x0664, 0x0294, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT15__WEIM_WEIM_D_11 \ + IOMUX_PAD(0x0664, 0x0294, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT15__PCIE_CTRL_DIAG_STATUS_BUS_MUX_19 \ + IOMUX_PAD(0x0664, 0x0294, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT15__UART5_TXD \ + IOMUX_PAD(0x0664, 0x0294, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT15__UART5_RXD \ + IOMUX_PAD(0x0664, 0x0294, 3, 0x0940, 3, 0) +#define _MX6Q_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 \ + IOMUX_PAD(0x0664, 0x0294, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT15__GPIO_6_1 \ + IOMUX_PAD(0x0664, 0x0294, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38 \ + IOMUX_PAD(0x0664, 0x0294, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT15__CHEETAH_TRACE_12 \ + IOMUX_PAD(0x0664, 0x0294, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_D_16 \ + IOMUX_PAD(0x0668, 0x0298, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT16__WEIM_WEIM_D_12 \ + IOMUX_PAD(0x0668, 0x0298, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT16__PCIE_CTRL_DIAG_STATUS_BUS_MUX_20 \ + IOMUX_PAD(0x0668, 0x0298, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT16__UART4_CTS \ + IOMUX_PAD(0x0668, 0x0298, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT16__UART4_RTS \ + IOMUX_PAD(0x0668, 0x0298, 3, 0x0934, 0, 0) +#define _MX6Q_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 \ + IOMUX_PAD(0x0668, 0x0298, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT16__GPIO_6_2 \ + IOMUX_PAD(0x0668, 0x0298, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39 \ + IOMUX_PAD(0x0668, 0x0298, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT16__CHEETAH_TRACE_13 \ + IOMUX_PAD(0x0668, 0x0298, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_D_17 \ + IOMUX_PAD(0x066C, 0x029C, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT17__WEIM_WEIM_D_13 \ + IOMUX_PAD(0x066C, 0x029C, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT17__PCIE_CTRL_DIAG_STATUS_BUS_MUX_21 \ + IOMUX_PAD(0x066C, 0x029C, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT17__UART4_CTS \ + IOMUX_PAD(0x066C, 0x029C, 3, 0x0934, 1, 0) +#define _MX6Q_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 \ + IOMUX_PAD(0x066C, 0x029C, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT17__GPIO_6_3 \ + IOMUX_PAD(0x066C, 0x029C, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40 \ + IOMUX_PAD(0x066C, 0x029C, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT17__CHEETAH_TRACE_14 \ + IOMUX_PAD(0x066C, 0x029C, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_D_18 \ + IOMUX_PAD(0x0670, 0x02A0, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT18__WEIM_WEIM_D_14 \ + IOMUX_PAD(0x0670, 0x02A0, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT18__PCIE_CTRL_DIAG_STATUS_BUS_MUX_22 \ + IOMUX_PAD(0x0670, 0x02A0, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT18__UART5_CTS \ + IOMUX_PAD(0x0670, 0x02A0, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT18__UART5_RTS \ + IOMUX_PAD(0x0670, 0x02A0, 3, 0x093C, 2, 0) +#define _MX6Q_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 \ + IOMUX_PAD(0x0670, 0x02A0, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT18__GPIO_6_4 \ + IOMUX_PAD(0x0670, 0x02A0, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41 \ + IOMUX_PAD(0x0670, 0x02A0, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT18__CHEETAH_TRACE_15 \ + IOMUX_PAD(0x0670, 0x02A0, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_D_19 \ + IOMUX_PAD(0x0674, 0x02A4, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT19__WEIM_WEIM_D_15 \ + IOMUX_PAD(0x0674, 0x02A4, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT19__PCIE_CTRL_DIAG_STATUS_BUS_MUX_23 \ + IOMUX_PAD(0x0674, 0x02A4, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT19__UART5_CTS \ + IOMUX_PAD(0x0674, 0x02A4, 3, 0x093C, 3, 0) +#define _MX6Q_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 \ + IOMUX_PAD(0x0674, 0x02A4, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT19__GPIO_6_5 \ + IOMUX_PAD(0x0674, 0x02A4, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42 \ + IOMUX_PAD(0x0674, 0x02A4, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_CSI0_DAT19__ANATOP_ANATOP_TESTO_9 \ + IOMUX_PAD(0x0674, 0x02A4, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_JTAG_TMS__SJC_TMS \ + IOMUX_PAD(0x0678, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_JTAG_MOD__SJC_MOD \ + IOMUX_PAD(0x067C, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_JTAG_TRSTB__SJC_TRSTB \ + IOMUX_PAD(0x0680, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_JTAG_TDI__SJC_TDI \ + IOMUX_PAD(0x0684, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_JTAG_TCK__SJC_TCK \ + IOMUX_PAD(0x0688, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_JTAG_TDO__SJC_TDO \ + IOMUX_PAD(0x068C, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_TAMPER__SNVS_LP_WRAPPER_SNVS_TD1 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_PMIC_ON_REQ__SNVS_LP_WRAPPER_SNVS_WAKEUP_ALARM \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_PMIC_STBY_REQ__CCM_PMIC_VSTBY_REQ \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_POR_B__SRC_POR_B \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_BOOT_MODE1__SRC_BOOT_MODE_1 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_RESET_IN_B__SRC_RESET_B \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_BOOT_MODE0__SRC_BOOT_MODE_0 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_TEST_MODE__TCU_TEST_MODE \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0) + +#define _MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 \ + IOMUX_PAD(0x0690, 0x02A8, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_SD3_DAT7__UART1_TXD \ + IOMUX_PAD(0x0690, 0x02A8, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_SD3_DAT7__UART1_RXD \ + IOMUX_PAD(0x0690, 0x02A8, 1, 0x0920, 2, 0) +#define _MX6Q_PAD_SD3_DAT7__PCIE_CTRL_DIAG_STATUS_BUS_MUX_24 \ + IOMUX_PAD(0x0690, 0x02A8, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0 \ + IOMUX_PAD(0x0690, 0x02A8, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0 \ + IOMUX_PAD(0x0690, 0x02A8, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_SD3_DAT7__GPIO_6_17 \ + IOMUX_PAD(0x0690, 0x02A8, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_SD3_DAT7__MIPI_CORE_DPHY_TEST_IN_12 \ + IOMUX_PAD(0x0690, 0x02A8, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_SD3_DAT7__ANATOP_USBPHY2_TSTO_PLL_CLK20DIV \ + IOMUX_PAD(0x0690, 0x02A8, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 \ + IOMUX_PAD(0x0694, 0x02AC, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_SD3_DAT6__UART1_TXD \ + IOMUX_PAD(0x0694, 0x02AC, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_SD3_DAT6__UART1_RXD \ + IOMUX_PAD(0x0694, 0x02AC, 1, 0x0920, 3, 0) +#define _MX6Q_PAD_SD3_DAT6__PCIE_CTRL_DIAG_STATUS_BUS_MUX_25 \ + IOMUX_PAD(0x0694, 0x02AC, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1 \ + IOMUX_PAD(0x0694, 0x02AC, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1 \ + IOMUX_PAD(0x0694, 0x02AC, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_SD3_DAT6__GPIO_6_18 \ + IOMUX_PAD(0x0694, 0x02AC, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_SD3_DAT6__MIPI_CORE_DPHY_TEST_IN_13 \ + IOMUX_PAD(0x0694, 0x02AC, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_SD3_DAT6__ANATOP_ANATOP_TESTO_10 \ + IOMUX_PAD(0x0694, 0x02AC, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 \ + IOMUX_PAD(0x0698, 0x02B0, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_SD3_DAT5__UART2_TXD \ + IOMUX_PAD(0x0698, 0x02B0, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_SD3_DAT5__UART2_RXD \ + IOMUX_PAD(0x0698, 0x02B0, 1, 0x0928, 4, 0) +#define _MX6Q_PAD_SD3_DAT5__PCIE_CTRL_DIAG_STATUS_BUS_MUX_26 \ + IOMUX_PAD(0x0698, 0x02B0, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2 \ + IOMUX_PAD(0x0698, 0x02B0, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2 \ + IOMUX_PAD(0x0698, 0x02B0, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_SD3_DAT5__GPIO_7_0 \ + IOMUX_PAD(0x0698, 0x02B0, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_SD3_DAT5__MIPI_CORE_DPHY_TEST_IN_14 \ + IOMUX_PAD(0x0698, 0x02B0, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_SD3_DAT5__ANATOP_ANATOP_TESTO_11 \ + IOMUX_PAD(0x0698, 0x02B0, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 \ + IOMUX_PAD(0x069C, 0x02B4, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_SD3_DAT4__UART2_TXD \ + IOMUX_PAD(0x069C, 0x02B4, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_SD3_DAT4__UART2_RXD \ + IOMUX_PAD(0x069C, 0x02B4, 1, 0x0928, 5, 0) +#define _MX6Q_PAD_SD3_DAT4__PCIE_CTRL_DIAG_STATUS_BUS_MUX_27 \ + IOMUX_PAD(0x069C, 0x02B4, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3 \ + IOMUX_PAD(0x069C, 0x02B4, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3 \ + IOMUX_PAD(0x069C, 0x02B4, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_SD3_DAT4__GPIO_7_1 \ + IOMUX_PAD(0x069C, 0x02B4, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_SD3_DAT4__MIPI_CORE_DPHY_TEST_IN_15 \ + IOMUX_PAD(0x069C, 0x02B4, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_SD3_DAT4__ANATOP_ANATOP_TESTO_12 \ + IOMUX_PAD(0x069C, 0x02B4, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_SD3_CMD__USDHC3_CMD \ + IOMUX_PAD(0x06A0, 0x02B8, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0) +#define _MX6Q_PAD_SD3_CMD__UART2_CTS \ + IOMUX_PAD(0x06A0, 0x02B8, 1, 0x0924, 2, 0) +#define _MX6Q_PAD_SD3_CMD__CAN1_TXCAN \ + IOMUX_PAD(0x06A0, 0x02B8, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4 \ + IOMUX_PAD(0x06A0, 0x02B8, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4 \ + IOMUX_PAD(0x06A0, 0x02B8, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_SD3_CMD__GPIO_7_2 \ + IOMUX_PAD(0x06A0, 0x02B8, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_SD3_CMD__MIPI_CORE_DPHY_TEST_IN_16 \ + IOMUX_PAD(0x06A0, 0x02B8, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_SD3_CMD__ANATOP_ANATOP_TESTO_13 \ + IOMUX_PAD(0x06A0, 0x02B8, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_SD3_CLK__USDHC3_CLK \ + IOMUX_PAD(0x06A4, 0x02BC, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_SD3_CLK__UART2_CTS \ + IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_SD3_CLK__UART2_RTS \ + IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0924, 3, 0) +#define _MX6Q_PAD_SD3_CLK__CAN1_RXCAN \ + IOMUX_PAD(0x06A4, 0x02BC, 2, 0x07E4, 2, 0) +#define _MX6Q_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5 \ + IOMUX_PAD(0x06A4, 0x02BC, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5 \ + IOMUX_PAD(0x06A4, 0x02BC, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_SD3_CLK__GPIO_7_3 \ + IOMUX_PAD(0x06A4, 0x02BC, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_SD3_CLK__MIPI_CORE_DPHY_TEST_IN_17 \ + IOMUX_PAD(0x06A4, 0x02BC, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_SD3_CLK__ANATOP_ANATOP_TESTO_14 \ + IOMUX_PAD(0x06A4, 0x02BC, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 \ + IOMUX_PAD(0x06A8, 0x02C0, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_SD3_DAT0__UART1_CTS \ + IOMUX_PAD(0x06A8, 0x02C0, 1, 0x091C, 2, 0) +#define _MX6Q_PAD_SD3_DAT0__CAN2_TXCAN \ + IOMUX_PAD(0x06A8, 0x02C0, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6 \ + IOMUX_PAD(0x06A8, 0x02C0, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6 \ + IOMUX_PAD(0x06A8, 0x02C0, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_SD3_DAT0__GPIO_7_4 \ + IOMUX_PAD(0x06A8, 0x02C0, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_SD3_DAT0__MIPI_CORE_DPHY_TEST_IN_18 \ + IOMUX_PAD(0x06A8, 0x02C0, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_SD3_DAT0__ANATOP_ANATOP_TESTO_15 \ + IOMUX_PAD(0x06A8, 0x02C0, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 \ + IOMUX_PAD(0x06AC, 0x02C4, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_SD3_DAT1__UART1_CTS \ + IOMUX_PAD(0x06AC, 0x02C4, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_SD3_DAT1__UART1_RTS \ + IOMUX_PAD(0x06AC, 0x02C4, 1, 0x091C, 3, 0) +#define _MX6Q_PAD_SD3_DAT1__CAN2_RXCAN \ + IOMUX_PAD(0x06AC, 0x02C4, 2, 0x07E8, 1, 0) +#define _MX6Q_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7 \ + IOMUX_PAD(0x06AC, 0x02C4, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7 \ + IOMUX_PAD(0x06AC, 0x02C4, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_SD3_DAT1__GPIO_7_5 \ + IOMUX_PAD(0x06AC, 0x02C4, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_SD3_DAT1__MIPI_CORE_DPHY_TEST_IN_19 \ + IOMUX_PAD(0x06AC, 0x02C4, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_SD3_DAT1__ANATOP_ANATOP_TESTI_0 \ + IOMUX_PAD(0x06AC, 0x02C4, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 \ + IOMUX_PAD(0x06B0, 0x02C8, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_SD3_DAT2__PCIE_CTRL_DIAG_STATUS_BUS_MUX_28 \ + IOMUX_PAD(0x06B0, 0x02C8, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8 \ + IOMUX_PAD(0x06B0, 0x02C8, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8 \ + IOMUX_PAD(0x06B0, 0x02C8, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_SD3_DAT2__GPIO_7_6 \ + IOMUX_PAD(0x06B0, 0x02C8, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_SD3_DAT2__MIPI_CORE_DPHY_TEST_IN_20 \ + IOMUX_PAD(0x06B0, 0x02C8, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_SD3_DAT2__ANATOP_ANATOP_TESTI_1 \ + IOMUX_PAD(0x06B0, 0x02C8, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 \ + IOMUX_PAD(0x06B4, 0x02CC, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_SD3_DAT3__UART3_CTS \ + IOMUX_PAD(0x06B4, 0x02CC, 1, 0x092C, 4, 0) +#define _MX6Q_PAD_SD3_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_29 \ + IOMUX_PAD(0x06B4, 0x02CC, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9 \ + IOMUX_PAD(0x06B4, 0x02CC, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9 \ + IOMUX_PAD(0x06B4, 0x02CC, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_SD3_DAT3__GPIO_7_7 \ + IOMUX_PAD(0x06B4, 0x02CC, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_SD3_DAT3__MIPI_CORE_DPHY_TEST_IN_21 \ + IOMUX_PAD(0x06B4, 0x02CC, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_SD3_DAT3__ANATOP_ANATOP_TESTI_2 \ + IOMUX_PAD(0x06B4, 0x02CC, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_SD3_RST__USDHC3_RST \ + IOMUX_PAD(0x06B8, 0x02D0, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_SD3_RST__UART3_CTS \ + IOMUX_PAD(0x06B8, 0x02D0, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_SD3_RST__UART3_RTS \ + IOMUX_PAD(0x06B8, 0x02D0, 1, 0x092C, 5, 0) +#define _MX6Q_PAD_SD3_RST__PCIE_CTRL_DIAG_STATUS_BUS_MUX_30 \ + IOMUX_PAD(0x06B8, 0x02D0, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10 \ + IOMUX_PAD(0x06B8, 0x02D0, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10 \ + IOMUX_PAD(0x06B8, 0x02D0, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_SD3_RST__GPIO_7_8 \ + IOMUX_PAD(0x06B8, 0x02D0, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_SD3_RST__MIPI_CORE_DPHY_TEST_IN_22 \ + IOMUX_PAD(0x06B8, 0x02D0, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3 \ + IOMUX_PAD(0x06B8, 0x02D0, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_NANDF_CLE__RAWNAND_CLE \ + IOMUX_PAD(0x06BC, 0x02D4, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_CLE__IPU2_SISG_4 \ + IOMUX_PAD(0x06BC, 0x02D4, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_CLE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_31 \ + IOMUX_PAD(0x06BC, 0x02D4, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_CLE__USBOH3_UH3_DFD_OUT_11 \ + IOMUX_PAD(0x06BC, 0x02D4, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_CLE__USBOH3_UH2_DFD_OUT_11 \ + IOMUX_PAD(0x06BC, 0x02D4, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_CLE__GPIO_6_7 \ + IOMUX_PAD(0x06BC, 0x02D4, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_CLE__MIPI_CORE_DPHY_TEST_IN_23 \ + IOMUX_PAD(0x06BC, 0x02D4, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_CLE__TPSMP_HTRANS_0 \ + IOMUX_PAD(0x06BC, 0x02D4, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_NANDF_ALE__RAWNAND_ALE \ + IOMUX_PAD(0x06C0, 0x02D8, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_ALE__USDHC4_RST \ + IOMUX_PAD(0x06C0, 0x02D8, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_ALE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_0 \ + IOMUX_PAD(0x06C0, 0x02D8, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_ALE__USBOH3_UH3_DFD_OUT_12 \ + IOMUX_PAD(0x06C0, 0x02D8, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_ALE__USBOH3_UH2_DFD_OUT_12 \ + IOMUX_PAD(0x06C0, 0x02D8, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_ALE__GPIO_6_8 \ + IOMUX_PAD(0x06C0, 0x02D8, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_ALE__MIPI_CORE_DPHY_TEST_IN_24 \ + IOMUX_PAD(0x06C0, 0x02D8, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_ALE__TPSMP_HTRANS_1 \ + IOMUX_PAD(0x06C0, 0x02D8, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN \ + IOMUX_PAD(0x06C4, 0x02DC, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_WP_B__IPU2_SISG_5 \ + IOMUX_PAD(0x06C4, 0x02DC, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_WP_B__PCIE_CTRL_DIAG_STATUS_BUS_MUX_1 \ + IOMUX_PAD(0x06C4, 0x02DC, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_WP_B__USBOH3_UH3_DFD_OUT_13 \ + IOMUX_PAD(0x06C4, 0x02DC, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_WP_B__USBOH3_UH2_DFD_OUT_13 \ + IOMUX_PAD(0x06C4, 0x02DC, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_WP_B__GPIO_6_9 \ + IOMUX_PAD(0x06C4, 0x02DC, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_WP_B__MIPI_CORE_DPHY_TEST_OUT_32 \ + IOMUX_PAD(0x06C4, 0x02DC, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_WP_B__PL301_MX6QPER1_HSIZE_0 \ + IOMUX_PAD(0x06C4, 0x02DC, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 \ + IOMUX_PAD(0x06C8, 0x02E0, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_RB0__IPU2_DI0_PIN1 \ + IOMUX_PAD(0x06C8, 0x02E0, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_RB0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_2 \ + IOMUX_PAD(0x06C8, 0x02E0, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_RB0__USBOH3_UH3_DFD_OUT_14 \ + IOMUX_PAD(0x06C8, 0x02E0, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_RB0__USBOH3_UH2_DFD_OUT_14 \ + IOMUX_PAD(0x06C8, 0x02E0, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_RB0__GPIO_6_10 \ + IOMUX_PAD(0x06C8, 0x02E0, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_RB0__MIPI_CORE_DPHY_TEST_OUT_33 \ + IOMUX_PAD(0x06C8, 0x02E0, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_RB0__PL301_MX6QPER1_HSIZE_1 \ + IOMUX_PAD(0x06C8, 0x02E0, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N \ + IOMUX_PAD(0x06CC, 0x02E4, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_CS0__USBOH3_UH3_DFD_OUT_15 \ + IOMUX_PAD(0x06CC, 0x02E4, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_CS0__USBOH3_UH2_DFD_OUT_15 \ + IOMUX_PAD(0x06CC, 0x02E4, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_CS0__GPIO_6_11 \ + IOMUX_PAD(0x06CC, 0x02E4, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_CS0__PL301_MX6QPER1_HSIZE_2 \ + IOMUX_PAD(0x06CC, 0x02E4, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N \ + IOMUX_PAD(0x06D0, 0x02E8, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_CS1__USDHC4_VSELECT \ + IOMUX_PAD(0x06D0, 0x02E8, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_CS1__USDHC3_VSELECT \ + IOMUX_PAD(0x06D0, 0x02E8, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_CS1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_3 \ + IOMUX_PAD(0x06D0, 0x02E8, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_CS1__GPIO_6_14 \ + IOMUX_PAD(0x06D0, 0x02E8, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_CS1__PL301_MX6QPER1_HREADYOUT \ + IOMUX_PAD(0x06D0, 0x02E8, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N \ + IOMUX_PAD(0x06D4, 0x02EC, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_CS2__IPU1_SISG_0 \ + IOMUX_PAD(0x06D4, 0x02EC, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_CS2__ESAI1_TX0 \ + IOMUX_PAD(0x06D4, 0x02EC, 2, 0x0874, 1, 0) +#define _MX6Q_PAD_NANDF_CS2__WEIM_WEIM_CRE \ + IOMUX_PAD(0x06D4, 0x02EC, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_CS2__CCM_CLKO2 \ + IOMUX_PAD(0x06D4, 0x02EC, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_CS2__GPIO_6_15 \ + IOMUX_PAD(0x06D4, 0x02EC, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_CS2__IPU2_SISG_0 \ + IOMUX_PAD(0x06D4, 0x02EC, 6, 0x0000, 0, 0) + +#define _MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N \ + IOMUX_PAD(0x06D8, 0x02F0, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_CS3__IPU1_SISG_1 \ + IOMUX_PAD(0x06D8, 0x02F0, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_CS3__ESAI1_TX1 \ + IOMUX_PAD(0x06D8, 0x02F0, 2, 0x0878, 1, 0) +#define _MX6Q_PAD_NANDF_CS3__WEIM_WEIM_A_26 \ + IOMUX_PAD(0x06D8, 0x02F0, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_CS3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_4 \ + IOMUX_PAD(0x06D8, 0x02F0, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_CS3__GPIO_6_16 \ + IOMUX_PAD(0x06D8, 0x02F0, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_CS3__IPU2_SISG_1 \ + IOMUX_PAD(0x06D8, 0x02F0, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_CS3__TPSMP_CLK \ + IOMUX_PAD(0x06D8, 0x02F0, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_SD4_CMD__USDHC4_CMD \ + IOMUX_PAD(0x06DC, 0x02F4, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0) +#define _MX6Q_PAD_SD4_CMD__RAWNAND_RDN \ + IOMUX_PAD(0x06DC, 0x02F4, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_SD4_CMD__UART3_TXD \ + IOMUX_PAD(0x06DC, 0x02F4, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_SD4_CMD__UART3_RXD \ + IOMUX_PAD(0x06DC, 0x02F4, 2, 0x0930, 2, 0) +#define _MX6Q_PAD_SD4_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_5 \ + IOMUX_PAD(0x06DC, 0x02F4, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_SD4_CMD__GPIO_7_9 \ + IOMUX_PAD(0x06DC, 0x02F4, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_SD4_CMD__TPSMP_HDATA_DIR \ + IOMUX_PAD(0x06DC, 0x02F4, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_SD4_CLK__USDHC4_CLK \ + IOMUX_PAD(0x06E0, 0x02F8, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_SD4_CLK__RAWNAND_WRN \ + IOMUX_PAD(0x06E0, 0x02F8, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_SD4_CLK__UART3_TXD \ + IOMUX_PAD(0x06E0, 0x02F8, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_SD4_CLK__UART3_RXD \ + IOMUX_PAD(0x06E0, 0x02F8, 2, 0x0930, 3, 0) +#define _MX6Q_PAD_SD4_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_6 \ + IOMUX_PAD(0x06E0, 0x02F8, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_SD4_CLK__GPIO_7_10 \ + IOMUX_PAD(0x06E0, 0x02F8, 5, 0x0000, 0, 0) + +#define _MX6Q_PAD_NANDF_D0__RAWNAND_D0 \ + IOMUX_PAD(0x06E4, 0x02FC, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_D0__USDHC1_DAT4 \ + IOMUX_PAD(0x06E4, 0x02FC, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_D0__GPU3D_GPU_DEBUG_OUT_0 \ + IOMUX_PAD(0x06E4, 0x02FC, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT_16 \ + IOMUX_PAD(0x06E4, 0x02FC, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT_16 \ + IOMUX_PAD(0x06E4, 0x02FC, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_D0__GPIO_2_0 \ + IOMUX_PAD(0x06E4, 0x02FC, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0 \ + IOMUX_PAD(0x06E4, 0x02FC, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_D0__IPU2_IPU_DIAG_BUS_0 \ + IOMUX_PAD(0x06E4, 0x02FC, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_NANDF_D1__RAWNAND_D1 \ + IOMUX_PAD(0x06E8, 0x0300, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_D1__USDHC1_DAT5 \ + IOMUX_PAD(0x06E8, 0x0300, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT_1 \ + IOMUX_PAD(0x06E8, 0x0300, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT_17 \ + IOMUX_PAD(0x06E8, 0x0300, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT_17 \ + IOMUX_PAD(0x06E8, 0x0300, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_D1__GPIO_2_1 \ + IOMUX_PAD(0x06E8, 0x0300, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1 \ + IOMUX_PAD(0x06E8, 0x0300, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_D1__IPU2_IPU_DIAG_BUS_1 \ + IOMUX_PAD(0x06E8, 0x0300, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_NANDF_D2__RAWNAND_D2 \ + IOMUX_PAD(0x06EC, 0x0304, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_D2__USDHC1_DAT6 \ + IOMUX_PAD(0x06EC, 0x0304, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_D2__GPU3D_GPU_DEBUG_OUT_2 \ + IOMUX_PAD(0x06EC, 0x0304, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT_18 \ + IOMUX_PAD(0x06EC, 0x0304, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT_18 \ + IOMUX_PAD(0x06EC, 0x0304, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_D2__GPIO_2_2 \ + IOMUX_PAD(0x06EC, 0x0304, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2 \ + IOMUX_PAD(0x06EC, 0x0304, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_D2__IPU2_IPU_DIAG_BUS_2 \ + IOMUX_PAD(0x06EC, 0x0304, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_NANDF_D3__RAWNAND_D3 \ + IOMUX_PAD(0x06F0, 0x0308, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_D3__USDHC1_DAT7 \ + IOMUX_PAD(0x06F0, 0x0308, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_D3__GPU3D_GPU_DEBUG_OUT_3 \ + IOMUX_PAD(0x06F0, 0x0308, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT_19 \ + IOMUX_PAD(0x06F0, 0x0308, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT_19 \ + IOMUX_PAD(0x06F0, 0x0308, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_D3__GPIO_2_3 \ + IOMUX_PAD(0x06F0, 0x0308, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3 \ + IOMUX_PAD(0x06F0, 0x0308, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_D3__IPU2_IPU_DIAG_BUS_3 \ + IOMUX_PAD(0x06F0, 0x0308, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_NANDF_D4__RAWNAND_D4 \ + IOMUX_PAD(0x06F4, 0x030C, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_D4__USDHC2_DAT4 \ + IOMUX_PAD(0x06F4, 0x030C, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_D4__GPU3D_GPU_DEBUG_OUT_4 \ + IOMUX_PAD(0x06F4, 0x030C, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT_20 \ + IOMUX_PAD(0x06F4, 0x030C, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT_20 \ + IOMUX_PAD(0x06F4, 0x030C, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_D4__GPIO_2_4 \ + IOMUX_PAD(0x06F4, 0x030C, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4 \ + IOMUX_PAD(0x06F4, 0x030C, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_D4__IPU2_IPU_DIAG_BUS_4 \ + IOMUX_PAD(0x06F4, 0x030C, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_NANDF_D5__RAWNAND_D5 \ + IOMUX_PAD(0x06F8, 0x0310, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_D5__USDHC2_DAT5 \ + IOMUX_PAD(0x06F8, 0x0310, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_D5__GPU3D_GPU_DEBUG_OUT_5 \ + IOMUX_PAD(0x06F8, 0x0310, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT_21 \ + IOMUX_PAD(0x06F8, 0x0310, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT_21 \ + IOMUX_PAD(0x06F8, 0x0310, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_D5__GPIO_2_5 \ + IOMUX_PAD(0x06F8, 0x0310, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5 \ + IOMUX_PAD(0x06F8, 0x0310, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_D5__IPU2_IPU_DIAG_BUS_5 \ + IOMUX_PAD(0x06F8, 0x0310, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_NANDF_D6__RAWNAND_D6 \ + IOMUX_PAD(0x06FC, 0x0314, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_D6__USDHC2_DAT6 \ + IOMUX_PAD(0x06FC, 0x0314, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_D6__GPU3D_GPU_DEBUG_OUT_6 \ + IOMUX_PAD(0x06FC, 0x0314, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT_22 \ + IOMUX_PAD(0x06FC, 0x0314, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT_22 \ + IOMUX_PAD(0x06FC, 0x0314, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_D6__GPIO_2_6 \ + IOMUX_PAD(0x06FC, 0x0314, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6 \ + IOMUX_PAD(0x06FC, 0x0314, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_D6__IPU2_IPU_DIAG_BUS_6 \ + IOMUX_PAD(0x06FC, 0x0314, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_NANDF_D7__RAWNAND_D7 \ + IOMUX_PAD(0x0700, 0x0318, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_D7__USDHC2_DAT7 \ + IOMUX_PAD(0x0700, 0x0318, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_D7__GPU3D_GPU_DEBUG_OUT_7 \ + IOMUX_PAD(0x0700, 0x0318, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT_23 \ + IOMUX_PAD(0x0700, 0x0318, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT_23 \ + IOMUX_PAD(0x0700, 0x0318, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_D7__GPIO_2_7 \ + IOMUX_PAD(0x0700, 0x0318, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7 \ + IOMUX_PAD(0x0700, 0x0318, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_NANDF_D7__IPU2_IPU_DIAG_BUS_7 \ + IOMUX_PAD(0x0700, 0x0318, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_SD4_DAT0__RAWNAND_D8 \ + IOMUX_PAD(0x0704, 0x031C, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 \ + IOMUX_PAD(0x0704, 0x031C, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_SD4_DAT0__RAWNAND_DQS \ + IOMUX_PAD(0x0704, 0x031C, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT_24 \ + IOMUX_PAD(0x0704, 0x031C, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT_24 \ + IOMUX_PAD(0x0704, 0x031C, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_SD4_DAT0__GPIO_2_8 \ + IOMUX_PAD(0x0704, 0x031C, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8 \ + IOMUX_PAD(0x0704, 0x031C, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_SD4_DAT0__IPU2_IPU_DIAG_BUS_8 \ + IOMUX_PAD(0x0704, 0x031C, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_SD4_DAT1__RAWNAND_D9 \ + IOMUX_PAD(0x0708, 0x0320, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 \ + IOMUX_PAD(0x0708, 0x0320, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_SD4_DAT1__PWM3_PWMO \ + IOMUX_PAD(0x0708, 0x0320, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT_25 \ + IOMUX_PAD(0x0708, 0x0320, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT_25 \ + IOMUX_PAD(0x0708, 0x0320, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_SD4_DAT1__GPIO_2_9 \ + IOMUX_PAD(0x0708, 0x0320, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9 \ + IOMUX_PAD(0x0708, 0x0320, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_SD4_DAT1__IPU2_IPU_DIAG_BUS_9 \ + IOMUX_PAD(0x0708, 0x0320, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_SD4_DAT2__RAWNAND_D10 \ + IOMUX_PAD(0x070C, 0x0324, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 \ + IOMUX_PAD(0x070C, 0x0324, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_SD4_DAT2__PWM4_PWMO \ + IOMUX_PAD(0x070C, 0x0324, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT_26 \ + IOMUX_PAD(0x070C, 0x0324, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT_26 \ + IOMUX_PAD(0x070C, 0x0324, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_SD4_DAT2__GPIO_2_10 \ + IOMUX_PAD(0x070C, 0x0324, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10 \ + IOMUX_PAD(0x070C, 0x0324, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_SD4_DAT2__IPU2_IPU_DIAG_BUS_10 \ + IOMUX_PAD(0x070C, 0x0324, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_SD4_DAT3__RAWNAND_D11 \ + IOMUX_PAD(0x0710, 0x0328, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 \ + IOMUX_PAD(0x0710, 0x0328, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT_27 \ + IOMUX_PAD(0x0710, 0x0328, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT_27 \ + IOMUX_PAD(0x0710, 0x0328, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_SD4_DAT3__GPIO_2_11 \ + IOMUX_PAD(0x0710, 0x0328, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11 \ + IOMUX_PAD(0x0710, 0x0328, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_SD4_DAT3__IPU2_IPU_DIAG_BUS_11 \ + IOMUX_PAD(0x0710, 0x0328, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_SD4_DAT4__RAWNAND_D12 \ + IOMUX_PAD(0x0714, 0x032C, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 \ + IOMUX_PAD(0x0714, 0x032C, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_SD4_DAT4__UART2_TXD \ + IOMUX_PAD(0x0714, 0x032C, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_SD4_DAT4__UART2_RXD \ + IOMUX_PAD(0x0714, 0x032C, 2, 0x0928, 6, 0) +#define _MX6Q_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT_28 \ + IOMUX_PAD(0x0714, 0x032C, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT_28 \ + IOMUX_PAD(0x0714, 0x032C, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_SD4_DAT4__GPIO_2_12 \ + IOMUX_PAD(0x0714, 0x032C, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12 \ + IOMUX_PAD(0x0714, 0x032C, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_SD4_DAT4__IPU2_IPU_DIAG_BUS_12 \ + IOMUX_PAD(0x0714, 0x032C, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_SD4_DAT5__RAWNAND_D13 \ + IOMUX_PAD(0x0718, 0x0330, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 \ + IOMUX_PAD(0x0718, 0x0330, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_SD4_DAT5__UART2_CTS \ + IOMUX_PAD(0x0718, 0x0330, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_SD4_DAT5__UART2_RTS \ + IOMUX_PAD(0x0718, 0x0330, 2, 0x0924, 4, 0) +#define _MX6Q_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT_29 \ + IOMUX_PAD(0x0718, 0x0330, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT_29 \ + IOMUX_PAD(0x0718, 0x0330, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_SD4_DAT5__GPIO_2_13 \ + IOMUX_PAD(0x0718, 0x0330, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13 \ + IOMUX_PAD(0x0718, 0x0330, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_SD4_DAT5__IPU2_IPU_DIAG_BUS_13 \ + IOMUX_PAD(0x0718, 0x0330, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_SD4_DAT6__RAWNAND_D14 \ + IOMUX_PAD(0x071C, 0x0334, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 \ + IOMUX_PAD(0x071C, 0x0334, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_SD4_DAT6__UART2_CTS \ + IOMUX_PAD(0x071C, 0x0334, 2, 0x0924, 5, 0) +#define _MX6Q_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT_30 \ + IOMUX_PAD(0x071C, 0x0334, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT_30 \ + IOMUX_PAD(0x071C, 0x0334, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_SD4_DAT6__GPIO_2_14 \ + IOMUX_PAD(0x071C, 0x0334, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14 \ + IOMUX_PAD(0x071C, 0x0334, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_SD4_DAT6__IPU2_IPU_DIAG_BUS_14 \ + IOMUX_PAD(0x071C, 0x0334, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_SD4_DAT7__RAWNAND_D15 \ + IOMUX_PAD(0x0720, 0x0338, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 \ + IOMUX_PAD(0x0720, 0x0338, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_SD4_DAT7__UART2_TXD \ + IOMUX_PAD(0x0720, 0x0338, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_SD4_DAT7__UART2_RXD \ + IOMUX_PAD(0x0720, 0x0338, 2, 0x0928, 7, 0) +#define _MX6Q_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT_31 \ + IOMUX_PAD(0x0720, 0x0338, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT_31 \ + IOMUX_PAD(0x0720, 0x0338, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_SD4_DAT7__GPIO_2_15 \ + IOMUX_PAD(0x0720, 0x0338, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15 \ + IOMUX_PAD(0x0720, 0x0338, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_SD4_DAT7__IPU2_IPU_DIAG_BUS_15 \ + IOMUX_PAD(0x0720, 0x0338, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_SD1_DAT1__USDHC1_DAT1 \ + IOMUX_PAD(0x0724, 0x033C, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_SD1_DAT1__ECSPI5_SS0 \ + IOMUX_PAD(0x0724, 0x033C, 1, 0x0834, 1, 0) +#define _MX6Q_PAD_SD1_DAT1__PWM3_PWMO \ + IOMUX_PAD(0x0724, 0x033C, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_SD1_DAT1__GPT_CAPIN2 \ + IOMUX_PAD(0x0724, 0x033C, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_SD1_DAT1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_7 \ + IOMUX_PAD(0x0724, 0x033C, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_SD1_DAT1__GPIO_1_17 \ + IOMUX_PAD(0x0724, 0x033C, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0 \ + IOMUX_PAD(0x0724, 0x033C, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_SD1_DAT1__ANATOP_ANATOP_TESTO_8 \ + IOMUX_PAD(0x0724, 0x033C, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_SD1_DAT0__USDHC1_DAT0 \ + IOMUX_PAD(0x0728, 0x0340, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_SD1_DAT0__ECSPI5_MISO \ + IOMUX_PAD(0x0728, 0x0340, 1, 0x082C, 1, 0) +#define _MX6Q_PAD_SD1_DAT0__CAAM_WRAPPER_RNG_OSC_OBS \ + IOMUX_PAD(0x0728, 0x0340, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_SD1_DAT0__GPT_CAPIN1 \ + IOMUX_PAD(0x0728, 0x0340, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_SD1_DAT0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_8 \ + IOMUX_PAD(0x0728, 0x0340, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_SD1_DAT0__GPIO_1_16 \ + IOMUX_PAD(0x0728, 0x0340, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1 \ + IOMUX_PAD(0x0728, 0x0340, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_SD1_DAT0__ANATOP_ANATOP_TESTO_7 \ + IOMUX_PAD(0x0728, 0x0340, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_SD1_DAT3__USDHC1_DAT3 \ + IOMUX_PAD(0x072C, 0x0344, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_SD1_DAT3__ECSPI5_SS2 \ + IOMUX_PAD(0x072C, 0x0344, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_SD1_DAT3__GPT_CMPOUT3 \ + IOMUX_PAD(0x072C, 0x0344, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_SD1_DAT3__PWM1_PWMO \ + IOMUX_PAD(0x072C, 0x0344, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_B \ + IOMUX_PAD(0x072C, 0x0344, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_SD1_DAT3__GPIO_1_21 \ + IOMUX_PAD(0x072C, 0x0344, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB \ + IOMUX_PAD(0x072C, 0x0344, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_SD1_DAT3__ANATOP_ANATOP_TESTO_6 \ + IOMUX_PAD(0x072C, 0x0344, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_SD1_CMD__USDHC1_CMD \ + IOMUX_PAD(0x0730, 0x0348, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0) +#define _MX6Q_PAD_SD1_CMD__ECSPI5_MOSI \ + IOMUX_PAD(0x0730, 0x0348, 1, 0x0830, 0, 0) +#define _MX6Q_PAD_SD1_CMD__PWM4_PWMO \ + IOMUX_PAD(0x0730, 0x0348, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_SD1_CMD__GPT_CMPOUT1 \ + IOMUX_PAD(0x0730, 0x0348, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_SD1_CMD__GPIO_1_18 \ + IOMUX_PAD(0x0730, 0x0348, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_SD1_CMD__ANATOP_ANATOP_TESTO_5 \ + IOMUX_PAD(0x0730, 0x0348, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_SD1_DAT2__USDHC1_DAT2 \ + IOMUX_PAD(0x0734, 0x034C, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_SD1_DAT2__ECSPI5_SS1 \ + IOMUX_PAD(0x0734, 0x034C, 1, 0x0838, 1, 0) +#define _MX6Q_PAD_SD1_DAT2__GPT_CMPOUT2 \ + IOMUX_PAD(0x0734, 0x034C, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_SD1_DAT2__PWM2_PWMO \ + IOMUX_PAD(0x0734, 0x034C, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_B \ + IOMUX_PAD(0x0734, 0x034C, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_SD1_DAT2__GPIO_1_19 \ + IOMUX_PAD(0x0734, 0x034C, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB \ + IOMUX_PAD(0x0734, 0x034C, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_SD1_DAT2__ANATOP_ANATOP_TESTO_4 \ + IOMUX_PAD(0x0734, 0x034C, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_SD1_CLK__USDHC1_CLK \ + IOMUX_PAD(0x0738, 0x0350, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_SD1_CLK__ECSPI5_SCLK \ + IOMUX_PAD(0x0738, 0x0350, 1, 0x0828, 0, 0) +#define _MX6Q_PAD_SD1_CLK__OSC32K_32K_OUT \ + IOMUX_PAD(0x0738, 0x0350, 2, 0x0000, 0, 0) +#define _MX6Q_PAD_SD1_CLK__GPT_CLKIN \ + IOMUX_PAD(0x0738, 0x0350, 3, 0x0000, 0, 0) +#define _MX6Q_PAD_SD1_CLK__GPIO_1_20 \ + IOMUX_PAD(0x0738, 0x0350, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_SD1_CLK__PHY_DTB_0 \ + IOMUX_PAD(0x0738, 0x0350, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_SD1_CLK__SATA_PHY_DTB_0 \ + IOMUX_PAD(0x0738, 0x0350, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_SD2_CLK__USDHC2_CLK \ + IOMUX_PAD(0x073C, 0x0354, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_SD2_CLK__ECSPI5_SCLK \ + IOMUX_PAD(0x073C, 0x0354, 1, 0x0828, 1, 0) +#define _MX6Q_PAD_SD2_CLK__KPP_COL_5 \ + IOMUX_PAD(0x073C, 0x0354, 2, 0x08E8, 3, 0) +#define _MX6Q_PAD_SD2_CLK__AUDMUX_AUD4_RXFS \ + IOMUX_PAD(0x073C, 0x0354, 3, 0x07C0, 1, 0) +#define _MX6Q_PAD_SD2_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_9 \ + IOMUX_PAD(0x073C, 0x0354, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_SD2_CLK__GPIO_1_10 \ + IOMUX_PAD(0x073C, 0x0354, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_SD2_CLK__PHY_DTB_1 \ + IOMUX_PAD(0x073C, 0x0354, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_SD2_CLK__SATA_PHY_DTB_1 \ + IOMUX_PAD(0x073C, 0x0354, 7, 0x0000, 0, 0) + +#define _MX6Q_PAD_SD2_CMD__USDHC2_CMD \ + IOMUX_PAD(0x0740, 0x0358, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0) +#define _MX6Q_PAD_SD2_CMD__ECSPI5_MOSI \ + IOMUX_PAD(0x0740, 0x0358, 1, 0x0830, 1, 0) +#define _MX6Q_PAD_SD2_CMD__KPP_ROW_5 \ + IOMUX_PAD(0x0740, 0x0358, 2, 0x08F4, 2, 0) +#define _MX6Q_PAD_SD2_CMD__AUDMUX_AUD4_RXC \ + IOMUX_PAD(0x0740, 0x0358, 3, 0x07BC, 1, 0) +#define _MX6Q_PAD_SD2_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_10 \ + IOMUX_PAD(0x0740, 0x0358, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_SD2_CMD__GPIO_1_11 \ + IOMUX_PAD(0x0740, 0x0358, 5, 0x0000, 0, 0) + +#define _MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 \ + IOMUX_PAD(0x0744, 0x035C, 0, 0x0000, 0, 0) +#define _MX6Q_PAD_SD2_DAT3__ECSPI5_SS3 \ + IOMUX_PAD(0x0744, 0x035C, 1, 0x0000, 0, 0) +#define _MX6Q_PAD_SD2_DAT3__KPP_COL_6 \ + IOMUX_PAD(0x0744, 0x035C, 2, 0x08EC, 2, 0) +#define _MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC \ + IOMUX_PAD(0x0744, 0x035C, 3, 0x07C4, 1, 0) +#define _MX6Q_PAD_SD2_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_11 \ + IOMUX_PAD(0x0744, 0x035C, 4, 0x0000, 0, 0) +#define _MX6Q_PAD_SD2_DAT3__GPIO_1_12 \ + IOMUX_PAD(0x0744, 0x035C, 5, 0x0000, 0, 0) +#define _MX6Q_PAD_SD2_DAT3__SJC_DONE \ + IOMUX_PAD(0x0744, 0x035C, 6, 0x0000, 0, 0) +#define _MX6Q_PAD_SD2_DAT3__ANATOP_ANATOP_TESTO_3 \ + IOMUX_PAD(0x0744, 0x035C, 7, 0x0000, 0, 0) + + + +#define MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 \ + (_MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) +#define MX6Q_PAD_SD2_DAT1__ECSPI5_SS0 \ + (_MX6Q_PAD_SD2_DAT1__ECSPI5_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD2_DAT1__WEIM_WEIM_CS_2 \ + (_MX6Q_PAD_SD2_DAT1__WEIM_WEIM_CS_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS \ + (_MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD2_DAT1__KPP_COL_7 \ + (_MX6Q_PAD_SD2_DAT1__KPP_COL_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD2_DAT1__GPIO_1_14 \ + (_MX6Q_PAD_SD2_DAT1__GPIO_1_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD2_DAT1__CCM_WAIT \ + (_MX6Q_PAD_SD2_DAT1__CCM_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD2_DAT1__ANATOP_ANATOP_TESTO_0 \ + (_MX6Q_PAD_SD2_DAT1__ANATOP_ANATOP_TESTO_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 \ + (_MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) +#define MX6Q_PAD_SD2_DAT2__ECSPI5_SS1 \ + (_MX6Q_PAD_SD2_DAT2__ECSPI5_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD2_DAT2__WEIM_WEIM_CS_3 \ + (_MX6Q_PAD_SD2_DAT2__WEIM_WEIM_CS_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD \ + (_MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD2_DAT2__KPP_ROW_6 \ + (_MX6Q_PAD_SD2_DAT2__KPP_ROW_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD2_DAT2__GPIO_1_13 \ + (_MX6Q_PAD_SD2_DAT2__GPIO_1_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD2_DAT2__CCM_STOP \ + (_MX6Q_PAD_SD2_DAT2__CCM_STOP | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD2_DAT2__ANATOP_ANATOP_TESTO_1 \ + (_MX6Q_PAD_SD2_DAT2__ANATOP_ANATOP_TESTO_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 \ + (_MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) +#define MX6Q_PAD_SD2_DAT0__ECSPI5_MISO \ + (_MX6Q_PAD_SD2_DAT0__ECSPI5_MISO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD \ + (_MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD2_DAT0__KPP_ROW_7 \ + (_MX6Q_PAD_SD2_DAT0__KPP_ROW_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD2_DAT0__GPIO_1_15 \ + (_MX6Q_PAD_SD2_DAT0__GPIO_1_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD2_DAT0__DCIC2_DCIC_OUT \ + (_MX6Q_PAD_SD2_DAT0__DCIC2_DCIC_OUT | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD2_DAT0__ANATOP_ANATOP_TESTO_2 \ + (_MX6Q_PAD_SD2_DAT0__ANATOP_ANATOP_TESTO_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) + + +#define MX6Q_PAD_RGMII_TXC__USBOH3_H2_DATA \ + (_MX6Q_PAD_RGMII_TXC__USBOH3_H2_DATA | MUX_PAD_CTRL(MX6Q_USB_HSIC_PAD_CTRL)) +#define MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC \ + (_MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL)) +#define MX6Q_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK \ + (_MX6Q_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_RGMII_TXC__GPIO_6_19 \ + (_MX6Q_PAD_RGMII_TXC__GPIO_6_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_RGMII_TXC__MIPI_CORE_DPHY_TEST_IN_0 \ + (_MX6Q_PAD_RGMII_TXC__MIPI_CORE_DPHY_TEST_IN_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_RGMII_TXC__ANATOP_ANATOP_24M_OUT \ + (_MX6Q_PAD_RGMII_TXC__ANATOP_ANATOP_24M_OUT | MUX_PAD_CTRL(NO_PAD_CTRL)) + + +#define MX6Q_PAD_RGMII_TD0__MIPI_HSI_CTRL_TX_READY \ + (_MX6Q_PAD_RGMII_TD0__MIPI_HSI_CTRL_TX_READY | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 \ + (_MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL)) +#define MX6Q_PAD_RGMII_TD0__GPIO_6_20 \ + (_MX6Q_PAD_RGMII_TD0__GPIO_6_20 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_RGMII_TD0__MIPI_CORE_DPHY_TEST_IN_1 \ + (_MX6Q_PAD_RGMII_TD0__MIPI_CORE_DPHY_TEST_IN_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_RGMII_TD1__MIPI_HSI_CTRL_RX_FLAG \ + (_MX6Q_PAD_RGMII_TD1__MIPI_HSI_CTRL_RX_FLAG | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 \ + (_MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL)) +#define MX6Q_PAD_RGMII_TD1__GPIO_6_21 \ + (_MX6Q_PAD_RGMII_TD1__GPIO_6_21 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_RGMII_TD1__MIPI_CORE_DPHY_TEST_IN_2 \ + (_MX6Q_PAD_RGMII_TD1__MIPI_CORE_DPHY_TEST_IN_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_RGMII_TD1__CCM_PLL3_BYP \ + (_MX6Q_PAD_RGMII_TD1__CCM_PLL3_BYP | MUX_PAD_CTRL(NO_PAD_CTRL)) + + +#define MX6Q_PAD_RGMII_TD2__MIPI_HSI_CTRL_RX_DATA \ + (_MX6Q_PAD_RGMII_TD2__MIPI_HSI_CTRL_RX_DATA | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 \ + (_MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL)) +#define MX6Q_PAD_RGMII_TD2__GPIO_6_22 \ + (_MX6Q_PAD_RGMII_TD2__GPIO_6_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_RGMII_TD2__MIPI_CORE_DPHY_TEST_IN_3 \ + (_MX6Q_PAD_RGMII_TD2__MIPI_CORE_DPHY_TEST_IN_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_RGMII_TD2__CCM_PLL2_BYP \ + (_MX6Q_PAD_RGMII_TD2__CCM_PLL2_BYP | MUX_PAD_CTRL(NO_PAD_CTRL)) + + +#define MX6Q_PAD_RGMII_TD3__MIPI_HSI_CTRL_RX_WAKE \ + (_MX6Q_PAD_RGMII_TD3__MIPI_HSI_CTRL_RX_WAKE | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 \ + (_MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL)) +#define MX6Q_PAD_RGMII_TD3__GPIO_6_23 \ + (_MX6Q_PAD_RGMII_TD3__GPIO_6_23 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_RGMII_TD3__MIPI_CORE_DPHY_TEST_IN_4 \ + (_MX6Q_PAD_RGMII_TD3__MIPI_CORE_DPHY_TEST_IN_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) + + +#define MX6Q_PAD_RGMII_RX_CTL__USBOH3_H3_DATA \ + (_MX6Q_PAD_RGMII_RX_CTL__USBOH3_H3_DATA | MUX_PAD_CTRL(MX6Q_USB_HSIC_PAD_CTRL)) +#define MX6Q_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL \ + (_MX6Q_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL)) +#define MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24 \ + (_MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_RGMII_RX_CTL__MIPI_CORE_DPHY_TEST_IN_5 \ + (_MX6Q_PAD_RGMII_RX_CTL__MIPI_CORE_DPHY_TEST_IN_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) + + +#define MX6Q_PAD_RGMII_RD0__MIPI_HSI_CTRL_RX_READY \ + (_MX6Q_PAD_RGMII_RD0__MIPI_HSI_CTRL_RX_READY | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 \ + (_MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL)) +#define MX6Q_PAD_RGMII_RD0__GPIO_6_25 \ + (_MX6Q_PAD_RGMII_RD0__GPIO_6_25 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_RGMII_RD0__MIPI_CORE_DPHY_TEST_IN_6 \ + (_MX6Q_PAD_RGMII_RD0__MIPI_CORE_DPHY_TEST_IN_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) + + +#define MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE \ + (_MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE | MUX_PAD_CTRL(MX6Q_USB_HSIC_PAD_CTRL)) +#define MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE_START \ + (_MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE | \ + MUX_PAD_CTRL(MX6Q_USB_HSIC_PAD_CTRL | PAD_CTL_PUS_47K_UP)\ + ) +#define MX6Q_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL \ + (_MX6Q_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL)) +#define MX6Q_PAD_RGMII_TX_CTL__GPIO_6_26 \ + (_MX6Q_PAD_RGMII_TX_CTL__GPIO_6_26 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_RGMII_TX_CTL__MIPI_CORE_DPHY_TEST_IN_7 \ + (_MX6Q_PAD_RGMII_TX_CTL__MIPI_CORE_DPHY_TEST_IN_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_RGMII_TX_CTL__ENET_ANATOP_ETHERNET_REF_OUT \ + (_MX6Q_PAD_RGMII_TX_CTL__ENET_ANATOP_ETHERNET_REF_OUT | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FLAG \ + (_MX6Q_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FLAG | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 \ + (_MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL)) +#define MX6Q_PAD_RGMII_RD1__GPIO_6_27 \ + (_MX6Q_PAD_RGMII_RD1__GPIO_6_27 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_RGMII_RD1__MIPI_CORE_DPHY_TEST_IN_8 \ + (_MX6Q_PAD_RGMII_RD1__MIPI_CORE_DPHY_TEST_IN_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_RGMII_RD1__SJC_FAIL \ + (_MX6Q_PAD_RGMII_RD1__SJC_FAIL | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_RGMII_RD2__MIPI_HSI_CTRL_TX_DATA \ + (_MX6Q_PAD_RGMII_RD2__MIPI_HSI_CTRL_TX_DATA | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 \ + (_MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL)) +#define MX6Q_PAD_RGMII_RD2__GPIO_6_28 \ + (_MX6Q_PAD_RGMII_RD2__GPIO_6_28 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_RGMII_RD2__MIPI_CORE_DPHY_TEST_IN_9 \ + (_MX6Q_PAD_RGMII_RD2__MIPI_CORE_DPHY_TEST_IN_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_RGMII_RD3__MIPI_HSI_CTRL_TX_WAKE \ + (_MX6Q_PAD_RGMII_RD3__MIPI_HSI_CTRL_TX_WAKE | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 \ + (_MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL)) +#define MX6Q_PAD_RGMII_RD3__GPIO_6_29 \ + (_MX6Q_PAD_RGMII_RD3__GPIO_6_29 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_RGMII_RD3__MIPI_CORE_DPHY_TEST_IN_10 \ + (_MX6Q_PAD_RGMII_RD3__MIPI_CORE_DPHY_TEST_IN_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE \ + (_MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE | MUX_PAD_CTRL(MX6Q_USB_HSIC_PAD_CTRL)) +#define MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE_START \ + (_MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE | MUX_PAD_CTRL(MX6Q_USB_HSIC_PAD_CTRL | PAD_CTL_PUS_47K_UP)) +#define MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC \ + (_MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL)) +#define MX6Q_PAD_RGMII_RXC__GPIO_6_30 \ + (_MX6Q_PAD_RGMII_RXC__GPIO_6_30 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_RGMII_RXC__MIPI_CORE_DPHY_TEST_IN_11 \ + (_MX6Q_PAD_RGMII_RXC__MIPI_CORE_DPHY_TEST_IN_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_EIM_A25__WEIM_WEIM_A_25 \ + (_MX6Q_PAD_EIM_A25__WEIM_WEIM_A_25 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_A25__ECSPI4_SS1 \ + (_MX6Q_PAD_EIM_A25__ECSPI4_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_A25__ECSPI2_RDY \ + (_MX6Q_PAD_EIM_A25__ECSPI2_RDY | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_A25__IPU1_DI1_PIN12 \ + (_MX6Q_PAD_EIM_A25__IPU1_DI1_PIN12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_A25__IPU1_DI0_D1_CS \ + (_MX6Q_PAD_EIM_A25__IPU1_DI0_D1_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_A25__GPIO_5_2 \ + (_MX6Q_PAD_EIM_A25__GPIO_5_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE \ + (_MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE | MUX_PAD_CTRL(MX6Q_HDMICEC_PAD_CTRL)) +#define MX6Q_PAD_EIM_A25__PL301_MX6QPER1_HBURST_0 \ + (_MX6Q_PAD_EIM_A25__PL301_MX6QPER1_HBURST_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_EIM_EB2__WEIM_WEIM_EB_2 \ + (_MX6Q_PAD_EIM_EB2__WEIM_WEIM_EB_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_EB2__ECSPI1_SS0 \ + (_MX6Q_PAD_EIM_EB2__ECSPI1_SS0 | MUX_PAD_CTRL(MX6Q_ECSPI_PAD_CTRL)) +#define MX6Q_PAD_EIM_EB2__CCM_DI1_EXT_CLK \ + (_MX6Q_PAD_EIM_EB2__CCM_DI1_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_EB2__IPU2_CSI1_D_19 \ + (_MX6Q_PAD_EIM_EB2__IPU2_CSI1_D_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL \ + (_MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_EB2__GPIO_2_30 \ + (_MX6Q_PAD_EIM_EB2__GPIO_2_30 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_EB2__I2C2_SCL \ + (_MX6Q_PAD_EIM_EB2__I2C2_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL)) +#define MX6Q_PAD_EIM_EB2__SRC_BT_CFG_30 \ + (_MX6Q_PAD_EIM_EB2__SRC_BT_CFG_30 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16 \ + (_MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16 | MUX_PAD_CTRL(MX6Q_WEIM_NOR_PAD_CTRL)) +#define MX6Q_PAD_EIM_D16__ECSPI1_SCLK \ + (_MX6Q_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(MX6Q_ECSPI_PAD_CTRL)) +#define MX6Q_PAD_EIM_D16__IPU1_DI0_PIN5 \ + (_MX6Q_PAD_EIM_D16__IPU1_DI0_PIN5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_D16__IPU2_CSI1_D_18 \ + (_MX6Q_PAD_EIM_D16__IPU2_CSI1_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA \ + (_MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_D16__GPIO_3_16 \ + (_MX6Q_PAD_EIM_D16__GPIO_3_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_D16__I2C2_SDA \ + (_MX6Q_PAD_EIM_D16__I2C2_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL)) + +#define MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17 \ + (_MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17 | MUX_PAD_CTRL(MX6Q_WEIM_NOR_PAD_CTRL)) +#define MX6Q_PAD_EIM_D17__ECSPI1_MISO \ + (_MX6Q_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(MX6Q_ECSPI_PAD_CTRL)) +#define MX6Q_PAD_EIM_D17__IPU1_DI0_PIN6 \ + (_MX6Q_PAD_EIM_D17__IPU1_DI0_PIN6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK \ + (_MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_D17__DCIC1_DCIC_OUT \ + (_MX6Q_PAD_EIM_D17__DCIC1_DCIC_OUT | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_D17__GPIO_3_17 \ + (_MX6Q_PAD_EIM_D17__GPIO_3_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_D17__I2C3_SCL \ + (_MX6Q_PAD_EIM_D17__I2C3_SCL | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_D17__PL301_MX6QPER1_HBURST_1 \ + (_MX6Q_PAD_EIM_D17__PL301_MX6QPER1_HBURST_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18 \ + (_MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18 | MUX_PAD_CTRL(MX6Q_WEIM_NOR_PAD_CTRL)) +#define MX6Q_PAD_EIM_D18__ECSPI1_MOSI \ + (_MX6Q_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(MX6Q_ECSPI_PAD_CTRL)) +#define MX6Q_PAD_EIM_D18__IPU1_DI0_PIN7 \ + (_MX6Q_PAD_EIM_D18__IPU1_DI0_PIN7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_D18__IPU2_CSI1_D_17 \ + (_MX6Q_PAD_EIM_D18__IPU2_CSI1_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS \ + (_MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_D18__GPIO_3_18 \ + (_MX6Q_PAD_EIM_D18__GPIO_3_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_D18__I2C3_SDA \ + (_MX6Q_PAD_EIM_D18__I2C3_SDA | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_D18__PL301_MX6QPER1_HBURST_2 \ + (_MX6Q_PAD_EIM_D18__PL301_MX6QPER1_HBURST_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19 \ + (_MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19 | MUX_PAD_CTRL(MX6Q_WEIM_NOR_PAD_CTRL)) +#define MX6Q_PAD_EIM_D19__ECSPI1_SS1 \ + (_MX6Q_PAD_EIM_D19__ECSPI1_SS1 | MUX_PAD_CTRL(MX6Q_ECSPI_PAD_CTRL)) +#define MX6Q_PAD_EIM_D19__IPU1_DI0_PIN8 \ + (_MX6Q_PAD_EIM_D19__IPU1_DI0_PIN8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_D19__IPU2_CSI1_D_16 \ + (_MX6Q_PAD_EIM_D19__IPU2_CSI1_D_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_D19__UART1_CTS \ + (_MX6Q_PAD_EIM_D19__UART1_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) +#define MX6Q_PAD_EIM_D19__GPIO_3_19 \ + (_MX6Q_PAD_EIM_D19__GPIO_3_19 | MUX_PAD_CTRL(MX6Q_ECSPI_PAD_CTRL)) +#define MX6Q_PAD_EIM_D19__EPIT1_EPITO \ + (_MX6Q_PAD_EIM_D19__EPIT1_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_D19__PL301_MX6QPER1_HRESP \ + (_MX6Q_PAD_EIM_D19__PL301_MX6QPER1_HRESP | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20 \ + (_MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20 | MUX_PAD_CTRL(MX6Q_WEIM_NOR_PAD_CTRL)) +#define MX6Q_PAD_EIM_D20__ECSPI4_SS0 \ + (_MX6Q_PAD_EIM_D20__ECSPI4_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_D20__IPU1_DI0_PIN16 \ + (_MX6Q_PAD_EIM_D20__IPU1_DI0_PIN16 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_D20__IPU2_CSI1_D_15 \ + (_MX6Q_PAD_EIM_D20__IPU2_CSI1_D_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_D20__UART1_CTS \ + (_MX6Q_PAD_EIM_D20__UART1_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) +#define MX6Q_PAD_EIM_D20__UART1_RTS \ + (_MX6Q_PAD_EIM_D20__UART1_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) +#define MX6Q_PAD_EIM_D20__GPIO_3_20 \ + (_MX6Q_PAD_EIM_D20__GPIO_3_20 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_D20__EPIT2_EPITO \ + (_MX6Q_PAD_EIM_D20__EPIT2_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21 \ + (_MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21 | MUX_PAD_CTRL(MX6Q_WEIM_NOR_PAD_CTRL)) +#define MX6Q_PAD_EIM_D21__ECSPI4_SCLK \ + (_MX6Q_PAD_EIM_D21__ECSPI4_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_D21__IPU1_DI0_PIN17 \ + (_MX6Q_PAD_EIM_D21__IPU1_DI0_PIN17 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_D21__IPU2_CSI1_D_11 \ + (_MX6Q_PAD_EIM_D21__IPU2_CSI1_D_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_D21__USBOH3_USBOTG_OC \ + (_MX6Q_PAD_EIM_D21__USBOH3_USBOTG_OC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_D21__GPIO_3_21 \ + (_MX6Q_PAD_EIM_D21__GPIO_3_21 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_D21__I2C1_SCL \ + (_MX6Q_PAD_EIM_D21__I2C1_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL)) +#define MX6Q_PAD_EIM_D21__SPDIF_IN1 \ + (_MX6Q_PAD_EIM_D21__SPDIF_IN1 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22 \ + (_MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22 | MUX_PAD_CTRL(MX6Q_WEIM_NOR_PAD_CTRL)) +#define MX6Q_PAD_EIM_D22__ECSPI4_MISO \ + (_MX6Q_PAD_EIM_D22__ECSPI4_MISO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_D22__IPU1_DI0_PIN1 \ + (_MX6Q_PAD_EIM_D22__IPU1_DI0_PIN1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_D22__IPU2_CSI1_D_10 \ + (_MX6Q_PAD_EIM_D22__IPU2_CSI1_D_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_D22__USBOH3_USBOTG_PWR \ + (_MX6Q_PAD_EIM_D22__USBOH3_USBOTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_D22__GPIO_3_22 \ + (_MX6Q_PAD_EIM_D22__GPIO_3_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_D22__SPDIF_OUT1 \ + (_MX6Q_PAD_EIM_D22__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_D22__PL301_MX6QPER1_HWRITE \ + (_MX6Q_PAD_EIM_D22__PL301_MX6QPER1_HWRITE | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23 \ + (_MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23 | MUX_PAD_CTRL(MX6Q_WEIM_NOR_PAD_CTRL)) +#define MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS \ + (_MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_D23__UART3_CTS \ + (_MX6Q_PAD_EIM_D23__UART3_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) +#define MX6Q_PAD_EIM_D23__UART1_DCD \ + (_MX6Q_PAD_EIM_D23__UART1_DCD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) +#define MX6Q_PAD_EIM_D23__IPU2_CSI1_DATA_EN \ + (_MX6Q_PAD_EIM_D23__IPU2_CSI1_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_D23__GPIO_3_23 \ + (_MX6Q_PAD_EIM_D23__GPIO_3_23 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_D23__IPU1_DI1_PIN2 \ + (_MX6Q_PAD_EIM_D23__IPU1_DI1_PIN2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_D23__IPU1_DI1_PIN14 \ + (_MX6Q_PAD_EIM_D23__IPU1_DI1_PIN14 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_EIM_EB3__WEIM_WEIM_EB_3 \ + (_MX6Q_PAD_EIM_EB3__WEIM_WEIM_EB_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_EB3__ECSPI4_RDY \ + (_MX6Q_PAD_EIM_EB3__ECSPI4_RDY | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_EB3__UART3_CTS \ + (_MX6Q_PAD_EIM_EB3__UART3_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) +#define MX6Q_PAD_EIM_EB3__UART3_RTS \ + (_MX6Q_PAD_EIM_EB3__UART3_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) +#define MX6Q_PAD_EIM_EB3__UART1_RI \ + (_MX6Q_PAD_EIM_EB3__UART1_RI | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) +#define MX6Q_PAD_EIM_EB3__IPU2_CSI1_HSYNC \ + (_MX6Q_PAD_EIM_EB3__IPU2_CSI1_HSYNC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_EB3__GPIO_2_31 \ + (_MX6Q_PAD_EIM_EB3__GPIO_2_31 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_EB3__IPU1_DI1_PIN3 \ + (_MX6Q_PAD_EIM_EB3__IPU1_DI1_PIN3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_EB3__SRC_BT_CFG_31 \ + (_MX6Q_PAD_EIM_EB3__SRC_BT_CFG_31 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24 \ + (_MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24 | MUX_PAD_CTRL(MX6Q_WEIM_NOR_PAD_CTRL)) +#define MX6Q_PAD_EIM_D24__ECSPI4_SS2 \ + (_MX6Q_PAD_EIM_D24__ECSPI4_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_D24__UART3_TXD \ + (_MX6Q_PAD_EIM_D24__UART3_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) +#define MX6Q_PAD_EIM_D24__UART3_RXD \ + (_MX6Q_PAD_EIM_D24__UART3_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) +#define MX6Q_PAD_EIM_D24__ECSPI1_SS2 \ + (_MX6Q_PAD_EIM_D24__ECSPI1_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_D24__ECSPI2_SS2 \ + (_MX6Q_PAD_EIM_D24__ECSPI2_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_D24__GPIO_3_24 \ + (_MX6Q_PAD_EIM_D24__GPIO_3_24 | MUX_PAD_CTRL(MX6Q_HIGH_DRV)) +#define MX6Q_PAD_EIM_D24__AUDMUX_AUD5_RXFS \ + (_MX6Q_PAD_EIM_D24__AUDMUX_AUD5_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_D24__UART1_DTR \ + (_MX6Q_PAD_EIM_D24__UART1_DTR | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) + +#define MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25 \ + (_MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25 | MUX_PAD_CTRL(MX6Q_WEIM_NOR_PAD_CTRL)) +#define MX6Q_PAD_EIM_D25__ECSPI4_SS3 \ + (_MX6Q_PAD_EIM_D25__ECSPI4_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_D25__UART3_TXD \ + (_MX6Q_PAD_EIM_D25__UART3_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) +#define MX6Q_PAD_EIM_D25__UART3_RXD \ + (_MX6Q_PAD_EIM_D25__UART3_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) +#define MX6Q_PAD_EIM_D25__ECSPI1_SS3 \ + (_MX6Q_PAD_EIM_D25__ECSPI1_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_D25__ECSPI2_SS3 \ + (_MX6Q_PAD_EIM_D25__ECSPI2_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_D25__GPIO_3_25 \ + (_MX6Q_PAD_EIM_D25__GPIO_3_25 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_D25__AUDMUX_AUD5_RXC \ + (_MX6Q_PAD_EIM_D25__AUDMUX_AUD5_RXC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_D25__UART1_DSR \ + (_MX6Q_PAD_EIM_D25__UART1_DSR | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) + +#define MX6Q_PAD_EIM_D26__WEIM_WEIM_D_26 \ + (_MX6Q_PAD_EIM_D26__WEIM_WEIM_D_26 | MUX_PAD_CTRL(MX6Q_WEIM_NOR_PAD_CTRL)) +#define MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11 \ + (_MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_D26__IPU1_CSI0_D_1 \ + (_MX6Q_PAD_EIM_D26__IPU1_CSI0_D_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_D26__IPU2_CSI1_D_14 \ + (_MX6Q_PAD_EIM_D26__IPU2_CSI1_D_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_D26__UART2_TXD \ + (_MX6Q_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) +#define MX6Q_PAD_EIM_D26__UART2_RXD \ + (_MX6Q_PAD_EIM_D26__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) +#define MX6Q_PAD_EIM_D26__GPIO_3_26 \ + (_MX6Q_PAD_EIM_D26__GPIO_3_26 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_D26__IPU1_SISG_2 \ + (_MX6Q_PAD_EIM_D26__IPU1_SISG_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_D26__IPU1_DISP1_DAT_22 \ + (_MX6Q_PAD_EIM_D26__IPU1_DISP1_DAT_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_EIM_D27__WEIM_WEIM_D_27 \ + (_MX6Q_PAD_EIM_D27__WEIM_WEIM_D_27 | MUX_PAD_CTRL(MX6Q_WEIM_NOR_PAD_CTRL)) +#define MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13 \ + (_MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_D27__IPU1_CSI0_D_0 \ + (_MX6Q_PAD_EIM_D27__IPU1_CSI0_D_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_D27__IPU2_CSI1_D_13 \ + (_MX6Q_PAD_EIM_D27__IPU2_CSI1_D_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_D27__UART2_TXD \ + (_MX6Q_PAD_EIM_D27__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) +#define MX6Q_PAD_EIM_D27__UART2_RXD \ + (_MX6Q_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) +#define MX6Q_PAD_EIM_D27__GPIO_3_27 \ + (_MX6Q_PAD_EIM_D27__GPIO_3_27 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_D27__IPU1_SISG_3 \ + (_MX6Q_PAD_EIM_D27__IPU1_SISG_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_D27__IPU1_DISP1_DAT_23 \ + (_MX6Q_PAD_EIM_D27__IPU1_DISP1_DAT_23 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28 \ + (_MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28 | MUX_PAD_CTRL(MX6Q_WEIM_NOR_PAD_CTRL)) +#define MX6Q_PAD_EIM_D28__I2C1_SDA \ + (_MX6Q_PAD_EIM_D28__I2C1_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL)) +#define MX6Q_PAD_EIM_D28__ECSPI4_MOSI \ + (_MX6Q_PAD_EIM_D28__ECSPI4_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_D28__IPU2_CSI1_D_12 \ + (_MX6Q_PAD_EIM_D28__IPU2_CSI1_D_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_D28__UART2_CTS \ + (_MX6Q_PAD_EIM_D28__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) +#define MX6Q_PAD_EIM_D28__UART2_RTS \ + (_MX6Q_PAD_EIM_D28__UART2_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) +#define MX6Q_PAD_EIM_D28__GPIO_3_28 \ + (_MX6Q_PAD_EIM_D28__GPIO_3_28 | MUX_PAD_CTRL(MX6Q_HIGH_DRV)) +#define MX6Q_PAD_EIM_D28__IPU1_EXT_TRIG \ + (_MX6Q_PAD_EIM_D28__IPU1_EXT_TRIG | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_D28__IPU1_DI0_PIN13 \ + (_MX6Q_PAD_EIM_D28__IPU1_DI0_PIN13 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_EIM_D29__WEIM_WEIM_D_29 \ + (_MX6Q_PAD_EIM_D29__WEIM_WEIM_D_29 | MUX_PAD_CTRL(MX6Q_WEIM_NOR_PAD_CTRL)) +#define MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15 \ + (_MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_D29__ECSPI4_SS0 \ + (_MX6Q_PAD_EIM_D29__ECSPI4_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_D29__UART2_CTS \ + (_MX6Q_PAD_EIM_D29__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) +#define MX6Q_PAD_EIM_D29__UART2_RTS \ + (_MX6Q_PAD_EIM_D29__UART2_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) +#define MX6Q_PAD_EIM_D29__GPIO_3_29 \ + (_MX6Q_PAD_EIM_D29__GPIO_3_29 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_D29__IPU2_CSI1_VSYNC \ + (_MX6Q_PAD_EIM_D29__IPU2_CSI1_VSYNC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_D29__IPU1_DI0_PIN14 \ + (_MX6Q_PAD_EIM_D29__IPU1_DI0_PIN14 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_EIM_D30__WEIM_WEIM_D_30 \ + (_MX6Q_PAD_EIM_D30__WEIM_WEIM_D_30 | MUX_PAD_CTRL(MX6Q_WEIM_NOR_PAD_CTRL)) +#define MX6Q_PAD_EIM_D30__IPU1_DISP1_DAT_21 \ + (_MX6Q_PAD_EIM_D30__IPU1_DISP1_DAT_21 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_D30__IPU1_DI0_PIN11 \ + (_MX6Q_PAD_EIM_D30__IPU1_DI0_PIN11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_D30__IPU1_CSI0_D_3 \ + (_MX6Q_PAD_EIM_D30__IPU1_CSI0_D_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_D30__UART3_CTS \ + (_MX6Q_PAD_EIM_D30__UART3_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) +#define MX6Q_PAD_EIM_D30__GPIO_3_30 \ + (_MX6Q_PAD_EIM_D30__GPIO_3_30 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_D30__USBOH3_USBH1_OC \ + (_MX6Q_PAD_EIM_D30__USBOH3_USBH1_OC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_D30__PL301_MX6QPER1_HPROT_0 \ + (_MX6Q_PAD_EIM_D30__PL301_MX6QPER1_HPROT_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_EIM_D31__WEIM_WEIM_D_31 \ + (_MX6Q_PAD_EIM_D31__WEIM_WEIM_D_31 | MUX_PAD_CTRL(MX6Q_WEIM_NOR_PAD_CTRL)) +#define MX6Q_PAD_EIM_D31__IPU1_DISP1_DAT_20 \ + (_MX6Q_PAD_EIM_D31__IPU1_DISP1_DAT_20 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_D31__IPU1_DI0_PIN12 \ + (_MX6Q_PAD_EIM_D31__IPU1_DI0_PIN12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_D31__IPU1_CSI0_D_2 \ + (_MX6Q_PAD_EIM_D31__IPU1_CSI0_D_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_D31__UART3_CTS \ + (_MX6Q_PAD_EIM_D31__UART3_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) +#define MX6Q_PAD_EIM_D31__UART3_RTS \ + (_MX6Q_PAD_EIM_D31__UART3_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) +#define MX6Q_PAD_EIM_D31__GPIO_3_31 \ + (_MX6Q_PAD_EIM_D31__GPIO_3_31 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_D31__USBOH3_USBH1_PWR \ + (_MX6Q_PAD_EIM_D31__USBOH3_USBH1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_D31__PL301_MX6QPER1_HPROT_1 \ + (_MX6Q_PAD_EIM_D31__PL301_MX6QPER1_HPROT_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_EIM_A24__WEIM_WEIM_A_24 \ + (_MX6Q_PAD_EIM_A24__WEIM_WEIM_A_24 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_A24__IPU1_DISP1_DAT_19 \ + (_MX6Q_PAD_EIM_A24__IPU1_DISP1_DAT_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_A24__IPU2_CSI1_D_19 \ + (_MX6Q_PAD_EIM_A24__IPU2_CSI1_D_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_A24__IPU2_SISG_2 \ + (_MX6Q_PAD_EIM_A24__IPU2_SISG_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_A24__IPU1_SISG_2 \ + (_MX6Q_PAD_EIM_A24__IPU1_SISG_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_A24__GPIO_5_4 \ + (_MX6Q_PAD_EIM_A24__GPIO_5_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_A24__PL301_MX6QPER1_HPROT_2 \ + (_MX6Q_PAD_EIM_A24__PL301_MX6QPER1_HPROT_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_A24__SRC_BT_CFG_24 \ + (_MX6Q_PAD_EIM_A24__SRC_BT_CFG_24 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_EIM_A23__WEIM_WEIM_A_23 \ + (_MX6Q_PAD_EIM_A23__WEIM_WEIM_A_23 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_A23__IPU1_DISP1_DAT_18 \ + (_MX6Q_PAD_EIM_A23__IPU1_DISP1_DAT_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_A23__IPU2_CSI1_D_18 \ + (_MX6Q_PAD_EIM_A23__IPU2_CSI1_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_A23__IPU2_SISG_3 \ + (_MX6Q_PAD_EIM_A23__IPU2_SISG_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_A23__IPU1_SISG_3 \ + (_MX6Q_PAD_EIM_A23__IPU1_SISG_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_A23__GPIO_6_6 \ + (_MX6Q_PAD_EIM_A23__GPIO_6_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_A23__PL301_MX6QPER1_HPROT_3 \ + (_MX6Q_PAD_EIM_A23__PL301_MX6QPER1_HPROT_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_A23__SRC_BT_CFG_23 \ + (_MX6Q_PAD_EIM_A23__SRC_BT_CFG_23 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_EIM_A22__WEIM_WEIM_A_22 \ + (_MX6Q_PAD_EIM_A22__WEIM_WEIM_A_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_A22__IPU1_DISP1_DAT_17 \ + (_MX6Q_PAD_EIM_A22__IPU1_DISP1_DAT_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_A22__IPU2_CSI1_D_17 \ + (_MX6Q_PAD_EIM_A22__IPU2_CSI1_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_A22__GPIO_2_16 \ + (_MX6Q_PAD_EIM_A22__GPIO_2_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_A22__TPSMP_HDATA_0 \ + (_MX6Q_PAD_EIM_A22__TPSMP_HDATA_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_A22__SRC_BT_CFG_22 \ + (_MX6Q_PAD_EIM_A22__SRC_BT_CFG_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_EIM_A21__WEIM_WEIM_A_21 \ + (_MX6Q_PAD_EIM_A21__WEIM_WEIM_A_21 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_A21__IPU1_DISP1_DAT_16 \ + (_MX6Q_PAD_EIM_A21__IPU1_DISP1_DAT_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_A21__IPU2_CSI1_D_16 \ + (_MX6Q_PAD_EIM_A21__IPU2_CSI1_D_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_A21__RESERVED_RESERVED \ + (_MX6Q_PAD_EIM_A21__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_A21__MIPI_CORE_DPHY_TEST_OUT_18 \ + (_MX6Q_PAD_EIM_A21__MIPI_CORE_DPHY_TEST_OUT_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_A21__GPIO_2_17 \ + (_MX6Q_PAD_EIM_A21__GPIO_2_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_A21__TPSMP_HDATA_1 \ + (_MX6Q_PAD_EIM_A21__TPSMP_HDATA_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_A21__SRC_BT_CFG_21 \ + (_MX6Q_PAD_EIM_A21__SRC_BT_CFG_21 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_EIM_A20__WEIM_WEIM_A_20 \ + (_MX6Q_PAD_EIM_A20__WEIM_WEIM_A_20 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_A20__IPU1_DISP1_DAT_15 \ + (_MX6Q_PAD_EIM_A20__IPU1_DISP1_DAT_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_A20__IPU2_CSI1_D_15 \ + (_MX6Q_PAD_EIM_A20__IPU2_CSI1_D_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_A20__RESERVED_RESERVED \ + (_MX6Q_PAD_EIM_A20__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_A20__MIPI_CORE_DPHY_TEST_OUT_19 \ + (_MX6Q_PAD_EIM_A20__MIPI_CORE_DPHY_TEST_OUT_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_A20__GPIO_2_18 \ + (_MX6Q_PAD_EIM_A20__GPIO_2_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_A20__TPSMP_HDATA_2 \ + (_MX6Q_PAD_EIM_A20__TPSMP_HDATA_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_A20__SRC_BT_CFG_20 \ + (_MX6Q_PAD_EIM_A20__SRC_BT_CFG_20 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_EIM_A19__WEIM_WEIM_A_19 \ + (_MX6Q_PAD_EIM_A19__WEIM_WEIM_A_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_A19__IPU1_DISP1_DAT_14 \ + (_MX6Q_PAD_EIM_A19__IPU1_DISP1_DAT_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_A19__IPU2_CSI1_D_14 \ + (_MX6Q_PAD_EIM_A19__IPU2_CSI1_D_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_A19__RESERVED_RESERVED \ + (_MX6Q_PAD_EIM_A19__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_A19__MIPI_CORE_DPHY_TEST_OUT_20 \ + (_MX6Q_PAD_EIM_A19__MIPI_CORE_DPHY_TEST_OUT_20 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_A19__GPIO_2_19 \ + (_MX6Q_PAD_EIM_A19__GPIO_2_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_A19__TPSMP_HDATA_3 \ + (_MX6Q_PAD_EIM_A19__TPSMP_HDATA_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_A19__SRC_BT_CFG_19 \ + (_MX6Q_PAD_EIM_A19__SRC_BT_CFG_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_EIM_A18__WEIM_WEIM_A_18 \ + (_MX6Q_PAD_EIM_A18__WEIM_WEIM_A_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_A18__IPU1_DISP1_DAT_13 \ + (_MX6Q_PAD_EIM_A18__IPU1_DISP1_DAT_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_A18__IPU2_CSI1_D_13 \ + (_MX6Q_PAD_EIM_A18__IPU2_CSI1_D_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_A18__RESERVED_RESERVED \ + (_MX6Q_PAD_EIM_A18__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_A18__MIPI_CORE_DPHY_TEST_OUT_21 \ + (_MX6Q_PAD_EIM_A18__MIPI_CORE_DPHY_TEST_OUT_21 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_A18__GPIO_2_20 \ + (_MX6Q_PAD_EIM_A18__GPIO_2_20 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_A18__TPSMP_HDATA_4 \ + (_MX6Q_PAD_EIM_A18__TPSMP_HDATA_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_A18__SRC_BT_CFG_18 \ + (_MX6Q_PAD_EIM_A18__SRC_BT_CFG_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_EIM_A17__WEIM_WEIM_A_17 \ + (_MX6Q_PAD_EIM_A17__WEIM_WEIM_A_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_A17__IPU1_DISP1_DAT_12 \ + (_MX6Q_PAD_EIM_A17__IPU1_DISP1_DAT_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_A17__IPU2_CSI1_D_12 \ + (_MX6Q_PAD_EIM_A17__IPU2_CSI1_D_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_A17__RESERVED_RESERVED \ + (_MX6Q_PAD_EIM_A17__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_A17__MIPI_CORE_DPHY_TEST_OUT_22 \ + (_MX6Q_PAD_EIM_A17__MIPI_CORE_DPHY_TEST_OUT_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_A17__GPIO_2_21 \ + (_MX6Q_PAD_EIM_A17__GPIO_2_21 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_A17__TPSMP_HDATA_5 \ + (_MX6Q_PAD_EIM_A17__TPSMP_HDATA_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_A17__SRC_BT_CFG_17 \ + (_MX6Q_PAD_EIM_A17__SRC_BT_CFG_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_EIM_A16__WEIM_WEIM_A_16 \ + (_MX6Q_PAD_EIM_A16__WEIM_WEIM_A_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_A16__IPU1_DI1_DISP_CLK \ + (_MX6Q_PAD_EIM_A16__IPU1_DI1_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK \ + (_MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_A16__MIPI_CORE_DPHY_TEST_OUT_23 \ + (_MX6Q_PAD_EIM_A16__MIPI_CORE_DPHY_TEST_OUT_23 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_A16__GPIO_2_22 \ + (_MX6Q_PAD_EIM_A16__GPIO_2_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_A16__TPSMP_HDATA_6 \ + (_MX6Q_PAD_EIM_A16__TPSMP_HDATA_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_A16__SRC_BT_CFG_16 \ + (_MX6Q_PAD_EIM_A16__SRC_BT_CFG_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0 \ + (_MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_CS0__IPU1_DI1_PIN5 \ + (_MX6Q_PAD_EIM_CS0__IPU1_DI1_PIN5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_CS0__ECSPI2_SCLK \ + (_MX6Q_PAD_EIM_CS0__ECSPI2_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_CS0__MIPI_CORE_DPHY_TEST_OUT_24 \ + (_MX6Q_PAD_EIM_CS0__MIPI_CORE_DPHY_TEST_OUT_24 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_CS0__GPIO_2_23 \ + (_MX6Q_PAD_EIM_CS0__GPIO_2_23 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_CS0__TPSMP_HDATA_7 \ + (_MX6Q_PAD_EIM_CS0__TPSMP_HDATA_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_EIM_CS1__WEIM_WEIM_CS_1 \ + (_MX6Q_PAD_EIM_CS1__WEIM_WEIM_CS_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_CS1__IPU1_DI1_PIN6 \ + (_MX6Q_PAD_EIM_CS1__IPU1_DI1_PIN6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_CS1__ECSPI2_MOSI \ + (_MX6Q_PAD_EIM_CS1__ECSPI2_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_CS1__MIPI_CORE_DPHY_TEST_OUT_25 \ + (_MX6Q_PAD_EIM_CS1__MIPI_CORE_DPHY_TEST_OUT_25 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_CS1__GPIO_2_24 \ + (_MX6Q_PAD_EIM_CS1__GPIO_2_24 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_CS1__TPSMP_HDATA_8 \ + (_MX6Q_PAD_EIM_CS1__TPSMP_HDATA_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_EIM_OE__WEIM_WEIM_OE \ + (_MX6Q_PAD_EIM_OE__WEIM_WEIM_OE | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_OE__IPU1_DI1_PIN7 \ + (_MX6Q_PAD_EIM_OE__IPU1_DI1_PIN7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_OE__ECSPI2_MISO \ + (_MX6Q_PAD_EIM_OE__ECSPI2_MISO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_OE__MIPI_CORE_DPHY_TEST_OUT_26 \ + (_MX6Q_PAD_EIM_OE__MIPI_CORE_DPHY_TEST_OUT_26 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_OE__GPIO_2_25 \ + (_MX6Q_PAD_EIM_OE__GPIO_2_25 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_OE__TPSMP_HDATA_9 \ + (_MX6Q_PAD_EIM_OE__TPSMP_HDATA_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_EIM_RW__WEIM_WEIM_RW \ + (_MX6Q_PAD_EIM_RW__WEIM_WEIM_RW | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_RW__IPU1_DI1_PIN8 \ + (_MX6Q_PAD_EIM_RW__IPU1_DI1_PIN8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_RW__ECSPI2_SS0 \ + (_MX6Q_PAD_EIM_RW__ECSPI2_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_RW__MIPI_CORE_DPHY_TEST_OUT_27 \ + (_MX6Q_PAD_EIM_RW__MIPI_CORE_DPHY_TEST_OUT_27 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_RW__GPIO_2_26 \ + (_MX6Q_PAD_EIM_RW__GPIO_2_26 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_RW__TPSMP_HDATA_10 \ + (_MX6Q_PAD_EIM_RW__TPSMP_HDATA_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_RW__SRC_BT_CFG_29 \ + (_MX6Q_PAD_EIM_RW__SRC_BT_CFG_29 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_EIM_LBA__WEIM_WEIM_LBA \ + (_MX6Q_PAD_EIM_LBA__WEIM_WEIM_LBA | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_LBA__IPU1_DI1_PIN17 \ + (_MX6Q_PAD_EIM_LBA__IPU1_DI1_PIN17 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_LBA__ECSPI2_SS1 \ + (_MX6Q_PAD_EIM_LBA__ECSPI2_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_LBA__GPIO_2_27 \ + (_MX6Q_PAD_EIM_LBA__GPIO_2_27 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_LBA__TPSMP_HDATA_11 \ + (_MX6Q_PAD_EIM_LBA__TPSMP_HDATA_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_LBA__SRC_BT_CFG_26 \ + (_MX6Q_PAD_EIM_LBA__SRC_BT_CFG_26 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_EIM_EB0__WEIM_WEIM_EB_0 \ + (_MX6Q_PAD_EIM_EB0__WEIM_WEIM_EB_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_EB0__IPU1_DISP1_DAT_11 \ + (_MX6Q_PAD_EIM_EB0__IPU1_DISP1_DAT_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_EB0__IPU2_CSI1_D_11 \ + (_MX6Q_PAD_EIM_EB0__IPU2_CSI1_D_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_EB0__MIPI_CORE_DPHY_TEST_OUT_0 \ + (_MX6Q_PAD_EIM_EB0__MIPI_CORE_DPHY_TEST_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_EB0__CCM_PMIC_RDY \ + (_MX6Q_PAD_EIM_EB0__CCM_PMIC_RDY | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_EB0__GPIO_2_28 \ + (_MX6Q_PAD_EIM_EB0__GPIO_2_28 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_EB0__TPSMP_HDATA_12 \ + (_MX6Q_PAD_EIM_EB0__TPSMP_HDATA_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_EB0__SRC_BT_CFG_27 \ + (_MX6Q_PAD_EIM_EB0__SRC_BT_CFG_27 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_EIM_EB1__WEIM_WEIM_EB_1 \ + (_MX6Q_PAD_EIM_EB1__WEIM_WEIM_EB_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_EB1__IPU1_DISP1_DAT_10 \ + (_MX6Q_PAD_EIM_EB1__IPU1_DISP1_DAT_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_EB1__IPU2_CSI1_D_10 \ + (_MX6Q_PAD_EIM_EB1__IPU2_CSI1_D_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_EB1__MIPI_CORE_DPHY_TEST_OUT_1 \ + (_MX6Q_PAD_EIM_EB1__MIPI_CORE_DPHY_TEST_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_EB1__GPIO_2_29 \ + (_MX6Q_PAD_EIM_EB1__GPIO_2_29 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_EB1__TPSMP_HDATA_13 \ + (_MX6Q_PAD_EIM_EB1__TPSMP_HDATA_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_EB1__SRC_BT_CFG_28 \ + (_MX6Q_PAD_EIM_EB1__SRC_BT_CFG_28 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_EIM_DA0__WEIM_WEIM_DA_A_0 \ + (_MX6Q_PAD_EIM_DA0__WEIM_WEIM_DA_A_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA0__IPU1_DISP1_DAT_9 \ + (_MX6Q_PAD_EIM_DA0__IPU1_DISP1_DAT_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA0__IPU2_CSI1_D_9 \ + (_MX6Q_PAD_EIM_DA0__IPU2_CSI1_D_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA0__MIPI_CORE_DPHY_TEST_OUT_2 \ + (_MX6Q_PAD_EIM_DA0__MIPI_CORE_DPHY_TEST_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA0__GPIO_3_0 \ + (_MX6Q_PAD_EIM_DA0__GPIO_3_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA0__TPSMP_HDATA_14 \ + (_MX6Q_PAD_EIM_DA0__TPSMP_HDATA_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA0__SRC_BT_CFG_0 \ + (_MX6Q_PAD_EIM_DA0__SRC_BT_CFG_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_EIM_DA1__WEIM_WEIM_DA_A_1 \ + (_MX6Q_PAD_EIM_DA1__WEIM_WEIM_DA_A_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA1__IPU1_DISP1_DAT_8 \ + (_MX6Q_PAD_EIM_DA1__IPU1_DISP1_DAT_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA1__IPU2_CSI1_D_8 \ + (_MX6Q_PAD_EIM_DA1__IPU2_CSI1_D_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA1__MIPI_CORE_DPHY_TEST_OUT_3 \ + (_MX6Q_PAD_EIM_DA1__MIPI_CORE_DPHY_TEST_OUT_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA1__ANATOP_USBPHY1_TSTI_TX_LS_MODE \ + (_MX6Q_PAD_EIM_DA1__ANATOP_USBPHY1_TSTI_TX_LS_MODE | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA1__GPIO_3_1 \ + (_MX6Q_PAD_EIM_DA1__GPIO_3_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA1__TPSMP_HDATA_15 \ + (_MX6Q_PAD_EIM_DA1__TPSMP_HDATA_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA1__SRC_BT_CFG_1 \ + (_MX6Q_PAD_EIM_DA1__SRC_BT_CFG_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_EIM_DA2__WEIM_WEIM_DA_A_2 \ + (_MX6Q_PAD_EIM_DA2__WEIM_WEIM_DA_A_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA2__IPU1_DISP1_DAT_7 \ + (_MX6Q_PAD_EIM_DA2__IPU1_DISP1_DAT_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA2__IPU2_CSI1_D_7 \ + (_MX6Q_PAD_EIM_DA2__IPU2_CSI1_D_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA2__MIPI_CORE_DPHY_TEST_OUT_4 \ + (_MX6Q_PAD_EIM_DA2__MIPI_CORE_DPHY_TEST_OUT_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA2__ANATOP_USBPHY1_TSTI_TX_HS_MODE \ + (_MX6Q_PAD_EIM_DA2__ANATOP_USBPHY1_TSTI_TX_HS_MODE | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA2__GPIO_3_2 \ + (_MX6Q_PAD_EIM_DA2__GPIO_3_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA2__TPSMP_HDATA_16 \ + (_MX6Q_PAD_EIM_DA2__TPSMP_HDATA_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA2__SRC_BT_CFG_2 \ + (_MX6Q_PAD_EIM_DA2__SRC_BT_CFG_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_EIM_DA3__WEIM_WEIM_DA_A_3 \ + (_MX6Q_PAD_EIM_DA3__WEIM_WEIM_DA_A_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA3__IPU1_DISP1_DAT_6 \ + (_MX6Q_PAD_EIM_DA3__IPU1_DISP1_DAT_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA3__IPU2_CSI1_D_6 \ + (_MX6Q_PAD_EIM_DA3__IPU2_CSI1_D_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA3__MIPI_CORE_DPHY_TEST_OUT_5 \ + (_MX6Q_PAD_EIM_DA3__MIPI_CORE_DPHY_TEST_OUT_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA3__ANATOP_USBPHY1_TSTI_TX_HIZ \ + (_MX6Q_PAD_EIM_DA3__ANATOP_USBPHY1_TSTI_TX_HIZ | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA3__GPIO_3_3 \ + (_MX6Q_PAD_EIM_DA3__GPIO_3_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA3__TPSMP_HDATA_17 \ + (_MX6Q_PAD_EIM_DA3__TPSMP_HDATA_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA3__SRC_BT_CFG_3 \ + (_MX6Q_PAD_EIM_DA3__SRC_BT_CFG_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_EIM_DA4__WEIM_WEIM_DA_A_4 \ + (_MX6Q_PAD_EIM_DA4__WEIM_WEIM_DA_A_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA4__IPU1_DISP1_DAT_5 \ + (_MX6Q_PAD_EIM_DA4__IPU1_DISP1_DAT_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA4__IPU2_CSI1_D_5 \ + (_MX6Q_PAD_EIM_DA4__IPU2_CSI1_D_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA4__MIPI_CORE_DPHY_TEST_OUT_6 \ + (_MX6Q_PAD_EIM_DA4__MIPI_CORE_DPHY_TEST_OUT_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA4__ANATOP_USBPHY1_TSTI_TX_EN \ + (_MX6Q_PAD_EIM_DA4__ANATOP_USBPHY1_TSTI_TX_EN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA4__GPIO_3_4 \ + (_MX6Q_PAD_EIM_DA4__GPIO_3_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA4__TPSMP_HDATA_18 \ + (_MX6Q_PAD_EIM_DA4__TPSMP_HDATA_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA4__SRC_BT_CFG_4 \ + (_MX6Q_PAD_EIM_DA4__SRC_BT_CFG_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_EIM_DA5__WEIM_WEIM_DA_A_5 \ + (_MX6Q_PAD_EIM_DA5__WEIM_WEIM_DA_A_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA5__IPU1_DISP1_DAT_4 \ + (_MX6Q_PAD_EIM_DA5__IPU1_DISP1_DAT_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA5__IPU2_CSI1_D_4 \ + (_MX6Q_PAD_EIM_DA5__IPU2_CSI1_D_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA5__MIPI_CORE_DPHY_TEST_OUT_7 \ + (_MX6Q_PAD_EIM_DA5__MIPI_CORE_DPHY_TEST_OUT_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA5__ANATOP_USBPHY1_TSTI_TX_DP \ + (_MX6Q_PAD_EIM_DA5__ANATOP_USBPHY1_TSTI_TX_DP | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA5__GPIO_3_5 \ + (_MX6Q_PAD_EIM_DA5__GPIO_3_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA5__TPSMP_HDATA_19 \ + (_MX6Q_PAD_EIM_DA5__TPSMP_HDATA_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA5__SRC_BT_CFG_5 \ + (_MX6Q_PAD_EIM_DA5__SRC_BT_CFG_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_EIM_DA6__WEIM_WEIM_DA_A_6 \ + (_MX6Q_PAD_EIM_DA6__WEIM_WEIM_DA_A_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA6__IPU1_DISP1_DAT_3 \ + (_MX6Q_PAD_EIM_DA6__IPU1_DISP1_DAT_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA6__IPU2_CSI1_D_3 \ + (_MX6Q_PAD_EIM_DA6__IPU2_CSI1_D_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA6__MIPI_CORE_DPHY_TEST_OUT_8 \ + (_MX6Q_PAD_EIM_DA6__MIPI_CORE_DPHY_TEST_OUT_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA6__ANATOP_USBPHY1_TSTI_TX_DN \ + (_MX6Q_PAD_EIM_DA6__ANATOP_USBPHY1_TSTI_TX_DN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA6__GPIO_3_6 \ + (_MX6Q_PAD_EIM_DA6__GPIO_3_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA6__TPSMP_HDATA_20 \ + (_MX6Q_PAD_EIM_DA6__TPSMP_HDATA_20 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA6__SRC_BT_CFG_6 \ + (_MX6Q_PAD_EIM_DA6__SRC_BT_CFG_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_EIM_DA7__WEIM_WEIM_DA_A_7 \ + (_MX6Q_PAD_EIM_DA7__WEIM_WEIM_DA_A_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA7__IPU1_DISP1_DAT_2 \ + (_MX6Q_PAD_EIM_DA7__IPU1_DISP1_DAT_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA7__IPU2_CSI1_D_2 \ + (_MX6Q_PAD_EIM_DA7__IPU2_CSI1_D_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA7__MIPI_CORE_DPHY_TEST_OUT_9 \ + (_MX6Q_PAD_EIM_DA7__MIPI_CORE_DPHY_TEST_OUT_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA7__GPIO_3_7 \ + (_MX6Q_PAD_EIM_DA7__GPIO_3_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA7__TPSMP_HDATA_21 \ + (_MX6Q_PAD_EIM_DA7__TPSMP_HDATA_21 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA7__SRC_BT_CFG_7 \ + (_MX6Q_PAD_EIM_DA7__SRC_BT_CFG_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_EIM_DA8__WEIM_WEIM_DA_A_8 \ + (_MX6Q_PAD_EIM_DA8__WEIM_WEIM_DA_A_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA8__IPU1_DISP1_DAT_1 \ + (_MX6Q_PAD_EIM_DA8__IPU1_DISP1_DAT_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA8__IPU2_CSI1_D_1 \ + (_MX6Q_PAD_EIM_DA8__IPU2_CSI1_D_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA8__MIPI_CORE_DPHY_TEST_OUT_10 \ + (_MX6Q_PAD_EIM_DA8__MIPI_CORE_DPHY_TEST_OUT_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA8__GPIO_3_8 \ + (_MX6Q_PAD_EIM_DA8__GPIO_3_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA8__TPSMP_HDATA_22 \ + (_MX6Q_PAD_EIM_DA8__TPSMP_HDATA_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA8__SRC_BT_CFG_8 \ + (_MX6Q_PAD_EIM_DA8__SRC_BT_CFG_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_EIM_DA9__WEIM_WEIM_DA_A_9 \ + (_MX6Q_PAD_EIM_DA9__WEIM_WEIM_DA_A_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA9__IPU1_DISP1_DAT_0 \ + (_MX6Q_PAD_EIM_DA9__IPU1_DISP1_DAT_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA9__IPU2_CSI1_D_0 \ + (_MX6Q_PAD_EIM_DA9__IPU2_CSI1_D_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA9__MIPI_CORE_DPHY_TEST_OUT_11 \ + (_MX6Q_PAD_EIM_DA9__MIPI_CORE_DPHY_TEST_OUT_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA9__GPIO_3_9 \ + (_MX6Q_PAD_EIM_DA9__GPIO_3_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA9__TPSMP_HDATA_23 \ + (_MX6Q_PAD_EIM_DA9__TPSMP_HDATA_23 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA9__SRC_BT_CFG_9 \ + (_MX6Q_PAD_EIM_DA9__SRC_BT_CFG_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_EIM_DA10__WEIM_WEIM_DA_A_10 \ + (_MX6Q_PAD_EIM_DA10__WEIM_WEIM_DA_A_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA10__IPU1_DI1_PIN15 \ + (_MX6Q_PAD_EIM_DA10__IPU1_DI1_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA10__IPU2_CSI1_DATA_EN \ + (_MX6Q_PAD_EIM_DA10__IPU2_CSI1_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA10__MIPI_CORE_DPHY_TEST_OUT_12 \ + (_MX6Q_PAD_EIM_DA10__MIPI_CORE_DPHY_TEST_OUT_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA10__GPIO_3_10 \ + (_MX6Q_PAD_EIM_DA10__GPIO_3_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA10__TPSMP_HDATA_24 \ + (_MX6Q_PAD_EIM_DA10__TPSMP_HDATA_24 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA10__SRC_BT_CFG_10 \ + (_MX6Q_PAD_EIM_DA10__SRC_BT_CFG_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_EIM_DA11__WEIM_WEIM_DA_A_11 \ + (_MX6Q_PAD_EIM_DA11__WEIM_WEIM_DA_A_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA11__IPU1_DI1_PIN2 \ + (_MX6Q_PAD_EIM_DA11__IPU1_DI1_PIN2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA11__IPU2_CSI1_HSYNC \ + (_MX6Q_PAD_EIM_DA11__IPU2_CSI1_HSYNC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA11__MIPI_CORE_DPHY_TEST_OUT_13 \ + (_MX6Q_PAD_EIM_DA11__MIPI_CORE_DPHY_TEST_OUT_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA11__SDMA_DEBUG_EVT_CHN_LINES_6 \ + (_MX6Q_PAD_EIM_DA11__SDMA_DEBUG_EVT_CHN_LINES_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA11__GPIO_3_11 \ + (_MX6Q_PAD_EIM_DA11__GPIO_3_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA11__TPSMP_HDATA_25 \ + (_MX6Q_PAD_EIM_DA11__TPSMP_HDATA_25 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA11__SRC_BT_CFG_11 \ + (_MX6Q_PAD_EIM_DA11__SRC_BT_CFG_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_EIM_DA12__WEIM_WEIM_DA_A_12 \ + (_MX6Q_PAD_EIM_DA12__WEIM_WEIM_DA_A_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA12__IPU1_DI1_PIN3 \ + (_MX6Q_PAD_EIM_DA12__IPU1_DI1_PIN3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA12__IPU2_CSI1_VSYNC \ + (_MX6Q_PAD_EIM_DA12__IPU2_CSI1_VSYNC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA12__MIPI_CORE_DPHY_TEST_OUT_14 \ + (_MX6Q_PAD_EIM_DA12__MIPI_CORE_DPHY_TEST_OUT_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_LINES_3 \ + (_MX6Q_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_LINES_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA12__GPIO_3_12 \ + (_MX6Q_PAD_EIM_DA12__GPIO_3_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA12__TPSMP_HDATA_26 \ + (_MX6Q_PAD_EIM_DA12__TPSMP_HDATA_26 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA12__SRC_BT_CFG_12 \ + (_MX6Q_PAD_EIM_DA12__SRC_BT_CFG_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_EIM_DA13__WEIM_WEIM_DA_A_13 \ + (_MX6Q_PAD_EIM_DA13__WEIM_WEIM_DA_A_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA13__IPU1_DI1_D0_CS \ + (_MX6Q_PAD_EIM_DA13__IPU1_DI1_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA13__CCM_DI1_EXT_CLK \ + (_MX6Q_PAD_EIM_DA13__CCM_DI1_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA13__MIPI_CORE_DPHY_TEST_OUT_15 \ + (_MX6Q_PAD_EIM_DA13__MIPI_CORE_DPHY_TEST_OUT_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_LINES_4 \ + (_MX6Q_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_LINES_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA13__GPIO_3_13 \ + (_MX6Q_PAD_EIM_DA13__GPIO_3_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA13__TPSMP_HDATA_27 \ + (_MX6Q_PAD_EIM_DA13__TPSMP_HDATA_27 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA13__SRC_BT_CFG_13 \ + (_MX6Q_PAD_EIM_DA13__SRC_BT_CFG_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_EIM_DA14__WEIM_WEIM_DA_A_14 \ + (_MX6Q_PAD_EIM_DA14__WEIM_WEIM_DA_A_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA14__IPU1_DI1_D1_CS \ + (_MX6Q_PAD_EIM_DA14__IPU1_DI1_D1_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA14__CCM_DI0_EXT_CLK \ + (_MX6Q_PAD_EIM_DA14__CCM_DI0_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA14__MIPI_CORE_DPHY_TEST_OUT_16 \ + (_MX6Q_PAD_EIM_DA14__MIPI_CORE_DPHY_TEST_OUT_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_LINES_5 \ + (_MX6Q_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_LINES_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA14__GPIO_3_14 \ + (_MX6Q_PAD_EIM_DA14__GPIO_3_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA14__TPSMP_HDATA_28 \ + (_MX6Q_PAD_EIM_DA14__TPSMP_HDATA_28 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA14__SRC_BT_CFG_14 \ + (_MX6Q_PAD_EIM_DA14__SRC_BT_CFG_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_EIM_DA15__WEIM_WEIM_DA_A_15 \ + (_MX6Q_PAD_EIM_DA15__WEIM_WEIM_DA_A_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN1 \ + (_MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN4 \ + (_MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA15__MIPI_CORE_DPHY_TEST_OUT_17 \ + (_MX6Q_PAD_EIM_DA15__MIPI_CORE_DPHY_TEST_OUT_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA15__GPIO_3_15 \ + (_MX6Q_PAD_EIM_DA15__GPIO_3_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA15__TPSMP_HDATA_29 \ + (_MX6Q_PAD_EIM_DA15__TPSMP_HDATA_29 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_DA15__SRC_BT_CFG_15 \ + (_MX6Q_PAD_EIM_DA15__SRC_BT_CFG_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_EIM_WAIT__WEIM_WEIM_WAIT \ + (_MX6Q_PAD_EIM_WAIT__WEIM_WEIM_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B \ + (_MX6Q_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_WAIT__GPIO_5_0 \ + (_MX6Q_PAD_EIM_WAIT__GPIO_5_0 | MUX_PAD_CTRL(MX6Q_HIGH_DRV)) +#define MX6Q_PAD_EIM_WAIT__TPSMP_HDATA_30 \ + (_MX6Q_PAD_EIM_WAIT__TPSMP_HDATA_30 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_WAIT__SRC_BT_CFG_25 \ + (_MX6Q_PAD_EIM_WAIT__SRC_BT_CFG_25 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_EIM_BCLK__WEIM_WEIM_BCLK \ + (_MX6Q_PAD_EIM_BCLK__WEIM_WEIM_BCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16 \ + (_MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_BCLK__GPIO_6_31 \ + (_MX6Q_PAD_EIM_BCLK__GPIO_6_31 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_BCLK__TPSMP_HDATA_31 \ + (_MX6Q_PAD_EIM_BCLK__TPSMP_HDATA_31 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK \ + (_MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT)) +#define MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK \ + (_MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT)) +#define MX6Q_PAD_DI0_DISP_CLK__MIPI_CORE_DPHY_TEST_OUT_28 \ + (_MX6Q_PAD_DI0_DISP_CLK__MIPI_CORE_DPHY_TEST_OUT_28 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 \ + (_MX6Q_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DI0_DISP_CLK__GPIO_4_16 \ + (_MX6Q_PAD_DI0_DISP_CLK__GPIO_4_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DI0_DISP_CLK__MMDC_MMDC_DEBUG_0 \ + (_MX6Q_PAD_DI0_DISP_CLK__MMDC_MMDC_DEBUG_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15 \ + (_MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT)) +#define MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15 \ + (_MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT)) +#define MX6Q_PAD_DI0_PIN15__AUDMUX_AUD6_TXC \ + (_MX6Q_PAD_DI0_PIN15__AUDMUX_AUD6_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DI0_PIN15__MIPI_CORE_DPHY_TEST_OUT_29 \ + (_MX6Q_PAD_DI0_PIN15__MIPI_CORE_DPHY_TEST_OUT_29 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 \ + (_MX6Q_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DI0_PIN15__GPIO_4_17 \ + (_MX6Q_PAD_DI0_PIN15__GPIO_4_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1 \ + (_MX6Q_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2 \ + (_MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT)) +#define MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN2 \ + (_MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN2 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT)) +#define MX6Q_PAD_DI0_PIN2__AUDMUX_AUD6_TXD \ + (_MX6Q_PAD_DI0_PIN2__AUDMUX_AUD6_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DI0_PIN2__MIPI_CORE_DPHY_TEST_OUT_30 \ + (_MX6Q_PAD_DI0_PIN2__MIPI_CORE_DPHY_TEST_OUT_30 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 \ + (_MX6Q_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DI0_PIN2__GPIO_4_18 \ + (_MX6Q_PAD_DI0_PIN2__GPIO_4_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DI0_PIN2__MMDC_MMDC_DEBUG_2 \ + (_MX6Q_PAD_DI0_PIN2__MMDC_MMDC_DEBUG_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DI0_PIN2__PL301_MX6QPER1_HADDR_9 \ + (_MX6Q_PAD_DI0_PIN2__PL301_MX6QPER1_HADDR_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3 \ + (_MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT)) +#define MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN3 \ + (_MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN3 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT)) +#define MX6Q_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS \ + (_MX6Q_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DI0_PIN3__MIPI_CORE_DPHY_TEST_OUT_31 \ + (_MX6Q_PAD_DI0_PIN3__MIPI_CORE_DPHY_TEST_OUT_31 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 \ + (_MX6Q_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DI0_PIN3__GPIO_4_19 \ + (_MX6Q_PAD_DI0_PIN3__GPIO_4_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3 \ + (_MX6Q_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DI0_PIN3__PL301_MX6QPER1_HADDR_10 \ + (_MX6Q_PAD_DI0_PIN3__PL301_MX6QPER1_HADDR_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN4 \ + (_MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DI0_PIN4__IPU2_DI0_PIN4 \ + (_MX6Q_PAD_DI0_PIN4__IPU2_DI0_PIN4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DI0_PIN4__AUDMUX_AUD6_RXD \ + (_MX6Q_PAD_DI0_PIN4__AUDMUX_AUD6_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DI0_PIN4__USDHC1_WP \ + (_MX6Q_PAD_DI0_PIN4__USDHC1_WP | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) +#define MX6Q_PAD_DI0_PIN4__SDMA_DEBUG_YIELD \ + (_MX6Q_PAD_DI0_PIN4__SDMA_DEBUG_YIELD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DI0_PIN4__GPIO_4_20 \ + (_MX6Q_PAD_DI0_PIN4__GPIO_4_20 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4 \ + (_MX6Q_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DI0_PIN4__PL301_MX6QPER1_HADDR_11 \ + (_MX6Q_PAD_DI0_PIN4__PL301_MX6QPER1_HADDR_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 \ + (_MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT)) +#define MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0 \ + (_MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT)) +#define MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK \ + (_MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT0__USDHC1_USDHC_DEBUG_0 \ + (_MX6Q_PAD_DISP0_DAT0__USDHC1_USDHC_DEBUG_0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN \ + (_MX6Q_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT0__GPIO_4_21 \ + (_MX6Q_PAD_DISP0_DAT0__GPIO_4_21 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5 \ + (_MX6Q_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 \ + (_MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT)) +#define MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1 \ + (_MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT)) +#define MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI \ + (_MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT1__USDHC1_USDHC_DEBUG_1 \ + (_MX6Q_PAD_DISP0_DAT1__USDHC1_USDHC_DEBUG_1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL \ + (_MX6Q_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT1__GPIO_4_22 \ + (_MX6Q_PAD_DISP0_DAT1__GPIO_4_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT1__MMDC_MMDC_DEBUG_6 \ + (_MX6Q_PAD_DISP0_DAT1__MMDC_MMDC_DEBUG_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT1__PL301_MX6QPER1_HADDR_12 \ + (_MX6Q_PAD_DISP0_DAT1__PL301_MX6QPER1_HADDR_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 \ + (_MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT)) +#define MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2 \ + (_MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT)) +#define MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO \ + (_MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT2__USDHC1_USDHC_DEBUG_2 \ + (_MX6Q_PAD_DISP0_DAT2__USDHC1_USDHC_DEBUG_2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT2__SDMA_DEBUG_MODE \ + (_MX6Q_PAD_DISP0_DAT2__SDMA_DEBUG_MODE | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT2__GPIO_4_23 \ + (_MX6Q_PAD_DISP0_DAT2__GPIO_4_23 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT2__MMDC_MMDC_DEBUG_7 \ + (_MX6Q_PAD_DISP0_DAT2__MMDC_MMDC_DEBUG_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT2__PL301_MX6QPER1_HADDR_13 \ + (_MX6Q_PAD_DISP0_DAT2__PL301_MX6QPER1_HADDR_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 \ + (_MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT)) +#define MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3 \ + (_MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT)) +#define MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0 \ + (_MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT3__USDHC1_USDHC_DEBUG_3 \ + (_MX6Q_PAD_DISP0_DAT3__USDHC1_USDHC_DEBUG_3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR \ + (_MX6Q_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT3__GPIO_4_24 \ + (_MX6Q_PAD_DISP0_DAT3__GPIO_4_24 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT3__MMDC_MMDC_DEBUG_8 \ + (_MX6Q_PAD_DISP0_DAT3__MMDC_MMDC_DEBUG_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT3__PL301_MX6QPER1_HADDR_14 \ + (_MX6Q_PAD_DISP0_DAT3__PL301_MX6QPER1_HADDR_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 \ + (_MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT)) +#define MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4 \ + (_MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT)) +#define MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1 \ + (_MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT4__USDHC1_USDHC_DEBUG_4 \ + (_MX6Q_PAD_DISP0_DAT4__USDHC1_USDHC_DEBUG_4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB \ + (_MX6Q_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT4__GPIO_4_25 \ + (_MX6Q_PAD_DISP0_DAT4__GPIO_4_25 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9 \ + (_MX6Q_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT4__PL301_MX6QPER1_HADDR_15 \ + (_MX6Q_PAD_DISP0_DAT4__PL301_MX6QPER1_HADDR_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 \ + (_MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT)) +#define MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5 \ + (_MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT)) +#define MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2 \ + (_MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS \ + (_MX6Q_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS \ + (_MX6Q_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT5__GPIO_4_26 \ + (_MX6Q_PAD_DISP0_DAT5__GPIO_4_26 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT5__MMDC_MMDC_DEBUG_10 \ + (_MX6Q_PAD_DISP0_DAT5__MMDC_MMDC_DEBUG_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT5__PL301_MX6QPER1_HADDR_16 \ + (_MX6Q_PAD_DISP0_DAT5__PL301_MX6QPER1_HADDR_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 \ + (_MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT)) +#define MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6 \ + (_MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT)) +#define MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3 \ + (_MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC \ + (_MX6Q_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE \ + (_MX6Q_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT6__GPIO_4_27 \ + (_MX6Q_PAD_DISP0_DAT6__GPIO_4_27 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT6__MMDC_MMDC_DEBUG_11 \ + (_MX6Q_PAD_DISP0_DAT6__MMDC_MMDC_DEBUG_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT6__PL301_MX6QPER1_HADDR_17 \ + (_MX6Q_PAD_DISP0_DAT6__PL301_MX6QPER1_HADDR_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 \ + (_MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT)) +#define MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7 \ + (_MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT)) +#define MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY \ + (_MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT7__USDHC1_USDHC_DEBUG_5 \ + (_MX6Q_PAD_DISP0_DAT7__USDHC1_USDHC_DEBUG_5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 \ + (_MX6Q_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT7__GPIO_4_28 \ + (_MX6Q_PAD_DISP0_DAT7__GPIO_4_28 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT7__MMDC_MMDC_DEBUG_12 \ + (_MX6Q_PAD_DISP0_DAT7__MMDC_MMDC_DEBUG_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT7__PL301_MX6QPER1_HADDR_18 \ + (_MX6Q_PAD_DISP0_DAT7__PL301_MX6QPER1_HADDR_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 \ + (_MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT)) +#define MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8 \ + (_MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT)) +#define MX6Q_PAD_DISP0_DAT8__PWM1_PWMO \ + (_MX6Q_PAD_DISP0_DAT8__PWM1_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT8__WDOG1_WDOG_B \ + (_MX6Q_PAD_DISP0_DAT8__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 \ + (_MX6Q_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT8__GPIO_4_29 \ + (_MX6Q_PAD_DISP0_DAT8__GPIO_4_29 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT8__MMDC_MMDC_DEBUG_13 \ + (_MX6Q_PAD_DISP0_DAT8__MMDC_MMDC_DEBUG_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT8__PL301_MX6QPER1_HADDR_19 \ + (_MX6Q_PAD_DISP0_DAT8__PL301_MX6QPER1_HADDR_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 \ + (_MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT)) +#define MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9 \ + (_MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT)) +#define MX6Q_PAD_DISP0_DAT9__PWM2_PWMO \ + (_MX6Q_PAD_DISP0_DAT9__PWM2_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT9__WDOG2_WDOG_B \ + (_MX6Q_PAD_DISP0_DAT9__WDOG2_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 \ + (_MX6Q_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT9__GPIO_4_30 \ + (_MX6Q_PAD_DISP0_DAT9__GPIO_4_30 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT9__MMDC_MMDC_DEBUG_14 \ + (_MX6Q_PAD_DISP0_DAT9__MMDC_MMDC_DEBUG_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT9__PL301_MX6QPER1_HADDR_20 \ + (_MX6Q_PAD_DISP0_DAT9__PL301_MX6QPER1_HADDR_20 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 \ + (_MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT)) +#define MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10 \ + (_MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT)) +#define MX6Q_PAD_DISP0_DAT10__USDHC1_USDHC_DEBUG_6 \ + (_MX6Q_PAD_DISP0_DAT10__USDHC1_USDHC_DEBUG_6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 \ + (_MX6Q_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT10__GPIO_4_31 \ + (_MX6Q_PAD_DISP0_DAT10__GPIO_4_31 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT10__MMDC_MMDC_DEBUG_15 \ + (_MX6Q_PAD_DISP0_DAT10__MMDC_MMDC_DEBUG_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT10__PL301_MX6QPER1_HADDR_21 \ + (_MX6Q_PAD_DISP0_DAT10__PL301_MX6QPER1_HADDR_21 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 \ + (_MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT)) +#define MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11 \ + (_MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT)) +#define MX6Q_PAD_DISP0_DAT11__USDHC1_USDHC_DEBUG_7 \ + (_MX6Q_PAD_DISP0_DAT11__USDHC1_USDHC_DEBUG_7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 \ + (_MX6Q_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT11__GPIO_5_5 \ + (_MX6Q_PAD_DISP0_DAT11__GPIO_5_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT11__MMDC_MMDC_DEBUG_16 \ + (_MX6Q_PAD_DISP0_DAT11__MMDC_MMDC_DEBUG_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT11__PL301_MX6QPER1_HADDR_22 \ + (_MX6Q_PAD_DISP0_DAT11__PL301_MX6QPER1_HADDR_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 \ + (_MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT)) +#define MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12 \ + (_MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT)) +#define MX6Q_PAD_DISP0_DAT12__RESERVED_RESERVED \ + (_MX6Q_PAD_DISP0_DAT12__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 \ + (_MX6Q_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT12__GPIO_5_6 \ + (_MX6Q_PAD_DISP0_DAT12__GPIO_5_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT12__MMDC_MMDC_DEBUG_17 \ + (_MX6Q_PAD_DISP0_DAT12__MMDC_MMDC_DEBUG_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT12__PL301_MX6QPER1_HADDR_23 \ + (_MX6Q_PAD_DISP0_DAT12__PL301_MX6QPER1_HADDR_23 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 \ + (_MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT)) +#define MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13 \ + (_MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT)) +#define MX6Q_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS \ + (_MX6Q_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 \ + (_MX6Q_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT13__GPIO_5_7 \ + (_MX6Q_PAD_DISP0_DAT13__GPIO_5_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT13__MMDC_MMDC_DEBUG_18 \ + (_MX6Q_PAD_DISP0_DAT13__MMDC_MMDC_DEBUG_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT13__PL301_MX6QPER1_HADDR_24 \ + (_MX6Q_PAD_DISP0_DAT13__PL301_MX6QPER1_HADDR_24 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 \ + (_MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT)) +#define MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14 \ + (_MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT)) +#define MX6Q_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC \ + (_MX6Q_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 \ + (_MX6Q_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT14__GPIO_5_8 \ + (_MX6Q_PAD_DISP0_DAT14__GPIO_5_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT14__MMDC_MMDC_DEBUG_19 \ + (_MX6Q_PAD_DISP0_DAT14__MMDC_MMDC_DEBUG_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 \ + (_MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT)) +#define MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15 \ + (_MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT)) +#define MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1 \ + (_MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT15__ECSPI2_SS1 \ + (_MX6Q_PAD_DISP0_DAT15__ECSPI2_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 \ + (_MX6Q_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT15__GPIO_5_9 \ + (_MX6Q_PAD_DISP0_DAT15__GPIO_5_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT15__MMDC_MMDC_DEBUG_20 \ + (_MX6Q_PAD_DISP0_DAT15__MMDC_MMDC_DEBUG_20 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT15__PL301_MX6QPER1_HADDR_25 \ + (_MX6Q_PAD_DISP0_DAT15__PL301_MX6QPER1_HADDR_25 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 \ + (_MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT)) +#define MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16 \ + (_MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT)) +#define MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI \ + (_MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC \ + (_MX6Q_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT16__SDMA_SDMA_EXT_EVENT_0 \ + (_MX6Q_PAD_DISP0_DAT16__SDMA_SDMA_EXT_EVENT_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT16__GPIO_5_10 \ + (_MX6Q_PAD_DISP0_DAT16__GPIO_5_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT16__MMDC_MMDC_DEBUG_21 \ + (_MX6Q_PAD_DISP0_DAT16__MMDC_MMDC_DEBUG_21 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT16__PL301_MX6QPER1_HADDR_26 \ + (_MX6Q_PAD_DISP0_DAT16__PL301_MX6QPER1_HADDR_26 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 \ + (_MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT)) +#define MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17 \ + (_MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT)) +#define MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO \ + (_MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD \ + (_MX6Q_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT17__SDMA_SDMA_EXT_EVENT_1 \ + (_MX6Q_PAD_DISP0_DAT17__SDMA_SDMA_EXT_EVENT_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT17__GPIO_5_11 \ + (_MX6Q_PAD_DISP0_DAT17__GPIO_5_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT17__MMDC_MMDC_DEBUG_22 \ + (_MX6Q_PAD_DISP0_DAT17__MMDC_MMDC_DEBUG_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT17__PL301_MX6QPER1_HADDR_27 \ + (_MX6Q_PAD_DISP0_DAT17__PL301_MX6QPER1_HADDR_27 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 \ + (_MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT)) +#define MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18 \ + (_MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT)) +#define MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0 \ + (_MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS \ + (_MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS \ + (_MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT18__GPIO_5_12 \ + (_MX6Q_PAD_DISP0_DAT18__GPIO_5_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT18__MMDC_MMDC_DEBUG_23 \ + (_MX6Q_PAD_DISP0_DAT18__MMDC_MMDC_DEBUG_23 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT18__WEIM_WEIM_CS_2 \ + (_MX6Q_PAD_DISP0_DAT18__WEIM_WEIM_CS_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 \ + (_MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT)) +#define MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19 \ + (_MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT)) +#define MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK \ + (_MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD \ + (_MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC \ + (_MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT19__GPIO_5_13 \ + (_MX6Q_PAD_DISP0_DAT19__GPIO_5_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT19__MMDC_MMDC_DEBUG_24 \ + (_MX6Q_PAD_DISP0_DAT19__MMDC_MMDC_DEBUG_24 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT19__WEIM_WEIM_CS_3 \ + (_MX6Q_PAD_DISP0_DAT19__WEIM_WEIM_CS_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 \ + (_MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT)) +#define MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20 \ + (_MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT)) +#define MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK \ + (_MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC \ + (_MX6Q_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 \ + (_MX6Q_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT20__GPIO_5_14 \ + (_MX6Q_PAD_DISP0_DAT20__GPIO_5_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT20__MMDC_MMDC_DEBUG_25 \ + (_MX6Q_PAD_DISP0_DAT20__MMDC_MMDC_DEBUG_25 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT20__PL301_MX6QPER1_HADDR_28 \ + (_MX6Q_PAD_DISP0_DAT20__PL301_MX6QPER1_HADDR_28 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 \ + (_MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT)) +#define MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21 \ + (_MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT)) +#define MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI \ + (_MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD \ + (_MX6Q_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 \ + (_MX6Q_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT21__GPIO_5_15 \ + (_MX6Q_PAD_DISP0_DAT21__GPIO_5_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT21__MMDC_MMDC_DEBUG_26 \ + (_MX6Q_PAD_DISP0_DAT21__MMDC_MMDC_DEBUG_26 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT21__PL301_MX6QPER1_HADDR_29 \ + (_MX6Q_PAD_DISP0_DAT21__PL301_MX6QPER1_HADDR_29 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 \ + (_MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT)) +#define MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22 \ + (_MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT)) +#define MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO \ + (_MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS \ + (_MX6Q_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 \ + (_MX6Q_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT22__GPIO_5_16 \ + (_MX6Q_PAD_DISP0_DAT22__GPIO_5_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT22__MMDC_MMDC_DEBUG_27 \ + (_MX6Q_PAD_DISP0_DAT22__MMDC_MMDC_DEBUG_27 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT22__PL301_MX6QPER1_HADDR_30 \ + (_MX6Q_PAD_DISP0_DAT22__PL301_MX6QPER1_HADDR_30 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 \ + (_MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT)) +#define MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23 \ + (_MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT)) +#define MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0 \ + (_MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD \ + (_MX6Q_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 \ + (_MX6Q_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT23__GPIO_5_17 \ + (_MX6Q_PAD_DISP0_DAT23__GPIO_5_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT23__MMDC_MMDC_DEBUG_28 \ + (_MX6Q_PAD_DISP0_DAT23__MMDC_MMDC_DEBUG_28 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_DISP0_DAT23__PL301_MX6QPER1_HADDR_31 \ + (_MX6Q_PAD_DISP0_DAT23__PL301_MX6QPER1_HADDR_31 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_ENET_MDIO__RESERVED_RESERVED \ + (_MX6Q_PAD_ENET_MDIO__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_ENET_MDIO__ENET_MDIO \ + (_MX6Q_PAD_ENET_MDIO__ENET_MDIO | \ + MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL)) +#define MX6Q_PAD_ENET_MDIO__ESAI1_SCKR \ + (_MX6Q_PAD_ENET_MDIO__ESAI1_SCKR | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL)) +#define MX6Q_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEVICE_3 \ + (_MX6Q_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEVICE_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT \ + (_MX6Q_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_ENET_MDIO__GPIO_1_22 \ + (_MX6Q_PAD_ENET_MDIO__GPIO_1_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_ENET_MDIO__SPDIF_PLOCK \ + (_MX6Q_PAD_ENET_MDIO__SPDIF_PLOCK | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_ENET_REF_CLK__RESERVED_RESERVED \ + (_MX6Q_PAD_ENET_REF_CLK__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK \ + (_MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(MX6Q_ENET_REF_CLK_PAD_CTRL)) +#define MX6Q_PAD_ENET_REF_CLK__ESAI1_FSR \ + (_MX6Q_PAD_ENET_REF_CLK__ESAI1_FSR | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL)) +#define MX6Q_PAD_ENET_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 \ + (_MX6Q_PAD_ENET_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_ENET_REF_CLK__GPIO_1_23 \ + (_MX6Q_PAD_ENET_REF_CLK__GPIO_1_23 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_ENET_REF_CLK__SPDIF_SRCLK \ + (_MX6Q_PAD_ENET_REF_CLK__SPDIF_SRCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_ENET_REF_CLK__ANATOP_USBPHY1_TSTO_RX_SQUELCH \ + (_MX6Q_PAD_ENET_REF_CLK__ANATOP_USBPHY1_TSTO_RX_SQUELCH | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_ENET_RX_ER__ANATOP_USBOTG_ID \ + (_MX6Q_PAD_ENET_RX_ER__ANATOP_USBOTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_ENET_RX_ER__ENET_RX_ER \ + (_MX6Q_PAD_ENET_RX_ER__ENET_RX_ER | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_ENET_RX_ER__ESAI1_HCKR \ + (_MX6Q_PAD_ENET_RX_ER__ESAI1_HCKR | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL)) +#define MX6Q_PAD_ENET_RX_ER__SPDIF_IN1 \ + (_MX6Q_PAD_ENET_RX_ER__SPDIF_IN1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT \ + (_MX6Q_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_ENET_RX_ER__GPIO_1_24 \ + (_MX6Q_PAD_ENET_RX_ER__GPIO_1_24 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_ENET_RX_ER__PHY_TDI \ + (_MX6Q_PAD_ENET_RX_ER__PHY_TDI | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_ENET_RX_ER__ANATOP_USBPHY1_TSTO_RX_HS_RXD \ + (_MX6Q_PAD_ENET_RX_ER__ANATOP_USBPHY1_TSTO_RX_HS_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_ENET_CRS_DV__RESERVED_RESERVED \ + (_MX6Q_PAD_ENET_CRS_DV__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN \ + (_MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_ENET_CRS_DV__ESAI1_SCKT \ + (_MX6Q_PAD_ENET_CRS_DV__ESAI1_SCKT | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL)) +#define MX6Q_PAD_ENET_CRS_DV__SPDIF_SPDIF_EXTCLK \ + (_MX6Q_PAD_ENET_CRS_DV__SPDIF_SPDIF_EXTCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_ENET_CRS_DV__GPIO_1_25 \ + (_MX6Q_PAD_ENET_CRS_DV__GPIO_1_25 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_ENET_CRS_DV__PHY_TDO \ + (_MX6Q_PAD_ENET_CRS_DV__PHY_TDO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_ENET_CRS_DV__ANATOP_USBPHY1_TSTO_RX_FS_RXD \ + (_MX6Q_PAD_ENET_CRS_DV__ANATOP_USBPHY1_TSTO_RX_FS_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_ENET_RXD1__MLB_MLBSIG \ + (_MX6Q_PAD_ENET_RXD1__MLB_MLBSIG | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_ENET_RXD1__ENET_RDATA_1 \ + (_MX6Q_PAD_ENET_RXD1__ENET_RDATA_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_ENET_RXD1__ESAI1_FST \ + (_MX6Q_PAD_ENET_RXD1__ESAI1_FST | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL)) +#define MX6Q_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT \ + (_MX6Q_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_ENET_RXD1__GPIO_1_26 \ + (_MX6Q_PAD_ENET_RXD1__GPIO_1_26 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_ENET_RXD1__PHY_TCK \ + (_MX6Q_PAD_ENET_RXD1__PHY_TCK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_ENET_RXD1__ANATOP_USBPHY1_TSTO_RX_DISCON_DET \ + (_MX6Q_PAD_ENET_RXD1__ANATOP_USBPHY1_TSTO_RX_DISCON_DET | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_ENET_RXD0__OSC32K_32K_OUT \ + (_MX6Q_PAD_ENET_RXD0__OSC32K_32K_OUT | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_ENET_RXD0__ENET_RDATA_0 \ + (_MX6Q_PAD_ENET_RXD0__ENET_RDATA_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_ENET_RXD0__ESAI1_HCKT \ + (_MX6Q_PAD_ENET_RXD0__ESAI1_HCKT | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL)) +#define MX6Q_PAD_ENET_RXD0__SPDIF_OUT1 \ + (_MX6Q_PAD_ENET_RXD0__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_ENET_RXD0__GPIO_1_27 \ + (_MX6Q_PAD_ENET_RXD0__GPIO_1_27 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_ENET_RXD0__PHY_TMS \ + (_MX6Q_PAD_ENET_RXD0__PHY_TMS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_ENET_RXD0__ANATOP_USBPHY1_TSTO_PLL_CLK20DIV \ + (_MX6Q_PAD_ENET_RXD0__ANATOP_USBPHY1_TSTO_PLL_CLK20DIV | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_ENET_TX_EN__RESERVED_RESERVED \ + (_MX6Q_PAD_ENET_TX_EN__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_ENET_TX_EN__ENET_TX_EN \ + (_MX6Q_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_ENET_TX_EN__ESAI1_TX3_RX2 \ + (_MX6Q_PAD_ENET_TX_EN__ESAI1_TX3_RX2 | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL)) +#define MX6Q_PAD_ENET_TX_EN__GPIO_1_28 \ + (_MX6Q_PAD_ENET_TX_EN__GPIO_1_28 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_ENET_TX_EN__SATA_PHY_TDI \ + (_MX6Q_PAD_ENET_TX_EN__SATA_PHY_TDI | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_ENET_TX_EN__ANATOP_USBPHY2_TSTO_RX_SQUELCH \ + (_MX6Q_PAD_ENET_TX_EN__ANATOP_USBPHY2_TSTO_RX_SQUELCH | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_ENET_TXD1__MLB_MLBCLK \ + (_MX6Q_PAD_ENET_TXD1__MLB_MLBCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_ENET_TXD1__ENET_TDATA_1 \ + (_MX6Q_PAD_ENET_TXD1__ENET_TDATA_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_ENET_TXD1__ESAI1_TX2_RX3 \ + (_MX6Q_PAD_ENET_TXD1__ESAI1_TX2_RX3 | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL)) +#define MX6Q_PAD_ENET_TXD1__ENET_1588_EVENT0_IN \ + (_MX6Q_PAD_ENET_TXD1__ENET_1588_EVENT0_IN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_ENET_TXD1__GPIO_1_29 \ + (_MX6Q_PAD_ENET_TXD1__GPIO_1_29 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_ENET_TXD1__SATA_PHY_TDO \ + (_MX6Q_PAD_ENET_TXD1__SATA_PHY_TDO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_ENET_TXD1__ANATOP_USBPHY2_TSTO_RX_HS_RXD \ + (_MX6Q_PAD_ENET_TXD1__ANATOP_USBPHY2_TSTO_RX_HS_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_ENET_TXD0__RESERVED_RESERVED \ + (_MX6Q_PAD_ENET_TXD0__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_ENET_TXD0__ENET_TDATA_0 \ + (_MX6Q_PAD_ENET_TXD0__ENET_TDATA_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_ENET_TXD0__ESAI1_TX4_RX1 \ + (_MX6Q_PAD_ENET_TXD0__ESAI1_TX4_RX1 | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL)) +#define MX6Q_PAD_ENET_TXD0__GPIO_1_30 \ + (_MX6Q_PAD_ENET_TXD0__GPIO_1_30 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_ENET_TXD0__SATA_PHY_TCK \ + (_MX6Q_PAD_ENET_TXD0__SATA_PHY_TCK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_ENET_TXD0__ANATOP_USBPHY2_TSTO_RX_FS_RXD \ + (_MX6Q_PAD_ENET_TXD0__ANATOP_USBPHY2_TSTO_RX_FS_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_ENET_MDC__MLB_MLBDAT \ + (_MX6Q_PAD_ENET_MDC__MLB_MLBDAT | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_ENET_MDC__ENET_MDC \ + (_MX6Q_PAD_ENET_MDC__ENET_MDC | \ + MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL)) +#define MX6Q_PAD_ENET_MDC__ESAI1_TX5_RX0 \ + (_MX6Q_PAD_ENET_MDC__ESAI1_TX5_RX0 | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL)) +#define MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN \ + (_MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_ENET_MDC__GPIO_1_31 \ + (_MX6Q_PAD_ENET_MDC__GPIO_1_31 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_ENET_MDC__SATA_PHY_TMS \ + (_MX6Q_PAD_ENET_MDC__SATA_PHY_TMS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_ENET_MDC__ANATOP_USBPHY2_TSTO_RX_DISCON_DET \ + (_MX6Q_PAD_ENET_MDC__ANATOP_USBPHY2_TSTO_RX_DISCON_DET | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_D40__MMDC_DRAM_D_40 \ + (_MX6Q_PAD_DRAM_D40__MMDC_DRAM_D_40 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_D41__MMDC_DRAM_D_41 \ + (_MX6Q_PAD_DRAM_D41__MMDC_DRAM_D_41 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_D42__MMDC_DRAM_D_42 \ + (_MX6Q_PAD_DRAM_D42__MMDC_DRAM_D_42 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_D43__MMDC_DRAM_D_43 \ + (_MX6Q_PAD_DRAM_D43__MMDC_DRAM_D_43 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_D44__MMDC_DRAM_D_44 \ + (_MX6Q_PAD_DRAM_D44__MMDC_DRAM_D_44 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_D45__MMDC_DRAM_D_45 \ + (_MX6Q_PAD_DRAM_D45__MMDC_DRAM_D_45 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_D46__MMDC_DRAM_D_46 \ + (_MX6Q_PAD_DRAM_D46__MMDC_DRAM_D_46 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_D47__MMDC_DRAM_D_47 \ + (_MX6Q_PAD_DRAM_D47__MMDC_DRAM_D_47 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5 \ + (_MX6Q_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5 \ + (_MX6Q_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_D32__MMDC_DRAM_D_32 \ + (_MX6Q_PAD_DRAM_D32__MMDC_DRAM_D_32 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_D33__MMDC_DRAM_D_33 \ + (_MX6Q_PAD_DRAM_D33__MMDC_DRAM_D_33 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_D34__MMDC_DRAM_D_34 \ + (_MX6Q_PAD_DRAM_D34__MMDC_DRAM_D_34 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_D35__MMDC_DRAM_D_35 \ + (_MX6Q_PAD_DRAM_D35__MMDC_DRAM_D_35 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_D36__MMDC_DRAM_D_36 \ + (_MX6Q_PAD_DRAM_D36__MMDC_DRAM_D_36 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_D37__MMDC_DRAM_D_37 \ + (_MX6Q_PAD_DRAM_D37__MMDC_DRAM_D_37 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_D38__MMDC_DRAM_D_38 \ + (_MX6Q_PAD_DRAM_D38__MMDC_DRAM_D_38 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_D39__MMDC_DRAM_D_39 \ + (_MX6Q_PAD_DRAM_D39__MMDC_DRAM_D_39 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4 \ + (_MX6Q_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4 \ + (_MX6Q_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_D24__MMDC_DRAM_D_24 \ + (_MX6Q_PAD_DRAM_D24__MMDC_DRAM_D_24 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_D25__MMDC_DRAM_D_25 \ + (_MX6Q_PAD_DRAM_D25__MMDC_DRAM_D_25 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_D26__MMDC_DRAM_D_26 \ + (_MX6Q_PAD_DRAM_D26__MMDC_DRAM_D_26 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_D27__MMDC_DRAM_D_27 \ + (_MX6Q_PAD_DRAM_D27__MMDC_DRAM_D_27 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_D28__MMDC_DRAM_D_28 \ + (_MX6Q_PAD_DRAM_D28__MMDC_DRAM_D_28 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_D29__MMDC_DRAM_D_29 \ + (_MX6Q_PAD_DRAM_D29__MMDC_DRAM_D_29 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3 \ + (_MX6Q_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_D30__MMDC_DRAM_D_30 \ + (_MX6Q_PAD_DRAM_D30__MMDC_DRAM_D_30 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_D31__MMDC_DRAM_D_31 \ + (_MX6Q_PAD_DRAM_D31__MMDC_DRAM_D_31 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3 \ + (_MX6Q_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_D16__MMDC_DRAM_D_16 \ + (_MX6Q_PAD_DRAM_D16__MMDC_DRAM_D_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_D17__MMDC_DRAM_D_17 \ + (_MX6Q_PAD_DRAM_D17__MMDC_DRAM_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_D18__MMDC_DRAM_D_18 \ + (_MX6Q_PAD_DRAM_D18__MMDC_DRAM_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_D19__MMDC_DRAM_D_19 \ + (_MX6Q_PAD_DRAM_D19__MMDC_DRAM_D_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_D20__MMDC_DRAM_D_20 \ + (_MX6Q_PAD_DRAM_D20__MMDC_DRAM_D_20 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_D21__MMDC_DRAM_D_21 \ + (_MX6Q_PAD_DRAM_D21__MMDC_DRAM_D_21 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_D22__MMDC_DRAM_D_22 \ + (_MX6Q_PAD_DRAM_D22__MMDC_DRAM_D_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2 \ + (_MX6Q_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_D23__MMDC_DRAM_D_23 \ + (_MX6Q_PAD_DRAM_D23__MMDC_DRAM_D_23 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2 \ + (_MX6Q_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_A0__MMDC_DRAM_A_0 \ + (_MX6Q_PAD_DRAM_A0__MMDC_DRAM_A_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_A1__MMDC_DRAM_A_1 \ + (_MX6Q_PAD_DRAM_A1__MMDC_DRAM_A_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_A2__MMDC_DRAM_A_2 \ + (_MX6Q_PAD_DRAM_A2__MMDC_DRAM_A_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_A3__MMDC_DRAM_A_3 \ + (_MX6Q_PAD_DRAM_A3__MMDC_DRAM_A_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_A4__MMDC_DRAM_A_4 \ + (_MX6Q_PAD_DRAM_A4__MMDC_DRAM_A_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_A5__MMDC_DRAM_A_5 \ + (_MX6Q_PAD_DRAM_A5__MMDC_DRAM_A_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_A6__MMDC_DRAM_A_6 \ + (_MX6Q_PAD_DRAM_A6__MMDC_DRAM_A_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_A7__MMDC_DRAM_A_7 \ + (_MX6Q_PAD_DRAM_A7__MMDC_DRAM_A_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_A8__MMDC_DRAM_A_8 \ + (_MX6Q_PAD_DRAM_A8__MMDC_DRAM_A_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_A9__MMDC_DRAM_A_9 \ + (_MX6Q_PAD_DRAM_A9__MMDC_DRAM_A_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_A10__MMDC_DRAM_A_10 \ + (_MX6Q_PAD_DRAM_A10__MMDC_DRAM_A_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_A11__MMDC_DRAM_A_11 \ + (_MX6Q_PAD_DRAM_A11__MMDC_DRAM_A_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_A12__MMDC_DRAM_A_12 \ + (_MX6Q_PAD_DRAM_A12__MMDC_DRAM_A_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_A13__MMDC_DRAM_A_13 \ + (_MX6Q_PAD_DRAM_A13__MMDC_DRAM_A_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_A14__MMDC_DRAM_A_14 \ + (_MX6Q_PAD_DRAM_A14__MMDC_DRAM_A_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_A15__MMDC_DRAM_A_15 \ + (_MX6Q_PAD_DRAM_A15__MMDC_DRAM_A_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_CAS__MMDC_DRAM_CAS \ + (_MX6Q_PAD_DRAM_CAS__MMDC_DRAM_CAS | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_CS0__MMDC_DRAM_CS_0 \ + (_MX6Q_PAD_DRAM_CS0__MMDC_DRAM_CS_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_CS1__MMDC_DRAM_CS_1 \ + (_MX6Q_PAD_DRAM_CS1__MMDC_DRAM_CS_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_RAS__MMDC_DRAM_RAS \ + (_MX6Q_PAD_DRAM_RAS__MMDC_DRAM_RAS | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_RESET__MMDC_DRAM_RESET \ + (_MX6Q_PAD_DRAM_RESET__MMDC_DRAM_RESET | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0 \ + (_MX6Q_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1 \ + (_MX6Q_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0 \ + (_MX6Q_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2 \ + (_MX6Q_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0 \ + (_MX6Q_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1 \ + (_MX6Q_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1 \ + (_MX6Q_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0 \ + (_MX6Q_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1 \ + (_MX6Q_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_SDWE__MMDC_DRAM_SDWE \ + (_MX6Q_PAD_DRAM_SDWE__MMDC_DRAM_SDWE | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_D0__MMDC_DRAM_D_0 \ + (_MX6Q_PAD_DRAM_D0__MMDC_DRAM_D_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_D1__MMDC_DRAM_D_1 \ + (_MX6Q_PAD_DRAM_D1__MMDC_DRAM_D_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_D2__MMDC_DRAM_D_2 \ + (_MX6Q_PAD_DRAM_D2__MMDC_DRAM_D_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_D3__MMDC_DRAM_D_3 \ + (_MX6Q_PAD_DRAM_D3__MMDC_DRAM_D_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_D4__MMDC_DRAM_D_4 \ + (_MX6Q_PAD_DRAM_D4__MMDC_DRAM_D_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_D5__MMDC_DRAM_D_5 \ + (_MX6Q_PAD_DRAM_D5__MMDC_DRAM_D_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0 \ + (_MX6Q_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_D6__MMDC_DRAM_D_6 \ + (_MX6Q_PAD_DRAM_D6__MMDC_DRAM_D_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_D7__MMDC_DRAM_D_7 \ + (_MX6Q_PAD_DRAM_D7__MMDC_DRAM_D_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0 \ + (_MX6Q_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_D8__MMDC_DRAM_D_8 \ + (_MX6Q_PAD_DRAM_D8__MMDC_DRAM_D_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_D9__MMDC_DRAM_D_9 \ + (_MX6Q_PAD_DRAM_D9__MMDC_DRAM_D_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_D10__MMDC_DRAM_D_10 \ + (_MX6Q_PAD_DRAM_D10__MMDC_DRAM_D_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_D11__MMDC_DRAM_D_11 \ + (_MX6Q_PAD_DRAM_D11__MMDC_DRAM_D_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_D12__MMDC_DRAM_D_12 \ + (_MX6Q_PAD_DRAM_D12__MMDC_DRAM_D_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_D13__MMDC_DRAM_D_13 \ + (_MX6Q_PAD_DRAM_D13__MMDC_DRAM_D_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_D14__MMDC_DRAM_D_14 \ + (_MX6Q_PAD_DRAM_D14__MMDC_DRAM_D_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1 \ + (_MX6Q_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_D15__MMDC_DRAM_D_15 \ + (_MX6Q_PAD_DRAM_D15__MMDC_DRAM_D_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1 \ + (_MX6Q_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_D48__MMDC_DRAM_D_48 \ + (_MX6Q_PAD_DRAM_D48__MMDC_DRAM_D_48 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_D49__MMDC_DRAM_D_49 \ + (_MX6Q_PAD_DRAM_D49__MMDC_DRAM_D_49 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_D50__MMDC_DRAM_D_50 \ + (_MX6Q_PAD_DRAM_D50__MMDC_DRAM_D_50 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_D51__MMDC_DRAM_D_51 \ + (_MX6Q_PAD_DRAM_D51__MMDC_DRAM_D_51 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_D52__MMDC_DRAM_D_52 \ + (_MX6Q_PAD_DRAM_D52__MMDC_DRAM_D_52 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_D53__MMDC_DRAM_D_53 \ + (_MX6Q_PAD_DRAM_D53__MMDC_DRAM_D_53 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_D54__MMDC_DRAM_D_54 \ + (_MX6Q_PAD_DRAM_D54__MMDC_DRAM_D_54 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_D55__MMDC_DRAM_D_55 \ + (_MX6Q_PAD_DRAM_D55__MMDC_DRAM_D_55 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6 \ + (_MX6Q_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6 \ + (_MX6Q_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_D56__MMDC_DRAM_D_56 \ + (_MX6Q_PAD_DRAM_D56__MMDC_DRAM_D_56 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7 \ + (_MX6Q_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_D57__MMDC_DRAM_D_57 \ + (_MX6Q_PAD_DRAM_D57__MMDC_DRAM_D_57 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_D58__MMDC_DRAM_D_58 \ + (_MX6Q_PAD_DRAM_D58__MMDC_DRAM_D_58 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_D59__MMDC_DRAM_D_59 \ + (_MX6Q_PAD_DRAM_D59__MMDC_DRAM_D_59 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_D60__MMDC_DRAM_D_60 \ + (_MX6Q_PAD_DRAM_D60__MMDC_DRAM_D_60 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7 \ + (_MX6Q_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_D61__MMDC_DRAM_D_61 \ + (_MX6Q_PAD_DRAM_D61__MMDC_DRAM_D_61 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_D62__MMDC_DRAM_D_62 \ + (_MX6Q_PAD_DRAM_D62__MMDC_DRAM_D_62 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_DRAM_D63__MMDC_DRAM_D_63 \ + (_MX6Q_PAD_DRAM_D63__MMDC_DRAM_D_63 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_KEY_COL0__ECSPI1_SCLK \ + (_MX6Q_PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_KEY_COL0__ENET_RDATA_3 \ + (_MX6Q_PAD_KEY_COL0__ENET_RDATA_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_KEY_COL0__AUDMUX_AUD5_TXC \ + (_MX6Q_PAD_KEY_COL0__AUDMUX_AUD5_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_KEY_COL0__KPP_COL_0 \ + (_MX6Q_PAD_KEY_COL0__KPP_COL_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_KEY_COL0__UART4_TXD \ + (_MX6Q_PAD_KEY_COL0__UART4_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) +#define MX6Q_PAD_KEY_COL0__UART4_RXD \ + (_MX6Q_PAD_KEY_COL0__UART4_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) +#define MX6Q_PAD_KEY_COL0__GPIO_4_6 \ + (_MX6Q_PAD_KEY_COL0__GPIO_4_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_KEY_COL0__DCIC1_DCIC_OUT \ + (_MX6Q_PAD_KEY_COL0__DCIC1_DCIC_OUT | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_KEY_COL0__SRC_ANY_PU_RST \ + (_MX6Q_PAD_KEY_COL0__SRC_ANY_PU_RST | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI \ + (_MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_KEY_ROW0__ENET_TDATA_3 \ + (_MX6Q_PAD_KEY_ROW0__ENET_TDATA_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_KEY_ROW0__AUDMUX_AUD5_TXD \ + (_MX6Q_PAD_KEY_ROW0__AUDMUX_AUD5_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_KEY_ROW0__KPP_ROW_0 \ + (_MX6Q_PAD_KEY_ROW0__KPP_ROW_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_KEY_ROW0__UART4_TXD \ + (_MX6Q_PAD_KEY_ROW0__UART4_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) +#define MX6Q_PAD_KEY_ROW0__UART4_RXD \ + (_MX6Q_PAD_KEY_ROW0__UART4_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) +#define MX6Q_PAD_KEY_ROW0__GPIO_4_7 \ + (_MX6Q_PAD_KEY_ROW0__GPIO_4_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_KEY_ROW0__DCIC2_DCIC_OUT \ + (_MX6Q_PAD_KEY_ROW0__DCIC2_DCIC_OUT | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_KEY_ROW0__PL301_MX6QPER1_HADDR_0 \ + (_MX6Q_PAD_KEY_ROW0__PL301_MX6QPER1_HADDR_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_KEY_COL1__ECSPI1_MISO \ + (_MX6Q_PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_KEY_COL1__ENET_MDIO \ + (_MX6Q_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL)) +#define MX6Q_PAD_KEY_COL1__AUDMUX_AUD5_TXFS \ + (_MX6Q_PAD_KEY_COL1__AUDMUX_AUD5_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_KEY_COL1__KPP_COL_1 \ + (_MX6Q_PAD_KEY_COL1__KPP_COL_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_KEY_COL1__UART5_TXD \ + (_MX6Q_PAD_KEY_COL1__UART5_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) +#define MX6Q_PAD_KEY_COL1__UART5_RXD \ + (_MX6Q_PAD_KEY_COL1__UART5_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) +#define MX6Q_PAD_KEY_COL1__GPIO_4_8 \ + (_MX6Q_PAD_KEY_COL1__GPIO_4_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_KEY_COL1__USDHC1_VSELECT \ + (_MX6Q_PAD_KEY_COL1__USDHC1_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) +#define MX6Q_PAD_KEY_COL1__PL301_MX6QPER1_HADDR_1 \ + (_MX6Q_PAD_KEY_COL1__PL301_MX6QPER1_HADDR_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_KEY_ROW1__ECSPI1_SS0 \ + (_MX6Q_PAD_KEY_ROW1__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_KEY_ROW1__ENET_COL \ + (_MX6Q_PAD_KEY_ROW1__ENET_COL | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_KEY_ROW1__AUDMUX_AUD5_RXD \ + (_MX6Q_PAD_KEY_ROW1__AUDMUX_AUD5_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_KEY_ROW1__KPP_ROW_1 \ + (_MX6Q_PAD_KEY_ROW1__KPP_ROW_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_KEY_ROW1__UART5_TXD \ + (_MX6Q_PAD_KEY_ROW1__UART5_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) +#define MX6Q_PAD_KEY_ROW1__UART5_RXD \ + (_MX6Q_PAD_KEY_ROW1__UART5_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) +#define MX6Q_PAD_KEY_ROW1__GPIO_4_9 \ + (_MX6Q_PAD_KEY_ROW1__GPIO_4_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_KEY_ROW1__USDHC2_VSELECT \ + (_MX6Q_PAD_KEY_ROW1__USDHC2_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) +#define MX6Q_PAD_KEY_ROW1__PL301_MX6QPER1_HADDR_2 \ + (_MX6Q_PAD_KEY_ROW1__PL301_MX6QPER1_HADDR_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_KEY_COL2__ECSPI1_SS1 \ + (_MX6Q_PAD_KEY_COL2__ECSPI1_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_KEY_COL2__ENET_RDATA_2 \ + (_MX6Q_PAD_KEY_COL2__ENET_RDATA_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_KEY_COL2__CAN1_TXCAN \ + (_MX6Q_PAD_KEY_COL2__CAN1_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_KEY_COL2__KPP_COL_2 \ + (_MX6Q_PAD_KEY_COL2__KPP_COL_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_KEY_COL2__ENET_MDC \ + (_MX6Q_PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL)) +#define MX6Q_PAD_KEY_COL2__GPIO_4_10 \ + (_MX6Q_PAD_KEY_COL2__GPIO_4_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_KEY_COL2__USBOH3_H1USB_PWRCTL_WAKEUP \ + (_MX6Q_PAD_KEY_COL2__USBOH3_H1USB_PWRCTL_WAKEUP | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_KEY_COL2__PL301_MX6QPER1_HADDR_3 \ + (_MX6Q_PAD_KEY_COL2__PL301_MX6QPER1_HADDR_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_KEY_ROW2__ECSPI1_SS2 \ + (_MX6Q_PAD_KEY_ROW2__ECSPI1_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_KEY_ROW2__ENET_TDATA_2 \ + (_MX6Q_PAD_KEY_ROW2__ENET_TDATA_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_KEY_ROW2__CAN1_RXCAN \ + (_MX6Q_PAD_KEY_ROW2__CAN1_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_KEY_ROW2__KPP_ROW_2 \ + (_MX6Q_PAD_KEY_ROW2__KPP_ROW_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_KEY_ROW2__USDHC2_VSELECT \ + (_MX6Q_PAD_KEY_ROW2__USDHC2_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) +#define MX6Q_PAD_KEY_ROW2__GPIO_4_11 \ + (_MX6Q_PAD_KEY_ROW2__GPIO_4_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE \ + (_MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE | MUX_PAD_CTRL(MX6Q_HDMICEC_PAD_CTRL)) +#define MX6Q_PAD_KEY_ROW2__PL301_MX6QPER1_HADDR_4 \ + (_MX6Q_PAD_KEY_ROW2__PL301_MX6QPER1_HADDR_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_KEY_COL3__ECSPI1_SS3 \ + (_MX6Q_PAD_KEY_COL3__ECSPI1_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_KEY_COL3__ENET_CRS \ + (_MX6Q_PAD_KEY_COL3__ENET_CRS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL \ + (_MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL)) +#define MX6Q_PAD_KEY_COL3__KPP_COL_3 \ + (_MX6Q_PAD_KEY_COL3__KPP_COL_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_KEY_COL3__I2C2_SCL \ + (_MX6Q_PAD_KEY_COL3__I2C2_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL)) +#define MX6Q_PAD_KEY_COL3__GPIO_4_12 \ + (_MX6Q_PAD_KEY_COL3__GPIO_4_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_KEY_COL3__SPDIF_IN1 \ + (_MX6Q_PAD_KEY_COL3__SPDIF_IN1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_KEY_COL3__PL301_MX6QPER1_HADDR_5 \ + (_MX6Q_PAD_KEY_COL3__PL301_MX6QPER1_HADDR_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_KEY_ROW3__OSC32K_32K_OUT \ + (_MX6Q_PAD_KEY_ROW3__OSC32K_32K_OUT | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK \ + (_MX6Q_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA \ + (_MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL)) +#define MX6Q_PAD_KEY_ROW3__KPP_ROW_3 \ + (_MX6Q_PAD_KEY_ROW3__KPP_ROW_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_KEY_ROW3__I2C2_SDA \ + (_MX6Q_PAD_KEY_ROW3__I2C2_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL)) +#define MX6Q_PAD_KEY_ROW3__GPIO_4_13 \ + (_MX6Q_PAD_KEY_ROW3__GPIO_4_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_KEY_ROW3__USDHC1_VSELECT \ + (_MX6Q_PAD_KEY_ROW3__USDHC1_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) +#define MX6Q_PAD_KEY_ROW3__PL301_MX6QPER1_HADDR_6 \ + (_MX6Q_PAD_KEY_ROW3__PL301_MX6QPER1_HADDR_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_KEY_COL4__CAN2_TXCAN \ + (_MX6Q_PAD_KEY_COL4__CAN2_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_KEY_COL4__IPU1_SISG_4 \ + (_MX6Q_PAD_KEY_COL4__IPU1_SISG_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_KEY_COL4__USBOH3_USBOTG_OC \ + (_MX6Q_PAD_KEY_COL4__USBOH3_USBOTG_OC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_KEY_COL4__KPP_COL_4 \ + (_MX6Q_PAD_KEY_COL4__KPP_COL_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_KEY_COL4__UART5_CTS \ + (_MX6Q_PAD_KEY_COL4__UART5_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) +#define MX6Q_PAD_KEY_COL4__UART5_RTS \ + (_MX6Q_PAD_KEY_COL4__UART5_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) +#define MX6Q_PAD_KEY_COL4__GPIO_4_14 \ + (_MX6Q_PAD_KEY_COL4__GPIO_4_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_KEY_COL4__MMDC_MMDC_DEBUG_49 \ + (_MX6Q_PAD_KEY_COL4__MMDC_MMDC_DEBUG_49 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_KEY_COL4__PL301_MX6QPER1_HADDR_7 \ + (_MX6Q_PAD_KEY_COL4__PL301_MX6QPER1_HADDR_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_KEY_ROW4__CAN2_RXCAN \ + (_MX6Q_PAD_KEY_ROW4__CAN2_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_KEY_ROW4__IPU1_SISG_5 \ + (_MX6Q_PAD_KEY_ROW4__IPU1_SISG_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_KEY_ROW4__USBOH3_USBOTG_PWR \ + (_MX6Q_PAD_KEY_ROW4__USBOH3_USBOTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_KEY_ROW4__KPP_ROW_4 \ + (_MX6Q_PAD_KEY_ROW4__KPP_ROW_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_KEY_ROW4__UART5_CTS \ + (_MX6Q_PAD_KEY_ROW4__UART5_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) +#define MX6Q_PAD_KEY_ROW4__GPIO_4_15 \ + (_MX6Q_PAD_KEY_ROW4__GPIO_4_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_KEY_ROW4__MMDC_MMDC_DEBUG_50 \ + (_MX6Q_PAD_KEY_ROW4__MMDC_MMDC_DEBUG_50 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_KEY_ROW4__PL301_MX6QPER1_HADDR_8 \ + (_MX6Q_PAD_KEY_ROW4__PL301_MX6QPER1_HADDR_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_GPIO_0__CCM_CLKO \ + (_MX6Q_PAD_GPIO_0__CCM_CLKO | MUX_PAD_CTRL(MX6Q_CCM_CLK0_PAD_CTRL)) +#define MX6Q_PAD_GPIO_0__KPP_COL_5 \ + (_MX6Q_PAD_GPIO_0__KPP_COL_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_GPIO_0__ASRC_ASRC_EXT_CLK \ + (_MX6Q_PAD_GPIO_0__ASRC_ASRC_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_GPIO_0__EPIT1_EPITO \ + (_MX6Q_PAD_GPIO_0__EPIT1_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_GPIO_0__GPIO_1_0 \ + (_MX6Q_PAD_GPIO_0__GPIO_1_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_GPIO_0__USBOH3_USBH1_PWR \ + (_MX6Q_PAD_GPIO_0__USBOH3_USBH1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_GPIO_0__SNVS_HP_WRAPPER_SNVS_VIO_5 \ + (_MX6Q_PAD_GPIO_0__SNVS_HP_WRAPPER_SNVS_VIO_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_GPIO_1__ESAI1_SCKR \ + (_MX6Q_PAD_GPIO_1__ESAI1_SCKR | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_GPIO_1__WDOG2_WDOG_B \ + (_MX6Q_PAD_GPIO_1__WDOG2_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_GPIO_1__KPP_ROW_5 \ + (_MX6Q_PAD_GPIO_1__KPP_ROW_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_GPIO_1__PWM2_PWMO \ + (_MX6Q_PAD_GPIO_1__PWM2_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_GPIO_1__GPIO_1_1 \ + (_MX6Q_PAD_GPIO_1__GPIO_1_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_GPIO_1__USDHC1_CD \ + (_MX6Q_PAD_GPIO_1__USDHC1_CD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) +#define MX6Q_PAD_GPIO_1__SRC_TESTER_ACK \ + (_MX6Q_PAD_GPIO_1__SRC_TESTER_ACK | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_GPIO_9__ESAI1_FSR \ + (_MX6Q_PAD_GPIO_9__ESAI1_FSR | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL)) +#define MX6Q_PAD_GPIO_9__WDOG1_WDOG_B \ + (_MX6Q_PAD_GPIO_9__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_GPIO_9__KPP_COL_6 \ + (_MX6Q_PAD_GPIO_9__KPP_COL_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_GPIO_9__CCM_REF_EN_B \ + (_MX6Q_PAD_GPIO_9__CCM_REF_EN_B | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_GPIO_9__PWM1_PWMO \ + (_MX6Q_PAD_GPIO_9__PWM1_PWMO | MUX_PAD_CTRL(MX6Q_HIGH_DRV)) +#define MX6Q_PAD_GPIO_9__GPIO_1_9 \ + (_MX6Q_PAD_GPIO_9__GPIO_1_9 | MUX_PAD_CTRL(MX6Q_HIGH_DRV)) +#define MX6Q_PAD_GPIO_9__USDHC1_WP \ + (_MX6Q_PAD_GPIO_9__USDHC1_WP | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) +#define MX6Q_PAD_GPIO_9__SRC_EARLY_RST \ + (_MX6Q_PAD_GPIO_9__SRC_EARLY_RST | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_GPIO_3__ESAI1_HCKR \ + (_MX6Q_PAD_GPIO_3__ESAI1_HCKR | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 \ + (_MX6Q_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_GPIO_3__I2C3_SCL \ + (_MX6Q_PAD_GPIO_3__I2C3_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL)) +#define MX6Q_PAD_GPIO_3__ANATOP_ANATOP_24M_OUT \ + (_MX6Q_PAD_GPIO_3__ANATOP_ANATOP_24M_OUT | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_GPIO_3__CCM_CLKO2 \ + (_MX6Q_PAD_GPIO_3__CCM_CLKO2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_GPIO_3__GPIO_1_3 \ + (_MX6Q_PAD_GPIO_3__GPIO_1_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_GPIO_3__USBOH3_USBH1_OC \ + (_MX6Q_PAD_GPIO_3__USBOH3_USBH1_OC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_GPIO_3__MLB_MLBCLK \ + (_MX6Q_PAD_GPIO_3__MLB_MLBCLK | MUX_PAD_CTRL(MX6Q_MLB150_PAD_CTRL)) + +#ifdef CONFIG_MX6_ENET_IRQ_TO_GPIO +#define MX6Q_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 \ + (_MX6Q_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 | MUX_PAD_CTRL(ENET_IRQ_PAD_CTRL)) +#else +#define MX6Q_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 \ + (_MX6Q_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_GPIO_6__ESAI1_SCKT \ + (_MX6Q_PAD_GPIO_6__ESAI1_SCKT | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_GPIO_6__GPIO_1_6 \ + (_MX6Q_PAD_GPIO_6__GPIO_1_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_GPIO_6__I2C3_SDA \ + (_MX6Q_PAD_GPIO_6__I2C3_SDA | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_GPIO_6__CCM_CCM_OUT_0 \ + (_MX6Q_PAD_GPIO_6__CCM_CCM_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_GPIO_6__CSU_CSU_INT_DEB \ + (_MX6Q_PAD_GPIO_6__CSU_CSU_INT_DEB | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_GPIO_6__USDHC2_LCTL \ + (_MX6Q_PAD_GPIO_6__USDHC2_LCTL | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) +#define MX6Q_PAD_GPIO_6__MLB_MLBSIG \ + (_MX6Q_PAD_GPIO_6__MLB_MLBSIG | MUX_PAD_CTRL(MX6Q_MLB150_PAD_CTRL)) +#endif + +#define MX6Q_PAD_GPIO_2__ESAI1_FST \ + (_MX6Q_PAD_GPIO_2__ESAI1_FST | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 \ + (_MX6Q_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_GPIO_2__KPP_ROW_6 \ + (_MX6Q_PAD_GPIO_2__KPP_ROW_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_GPIO_2__CCM_CCM_OUT_1 \ + (_MX6Q_PAD_GPIO_2__CCM_CCM_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 \ + (_MX6Q_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_GPIO_2__GPIO_1_2 \ + (_MX6Q_PAD_GPIO_2__GPIO_1_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_GPIO_2__USDHC2_WP \ + (_MX6Q_PAD_GPIO_2__USDHC2_WP | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) +#define MX6Q_PAD_GPIO_2__MLB_MLBDAT \ + (_MX6Q_PAD_GPIO_2__MLB_MLBDAT | MUX_PAD_CTRL(MX6Q_MLB150_PAD_CTRL)) + +#define MX6Q_PAD_GPIO_4__ESAI1_HCKT \ + (_MX6Q_PAD_GPIO_4__ESAI1_HCKT | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 \ + (_MX6Q_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_GPIO_4__KPP_COL_7 \ + (_MX6Q_PAD_GPIO_4__KPP_COL_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_GPIO_4__CCM_CCM_OUT_2 \ + (_MX6Q_PAD_GPIO_4__CCM_CCM_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 \ + (_MX6Q_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_GPIO_4__GPIO_1_4 \ + (_MX6Q_PAD_GPIO_4__GPIO_1_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_GPIO_4__USDHC2_CD \ + (_MX6Q_PAD_GPIO_4__USDHC2_CD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) +#define MX6Q_PAD_GPIO_4__OCOTP_CTRL_WRAPPER_FUSE_LATCHED \ + (_MX6Q_PAD_GPIO_4__OCOTP_CTRL_WRAPPER_FUSE_LATCHED | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_GPIO_5__ESAI1_TX2_RX3 \ + (_MX6Q_PAD_GPIO_5__ESAI1_TX2_RX3 | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL)) +#define MX6Q_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 \ + (_MX6Q_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_GPIO_5__KPP_ROW_7 \ + (_MX6Q_PAD_GPIO_5__KPP_ROW_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_GPIO_5__CCM_CLKO \ + (_MX6Q_PAD_GPIO_5__CCM_CLKO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 \ + (_MX6Q_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_GPIO_5__GPIO_1_5 \ + (_MX6Q_PAD_GPIO_5__GPIO_1_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_GPIO_5__I2C3_SCL \ + (_MX6Q_PAD_GPIO_5__I2C3_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL)) +#define MX6Q_PAD_GPIO_5__CHEETAH_EVENTI \ + (_MX6Q_PAD_GPIO_5__CHEETAH_EVENTI | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_GPIO_7__ESAI1_TX4_RX1 \ + (_MX6Q_PAD_GPIO_7__ESAI1_TX4_RX1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_GPIO_7__ECSPI5_RDY \ + (_MX6Q_PAD_GPIO_7__ECSPI5_RDY | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_GPIO_7__EPIT1_EPITO \ + (_MX6Q_PAD_GPIO_7__EPIT1_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_GPIO_7__CAN1_TXCAN \ + (_MX6Q_PAD_GPIO_7__CAN1_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_GPIO_7__UART2_TXD \ + (_MX6Q_PAD_GPIO_7__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) +#define MX6Q_PAD_GPIO_7__UART2_RXD \ + (_MX6Q_PAD_GPIO_7__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) +#define MX6Q_PAD_GPIO_7__GPIO_1_7 \ + (_MX6Q_PAD_GPIO_7__GPIO_1_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_GPIO_7__SPDIF_PLOCK \ + (_MX6Q_PAD_GPIO_7__SPDIF_PLOCK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_GPIO_7__USBOH3_OTGUSB_HOST_MODE \ + (_MX6Q_PAD_GPIO_7__USBOH3_OTGUSB_HOST_MODE | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_GPIO_8__ESAI1_TX5_RX0 \ + (_MX6Q_PAD_GPIO_8__ESAI1_TX5_RX0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT \ + (_MX6Q_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_GPIO_8__EPIT2_EPITO \ + (_MX6Q_PAD_GPIO_8__EPIT2_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_GPIO_8__CAN1_RXCAN \ + (_MX6Q_PAD_GPIO_8__CAN1_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_GPIO_8__UART2_TXD \ + (_MX6Q_PAD_GPIO_8__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) +#define MX6Q_PAD_GPIO_8__UART2_RXD \ + (_MX6Q_PAD_GPIO_8__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) +#define MX6Q_PAD_GPIO_8__GPIO_1_8 \ + (_MX6Q_PAD_GPIO_8__GPIO_1_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_GPIO_8__SPDIF_SRCLK \ + (_MX6Q_PAD_GPIO_8__SPDIF_SRCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_GPIO_8__USBOH3_OTGUSB_PWRCTL_WAKEUP \ + (_MX6Q_PAD_GPIO_8__USBOH3_OTGUSB_PWRCTL_WAKEUP | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_GPIO_16__ESAI1_TX3_RX2 \ + (_MX6Q_PAD_GPIO_16__ESAI1_TX3_RX2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN \ + (_MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT \ + (_MX6Q_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT | \ + MUX_PAD_CTRL(MX6Q_GPIO_16_PAD_CTRL)) +#define MX6Q_PAD_GPIO_16__USDHC1_LCTL \ + (_MX6Q_PAD_GPIO_16__USDHC1_LCTL | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) +#define MX6Q_PAD_GPIO_16__SPDIF_IN1 \ + (_MX6Q_PAD_GPIO_16__SPDIF_IN1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_GPIO_16__GPIO_7_11 \ + (_MX6Q_PAD_GPIO_16__GPIO_7_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_GPIO_16__I2C3_SDA \ + (_MX6Q_PAD_GPIO_16__I2C3_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL)) +#define MX6Q_PAD_GPIO_16__SJC_DE_B \ + (_MX6Q_PAD_GPIO_16__SJC_DE_B | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_GPIO_17__ESAI1_TX0 \ + (_MX6Q_PAD_GPIO_17__ESAI1_TX0 | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL)) +#define MX6Q_PAD_GPIO_17__ENET_1588_EVENT3_IN \ + (_MX6Q_PAD_GPIO_17__ENET_1588_EVENT3_IN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_GPIO_17__CCM_PMIC_RDY \ + (_MX6Q_PAD_GPIO_17__CCM_PMIC_RDY | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0 \ + (_MX6Q_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_GPIO_17__SPDIF_OUT1 \ + (_MX6Q_PAD_GPIO_17__SPDIF_OUT1 | MUX_PAD_CTRL(MX6Q_SPDIF_OUT_PAD_CTRL)) +#define MX6Q_PAD_GPIO_17__GPIO_7_12 \ + (_MX6Q_PAD_GPIO_17__GPIO_7_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_GPIO_17__SJC_JTAG_ACT \ + (_MX6Q_PAD_GPIO_17__SJC_JTAG_ACT | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_GPIO_18__ESAI1_TX1 \ + (_MX6Q_PAD_GPIO_18__ESAI1_TX1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_GPIO_18__ENET_RX_CLK \ + (_MX6Q_PAD_GPIO_18__ENET_RX_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_GPIO_18__USDHC3_VSELECT \ + (_MX6Q_PAD_GPIO_18__USDHC3_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) +#define MX6Q_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1 \ + (_MX6Q_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_GPIO_18__ASRC_ASRC_EXT_CLK \ + (_MX6Q_PAD_GPIO_18__ASRC_ASRC_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_GPIO_18__GPIO_7_13 \ + (_MX6Q_PAD_GPIO_18__GPIO_7_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_GPIO_18__SNVS_HP_WRAPPER_SNVS_VIO_5_CTL \ + (_MX6Q_PAD_GPIO_18__SNVS_HP_WRAPPER_SNVS_VIO_5_CTL | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_GPIO_18__SRC_SYSTEM_RST \ + (_MX6Q_PAD_GPIO_18__SRC_SYSTEM_RST | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_GPIO_19__KPP_COL_5 \ + (_MX6Q_PAD_GPIO_19__KPP_COL_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_GPIO_19__ENET_1588_EVENT0_OUT \ + (_MX6Q_PAD_GPIO_19__ENET_1588_EVENT0_OUT | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_GPIO_19__SPDIF_OUT1 \ + (_MX6Q_PAD_GPIO_19__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_GPIO_19__CCM_CLKO \ + (_MX6Q_PAD_GPIO_19__CCM_CLKO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_GPIO_19__ECSPI1_RDY \ + (_MX6Q_PAD_GPIO_19__ECSPI1_RDY | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_GPIO_19__GPIO_4_5 \ + (_MX6Q_PAD_GPIO_19__GPIO_4_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_GPIO_19__ENET_TX_ER \ + (_MX6Q_PAD_GPIO_19__ENET_TX_ER | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_GPIO_19__SRC_INT_BOOT \ + (_MX6Q_PAD_GPIO_19__SRC_INT_BOOT | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK \ + (_MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_PIXCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_12 \ + (_MX6Q_PAD_CSI0_PIXCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 \ + (_MX6Q_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_PIXCLK__GPIO_5_18 \ + (_MX6Q_PAD_CSI0_PIXCLK__GPIO_5_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_PIXCLK__MMDC_MMDC_DEBUG_29 \ + (_MX6Q_PAD_CSI0_PIXCLK__MMDC_MMDC_DEBUG_29 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_PIXCLK__CHEETAH_EVENTO \ + (_MX6Q_PAD_CSI0_PIXCLK__CHEETAH_EVENTO | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC \ + (_MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_MCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_13 \ + (_MX6Q_PAD_CSI0_MCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_MCLK__CCM_CLKO \ + (_MX6Q_PAD_CSI0_MCLK__CCM_CLKO | MUX_PAD_CTRL(MX6Q_CCM_CLK0_PAD_CTRL)) +#define MX6Q_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 \ + (_MX6Q_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_MCLK__GPIO_5_19 \ + (_MX6Q_PAD_CSI0_MCLK__GPIO_5_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30 \ + (_MX6Q_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_MCLK__CHEETAH_TRCTL \ + (_MX6Q_PAD_CSI0_MCLK__CHEETAH_TRCTL | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN \ + (_MX6Q_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0 \ + (_MX6Q_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DATA_EN__PCIE_CTRL_DIAG_STATUS_BUS_MUX_14 \ + (_MX6Q_PAD_CSI0_DATA_EN__PCIE_CTRL_DIAG_STATUS_BUS_MUX_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 \ + (_MX6Q_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DATA_EN__GPIO_5_20 \ + (_MX6Q_PAD_CSI0_DATA_EN__GPIO_5_20 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DATA_EN__MMDC_MMDC_DEBUG_31 \ + (_MX6Q_PAD_CSI0_DATA_EN__MMDC_MMDC_DEBUG_31 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DATA_EN__CHEETAH_TRCLK \ + (_MX6Q_PAD_CSI0_DATA_EN__CHEETAH_TRCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC \ + (_MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_VSYNC__WEIM_WEIM_D_1 \ + (_MX6Q_PAD_CSI0_VSYNC__WEIM_WEIM_D_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_VSYNC__PCIE_CTRL_DIAG_STATUS_BUS_MUX_15 \ + (_MX6Q_PAD_CSI0_VSYNC__PCIE_CTRL_DIAG_STATUS_BUS_MUX_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 \ + (_MX6Q_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_VSYNC__GPIO_5_21 \ + (_MX6Q_PAD_CSI0_VSYNC__GPIO_5_21 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_VSYNC__MMDC_MMDC_DEBUG_32 \ + (_MX6Q_PAD_CSI0_VSYNC__MMDC_MMDC_DEBUG_32 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_VSYNC__CHEETAH_TRACE_0 \ + (_MX6Q_PAD_CSI0_VSYNC__CHEETAH_TRACE_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_CSI0_DAT4__IPU1_CSI0_D_4 \ + (_MX6Q_PAD_CSI0_DAT4__IPU1_CSI0_D_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT4__WEIM_WEIM_D_2 \ + (_MX6Q_PAD_CSI0_DAT4__WEIM_WEIM_D_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT4__ECSPI1_SCLK \ + (_MX6Q_PAD_CSI0_DAT4__ECSPI1_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT4__KPP_COL_5 \ + (_MX6Q_PAD_CSI0_DAT4__KPP_COL_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC \ + (_MX6Q_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT4__GPIO_5_22 \ + (_MX6Q_PAD_CSI0_DAT4__GPIO_5_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT4__MMDC_MMDC_DEBUG_43 \ + (_MX6Q_PAD_CSI0_DAT4__MMDC_MMDC_DEBUG_43 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT4__CHEETAH_TRACE_1 \ + (_MX6Q_PAD_CSI0_DAT4__CHEETAH_TRACE_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_CSI0_DAT5__IPU1_CSI0_D_5 \ + (_MX6Q_PAD_CSI0_DAT5__IPU1_CSI0_D_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT5__WEIM_WEIM_D_3 \ + (_MX6Q_PAD_CSI0_DAT5__WEIM_WEIM_D_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT5__ECSPI1_MOSI \ + (_MX6Q_PAD_CSI0_DAT5__ECSPI1_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT5__KPP_ROW_5 \ + (_MX6Q_PAD_CSI0_DAT5__KPP_ROW_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD \ + (_MX6Q_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD | \ + MUX_PAD_CTRL(MX6Q_ADU_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT5__GPIO_5_23 \ + (_MX6Q_PAD_CSI0_DAT5__GPIO_5_23 | MUX_PAD_CTRL(MX6Q_HIGH_DRV)) +#define MX6Q_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44 \ + (_MX6Q_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT5__CHEETAH_TRACE_2 \ + (_MX6Q_PAD_CSI0_DAT5__CHEETAH_TRACE_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_CSI0_DAT6__IPU1_CSI0_D_6 \ + (_MX6Q_PAD_CSI0_DAT6__IPU1_CSI0_D_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT6__WEIM_WEIM_D_4 \ + (_MX6Q_PAD_CSI0_DAT6__WEIM_WEIM_D_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT6__ECSPI1_MISO \ + (_MX6Q_PAD_CSI0_DAT6__ECSPI1_MISO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT6__KPP_COL_6 \ + (_MX6Q_PAD_CSI0_DAT6__KPP_COL_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS \ + (_MX6Q_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT6__GPIO_5_24 \ + (_MX6Q_PAD_CSI0_DAT6__GPIO_5_24 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45 \ + (_MX6Q_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT6__CHEETAH_TRACE_3 \ + (_MX6Q_PAD_CSI0_DAT6__CHEETAH_TRACE_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_CSI0_DAT7__IPU1_CSI0_D_7 \ + (_MX6Q_PAD_CSI0_DAT7__IPU1_CSI0_D_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT7__WEIM_WEIM_D_5 \ + (_MX6Q_PAD_CSI0_DAT7__WEIM_WEIM_D_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT7__ECSPI1_SS0 \ + (_MX6Q_PAD_CSI0_DAT7__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT7__KPP_ROW_6 \ + (_MX6Q_PAD_CSI0_DAT7__KPP_ROW_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD \ + (_MX6Q_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD | \ + MUX_PAD_CTRL(MX6Q_ADU_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT7__GPIO_5_25 \ + (_MX6Q_PAD_CSI0_DAT7__GPIO_5_25 | MUX_PAD_CTRL(MX6Q_HIGH_DRV)) +#define MX6Q_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46 \ + (_MX6Q_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT7__CHEETAH_TRACE_4 \ + (_MX6Q_PAD_CSI0_DAT7__CHEETAH_TRACE_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_CSI0_DAT8__IPU1_CSI0_D_8 \ + (_MX6Q_PAD_CSI0_DAT8__IPU1_CSI0_D_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT8__WEIM_WEIM_D_6 \ + (_MX6Q_PAD_CSI0_DAT8__WEIM_WEIM_D_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT8__ECSPI2_SCLK \ + (_MX6Q_PAD_CSI0_DAT8__ECSPI2_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT8__KPP_COL_7 \ + (_MX6Q_PAD_CSI0_DAT8__KPP_COL_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT8__I2C1_SDA \ + (_MX6Q_PAD_CSI0_DAT8__I2C1_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT8__GPIO_5_26 \ + (_MX6Q_PAD_CSI0_DAT8__GPIO_5_26 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47 \ + (_MX6Q_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT8__CHEETAH_TRACE_5 \ + (_MX6Q_PAD_CSI0_DAT8__CHEETAH_TRACE_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_CSI0_DAT9__IPU1_CSI0_D_9 \ + (_MX6Q_PAD_CSI0_DAT9__IPU1_CSI0_D_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT9__WEIM_WEIM_D_7 \ + (_MX6Q_PAD_CSI0_DAT9__WEIM_WEIM_D_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT9__ECSPI2_MOSI \ + (_MX6Q_PAD_CSI0_DAT9__ECSPI2_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT9__KPP_ROW_7 \ + (_MX6Q_PAD_CSI0_DAT9__KPP_ROW_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT9__I2C1_SCL \ + (_MX6Q_PAD_CSI0_DAT9__I2C1_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT9__GPIO_5_27 \ + (_MX6Q_PAD_CSI0_DAT9__GPIO_5_27 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48 \ + (_MX6Q_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT9__CHEETAH_TRACE_6 \ + (_MX6Q_PAD_CSI0_DAT9__CHEETAH_TRACE_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_D_10 \ + (_MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_D_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC \ + (_MX6Q_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT10__ECSPI2_MISO \ + (_MX6Q_PAD_CSI0_DAT10__ECSPI2_MISO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT10__UART1_TXD \ + (_MX6Q_PAD_CSI0_DAT10__UART1_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT10__UART1_RXD \ + (_MX6Q_PAD_CSI0_DAT10__UART1_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 \ + (_MX6Q_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT10__GPIO_5_28 \ + (_MX6Q_PAD_CSI0_DAT10__GPIO_5_28 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33 \ + (_MX6Q_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT10__CHEETAH_TRACE_7 \ + (_MX6Q_PAD_CSI0_DAT10__CHEETAH_TRACE_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_D_11 \ + (_MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_D_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS \ + (_MX6Q_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT11__ECSPI2_SS0 \ + (_MX6Q_PAD_CSI0_DAT11__ECSPI2_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT11__UART1_TXD \ + (_MX6Q_PAD_CSI0_DAT11__UART1_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT11__UART1_RXD \ + (_MX6Q_PAD_CSI0_DAT11__UART1_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 \ + (_MX6Q_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT11__GPIO_5_29 \ + (_MX6Q_PAD_CSI0_DAT11__GPIO_5_29 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34 \ + (_MX6Q_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT11__CHEETAH_TRACE_8 \ + (_MX6Q_PAD_CSI0_DAT11__CHEETAH_TRACE_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_D_12 \ + (_MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_D_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT12__WEIM_WEIM_D_8 \ + (_MX6Q_PAD_CSI0_DAT12__WEIM_WEIM_D_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT12__PCIE_CTRL_DIAG_STATUS_BUS_MUX_16 \ + (_MX6Q_PAD_CSI0_DAT12__PCIE_CTRL_DIAG_STATUS_BUS_MUX_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT12__UART4_TXD \ + (_MX6Q_PAD_CSI0_DAT12__UART4_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT12__UART4_RXD \ + (_MX6Q_PAD_CSI0_DAT12__UART4_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 \ + (_MX6Q_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT12__GPIO_5_30 \ + (_MX6Q_PAD_CSI0_DAT12__GPIO_5_30 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35 \ + (_MX6Q_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT12__CHEETAH_TRACE_9 \ + (_MX6Q_PAD_CSI0_DAT12__CHEETAH_TRACE_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_D_13 \ + (_MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_D_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT13__WEIM_WEIM_D_9 \ + (_MX6Q_PAD_CSI0_DAT13__WEIM_WEIM_D_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT13__PCIE_CTRL_DIAG_STATUS_BUS_MUX_17 \ + (_MX6Q_PAD_CSI0_DAT13__PCIE_CTRL_DIAG_STATUS_BUS_MUX_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT13__UART4_TXD \ + (_MX6Q_PAD_CSI0_DAT13__UART4_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT13__UART4_RXD \ + (_MX6Q_PAD_CSI0_DAT13__UART4_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 \ + (_MX6Q_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT13__GPIO_5_31 \ + (_MX6Q_PAD_CSI0_DAT13__GPIO_5_31 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36 \ + (_MX6Q_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT13__CHEETAH_TRACE_10 \ + (_MX6Q_PAD_CSI0_DAT13__CHEETAH_TRACE_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_D_14 \ + (_MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_D_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT14__WEIM_WEIM_D_10 \ + (_MX6Q_PAD_CSI0_DAT14__WEIM_WEIM_D_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT14__PCIE_CTRL_DIAG_STATUS_BUS_MUX_18 \ + (_MX6Q_PAD_CSI0_DAT14__PCIE_CTRL_DIAG_STATUS_BUS_MUX_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT14__UART5_TXD \ + (_MX6Q_PAD_CSI0_DAT14__UART5_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT14__UART5_RXD \ + (_MX6Q_PAD_CSI0_DAT14__UART5_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 \ + (_MX6Q_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT14__GPIO_6_0 \ + (_MX6Q_PAD_CSI0_DAT14__GPIO_6_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37 \ + (_MX6Q_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT14__CHEETAH_TRACE_11 \ + (_MX6Q_PAD_CSI0_DAT14__CHEETAH_TRACE_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_D_15 \ + (_MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_D_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT15__WEIM_WEIM_D_11 \ + (_MX6Q_PAD_CSI0_DAT15__WEIM_WEIM_D_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT15__PCIE_CTRL_DIAG_STATUS_BUS_MUX_19 \ + (_MX6Q_PAD_CSI0_DAT15__PCIE_CTRL_DIAG_STATUS_BUS_MUX_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT15__UART5_TXD \ + (_MX6Q_PAD_CSI0_DAT15__UART5_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT15__UART5_RXD \ + (_MX6Q_PAD_CSI0_DAT15__UART5_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 \ + (_MX6Q_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT15__GPIO_6_1 \ + (_MX6Q_PAD_CSI0_DAT15__GPIO_6_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38 \ + (_MX6Q_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT15__CHEETAH_TRACE_12 \ + (_MX6Q_PAD_CSI0_DAT15__CHEETAH_TRACE_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_D_16 \ + (_MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_D_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT16__WEIM_WEIM_D_12 \ + (_MX6Q_PAD_CSI0_DAT16__WEIM_WEIM_D_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT16__PCIE_CTRL_DIAG_STATUS_BUS_MUX_20 \ + (_MX6Q_PAD_CSI0_DAT16__PCIE_CTRL_DIAG_STATUS_BUS_MUX_20 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT16__UART4_CTS \ + (_MX6Q_PAD_CSI0_DAT16__UART4_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT16__UART4_RTS \ + (_MX6Q_PAD_CSI0_DAT16__UART4_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 \ + (_MX6Q_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT16__GPIO_6_2 \ + (_MX6Q_PAD_CSI0_DAT16__GPIO_6_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39 \ + (_MX6Q_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT16__CHEETAH_TRACE_13 \ + (_MX6Q_PAD_CSI0_DAT16__CHEETAH_TRACE_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_D_17 \ + (_MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT17__WEIM_WEIM_D_13 \ + (_MX6Q_PAD_CSI0_DAT17__WEIM_WEIM_D_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT17__PCIE_CTRL_DIAG_STATUS_BUS_MUX_21 \ + (_MX6Q_PAD_CSI0_DAT17__PCIE_CTRL_DIAG_STATUS_BUS_MUX_21 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT17__UART4_CTS \ + (_MX6Q_PAD_CSI0_DAT17__UART4_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 \ + (_MX6Q_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT17__GPIO_6_3 \ + (_MX6Q_PAD_CSI0_DAT17__GPIO_6_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40 \ + (_MX6Q_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT17__CHEETAH_TRACE_14 \ + (_MX6Q_PAD_CSI0_DAT17__CHEETAH_TRACE_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_D_18 \ + (_MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT18__WEIM_WEIM_D_14 \ + (_MX6Q_PAD_CSI0_DAT18__WEIM_WEIM_D_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT18__PCIE_CTRL_DIAG_STATUS_BUS_MUX_22 \ + (_MX6Q_PAD_CSI0_DAT18__PCIE_CTRL_DIAG_STATUS_BUS_MUX_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT18__UART5_CTS \ + (_MX6Q_PAD_CSI0_DAT18__UART5_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT18__UART5_RTS \ + (_MX6Q_PAD_CSI0_DAT18__UART5_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 \ + (_MX6Q_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT18__GPIO_6_4 \ + (_MX6Q_PAD_CSI0_DAT18__GPIO_6_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41 \ + (_MX6Q_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT18__CHEETAH_TRACE_15 \ + (_MX6Q_PAD_CSI0_DAT18__CHEETAH_TRACE_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_D_19 \ + (_MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_D_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT19__WEIM_WEIM_D_15 \ + (_MX6Q_PAD_CSI0_DAT19__WEIM_WEIM_D_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT19__PCIE_CTRL_DIAG_STATUS_BUS_MUX_23 \ + (_MX6Q_PAD_CSI0_DAT19__PCIE_CTRL_DIAG_STATUS_BUS_MUX_23 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT19__UART5_CTS \ + (_MX6Q_PAD_CSI0_DAT19__UART5_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 \ + (_MX6Q_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT19__GPIO_6_5 \ + (_MX6Q_PAD_CSI0_DAT19__GPIO_6_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42 \ + (_MX6Q_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_CSI0_DAT19__ANATOP_ANATOP_TESTO_9 \ + (_MX6Q_PAD_CSI0_DAT19__ANATOP_ANATOP_TESTO_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_JTAG_TMS__SJC_TMS \ + (_MX6Q_PAD_JTAG_TMS__SJC_TMS | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_JTAG_MOD__SJC_MOD \ + (_MX6Q_PAD_JTAG_MOD__SJC_MOD | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_JTAG_TRSTB__SJC_TRSTB \ + (_MX6Q_PAD_JTAG_TRSTB__SJC_TRSTB | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_JTAG_TDI__SJC_TDI \ + (_MX6Q_PAD_JTAG_TDI__SJC_TDI | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_JTAG_TCK__SJC_TCK \ + (_MX6Q_PAD_JTAG_TCK__SJC_TCK | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_JTAG_TDO__SJC_TDO \ + (_MX6Q_PAD_JTAG_TDO__SJC_TDO | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 \ + (_MX6Q_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 \ + (_MX6Q_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK \ + (_MX6Q_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 \ + (_MX6Q_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 \ + (_MX6Q_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 \ + (_MX6Q_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK \ + (_MX6Q_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 \ + (_MX6Q_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 \ + (_MX6Q_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 \ + (_MX6Q_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_TAMPER__SNVS_LP_WRAPPER_SNVS_TD1 \ + (_MX6Q_PAD_TAMPER__SNVS_LP_WRAPPER_SNVS_TD1 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_PMIC_ON_REQ__SNVS_LP_WRAPPER_SNVS_WAKEUP_ALARM \ + (_MX6Q_PAD_PMIC_ON_REQ__SNVS_LP_WRAPPER_SNVS_WAKEUP_ALARM | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_PMIC_STBY_REQ__CCM_PMIC_VSTBY_REQ \ + (_MX6Q_PAD_PMIC_STBY_REQ__CCM_PMIC_VSTBY_REQ | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_POR_B__SRC_POR_B \ + (_MX6Q_PAD_POR_B__SRC_POR_B | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_BOOT_MODE1__SRC_BOOT_MODE_1 \ + (_MX6Q_PAD_BOOT_MODE1__SRC_BOOT_MODE_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_RESET_IN_B__SRC_RESET_B \ + (_MX6Q_PAD_RESET_IN_B__SRC_RESET_B | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_BOOT_MODE0__SRC_BOOT_MODE_0 \ + (_MX6Q_PAD_BOOT_MODE0__SRC_BOOT_MODE_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_TEST_MODE__TCU_TEST_MODE \ + (_MX6Q_PAD_TEST_MODE__TCU_TEST_MODE | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_SD3_DAT7__USDHC3_DAT7_50MHZ \ + (_MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) +#define MX6Q_PAD_SD3_DAT7__USDHC3_DAT7_100MHZ \ + (_MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ)) +#define MX6Q_PAD_SD3_DAT7__USDHC3_DAT7_200MHZ \ + (_MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ)) +#define MX6Q_PAD_SD3_DAT7__UART1_TXD \ + (_MX6Q_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) +#define MX6Q_PAD_SD3_DAT7__UART1_RXD \ + (_MX6Q_PAD_SD3_DAT7__UART1_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) +#define MX6Q_PAD_SD3_DAT7__PCIE_CTRL_DIAG_STATUS_BUS_MUX_24 \ + (_MX6Q_PAD_SD3_DAT7__PCIE_CTRL_DIAG_STATUS_BUS_MUX_24 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0 \ + (_MX6Q_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0 \ + (_MX6Q_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD3_DAT7__GPIO_6_17 \ + (_MX6Q_PAD_SD3_DAT7__GPIO_6_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD3_DAT7__MIPI_CORE_DPHY_TEST_IN_12 \ + (_MX6Q_PAD_SD3_DAT7__MIPI_CORE_DPHY_TEST_IN_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD3_DAT7__ANATOP_USBPHY2_TSTO_PLL_CLK20DIV \ + (_MX6Q_PAD_SD3_DAT7__ANATOP_USBPHY2_TSTO_PLL_CLK20DIV | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_SD3_DAT6__USDHC3_DAT6_50MHZ \ + (_MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) +#define MX6Q_PAD_SD3_DAT6__USDHC3_DAT6_100MHZ \ + (_MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ)) +#define MX6Q_PAD_SD3_DAT6__USDHC3_DAT6_200MHZ \ + (_MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ)) +#define MX6Q_PAD_SD3_DAT6__UART1_TXD \ + (_MX6Q_PAD_SD3_DAT6__UART1_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) +#define MX6Q_PAD_SD3_DAT6__UART1_RXD \ + (_MX6Q_PAD_SD3_DAT6__UART1_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) +#define MX6Q_PAD_SD3_DAT6__PCIE_CTRL_DIAG_STATUS_BUS_MUX_25 \ + (_MX6Q_PAD_SD3_DAT6__PCIE_CTRL_DIAG_STATUS_BUS_MUX_25 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1 \ + (_MX6Q_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1 \ + (_MX6Q_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD3_DAT6__GPIO_6_18 \ + (_MX6Q_PAD_SD3_DAT6__GPIO_6_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD3_DAT6__MIPI_CORE_DPHY_TEST_IN_13 \ + (_MX6Q_PAD_SD3_DAT6__MIPI_CORE_DPHY_TEST_IN_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD3_DAT6__ANATOP_ANATOP_TESTO_10 \ + (_MX6Q_PAD_SD3_DAT6__ANATOP_ANATOP_TESTO_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_SD3_DAT5__USDHC3_DAT5_50MHZ \ + (_MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) +#define MX6Q_PAD_SD3_DAT5__USDHC3_DAT5_100MHZ \ + (_MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ)) +#define MX6Q_PAD_SD3_DAT5__USDHC3_DAT5_200MHZ \ + (_MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ)) +#define MX6Q_PAD_SD3_DAT5__UART2_TXD \ + (_MX6Q_PAD_SD3_DAT5__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) +#define MX6Q_PAD_SD3_DAT5__UART2_RXD \ + (_MX6Q_PAD_SD3_DAT5__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) +#define MX6Q_PAD_SD3_DAT5__PCIE_CTRL_DIAG_STATUS_BUS_MUX_26 \ + (_MX6Q_PAD_SD3_DAT5__PCIE_CTRL_DIAG_STATUS_BUS_MUX_26 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2 \ + (_MX6Q_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2 \ + (_MX6Q_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD3_DAT5__GPIO_7_0 \ + (_MX6Q_PAD_SD3_DAT5__GPIO_7_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD3_DAT5__MIPI_CORE_DPHY_TEST_IN_14 \ + (_MX6Q_PAD_SD3_DAT5__MIPI_CORE_DPHY_TEST_IN_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD3_DAT5__ANATOP_ANATOP_TESTO_11 \ + (_MX6Q_PAD_SD3_DAT5__ANATOP_ANATOP_TESTO_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_SD3_DAT4__USDHC3_DAT4_50MHZ \ + (_MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) +#define MX6Q_PAD_SD3_DAT4__USDHC3_DAT4_100MHZ \ + (_MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ)) +#define MX6Q_PAD_SD3_DAT4__USDHC3_DAT4_200MHZ \ + (_MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ)) +#define MX6Q_PAD_SD3_DAT4__UART2_TXD \ + (_MX6Q_PAD_SD3_DAT4__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) +#define MX6Q_PAD_SD3_DAT4__UART2_RXD \ + (_MX6Q_PAD_SD3_DAT4__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) +#define MX6Q_PAD_SD3_DAT4__PCIE_CTRL_DIAG_STATUS_BUS_MUX_27 \ + (_MX6Q_PAD_SD3_DAT4__PCIE_CTRL_DIAG_STATUS_BUS_MUX_27 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3 \ + (_MX6Q_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3 \ + (_MX6Q_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD3_DAT4__GPIO_7_1 \ + (_MX6Q_PAD_SD3_DAT4__GPIO_7_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD3_DAT4__MIPI_CORE_DPHY_TEST_IN_15 \ + (_MX6Q_PAD_SD3_DAT4__MIPI_CORE_DPHY_TEST_IN_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD3_DAT4__ANATOP_ANATOP_TESTO_12 \ + (_MX6Q_PAD_SD3_DAT4__ANATOP_ANATOP_TESTO_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_SD3_CMD__USDHC3_CMD_50MHZ \ + (_MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) +#define MX6Q_PAD_SD3_CMD__USDHC3_CMD_100MHZ \ + (_MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ)) +#define MX6Q_PAD_SD3_CMD__USDHC3_CMD_200MHZ \ + (_MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ)) +#define MX6Q_PAD_SD3_CMD__UART2_CTS \ + (_MX6Q_PAD_SD3_CMD__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) +#define MX6Q_PAD_SD3_CMD__CAN1_TXCAN \ + (_MX6Q_PAD_SD3_CMD__CAN1_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4 \ + (_MX6Q_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4 \ + (_MX6Q_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD3_CMD__GPIO_7_2 \ + (_MX6Q_PAD_SD3_CMD__GPIO_7_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD3_CMD__MIPI_CORE_DPHY_TEST_IN_16 \ + (_MX6Q_PAD_SD3_CMD__MIPI_CORE_DPHY_TEST_IN_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD3_CMD__ANATOP_ANATOP_TESTO_13 \ + (_MX6Q_PAD_SD3_CMD__ANATOP_ANATOP_TESTO_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_SD3_CLK__USDHC3_CLK_50MHZ \ + (_MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) +#define MX6Q_PAD_SD3_CLK__USDHC3_CLK_100MHZ \ + (_MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ)) +#define MX6Q_PAD_SD3_CLK__USDHC3_CLK_200MHZ \ + (_MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ)) +#define MX6Q_PAD_SD3_CLK__UART2_CTS \ + (_MX6Q_PAD_SD3_CLK__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) +#define MX6Q_PAD_SD3_CLK__UART2_RTS \ + (_MX6Q_PAD_SD3_CLK__UART2_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) +#define MX6Q_PAD_SD3_CLK__CAN1_RXCAN \ + (_MX6Q_PAD_SD3_CLK__CAN1_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5 \ + (_MX6Q_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5 \ + (_MX6Q_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD3_CLK__GPIO_7_3 \ + (_MX6Q_PAD_SD3_CLK__GPIO_7_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD3_CLK__MIPI_CORE_DPHY_TEST_IN_17 \ + (_MX6Q_PAD_SD3_CLK__MIPI_CORE_DPHY_TEST_IN_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD3_CLK__ANATOP_ANATOP_TESTO_14 \ + (_MX6Q_PAD_SD3_CLK__ANATOP_ANATOP_TESTO_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_SD3_DAT0__USDHC3_DAT0_50MHZ \ + (_MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) +#define MX6Q_PAD_SD3_DAT0__USDHC3_DAT0_100MHZ \ + (_MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ)) +#define MX6Q_PAD_SD3_DAT0__USDHC3_DAT0_200MHZ \ + (_MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ)) +#define MX6Q_PAD_SD3_DAT0__UART1_CTS \ + (_MX6Q_PAD_SD3_DAT0__UART1_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) +#define MX6Q_PAD_SD3_DAT0__CAN2_TXCAN \ + (_MX6Q_PAD_SD3_DAT0__CAN2_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6 \ + (_MX6Q_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6 \ + (_MX6Q_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD3_DAT0__GPIO_7_4 \ + (_MX6Q_PAD_SD3_DAT0__GPIO_7_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD3_DAT0__MIPI_CORE_DPHY_TEST_IN_18 \ + (_MX6Q_PAD_SD3_DAT0__MIPI_CORE_DPHY_TEST_IN_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD3_DAT0__ANATOP_ANATOP_TESTO_15 \ + (_MX6Q_PAD_SD3_DAT0__ANATOP_ANATOP_TESTO_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_SD3_DAT1__USDHC3_DAT1_50MHZ \ + (_MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) +#define MX6Q_PAD_SD3_DAT1__USDHC3_DAT1_100MHZ \ + (_MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ)) +#define MX6Q_PAD_SD3_DAT1__USDHC3_DAT1_200MHZ \ + (_MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ)) +#define MX6Q_PAD_SD3_DAT1__UART1_CTS \ + (_MX6Q_PAD_SD3_DAT1__UART1_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) +#define MX6Q_PAD_SD3_DAT1__UART1_RTS \ + (_MX6Q_PAD_SD3_DAT1__UART1_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) +#define MX6Q_PAD_SD3_DAT1__CAN2_RXCAN \ + (_MX6Q_PAD_SD3_DAT1__CAN2_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7 \ + (_MX6Q_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7 \ + (_MX6Q_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD3_DAT1__GPIO_7_5 \ + (_MX6Q_PAD_SD3_DAT1__GPIO_7_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD3_DAT1__MIPI_CORE_DPHY_TEST_IN_19 \ + (_MX6Q_PAD_SD3_DAT1__MIPI_CORE_DPHY_TEST_IN_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD3_DAT1__ANATOP_ANATOP_TESTI_0 \ + (_MX6Q_PAD_SD3_DAT1__ANATOP_ANATOP_TESTI_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_SD3_DAT2__USDHC3_DAT2_50MHZ \ + (_MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) +#define MX6Q_PAD_SD3_DAT2__USDHC3_DAT2_100MHZ \ + (_MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ)) +#define MX6Q_PAD_SD3_DAT2__USDHC3_DAT2_200MHZ \ + (_MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ)) +#define MX6Q_PAD_SD3_DAT2__PCIE_CTRL_DIAG_STATUS_BUS_MUX_28 \ + (_MX6Q_PAD_SD3_DAT2__PCIE_CTRL_DIAG_STATUS_BUS_MUX_28 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8 \ + (_MX6Q_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8 \ + (_MX6Q_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD3_DAT2__GPIO_7_6 \ + (_MX6Q_PAD_SD3_DAT2__GPIO_7_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD3_DAT2__MIPI_CORE_DPHY_TEST_IN_20 \ + (_MX6Q_PAD_SD3_DAT2__MIPI_CORE_DPHY_TEST_IN_20 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD3_DAT2__ANATOP_ANATOP_TESTI_1 \ + (_MX6Q_PAD_SD3_DAT2__ANATOP_ANATOP_TESTI_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_SD3_DAT3__USDHC3_DAT3_50MHZ \ + (_MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) +#define MX6Q_PAD_SD3_DAT3__USDHC3_DAT3_100MHZ \ + (_MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ)) +#define MX6Q_PAD_SD3_DAT3__USDHC3_DAT3_200MHZ \ + (_MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ)) +#define MX6Q_PAD_SD3_DAT3__UART3_CTS \ + (_MX6Q_PAD_SD3_DAT3__UART3_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) +#define MX6Q_PAD_SD3_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_29 \ + (_MX6Q_PAD_SD3_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_29 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9 \ + (_MX6Q_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9 \ + (_MX6Q_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD3_DAT3__GPIO_7_7 \ + (_MX6Q_PAD_SD3_DAT3__GPIO_7_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD3_DAT3__MIPI_CORE_DPHY_TEST_IN_21 \ + (_MX6Q_PAD_SD3_DAT3__MIPI_CORE_DPHY_TEST_IN_21 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD3_DAT3__ANATOP_ANATOP_TESTI_2 \ + (_MX6Q_PAD_SD3_DAT3__ANATOP_ANATOP_TESTI_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_SD3_RST__USDHC3_RST \ + (_MX6Q_PAD_SD3_RST__USDHC3_RST | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) +#define MX6Q_PAD_SD3_RST__UART3_CTS \ + (_MX6Q_PAD_SD3_RST__UART3_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) +#define MX6Q_PAD_SD3_RST__UART3_RTS \ + (_MX6Q_PAD_SD3_RST__UART3_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) +#define MX6Q_PAD_SD3_RST__PCIE_CTRL_DIAG_STATUS_BUS_MUX_30 \ + (_MX6Q_PAD_SD3_RST__PCIE_CTRL_DIAG_STATUS_BUS_MUX_30 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10 \ + (_MX6Q_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10 \ + (_MX6Q_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD3_RST__GPIO_7_8 \ + (_MX6Q_PAD_SD3_RST__GPIO_7_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD3_RST__MIPI_CORE_DPHY_TEST_IN_22 \ + (_MX6Q_PAD_SD3_RST__MIPI_CORE_DPHY_TEST_IN_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3 \ + (_MX6Q_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_NANDF_CLE__RAWNAND_CLE \ + (_MX6Q_PAD_NANDF_CLE__RAWNAND_CLE | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2)) +#define MX6Q_PAD_NANDF_CLE__IPU2_SISG_4 \ + (_MX6Q_PAD_NANDF_CLE__IPU2_SISG_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_NANDF_CLE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_31 \ + (_MX6Q_PAD_NANDF_CLE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_31 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_NANDF_CLE__USBOH3_UH3_DFD_OUT_11 \ + (_MX6Q_PAD_NANDF_CLE__USBOH3_UH3_DFD_OUT_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_NANDF_CLE__USBOH3_UH2_DFD_OUT_11 \ + (_MX6Q_PAD_NANDF_CLE__USBOH3_UH2_DFD_OUT_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_NANDF_CLE__GPIO_6_7 \ + (_MX6Q_PAD_NANDF_CLE__GPIO_6_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_NANDF_CLE__MIPI_CORE_DPHY_TEST_IN_23 \ + (_MX6Q_PAD_NANDF_CLE__MIPI_CORE_DPHY_TEST_IN_23 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_NANDF_CLE__TPSMP_HTRANS_0 \ + (_MX6Q_PAD_NANDF_CLE__TPSMP_HTRANS_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_NANDF_ALE__RAWNAND_ALE \ + (_MX6Q_PAD_NANDF_ALE__RAWNAND_ALE | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2)) +#define MX6Q_PAD_NANDF_ALE__USDHC4_RST \ + (_MX6Q_PAD_NANDF_ALE__USDHC4_RST | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) +#define MX6Q_PAD_NANDF_ALE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_0 \ + (_MX6Q_PAD_NANDF_ALE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_NANDF_ALE__USBOH3_UH3_DFD_OUT_12 \ + (_MX6Q_PAD_NANDF_ALE__USBOH3_UH3_DFD_OUT_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_NANDF_ALE__USBOH3_UH2_DFD_OUT_12 \ + (_MX6Q_PAD_NANDF_ALE__USBOH3_UH2_DFD_OUT_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_NANDF_ALE__GPIO_6_8 \ + (_MX6Q_PAD_NANDF_ALE__GPIO_6_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_NANDF_ALE__MIPI_CORE_DPHY_TEST_IN_24 \ + (_MX6Q_PAD_NANDF_ALE__MIPI_CORE_DPHY_TEST_IN_24 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_NANDF_ALE__TPSMP_HTRANS_1 \ + (_MX6Q_PAD_NANDF_ALE__TPSMP_HTRANS_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN \ + (_MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2)) +#define MX6Q_PAD_NANDF_WP_B__IPU2_SISG_5 \ + (_MX6Q_PAD_NANDF_WP_B__IPU2_SISG_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_NANDF_WP_B__PCIE_CTRL_DIAG_STATUS_BUS_MUX_1 \ + (_MX6Q_PAD_NANDF_WP_B__PCIE_CTRL_DIAG_STATUS_BUS_MUX_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_NANDF_WP_B__USBOH3_UH3_DFD_OUT_13 \ + (_MX6Q_PAD_NANDF_WP_B__USBOH3_UH3_DFD_OUT_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_NANDF_WP_B__USBOH3_UH2_DFD_OUT_13 \ + (_MX6Q_PAD_NANDF_WP_B__USBOH3_UH2_DFD_OUT_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_NANDF_WP_B__GPIO_6_9 \ + (_MX6Q_PAD_NANDF_WP_B__GPIO_6_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_NANDF_WP_B__MIPI_CORE_DPHY_TEST_OUT_32 \ + (_MX6Q_PAD_NANDF_WP_B__MIPI_CORE_DPHY_TEST_OUT_32 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_NANDF_WP_B__PL301_MX6QPER1_HSIZE_0 \ + (_MX6Q_PAD_NANDF_WP_B__PL301_MX6QPER1_HSIZE_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 \ + (_MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL0)) +#define MX6Q_PAD_NANDF_RB0__IPU2_DI0_PIN1 \ + (_MX6Q_PAD_NANDF_RB0__IPU2_DI0_PIN1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_NANDF_RB0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_2 \ + (_MX6Q_PAD_NANDF_RB0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_NANDF_RB0__USBOH3_UH3_DFD_OUT_14 \ + (_MX6Q_PAD_NANDF_RB0__USBOH3_UH3_DFD_OUT_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_NANDF_RB0__USBOH3_UH2_DFD_OUT_14 \ + (_MX6Q_PAD_NANDF_RB0__USBOH3_UH2_DFD_OUT_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_NANDF_RB0__GPIO_6_10 \ + (_MX6Q_PAD_NANDF_RB0__GPIO_6_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_NANDF_RB0__MIPI_CORE_DPHY_TEST_OUT_33 \ + (_MX6Q_PAD_NANDF_RB0__MIPI_CORE_DPHY_TEST_OUT_33 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_NANDF_RB0__PL301_MX6QPER1_HSIZE_1 \ + (_MX6Q_PAD_NANDF_RB0__PL301_MX6QPER1_HSIZE_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N \ + (_MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2)) +#define MX6Q_PAD_NANDF_CS0__USBOH3_UH3_DFD_OUT_15 \ + (_MX6Q_PAD_NANDF_CS0__USBOH3_UH3_DFD_OUT_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_NANDF_CS0__USBOH3_UH2_DFD_OUT_15 \ + (_MX6Q_PAD_NANDF_CS0__USBOH3_UH2_DFD_OUT_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_NANDF_CS0__GPIO_6_11 \ + (_MX6Q_PAD_NANDF_CS0__GPIO_6_11 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) +#define MX6Q_PAD_NANDF_CS0__PL301_MX6QPER1_HSIZE_2 \ + (_MX6Q_PAD_NANDF_CS0__PL301_MX6QPER1_HSIZE_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N \ + (_MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2)) +#define MX6Q_PAD_NANDF_CS1__USDHC4_VSELECT \ + (_MX6Q_PAD_NANDF_CS1__USDHC4_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) +#define MX6Q_PAD_NANDF_CS1__USDHC3_VSELECT \ + (_MX6Q_PAD_NANDF_CS1__USDHC3_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) +#define MX6Q_PAD_NANDF_CS1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_3 \ + (_MX6Q_PAD_NANDF_CS1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_NANDF_CS1__GPIO_6_14 \ + (_MX6Q_PAD_NANDF_CS1__GPIO_6_14 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) +#define MX6Q_PAD_NANDF_CS1__PL301_MX6QPER1_HREADYOUT \ + (_MX6Q_PAD_NANDF_CS1__PL301_MX6QPER1_HREADYOUT | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N \ + (_MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2)) +#define MX6Q_PAD_NANDF_CS2__IPU1_SISG_0 \ + (_MX6Q_PAD_NANDF_CS2__IPU1_SISG_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_NANDF_CS2__ESAI1_TX0 \ + (_MX6Q_PAD_NANDF_CS2__ESAI1_TX0 | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL)) +#define MX6Q_PAD_NANDF_CS2__WEIM_WEIM_CRE \ + (_MX6Q_PAD_NANDF_CS2__WEIM_WEIM_CRE | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_NANDF_CS2__CCM_CLKO2 \ + (_MX6Q_PAD_NANDF_CS2__CCM_CLKO2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_NANDF_CS2__GPIO_6_15 \ + (_MX6Q_PAD_NANDF_CS2__GPIO_6_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_NANDF_CS2__IPU2_SISG_0 \ + (_MX6Q_PAD_NANDF_CS2__IPU2_SISG_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N \ + (_MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2)) +#define MX6Q_PAD_NANDF_CS3__IPU1_SISG_1 \ + (_MX6Q_PAD_NANDF_CS3__IPU1_SISG_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_NANDF_CS3__ESAI1_TX1 \ + (_MX6Q_PAD_NANDF_CS3__ESAI1_TX1 | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL)) +#define MX6Q_PAD_NANDF_CS3__WEIM_WEIM_A_26 \ + (_MX6Q_PAD_NANDF_CS3__WEIM_WEIM_A_26 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_NANDF_CS3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_4 \ + (_MX6Q_PAD_NANDF_CS3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_NANDF_CS3__GPIO_6_16 \ + (_MX6Q_PAD_NANDF_CS3__GPIO_6_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_NANDF_CS3__IPU2_SISG_1 \ + (_MX6Q_PAD_NANDF_CS3__IPU2_SISG_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_NANDF_CS3__TPSMP_CLK \ + (_MX6Q_PAD_NANDF_CS3__TPSMP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_SD4_CMD__USDHC4_CMD_50MHZ \ + (_MX6Q_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) +#define MX6Q_PAD_SD4_CMD__USDHC4_CMD_100MHZ \ + (_MX6Q_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ)) +#define MX6Q_PAD_SD4_CMD__USDHC4_CMD_200MHZ \ + (_MX6Q_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ)) +#define MX6Q_PAD_SD4_CMD__RAWNAND_RDN \ + (_MX6Q_PAD_SD4_CMD__RAWNAND_RDN | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2)) +#define MX6Q_PAD_SD4_CMD__UART3_TXD \ + (_MX6Q_PAD_SD4_CMD__UART3_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) +#define MX6Q_PAD_SD4_CMD__UART3_RXD \ + (_MX6Q_PAD_SD4_CMD__UART3_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) +#define MX6Q_PAD_SD4_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_5 \ + (_MX6Q_PAD_SD4_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD4_CMD__GPIO_7_9 \ + (_MX6Q_PAD_SD4_CMD__GPIO_7_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD4_CMD__TPSMP_HDATA_DIR \ + (_MX6Q_PAD_SD4_CMD__TPSMP_HDATA_DIR | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_SD4_CLK__USDHC4_CLK_50MHZ \ + (_MX6Q_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) +#define MX6Q_PAD_SD4_CLK__USDHC4_CLK_100MHZ \ + (_MX6Q_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ)) +#define MX6Q_PAD_SD4_CLK__USDHC4_CLK_200MHZ \ + (_MX6Q_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ)) +#define MX6Q_PAD_SD4_CLK__RAWNAND_WRN \ + (_MX6Q_PAD_SD4_CLK__RAWNAND_WRN | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2)) +#define MX6Q_PAD_SD4_CLK__UART3_TXD \ + (_MX6Q_PAD_SD4_CLK__UART3_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) +#define MX6Q_PAD_SD4_CLK__UART3_RXD \ + (_MX6Q_PAD_SD4_CLK__UART3_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) +#define MX6Q_PAD_SD4_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_6 \ + (_MX6Q_PAD_SD4_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD4_CLK__GPIO_7_10 \ + (_MX6Q_PAD_SD4_CLK__GPIO_7_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_NANDF_D0__RAWNAND_D0 \ + (_MX6Q_PAD_NANDF_D0__RAWNAND_D0 | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2)) +#define MX6Q_PAD_NANDF_D0__USDHC1_DAT4 \ + (_MX6Q_PAD_NANDF_D0__USDHC1_DAT4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) +#define MX6Q_PAD_NANDF_D0__GPU3D_GPU_DEBUG_OUT_0 \ + (_MX6Q_PAD_NANDF_D0__GPU3D_GPU_DEBUG_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT_16 \ + (_MX6Q_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT_16 \ + (_MX6Q_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_NANDF_D0__GPIO_2_0 \ + (_MX6Q_PAD_NANDF_D0__GPIO_2_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0 \ + (_MX6Q_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_NANDF_D0__IPU2_IPU_DIAG_BUS_0 \ + (_MX6Q_PAD_NANDF_D0__IPU2_IPU_DIAG_BUS_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_NANDF_D1__RAWNAND_D1 \ + (_MX6Q_PAD_NANDF_D1__RAWNAND_D1 | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2)) +#define MX6Q_PAD_NANDF_D1__USDHC1_DAT5 \ + (_MX6Q_PAD_NANDF_D1__USDHC1_DAT5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) +#define MX6Q_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT_1 \ + (_MX6Q_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT_17 \ + (_MX6Q_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT_17 \ + (_MX6Q_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_NANDF_D1__GPIO_2_1 \ + (_MX6Q_PAD_NANDF_D1__GPIO_2_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1 \ + (_MX6Q_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_NANDF_D1__IPU2_IPU_DIAG_BUS_1 \ + (_MX6Q_PAD_NANDF_D1__IPU2_IPU_DIAG_BUS_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_NANDF_D2__RAWNAND_D2 \ + (_MX6Q_PAD_NANDF_D2__RAWNAND_D2 | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2)) +#define MX6Q_PAD_NANDF_D2__USDHC1_DAT6 \ + (_MX6Q_PAD_NANDF_D2__USDHC1_DAT6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) +#define MX6Q_PAD_NANDF_D2__GPU3D_GPU_DEBUG_OUT_2 \ + (_MX6Q_PAD_NANDF_D2__GPU3D_GPU_DEBUG_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT_18 \ + (_MX6Q_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT_18 \ + (_MX6Q_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_NANDF_D2__GPIO_2_2 \ + (_MX6Q_PAD_NANDF_D2__GPIO_2_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2 \ + (_MX6Q_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_NANDF_D2__IPU2_IPU_DIAG_BUS_2 \ + (_MX6Q_PAD_NANDF_D2__IPU2_IPU_DIAG_BUS_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_NANDF_D3__RAWNAND_D3 \ + (_MX6Q_PAD_NANDF_D3__RAWNAND_D3 | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2)) +#define MX6Q_PAD_NANDF_D3__USDHC1_DAT7 \ + (_MX6Q_PAD_NANDF_D3__USDHC1_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) +#define MX6Q_PAD_NANDF_D3__GPU3D_GPU_DEBUG_OUT_3 \ + (_MX6Q_PAD_NANDF_D3__GPU3D_GPU_DEBUG_OUT_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT_19 \ + (_MX6Q_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT_19 \ + (_MX6Q_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_NANDF_D3__GPIO_2_3 \ + (_MX6Q_PAD_NANDF_D3__GPIO_2_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3 \ + (_MX6Q_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_NANDF_D3__IPU2_IPU_DIAG_BUS_3 \ + (_MX6Q_PAD_NANDF_D3__IPU2_IPU_DIAG_BUS_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_NANDF_D4__RAWNAND_D4 \ + (_MX6Q_PAD_NANDF_D4__RAWNAND_D4 | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2)) +#define MX6Q_PAD_NANDF_D4__USDHC2_DAT4 \ + (_MX6Q_PAD_NANDF_D4__USDHC2_DAT4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) +#define MX6Q_PAD_NANDF_D4__GPU3D_GPU_DEBUG_OUT_4 \ + (_MX6Q_PAD_NANDF_D4__GPU3D_GPU_DEBUG_OUT_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT_20 \ + (_MX6Q_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT_20 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT_20 \ + (_MX6Q_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT_20 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_NANDF_D4__GPIO_2_4 \ + (_MX6Q_PAD_NANDF_D4__GPIO_2_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4 \ + (_MX6Q_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_NANDF_D4__IPU2_IPU_DIAG_BUS_4 \ + (_MX6Q_PAD_NANDF_D4__IPU2_IPU_DIAG_BUS_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_NANDF_D5__RAWNAND_D5 \ + (_MX6Q_PAD_NANDF_D5__RAWNAND_D5 | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2)) +#define MX6Q_PAD_NANDF_D5__USDHC2_DAT5 \ + (_MX6Q_PAD_NANDF_D5__USDHC2_DAT5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) +#define MX6Q_PAD_NANDF_D5__GPU3D_GPU_DEBUG_OUT_5 \ + (_MX6Q_PAD_NANDF_D5__GPU3D_GPU_DEBUG_OUT_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT_21 \ + (_MX6Q_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT_21 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT_21 \ + (_MX6Q_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT_21 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_NANDF_D5__GPIO_2_5 \ + (_MX6Q_PAD_NANDF_D5__GPIO_2_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5 \ + (_MX6Q_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_NANDF_D5__IPU2_IPU_DIAG_BUS_5 \ + (_MX6Q_PAD_NANDF_D5__IPU2_IPU_DIAG_BUS_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_NANDF_D6__RAWNAND_D6 \ + (_MX6Q_PAD_NANDF_D6__RAWNAND_D6 | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2)) +#define MX6Q_PAD_NANDF_D6__USDHC2_DAT6 \ + (_MX6Q_PAD_NANDF_D6__USDHC2_DAT6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) +#define MX6Q_PAD_NANDF_D6__GPU3D_GPU_DEBUG_OUT_6 \ + (_MX6Q_PAD_NANDF_D6__GPU3D_GPU_DEBUG_OUT_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT_22 \ + (_MX6Q_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT_22 \ + (_MX6Q_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_NANDF_D6__GPIO_2_6 \ + (_MX6Q_PAD_NANDF_D6__GPIO_2_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6 \ + (_MX6Q_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_NANDF_D6__IPU2_IPU_DIAG_BUS_6 \ + (_MX6Q_PAD_NANDF_D6__IPU2_IPU_DIAG_BUS_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_NANDF_D7__RAWNAND_D7 \ + (_MX6Q_PAD_NANDF_D7__RAWNAND_D7 | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2)) +#define MX6Q_PAD_NANDF_D7__USDHC2_DAT7 \ + (_MX6Q_PAD_NANDF_D7__USDHC2_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) +#define MX6Q_PAD_NANDF_D7__GPU3D_GPU_DEBUG_OUT_7 \ + (_MX6Q_PAD_NANDF_D7__GPU3D_GPU_DEBUG_OUT_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT_23 \ + (_MX6Q_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT_23 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT_23 \ + (_MX6Q_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT_23 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_NANDF_D7__GPIO_2_7 \ + (_MX6Q_PAD_NANDF_D7__GPIO_2_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7 \ + (_MX6Q_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_NANDF_D7__IPU2_IPU_DIAG_BUS_7 \ + (_MX6Q_PAD_NANDF_D7__IPU2_IPU_DIAG_BUS_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_SD4_DAT0__RAWNAND_D8 \ + (_MX6Q_PAD_SD4_DAT0__RAWNAND_D8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD4_DAT0__USDHC4_DAT0_50MHZ \ + (_MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) +#define MX6Q_PAD_SD4_DAT0__USDHC4_DAT0_100MHZ \ + (_MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ)) +#define MX6Q_PAD_SD4_DAT0__USDHC4_DAT0_200MHZ \ + (_MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ)) +#define MX6Q_PAD_SD4_DAT0__RAWNAND_DQS \ + (_MX6Q_PAD_SD4_DAT0__RAWNAND_DQS | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL1)) +#define MX6Q_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT_24 \ + (_MX6Q_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT_24 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT_24 \ + (_MX6Q_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT_24 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD4_DAT0__GPIO_2_8 \ + (_MX6Q_PAD_SD4_DAT0__GPIO_2_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8 \ + (_MX6Q_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD4_DAT0__IPU2_IPU_DIAG_BUS_8 \ + (_MX6Q_PAD_SD4_DAT0__IPU2_IPU_DIAG_BUS_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_SD4_DAT1__RAWNAND_D9 \ + (_MX6Q_PAD_SD4_DAT1__RAWNAND_D9 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD4_DAT1__USDHC4_DAT1_50MHZ \ + (_MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) +#define MX6Q_PAD_SD4_DAT1__USDHC4_DAT1_100MHZ \ + (_MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ)) +#define MX6Q_PAD_SD4_DAT1__USDHC4_DAT1_200MHZ \ + (_MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ)) +#define MX6Q_PAD_SD4_DAT1__PWM3_PWMO \ + (_MX6Q_PAD_SD4_DAT1__PWM3_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT_25 \ + (_MX6Q_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT_25 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT_25 \ + (_MX6Q_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT_25 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD4_DAT1__GPIO_2_9 \ + (_MX6Q_PAD_SD4_DAT1__GPIO_2_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9 \ + (_MX6Q_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD4_DAT1__IPU2_IPU_DIAG_BUS_9 \ + (_MX6Q_PAD_SD4_DAT1__IPU2_IPU_DIAG_BUS_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_SD4_DAT2__RAWNAND_D10 \ + (_MX6Q_PAD_SD4_DAT2__RAWNAND_D10 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD4_DAT2__USDHC4_DAT2_50MHZ \ + (_MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) +#define MX6Q_PAD_SD4_DAT2__USDHC4_DAT2_100MHZ \ + (_MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ)) +#define MX6Q_PAD_SD4_DAT2__USDHC4_DAT2_200MHZ \ + (_MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ)) +#define MX6Q_PAD_SD4_DAT2__PWM4_PWMO \ + (_MX6Q_PAD_SD4_DAT2__PWM4_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT_26 \ + (_MX6Q_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT_26 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT_26 \ + (_MX6Q_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT_26 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD4_DAT2__GPIO_2_10 \ + (_MX6Q_PAD_SD4_DAT2__GPIO_2_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10 \ + (_MX6Q_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD4_DAT2__IPU2_IPU_DIAG_BUS_10 \ + (_MX6Q_PAD_SD4_DAT2__IPU2_IPU_DIAG_BUS_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_SD4_DAT3__RAWNAND_D11 \ + (_MX6Q_PAD_SD4_DAT3__RAWNAND_D11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD4_DAT3__USDHC4_DAT3_50MHZ \ + (_MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) +#define MX6Q_PAD_SD4_DAT3__USDHC4_DAT3_100MHZ \ + (_MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ)) +#define MX6Q_PAD_SD4_DAT3__USDHC4_DAT3_200MHZ \ + (_MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ)) +#define MX6Q_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT_27 \ + (_MX6Q_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT_27 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT_27 \ + (_MX6Q_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT_27 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD4_DAT3__GPIO_2_11 \ + (_MX6Q_PAD_SD4_DAT3__GPIO_2_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11 \ + (_MX6Q_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD4_DAT3__IPU2_IPU_DIAG_BUS_11 \ + (_MX6Q_PAD_SD4_DAT3__IPU2_IPU_DIAG_BUS_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_SD4_DAT4__RAWNAND_D12 \ + (_MX6Q_PAD_SD4_DAT4__RAWNAND_D12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD4_DAT4__USDHC4_DAT4_50MHZ \ + (_MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) +#define MX6Q_PAD_SD4_DAT4__USDHC4_DAT4_100MHZ \ + (_MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ)) +#define MX6Q_PAD_SD4_DAT4__USDHC4_DAT4_200MHZ \ + (_MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ)) +#define MX6Q_PAD_SD4_DAT4__UART2_TXD \ + (_MX6Q_PAD_SD4_DAT4__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) +#define MX6Q_PAD_SD4_DAT4__UART2_RXD \ + (_MX6Q_PAD_SD4_DAT4__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) +#define MX6Q_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT_28 \ + (_MX6Q_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT_28 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT_28 \ + (_MX6Q_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT_28 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD4_DAT4__GPIO_2_12 \ + (_MX6Q_PAD_SD4_DAT4__GPIO_2_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12 \ + (_MX6Q_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD4_DAT4__IPU2_IPU_DIAG_BUS_12 \ + (_MX6Q_PAD_SD4_DAT4__IPU2_IPU_DIAG_BUS_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_SD4_DAT5__RAWNAND_D13 \ + (_MX6Q_PAD_SD4_DAT5__RAWNAND_D13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD4_DAT5__USDHC4_DAT5_50MHZ \ + (_MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) +#define MX6Q_PAD_SD4_DAT5__USDHC4_DAT5_100MHZ \ + (_MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ)) +#define MX6Q_PAD_SD4_DAT5__USDHC4_DAT5_200MHZ \ + (_MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ)) +#define MX6Q_PAD_SD4_DAT5__UART2_CTS \ + (_MX6Q_PAD_SD4_DAT5__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) +#define MX6Q_PAD_SD4_DAT5__UART2_RTS \ + (_MX6Q_PAD_SD4_DAT5__UART2_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) +#define MX6Q_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT_29 \ + (_MX6Q_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT_29 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT_29 \ + (_MX6Q_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT_29 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD4_DAT5__GPIO_2_13 \ + (_MX6Q_PAD_SD4_DAT5__GPIO_2_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13 \ + (_MX6Q_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD4_DAT5__IPU2_IPU_DIAG_BUS_13 \ + (_MX6Q_PAD_SD4_DAT5__IPU2_IPU_DIAG_BUS_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_SD4_DAT6__RAWNAND_D14 \ + (_MX6Q_PAD_SD4_DAT6__RAWNAND_D14 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD4_DAT6__USDHC4_DAT6_50MHZ \ + (_MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) +#define MX6Q_PAD_SD4_DAT6__USDHC4_DAT6_100MHZ \ + (_MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ)) +#define MX6Q_PAD_SD4_DAT6__USDHC4_DAT6_200MHZ \ + (_MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ)) +#define MX6Q_PAD_SD4_DAT6__UART2_CTS \ + (_MX6Q_PAD_SD4_DAT6__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) +#define MX6Q_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT_30 \ + (_MX6Q_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT_30 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT_30 \ + (_MX6Q_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT_30 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD4_DAT6__GPIO_2_14 \ + (_MX6Q_PAD_SD4_DAT6__GPIO_2_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14 \ + (_MX6Q_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD4_DAT6__IPU2_IPU_DIAG_BUS_14 \ + (_MX6Q_PAD_SD4_DAT6__IPU2_IPU_DIAG_BUS_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_SD4_DAT7__RAWNAND_D15 \ + (_MX6Q_PAD_SD4_DAT7__RAWNAND_D15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD4_DAT7__USDHC4_DAT7_50MHZ \ + (_MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) +#define MX6Q_PAD_SD4_DAT7__USDHC4_DAT7_100MHZ \ + (_MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ)) +#define MX6Q_PAD_SD4_DAT7__USDHC4_DAT7_200MHZ \ + (_MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ)) +#define MX6Q_PAD_SD4_DAT7__UART2_TXD \ + (_MX6Q_PAD_SD4_DAT7__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) +#define MX6Q_PAD_SD4_DAT7__UART2_RXD \ + (_MX6Q_PAD_SD4_DAT7__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) +#define MX6Q_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT_31 \ + (_MX6Q_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT_31 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT_31 \ + (_MX6Q_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT_31 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD4_DAT7__GPIO_2_15 \ + (_MX6Q_PAD_SD4_DAT7__GPIO_2_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15 \ + (_MX6Q_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD4_DAT7__IPU2_IPU_DIAG_BUS_15 \ + (_MX6Q_PAD_SD4_DAT7__IPU2_IPU_DIAG_BUS_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_SD1_DAT1__USDHC1_DAT1 \ + (_MX6Q_PAD_SD1_DAT1__USDHC1_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) +#define MX6Q_PAD_SD1_DAT1__USDHC1_DAT1_50MHZ_40OHM \ + (_MX6Q_PAD_SD1_DAT1__USDHC1_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_50MHZ_40OHM)) +#define MX6Q_PAD_SD1_DAT1__ECSPI5_SS0 \ + (_MX6Q_PAD_SD1_DAT1__ECSPI5_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD1_DAT1__PWM3_PWMO \ + (_MX6Q_PAD_SD1_DAT1__PWM3_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD1_DAT1__GPT_CAPIN2 \ + (_MX6Q_PAD_SD1_DAT1__GPT_CAPIN2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD1_DAT1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_7 \ + (_MX6Q_PAD_SD1_DAT1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD1_DAT1__GPIO_1_17 \ + (_MX6Q_PAD_SD1_DAT1__GPIO_1_17 | MUX_PAD_CTRL(MX6Q_HIGH_DRV)) +#define MX6Q_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0 \ + (_MX6Q_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD1_DAT1__ANATOP_ANATOP_TESTO_8 \ + (_MX6Q_PAD_SD1_DAT1__ANATOP_ANATOP_TESTO_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_SD1_DAT0__USDHC1_DAT0 \ + (_MX6Q_PAD_SD1_DAT0__USDHC1_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) +#define MX6Q_PAD_SD1_DAT0__USDHC1_DAT0_50MHZ_40OHM \ + (_MX6Q_PAD_SD1_DAT0__USDHC1_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_50MHZ_40OHM)) +#define MX6Q_PAD_SD1_DAT0__ECSPI5_MISO \ + (_MX6Q_PAD_SD1_DAT0__ECSPI5_MISO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD1_DAT0__CAAM_WRAPPER_RNG_OSC_OBS \ + (_MX6Q_PAD_SD1_DAT0__CAAM_WRAPPER_RNG_OSC_OBS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD1_DAT0__GPT_CAPIN1 \ + (_MX6Q_PAD_SD1_DAT0__GPT_CAPIN1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD1_DAT0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_8 \ + (_MX6Q_PAD_SD1_DAT0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD1_DAT0__GPIO_1_16 \ + (_MX6Q_PAD_SD1_DAT0__GPIO_1_16 | MUX_PAD_CTRL(MX6Q_HIGH_DRV)) +#define MX6Q_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1 \ + (_MX6Q_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD1_DAT0__ANATOP_ANATOP_TESTO_7 \ + (_MX6Q_PAD_SD1_DAT0__ANATOP_ANATOP_TESTO_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_SD1_DAT3__USDHC1_DAT3 \ + (_MX6Q_PAD_SD1_DAT3__USDHC1_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) +#define MX6Q_PAD_SD1_DAT3__USDHC1_DAT3_50MHZ_40OHM \ + (_MX6Q_PAD_SD1_DAT3__USDHC1_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_50MHZ_40OHM)) +#define MX6Q_PAD_SD1_DAT3__ECSPI5_SS2 \ + (_MX6Q_PAD_SD1_DAT3__ECSPI5_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD1_DAT3__GPT_CMPOUT3 \ + (_MX6Q_PAD_SD1_DAT3__GPT_CMPOUT3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD1_DAT3__PWM1_PWMO \ + (_MX6Q_PAD_SD1_DAT3__PWM1_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_B \ + (_MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD1_DAT3__GPIO_1_21 \ + (_MX6Q_PAD_SD1_DAT3__GPIO_1_21 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB \ + (_MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD1_DAT3__ANATOP_ANATOP_TESTO_6 \ + (_MX6Q_PAD_SD1_DAT3__ANATOP_ANATOP_TESTO_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_SD1_CMD__USDHC1_CMD \ + (_MX6Q_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) +#define MX6Q_PAD_SD1_CMD__USDHC1_CMD_50MHZ_40OHM \ + (_MX6Q_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_50MHZ_40OHM)) +#define MX6Q_PAD_SD1_CMD__ECSPI5_MOSI \ + (_MX6Q_PAD_SD1_CMD__ECSPI5_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD1_CMD__PWM4_PWMO \ + (_MX6Q_PAD_SD1_CMD__PWM4_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD1_CMD__GPT_CMPOUT1 \ + (_MX6Q_PAD_SD1_CMD__GPT_CMPOUT1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD1_CMD__GPIO_1_18 \ + (_MX6Q_PAD_SD1_CMD__GPIO_1_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD1_CMD__ANATOP_ANATOP_TESTO_5 \ + (_MX6Q_PAD_SD1_CMD__ANATOP_ANATOP_TESTO_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_SD1_DAT2__USDHC1_DAT2 \ + (_MX6Q_PAD_SD1_DAT2__USDHC1_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) +#define MX6Q_PAD_SD1_DAT2__USDHC1_DAT2_50MHZ_40OHM \ + (_MX6Q_PAD_SD1_DAT2__USDHC1_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_50MHZ_40OHM)) +#define MX6Q_PAD_SD1_DAT2__ECSPI5_SS1 \ + (_MX6Q_PAD_SD1_DAT2__ECSPI5_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD1_DAT2__GPT_CMPOUT2 \ + (_MX6Q_PAD_SD1_DAT2__GPT_CMPOUT2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD1_DAT2__PWM2_PWMO \ + (_MX6Q_PAD_SD1_DAT2__PWM2_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_B \ + (_MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD1_DAT2__GPIO_1_19 \ + (_MX6Q_PAD_SD1_DAT2__GPIO_1_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB \ + (_MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD1_DAT2__ANATOP_ANATOP_TESTO_4 \ + (_MX6Q_PAD_SD1_DAT2__ANATOP_ANATOP_TESTO_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_SD1_CLK__USDHC1_CLK \ + (_MX6Q_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) +#define MX6Q_PAD_SD1_CLK__USDHC1_CLK_50MHZ_40OHM \ + (_MX6Q_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_50MHZ_40OHM)) +#define MX6Q_PAD_SD1_CLK__ECSPI5_SCLK \ + (_MX6Q_PAD_SD1_CLK__ECSPI5_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD1_CLK__OSC32K_32K_OUT \ + (_MX6Q_PAD_SD1_CLK__OSC32K_32K_OUT | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD1_CLK__GPT_CLKIN \ + (_MX6Q_PAD_SD1_CLK__GPT_CLKIN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD1_CLK__GPIO_1_20 \ + (_MX6Q_PAD_SD1_CLK__GPIO_1_20 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD1_CLK__PHY_DTB_0 \ + (_MX6Q_PAD_SD1_CLK__PHY_DTB_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD1_CLK__SATA_PHY_DTB_0 \ + (_MX6Q_PAD_SD1_CLK__SATA_PHY_DTB_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_SD2_CLK__USDHC2_CLK \ + (_MX6Q_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) +#define MX6Q_PAD_SD2_CLK__ECSPI5_SCLK \ + (_MX6Q_PAD_SD2_CLK__ECSPI5_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD2_CLK__KPP_COL_5 \ + (_MX6Q_PAD_SD2_CLK__KPP_COL_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD2_CLK__AUDMUX_AUD4_RXFS \ + (_MX6Q_PAD_SD2_CLK__AUDMUX_AUD4_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD2_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_9 \ + (_MX6Q_PAD_SD2_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD2_CLK__GPIO_1_10 \ + (_MX6Q_PAD_SD2_CLK__GPIO_1_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD2_CLK__PHY_DTB_1 \ + (_MX6Q_PAD_SD2_CLK__PHY_DTB_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD2_CLK__SATA_PHY_DTB_1 \ + (_MX6Q_PAD_SD2_CLK__SATA_PHY_DTB_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_SD2_CMD__USDHC2_CMD \ + (_MX6Q_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) +#define MX6Q_PAD_SD2_CMD__ECSPI5_MOSI \ + (_MX6Q_PAD_SD2_CMD__ECSPI5_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD2_CMD__KPP_ROW_5 \ + (_MX6Q_PAD_SD2_CMD__KPP_ROW_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD2_CMD__AUDMUX_AUD4_RXC \ + (_MX6Q_PAD_SD2_CMD__AUDMUX_AUD4_RXC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD2_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_10 \ + (_MX6Q_PAD_SD2_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD2_CMD__GPIO_1_11 \ + (_MX6Q_PAD_SD2_CMD__GPIO_1_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#define MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 \ + (_MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) +#define MX6Q_PAD_SD2_DAT3__ECSPI5_SS3 \ + (_MX6Q_PAD_SD2_DAT3__ECSPI5_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD2_DAT3__KPP_COL_6 \ + (_MX6Q_PAD_SD2_DAT3__KPP_COL_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC \ + (_MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD2_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_11 \ + (_MX6Q_PAD_SD2_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD2_DAT3__GPIO_1_12 \ + (_MX6Q_PAD_SD2_DAT3__GPIO_1_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD2_DAT3__SJC_DONE \ + (_MX6Q_PAD_SD2_DAT3__SJC_DONE | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_SD2_DAT3__ANATOP_ANATOP_TESTO_3 \ + (_MX6Q_PAD_SD2_DAT3__ANATOP_ANATOP_TESTO_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) + +#endif diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx6sl.h b/arch/arm/plat-mxc/include/mach/iomux-mx6sl.h new file mode 100755 index 00000000..6f90c66b --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/iomux-mx6sl.h @@ -0,0 +1,3117 @@ +/* + * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Auto Generate file, please don't edit it + * + */ + +#ifndef __MACH_IOMUX_MX6SL_H__ +#define __MACH_IOMUX_MX6SL_H__ + +#include <mach/iomux-v3.h> + +#define MX6SL_HIGH_DRV PAD_CTL_DSE_120ohm +#define MX6SL_DISP_PAD_CLT MX6SL_HIGH_DRV + +#define MX6SL_CCM_CLKO_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define MX6SL_UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define MX6SL_INTR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + + +#define MX6SL_USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define MX6SL_USDHC_PAD_CTRL_100MHZ (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_34ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define MX6SL_USDHC_PAD_CTRL_200MHZ (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_HIGH | \ + PAD_CTL_DSE_34ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define MX6SL_ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define MX6SL_I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | \ + PAD_CTL_HYS | PAD_CTL_ODE) + +#define MX6SL_ECSPI_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define MX6SL_USB_HSIC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define MX6SL_HP_DET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) +#define MX6SL_LCDIF_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \ + PAD_CTL_PUE | PAD_CTL_PKE | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm) + +#define MX6SL_KEYPAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_120ohm) + +#define MX6SL_TOUCH_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_DSE_120ohm) + +#define MX6SL_TSPAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP) +#define MX6SL_ADU_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_DSE_40ohm | PAD_CTL_PUS_100K_DOWN | \ + PAD_CTL_HYS | PAD_CTL_SPEED_MED) +#define MX6SL_CHG_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP) +#define MX6SL_FLOAT_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm) + +#define MX6SL_EPDC_PAD_CTRL \ + (PAD_CTL_HYS|PAD_CTL_PKE|PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm) + +#define MX6SL_PAD_AUD_MCLK 0x02A4 +#define MX6SL_PAD_AUD_RXD 0x02AC +#define MX6SL_PAD_AUD_TXC 0x02B4 +#define MX6SL_PAD_AUD_TXD 0x02B8 +#define MX6SL_PAD_AUD_TXFS 0x02BC +#define MX6SL_PAD_HSIC_DAT 0x0444 +#define MX6SL_PAD_HSIC_STROBE 0x0448 + +#define MX6SL_PAD_AUD_MCLK__AUDMUX_AUDIO_CLK_OUT \ + IOMUX_PAD(0x02A4, 0x004C, 0, 0x0000, 0, MX6SL_ADU_PAD_CTRL) +#define MX6SL_PAD_AUD_MCLK__PWM4_PWMO \ + IOMUX_PAD(0x02A4, 0x004C, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY \ + IOMUX_PAD(0x02A4, 0x004C, 2, 0x06B4, 0, NO_PAD_CTRL) +#define MX6SL_PAD_AUD_MCLK__FEC_MDC \ + IOMUX_PAD(0x02A4, 0x004C, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_AUD_MCLK__WDOG2_WDOG_RST_B_DEB \ + IOMUX_PAD(0x02A4, 0x004C, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_AUD_MCLK__GPIO_1_6 \ + IOMUX_PAD(0x02A4, 0x004C, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_AUD_MCLK__SPDIF_SPDIF_EXT_CLK \ + IOMUX_PAD(0x02A4, 0x004C, 6, 0x07F4, 0, NO_PAD_CTRL) +#define MX6SL_PAD_AUD_MCLK__TPSMP_HDATA_27 \ + IOMUX_PAD(0x02A4, 0x004C, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_AUD_RXC__AUDMUX_AUD3_RXC \ + IOMUX_PAD(0x02A8, 0x0050, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_AUD_RXC__I2C1_SDA \ + IOMUX_PAD(0x02A8, 0x0050, 1 | IOMUX_CONFIG_SION, 0x0720, 0, MX6SL_I2C_PAD_CTRL) +#define MX6SL_PAD_AUD_RXC__UART3_TXD \ + IOMUX_PAD(0x02A8, 0x0050, 2, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_AUD_RXC__UART3_RXD \ + IOMUX_PAD(0x02A8, 0x0050, 2, 0x080C, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_AUD_RXC__FEC_TX_CLK \ + IOMUX_PAD(0x02A8, 0x0050, 3, 0x070C, 0, NO_PAD_CTRL) +#define MX6SL_PAD_AUD_RXC__I2C3_SDA \ + IOMUX_PAD(0x02A8, 0x0050, 4 | IOMUX_CONFIG_SION, 0x0730, 0, MX6SL_I2C_PAD_CTRL) +#define MX6SL_PAD_AUD_RXC__GPIO_1_1 \ + IOMUX_PAD(0x02A8, 0x0050, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_AUD_RXC__ECSPI3_SS1 \ + IOMUX_PAD(0x02A8, 0x0050, 6, 0x06C4, 0, NO_PAD_CTRL) +#define MX6SL_PAD_AUD_RXC__PL301_SIM_MX6SL_PER1_HREADYOUT \ + IOMUX_PAD(0x02A8, 0x0050, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_AUD_RXD__AUDMUX_AUD3_RXD \ + IOMUX_PAD(0x02AC, 0x0054, 0, 0x0000, 0, MX6SL_ADU_PAD_CTRL) +#define MX6SL_PAD_AUD_RXD__ECSPI3_MOSI \ + IOMUX_PAD(0x02AC, 0x0054, 1, 0x06BC, 0, NO_PAD_CTRL) +#define MX6SL_PAD_AUD_RXD__UART4_TXD \ + IOMUX_PAD(0x02AC, 0x0054, 2, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_AUD_RXD__UART4_RXD \ + IOMUX_PAD(0x02AC, 0x0054, 2, 0x0814, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_AUD_RXD__FEC_RX_ER \ + IOMUX_PAD(0x02AC, 0x0054, 3, 0x0708, 0, NO_PAD_CTRL) +#define MX6SL_PAD_AUD_RXD__USDHC1_LCTL \ + IOMUX_PAD(0x02AC, 0x0054, 4, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_AUD_RXD__GPIO_1_2 \ + IOMUX_PAD(0x02AC, 0x0054, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_AUD_RXD__SRC_INT_BOOT \ + IOMUX_PAD(0x02AC, 0x0054, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_AUD_RXD__PL301_SIM_MX6SL_PER1_HRESP \ + IOMUX_PAD(0x02AC, 0x0054, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_AUD_RXFS__AUDMUX_AUD3_RXFS \ + IOMUX_PAD(0x02B0, 0x0058, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_AUD_RXFS__I2C1_SCL \ + IOMUX_PAD(0x02B0, 0x0058, 1 | IOMUX_CONFIG_SION, 0x071C, 0, MX6SL_I2C_PAD_CTRL) +#define MX6SL_PAD_AUD_RXFS__UART3_TXD \ + IOMUX_PAD(0x02B0, 0x0058, 2, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_AUD_RXFS__UART3_RXD \ + IOMUX_PAD(0x02B0, 0x0058, 2, 0x080C, 1, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_AUD_RXFS__FEC_MDIO \ + IOMUX_PAD(0x02B0, 0x0058, 3, 0x06F4, 0, NO_PAD_CTRL) +#define MX6SL_PAD_AUD_RXFS__I2C3_SCL \ + IOMUX_PAD(0x02B0, 0x0058, 4 | IOMUX_CONFIG_SION, 0x072C, 0, MX6SL_I2C_PAD_CTRL) +#define MX6SL_PAD_AUD_RXFS__GPIO_1_0 \ + IOMUX_PAD(0x02B0, 0x0058, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_AUD_RXFS__ECSPI3_SS0 \ + IOMUX_PAD(0x02B0, 0x0058, 6, 0x06C0, 0, NO_PAD_CTRL) +#define MX6SL_PAD_AUD_RXFS__PL301_SIM_MX6SL_PER1_HPROT_1 \ + IOMUX_PAD(0x02B0, 0x0058, 7, 0x07EC, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_AUD_TXC__AUDMUX_AUD3_TXC \ + IOMUX_PAD(0x02B4, 0x005C, 0, 0x0000, 0, MX6SL_ADU_PAD_CTRL) +#define MX6SL_PAD_AUD_TXC__ECSPI3_MISO \ + IOMUX_PAD(0x02B4, 0x005C, 1, 0x06B8, 0, NO_PAD_CTRL) +#define MX6SL_PAD_AUD_TXC__UART4_TXD \ + IOMUX_PAD(0x02B4, 0x005C, 2, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_AUD_TXC__UART4_RXD \ + IOMUX_PAD(0x02B4, 0x005C, 2, 0x0814, 1, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_AUD_TXC__FEC_RX_DV \ + IOMUX_PAD(0x02B4, 0x005C, 3, 0x0704, 0, NO_PAD_CTRL) +#define MX6SL_PAD_AUD_TXC__USDHC2_LCTL \ + IOMUX_PAD(0x02B4, 0x005C, 4, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_AUD_TXC__GPIO_1_3 \ + IOMUX_PAD(0x02B4, 0x005C, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_AUD_TXC__SRC_SYSTEM_RST \ + IOMUX_PAD(0x02B4, 0x005C, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_AUD_TXC__TPSMP_HDATA_24 \ + IOMUX_PAD(0x02B4, 0x005C, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_AUD_TXD__AUDMUX_AUD3_TXD \ + IOMUX_PAD(0x02B8, 0x0060, 0, 0x0000, 0, MX6SL_ADU_PAD_CTRL) +#define MX6SL_PAD_AUD_TXD__ECSPI3_SCLK \ + IOMUX_PAD(0x02B8, 0x0060, 1, 0x06B0, 0, NO_PAD_CTRL) +#define MX6SL_PAD_AUD_TXD__UART4_CTS \ + IOMUX_PAD(0x02B8, 0x0060, 2, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_AUD_TXD__UART4_RTS \ + IOMUX_PAD(0x02B8, 0x0060, 2, 0x0810, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_AUD_TXD__FEC_TDATA_0 \ + IOMUX_PAD(0x02B8, 0x0060, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_AUD_TXD__USDHC4_LCTL \ + IOMUX_PAD(0x02B8, 0x0060, 4, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_AUD_TXD__GPIO_1_5 \ + IOMUX_PAD(0x02B8, 0x0060, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_AUD_TXD__ANATOP_ANATOP_TESTI_1 \ + IOMUX_PAD(0x02B8, 0x0060, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_AUD_TXD__TPSMP_HDATA_26 \ + IOMUX_PAD(0x02B8, 0x0060, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_AUD_TXFS__AUDMUX_AUD3_TXFS \ + IOMUX_PAD(0x02BC, 0x0064, 0, 0x0000, 0, MX6SL_ADU_PAD_CTRL) +#define MX6SL_PAD_AUD_TXFS__PWM3_PWMO \ + IOMUX_PAD(0x02BC, 0x0064, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_AUD_TXFS__UART4_CTS \ + IOMUX_PAD(0x02BC, 0x0064, 2, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_AUD_TXFS__UART4_RTS \ + IOMUX_PAD(0x02BC, 0x0064, 2, 0x0810, 1, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_AUD_TXFS__FEC_RDATA_1 \ + IOMUX_PAD(0x02BC, 0x0064, 3, 0x06FC, 0, NO_PAD_CTRL) +#define MX6SL_PAD_AUD_TXFS__USDHC3_LCTL \ + IOMUX_PAD(0x02BC, 0x0064, 4, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_AUD_TXFS__GPIO_1_4 \ + IOMUX_PAD(0x02BC, 0x0064, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_AUD_TXFS__ANATOP_ANATOP_TESTI_0 \ + IOMUX_PAD(0x02BC, 0x0064, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_AUD_TXFS__TPSMP_HDATA_25 \ + IOMUX_PAD(0x02BC, 0x0064, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_BOOT_MODE0__SRC_BOOT_MODE_0 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_BOOT_MODE1__SRC_BOOT_MODE_1 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_A0__MMDC_DRAM_A_0 \ + IOMUX_PAD(0x02C0, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_A1__MMDC_DRAM_A_1 \ + IOMUX_PAD(0x02C4, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_A10__MMDC_DRAM_A_10 \ + IOMUX_PAD(0x02C8, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_A11__MMDC_DRAM_A_11 \ + IOMUX_PAD(0x02CC, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_A12__MMDC_DRAM_A_12 \ + IOMUX_PAD(0x02D0, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_A13__MMDC_DRAM_A_13 \ + IOMUX_PAD(0x02D4, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_A14__MMDC_DRAM_A_14 \ + IOMUX_PAD(0x02D8, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_A15__MMDC_DRAM_A_15 \ + IOMUX_PAD(0x02DC, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_A2__MMDC_DRAM_A_2 \ + IOMUX_PAD(0x02E0, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_A3__MMDC_DRAM_A_3 \ + IOMUX_PAD(0x02E4, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_A4__MMDC_DRAM_A_4 \ + IOMUX_PAD(0x02E8, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_A5__MMDC_DRAM_A_5 \ + IOMUX_PAD(0x02EC, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_A6__MMDC_DRAM_A_6 \ + IOMUX_PAD(0x02F0, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_A7__MMDC_DRAM_A_7 \ + IOMUX_PAD(0x02F4, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_A8__MMDC_DRAM_A_8 \ + IOMUX_PAD(0x02F8, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_A9__MMDC_DRAM_A_9 \ + IOMUX_PAD(0x02FC, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_CAS__MMDC_DRAM_CAS \ + IOMUX_PAD(0x0300, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_CS0__MMDC_DRAM_CS_0 \ + IOMUX_PAD(0x0304, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_CS1__MMDC_DRAM_CS_1 \ + IOMUX_PAD(0x0308, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_D0__MMDC_DRAM_D_0 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_D1__MMDC_DRAM_D_1 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_D10__MMDC_DRAM_D_10 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_D11__MMDC_DRAM_D_11 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_D12__MMDC_DRAM_D_12 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_D13__MMDC_DRAM_D_13 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_D14__MMDC_DRAM_D_14 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_D15__MMDC_DRAM_D_15 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_D16__MMDC_DRAM_D_16 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_D17__MMDC_DRAM_D_17 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_D18__MMDC_DRAM_D_18 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_D19__MMDC_DRAM_D_19 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_D2__MMDC_DRAM_D_2 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_D20__MMDC_DRAM_D_20 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_D21__MMDC_DRAM_D_21 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_D22__MMDC_DRAM_D_22 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_D23__MMDC_DRAM_D_23 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_D24__MMDC_DRAM_D_24 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_D25__MMDC_DRAM_D_25 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_D26__MMDC_DRAM_D_26 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_D27__MMDC_DRAM_D_27 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_D28__MMDC_DRAM_D_28 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_D29__MMDC_DRAM_D_29 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_D3__MMDC_DRAM_D_3 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_D30__MMDC_DRAM_D_30 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_D31__MMDC_DRAM_D_31 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_D4__MMDC_DRAM_D_4 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_D5__MMDC_DRAM_D_5 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_D6__MMDC_DRAM_D_6 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_D7__MMDC_DRAM_D_7 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_D8__MMDC_DRAM_D_8 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_D9__MMDC_DRAM_D_9 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0 \ + IOMUX_PAD(0x030C, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1 \ + IOMUX_PAD(0x0310, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2 \ + IOMUX_PAD(0x0314, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3 \ + IOMUX_PAD(0x0318, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_RAS__MMDC_DRAM_RAS \ + IOMUX_PAD(0x031C, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_RESET__MMDC_DRAM_RESET \ + IOMUX_PAD(0x0320, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0 \ + IOMUX_PAD(0x0324, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1 \ + IOMUX_PAD(0x0328, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2 \ + IOMUX_PAD(0x032C, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0 \ + IOMUX_PAD(0x0330, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1 \ + IOMUX_PAD(0x0334, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0 \ + IOMUX_PAD(0x0338, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0 \ + IOMUX_PAD(0x033C, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1 \ + IOMUX_PAD(0x0340, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0 \ + IOMUX_PAD(0x0344, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1 \ + IOMUX_PAD(0x0348, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2 \ + IOMUX_PAD(0x034C, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3 \ + IOMUX_PAD(0x0350, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_SDWE__MMDC_DRAM_SDWE \ + IOMUX_PAD(0x0354, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_ECSPI1_MISO__ECSPI1_MISO \ + IOMUX_PAD(0x0358, 0x0068, 0, 0x0684, 0, MX6SL_ECSPI_PAD_CTRL) +#define MX6SL_PAD_ECSPI1_MISO__AUDMUX_AUD4_TXFS \ + IOMUX_PAD(0x0358, 0x0068, 1, 0x05F8, 0, NO_PAD_CTRL) +#define MX6SL_PAD_ECSPI1_MISO__UART5_CTS \ + IOMUX_PAD(0x0358, 0x0068, 2, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_ECSPI1_MISO__UART5_RTS \ + IOMUX_PAD(0x0358, 0x0068, 2, 0x0818, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_ECSPI1_MISO__EPDC_BDR_0 \ + IOMUX_PAD(0x0358, 0x0068, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_ECSPI1_MISO__USDHC2_WP \ + IOMUX_PAD(0x0358, 0x0068, 4, 0x0834, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_ECSPI1_MISO__GPIO_4_10 \ + IOMUX_PAD(0x0358, 0x0068, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_ECSPI1_MISO__CCM_PLL3_BYP \ + IOMUX_PAD(0x0358, 0x0068, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_ECSPI1_MISO__MMDC_MMDC_DEBUG_40 \ + IOMUX_PAD(0x0358, 0x0068, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_ECSPI1_MOSI__ECSPI1_MOSI \ + IOMUX_PAD(0x035C, 0x006C, 0, 0x0688, 0, MX6SL_ECSPI_PAD_CTRL) +#define MX6SL_PAD_ECSPI1_MOSI__AUDMUX_AUD4_TXC \ + IOMUX_PAD(0x035C, 0x006C, 1, 0x05F4, 0, NO_PAD_CTRL) +#define MX6SL_PAD_ECSPI1_MOSI__UART5_TXD \ + IOMUX_PAD(0x035C, 0x006C, 2, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_ECSPI1_MOSI__UART5_RXD \ + IOMUX_PAD(0x035C, 0x006C, 2, 0x081C, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_ECSPI1_MOSI__EPDC_VCOM_1 \ + IOMUX_PAD(0x035C, 0x006C, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_ECSPI1_MOSI__USDHC2_VSELECT \ + IOMUX_PAD(0x035C, 0x006C, 4, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_ECSPI1_MOSI__GPIO_4_9 \ + IOMUX_PAD(0x035C, 0x006C, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_ECSPI1_MOSI__CCM_PLL2_BYP \ + IOMUX_PAD(0x035C, 0x006C, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_ECSPI1_MOSI__MMDC_MMDC_DEBUG_49 \ + IOMUX_PAD(0x035C, 0x006C, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_ECSPI1_SCLK__ECSPI1_SCLK \ + IOMUX_PAD(0x0360, 0x0070, 0, 0x067C, 0, MX6SL_ECSPI_PAD_CTRL) +#define MX6SL_PAD_ECSPI1_SCLK__AUDMUX_AUD4_TXD \ + IOMUX_PAD(0x0360, 0x0070, 1, 0x05E8, 0, NO_PAD_CTRL) +#define MX6SL_PAD_ECSPI1_SCLK__UART5_TXD \ + IOMUX_PAD(0x0360, 0x0070, 2, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_ECSPI1_SCLK__UART5_RXD \ + IOMUX_PAD(0x0360, 0x0070, 2, 0x081C, 1, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_ECSPI1_SCLK__EPDC_VCOM_0 \ + IOMUX_PAD(0x0360, 0x0070, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_ECSPI1_SCLK__USDHC2_RST \ + IOMUX_PAD(0x0360, 0x0070, 4, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_ECSPI1_SCLK__GPIO_4_8 \ + IOMUX_PAD(0x0360, 0x0070, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_ECSPI1_SCLK__USB_USBOTG2_OC \ + IOMUX_PAD(0x0360, 0x0070, 6, 0x0820, 0, NO_PAD_CTRL) +#define MX6SL_PAD_ECSPI1_SCLK__TPSMP_HDATA_18 \ + IOMUX_PAD(0x0360, 0x0070, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_ECSPI1_SS0__ECSPI1_SS0 \ + IOMUX_PAD(0x0364, 0x0074, 0, 0x068C, 0, MX6SL_ECSPI_PAD_CTRL) +#define MX6SL_PAD_ECSPI1_SS0__AUDMUX_AUD4_RXD \ + IOMUX_PAD(0x0364, 0x0074, 1, 0x05E4, 0, NO_PAD_CTRL) +#define MX6SL_PAD_ECSPI1_SS0__UART5_CTS \ + IOMUX_PAD(0x0364, 0x0074, 2, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_ECSPI1_SS0__UART5_RTS \ + IOMUX_PAD(0x0364, 0x0074, 2, 0x0818, 1, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_ECSPI1_SS0__EPDC_BDR_1 \ + IOMUX_PAD(0x0364, 0x0074, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_ECSPI1_SS0__USDHC2_CD \ + IOMUX_PAD(0x0364, 0x0074, 4, 0x0830, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_ECSPI1_SS0__GPIO_4_11 \ + IOMUX_PAD(0x0364, 0x0074, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_ECSPI1_SS0__USB_USBOTG2_PWR \ + IOMUX_PAD(0x0364, 0x0074, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_ECSPI1_SS0__PL301_SIM_MX6SL_PER1_HADDR_23 \ + IOMUX_PAD(0x0364, 0x0074, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_ECSPI2_MISO__GPIO_4_14 \ + IOMUX_PAD(0x0368, 0x0078, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_ECSPI2_MISO__USB_USBOTG1_OC \ + IOMUX_PAD(0x0368, 0x0078, 6, 0x0824, 0, NO_PAD_CTRL) +#define MX6SL_PAD_ECSPI2_MISO__TPSMP_HDATA_23 \ + IOMUX_PAD(0x0368, 0x0078, 7, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_ECSPI2_MISO__ECSPI2_MISO \ + IOMUX_PAD(0x0368, 0x0078, 0, 0x06A0, 0, NO_PAD_CTRL) +#define MX6SL_PAD_ECSPI2_MISO__SDMA_SDMA_EXT_EVENT_0 \ + IOMUX_PAD(0x0368, 0x0078, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_ECSPI2_MISO__UART3_CTS \ + IOMUX_PAD(0x0368, 0x0078, 2, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_ECSPI2_MISO__UART3_RTS \ + IOMUX_PAD(0x0368, 0x0078, 2, 0x0808, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_ECSPI2_MISO__CSI_MCLK \ + IOMUX_PAD(0x0368, 0x0078, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_ECSPI2_MISO__USDHC1_WP \ + IOMUX_PAD(0x0368, 0x0078, 4, 0x082C, 0, MX6SL_USDHC_PAD_CTRL) + +#define MX6SL_PAD_ECSPI2_MOSI__ECSPI2_MOSI \ + IOMUX_PAD(0x036C, 0x007C, 0, 0x06A4, 0, NO_PAD_CTRL) +#define MX6SL_PAD_ECSPI2_MOSI__SDMA_SDMA_EXT_EVENT_1 \ + IOMUX_PAD(0x036C, 0x007C, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_ECSPI2_MOSI__UART3_TXD \ + IOMUX_PAD(0x036C, 0x007C, 2, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_ECSPI2_MOSI__UART3_RXD \ + IOMUX_PAD(0x036C, 0x007C, 2, 0x080C, 2, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_ECSPI2_MOSI__CSI_HSYNC \ + IOMUX_PAD(0x036C, 0x007C, 3, 0x0670, 0, NO_PAD_CTRL) +#define MX6SL_PAD_ECSPI2_MOSI__USDHC1_VSELECT \ + IOMUX_PAD(0x036C, 0x007C, 4, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_ECSPI2_MOSI__GPIO_4_13 \ + IOMUX_PAD(0x036C, 0x007C, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_ECSPI2_MOSI__ANATOP_ANATOP_TESTO_1 \ + IOMUX_PAD(0x036C, 0x007C, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_ECSPI2_MOSI__TPSMP_HDATA_22 \ + IOMUX_PAD(0x036C, 0x007C, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_ECSPI2_SCLK__ECSPI2_SCLK \ + IOMUX_PAD(0x0370, 0x0080, 0, 0x069C, 0, NO_PAD_CTRL) +#define MX6SL_PAD_ECSPI2_SCLK__SPDIF_SPDIF_EXT_CLK \ + IOMUX_PAD(0x0370, 0x0080, 1, 0x07F4, 1, NO_PAD_CTRL) +#define MX6SL_PAD_ECSPI2_SCLK__UART3_TXD \ + IOMUX_PAD(0x0370, 0x0080, 2, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_ECSPI2_SCLK__UART3_RXD \ + IOMUX_PAD(0x0370, 0x0080, 2, 0x080C, 3, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_ECSPI2_SCLK__CSI_PIXCLK \ + IOMUX_PAD(0x0370, 0x0080, 3, 0x0674, 0, NO_PAD_CTRL) +#define MX6SL_PAD_ECSPI2_SCLK__USDHC1_RST \ + IOMUX_PAD(0x0370, 0x0080, 4, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_ECSPI2_SCLK__GPIO_4_12 \ + IOMUX_PAD(0x0370, 0x0080, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_ECSPI2_SCLK__USB_USBOTG2_OC \ + IOMUX_PAD(0x0370, 0x0080, 6, 0x0820, 1, NO_PAD_CTRL) +#define MX6SL_PAD_ECSPI2_SCLK__TPSMP_HDATA_21 \ + IOMUX_PAD(0x0370, 0x0080, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_ECSPI2_SS0__ECSPI2_SS0 \ + IOMUX_PAD(0x0374, 0x0084, 0, 0x06A8, 0, NO_PAD_CTRL) +#define MX6SL_PAD_ECSPI2_SS0__ECSPI1_SS3 \ + IOMUX_PAD(0x0374, 0x0084, 1, 0x0698, 0, NO_PAD_CTRL) +#define MX6SL_PAD_ECSPI2_SS0__UART3_CTS \ + IOMUX_PAD(0x0374, 0x0084, 2, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_ECSPI2_SS0__UART3_RTS \ + IOMUX_PAD(0x0374, 0x0084, 2, 0x0808, 1, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_ECSPI2_SS0__CSI_VSYNC \ + IOMUX_PAD(0x0374, 0x0084, 3, 0x0678, 0, NO_PAD_CTRL) +#define MX6SL_PAD_ECSPI2_SS0__USDHC1_CD \ + IOMUX_PAD(0x0374, 0x0084, 4, 0x0828, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_ECSPI2_SS0__GPIO_4_15 \ + IOMUX_PAD(0x0374, 0x0084, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_ECSPI2_SS0__USB_USBOTG1_PWR \ + IOMUX_PAD(0x0374, 0x0084, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_ECSPI2_SS0__PL301_SIM_MX6SL_PER1_HADDR_24 \ + IOMUX_PAD(0x0374, 0x0084, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_EPDC_BDR0__EPDC_BDR_0 \ + IOMUX_PAD(0x0378, 0x0088, 0, 0x0000, 0, MX6SL_EPDC_PAD_CTRL) +#define MX6SL_PAD_EPDC_BDR0__USDHC4_CLK \ + IOMUX_PAD(0x0378, 0x0088, 1, 0x0850, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_EPDC_BDR0__UART3_CTS \ + IOMUX_PAD(0x0378, 0x0088, 2, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_EPDC_BDR0__UART3_RTS \ + IOMUX_PAD(0x0378, 0x0088, 2, 0x0808, 2, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_EPDC_BDR0__WEIM_WEIM_A_26 \ + IOMUX_PAD(0x0378, 0x0088, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_BDR0__TCON_RL \ + IOMUX_PAD(0x0378, 0x0088, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_BDR0__GPIO_2_5 \ + IOMUX_PAD(0x0378, 0x0088, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_BDR0__EPDC_SDCE_7 \ + IOMUX_PAD(0x0378, 0x0088, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_BDR0__MMDC_MMDC_DEBUG_9 \ + IOMUX_PAD(0x0378, 0x0088, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_EPDC_BDR1__EPDC_BDR_1 \ + IOMUX_PAD(0x037C, 0x008C, 0, 0x0000, 0, MX6SL_EPDC_PAD_CTRL) +#define MX6SL_PAD_EPDC_BDR1__USDHC4_CMD \ + IOMUX_PAD(0x037C, 0x008C, 1, 0x0858, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_EPDC_BDR1__UART3_CTS \ + IOMUX_PAD(0x037C, 0x008C, 2, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_EPDC_BDR1__UART3_RTS \ + IOMUX_PAD(0x037C, 0x008C, 2, 0x0808, 3, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_EPDC_BDR1__WEIM_WEIM_CRE \ + IOMUX_PAD(0x037C, 0x008C, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_BDR1__TCON_UD \ + IOMUX_PAD(0x037C, 0x008C, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_BDR1__GPIO_2_6 \ + IOMUX_PAD(0x037C, 0x008C, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_BDR1__EPDC_SDCE_8 \ + IOMUX_PAD(0x037C, 0x008C, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_BDR1__MMDC_MMDC_DEBUG_8 \ + IOMUX_PAD(0x037C, 0x008C, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_EPDC_D0__EPDC_SDDO_0 \ + IOMUX_PAD(0x0380, 0x0090, 0, 0x0000, 0, MX6SL_EPDC_PAD_CTRL) +#define MX6SL_PAD_EPDC_D0__ECSPI4_MOSI \ + IOMUX_PAD(0x0380, 0x0090, 1, 0x06D8, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D0__LCDIF_DAT_24 \ + IOMUX_PAD(0x0380, 0x0090, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D0__CSI_D_0 \ + IOMUX_PAD(0x0380, 0x0090, 3, 0x0630, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D0__TCON_E_DATA_0 \ + IOMUX_PAD(0x0380, 0x0090, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D0__GPIO_1_7 \ + IOMUX_PAD(0x0380, 0x0090, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D0__ANATOP_USBPHY1_TSTI_TX_HS_MODE \ + IOMUX_PAD(0x0380, 0x0090, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D0__OBSERVE_MUX_OUT_0 \ + IOMUX_PAD(0x0380, 0x0090, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_EPDC_D1__EPDC_SDDO_1 \ + IOMUX_PAD(0x0384, 0x0094, 0, 0x0000, 0, MX6SL_EPDC_PAD_CTRL) +#define MX6SL_PAD_EPDC_D1__ECSPI4_MISO \ + IOMUX_PAD(0x0384, 0x0094, 1, 0x06D4, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D1__LCDIF_DAT_25 \ + IOMUX_PAD(0x0384, 0x0094, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D1__CSI_D_1 \ + IOMUX_PAD(0x0384, 0x0094, 3, 0x0634, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D1__TCON_E_DATA_1 \ + IOMUX_PAD(0x0384, 0x0094, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D1__GPIO_1_8 \ + IOMUX_PAD(0x0384, 0x0094, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D1__ANATOP_USBPHY1_TSTI_TX_LS_MODE \ + IOMUX_PAD(0x0384, 0x0094, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D1__OBSERVE_MUX_OUT_1 \ + IOMUX_PAD(0x0384, 0x0094, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_EPDC_D10__EPDC_SDDO_10 \ + IOMUX_PAD(0x0388, 0x0098, 0, 0x0000, 0, MX6SL_EPDC_PAD_CTRL) +#define MX6SL_PAD_EPDC_D10__ECSPI3_SS0 \ + IOMUX_PAD(0x0388, 0x0098, 1, 0x06C0, 1, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D10__EPDC_PWRCTRL_2 \ + IOMUX_PAD(0x0388, 0x0098, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D10__WEIM_WEIM_A_18 \ + IOMUX_PAD(0x0388, 0x0098, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D10__TCON_E_DATA_10 \ + IOMUX_PAD(0x0388, 0x0098, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D10__GPIO_1_17 \ + IOMUX_PAD(0x0388, 0x0098, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D10__USDHC4_WP \ + IOMUX_PAD(0x0388, 0x0098, 6, 0x087C, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_EPDC_D10__MMDC_MMDC_DEBUG_29 \ + IOMUX_PAD(0x0388, 0x0098, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_EPDC_D11__EPDC_SDDO_11 \ + IOMUX_PAD(0x038C, 0x009C, 0, 0x0000, 0, MX6SL_EPDC_PAD_CTRL) +#define MX6SL_PAD_EPDC_D11__ECSPI3_SCLK \ + IOMUX_PAD(0x038C, 0x009C, 1, 0x06B0, 1, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D11__EPDC_PWRCTRL_3 \ + IOMUX_PAD(0x038C, 0x009C, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D11__WEIM_WEIM_A_19 \ + IOMUX_PAD(0x038C, 0x009C, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D11__TCON_E_DATA_11 \ + IOMUX_PAD(0x038C, 0x009C, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D11__GPIO_1_18 \ + IOMUX_PAD(0x038C, 0x009C, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D11__USDHC4_CD \ + IOMUX_PAD(0x038C, 0x009C, 6, 0x0854, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_EPDC_D11__MMDC_MMDC_DEBUG_28 \ + IOMUX_PAD(0x038C, 0x009C, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_EPDC_D12__EPDC_SDDO_12 \ + IOMUX_PAD(0x0390, 0x00A0, 0, 0x0000, 0, MX6SL_EPDC_PAD_CTRL) +#define MX6SL_PAD_EPDC_D12__UART2_TXD \ + IOMUX_PAD(0x0390, 0x00A0, 1, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_EPDC_D12__UART2_RXD \ + IOMUX_PAD(0x0390, 0x00A0, 1, 0x0804, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_EPDC_D12__EPDC_PWRCOM \ + IOMUX_PAD(0x0390, 0x00A0, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D12__WEIM_WEIM_A_20 \ + IOMUX_PAD(0x0390, 0x00A0, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D12__TCON_E_DATA_12 \ + IOMUX_PAD(0x0390, 0x00A0, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D12__GPIO_1_19 \ + IOMUX_PAD(0x0390, 0x00A0, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D12__ECSPI3_SS1 \ + IOMUX_PAD(0x0390, 0x00A0, 6, 0x06C4, 1, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D12__MMDC_MMDC_DEBUG_27 \ + IOMUX_PAD(0x0390, 0x00A0, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_EPDC_D13__EPDC_SDDO_13 \ + IOMUX_PAD(0x0394, 0x00A4, 0, 0x0000, 0, MX6SL_EPDC_PAD_CTRL) +#define MX6SL_PAD_EPDC_D13__UART2_TXD \ + IOMUX_PAD(0x0394, 0x00A4, 1, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_EPDC_D13__UART2_RXD \ + IOMUX_PAD(0x0394, 0x00A4, 1, 0x0804, 1, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_EPDC_D13__EPDC_PWRIRQ \ + IOMUX_PAD(0x0394, 0x00A4, 2, 0x06E8, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D13__WEIM_WEIM_A_21 \ + IOMUX_PAD(0x0394, 0x00A4, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D13__TCON_E_DATA_13 \ + IOMUX_PAD(0x0394, 0x00A4, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D13__GPIO_1_20 \ + IOMUX_PAD(0x0394, 0x00A4, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D13__ECSPI3_SS2 \ + IOMUX_PAD(0x0394, 0x00A4, 6, 0x06C8, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D13__MMDC_MMDC_DEBUG_26 \ + IOMUX_PAD(0x0394, 0x00A4, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_EPDC_D14__EPDC_SDDO_14 \ + IOMUX_PAD(0x0398, 0x00A8, 0, 0x0000, 0, MX6SL_EPDC_PAD_CTRL) +#define MX6SL_PAD_EPDC_D14__UART2_CTS \ + IOMUX_PAD(0x0398, 0x00A8, 1, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_EPDC_D14__UART2_RTS \ + IOMUX_PAD(0x0398, 0x00A8, 1, 0x0800, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_EPDC_D14__EPDC_PWRSTAT \ + IOMUX_PAD(0x0398, 0x00A8, 2, 0x06EC, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D14__WEIM_WEIM_A_22 \ + IOMUX_PAD(0x0398, 0x00A8, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D14__TCON_E_DATA_14 \ + IOMUX_PAD(0x0398, 0x00A8, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D14__GPIO_1_21 \ + IOMUX_PAD(0x0398, 0x00A8, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D14__ECSPI3_SS3 \ + IOMUX_PAD(0x0398, 0x00A8, 6, 0x06CC, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D14__MMDC_MMDC_DEBUG_25 \ + IOMUX_PAD(0x0398, 0x00A8, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_EPDC_D15__EPDC_SDDO_15 \ + IOMUX_PAD(0x039C, 0x00AC, 0, 0x0000, 0, MX6SL_EPDC_PAD_CTRL) +#define MX6SL_PAD_EPDC_D15__UART2_CTS \ + IOMUX_PAD(0x039C, 0x00AC, 1, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_EPDC_D15__UART2_RTS \ + IOMUX_PAD(0x039C, 0x00AC, 1, 0x0800, 1, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_EPDC_D15__EPDC_PWRWAKE \ + IOMUX_PAD(0x039C, 0x00AC, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D15__WEIM_WEIM_A_23 \ + IOMUX_PAD(0x039C, 0x00AC, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D15__TCON_E_DATA_15 \ + IOMUX_PAD(0x039C, 0x00AC, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D15__GPIO_1_22 \ + IOMUX_PAD(0x039C, 0x00AC, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D15__ECSPI3_RDY \ + IOMUX_PAD(0x039C, 0x00AC, 6, 0x06B4, 1, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D15__MMDC_MMDC_DEBUG_24 \ + IOMUX_PAD(0x039C, 0x00AC, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_EPDC_D2__EPDC_SDDO_2 \ + IOMUX_PAD(0x03A0, 0x00B0, 0, 0x0000, 0, MX6SL_EPDC_PAD_CTRL) +#define MX6SL_PAD_EPDC_D2__ECSPI4_SS0 \ + IOMUX_PAD(0x03A0, 0x00B0, 1, 0x06DC, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D2__LCDIF_DAT_26 \ + IOMUX_PAD(0x03A0, 0x00B0, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D2__CSI_D_2 \ + IOMUX_PAD(0x03A0, 0x00B0, 3, 0x0638, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D2__TCON_E_DATA_2 \ + IOMUX_PAD(0x03A0, 0x00B0, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D2__GPIO_1_9 \ + IOMUX_PAD(0x03A0, 0x00B0, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D2__ANATOP_USBPHY1_TSTI_TX_DN \ + IOMUX_PAD(0x03A0, 0x00B0, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D2__TPSMP_HDATA_28 \ + IOMUX_PAD(0x03A0, 0x00B0, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_EPDC_D3__EPDC_SDDO_3 \ + IOMUX_PAD(0x03A4, 0x00B4, 0, 0x0000, 0, MX6SL_EPDC_PAD_CTRL) +#define MX6SL_PAD_EPDC_D3__ECSPI4_SCLK \ + IOMUX_PAD(0x03A4, 0x00B4, 1, 0x06D0, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D3__LCDIF_DAT_27 \ + IOMUX_PAD(0x03A4, 0x00B4, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D3__CSI_D_3 \ + IOMUX_PAD(0x03A4, 0x00B4, 3, 0x063C, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D3__TCON_E_DATA_3 \ + IOMUX_PAD(0x03A4, 0x00B4, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D3__GPIO_1_10 \ + IOMUX_PAD(0x03A4, 0x00B4, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D3__ANATOP_USBPHY1_TSTI_TX_DP \ + IOMUX_PAD(0x03A4, 0x00B4, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D3__TPSMP_HDATA_29 \ + IOMUX_PAD(0x03A4, 0x00B4, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_EPDC_D4__EPDC_SDDO_4 \ + IOMUX_PAD(0x03A8, 0x00B8, 0, 0x0000, 0, MX6SL_EPDC_PAD_CTRL) +#define MX6SL_PAD_EPDC_D4__ECSPI4_SS1 \ + IOMUX_PAD(0x03A8, 0x00B8, 1, 0x06E0, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D4__LCDIF_DAT_28 \ + IOMUX_PAD(0x03A8, 0x00B8, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D4__CSI_D_4 \ + IOMUX_PAD(0x03A8, 0x00B8, 3, 0x0640, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D4__TCON_E_DATA_4 \ + IOMUX_PAD(0x03A8, 0x00B8, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D4__GPIO_1_11 \ + IOMUX_PAD(0x03A8, 0x00B8, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D4__ANATOP_USBPHY1_TSTI_TX_EN \ + IOMUX_PAD(0x03A8, 0x00B8, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D4__TPSMP_HDATA_30 \ + IOMUX_PAD(0x03A8, 0x00B8, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_EPDC_D5__EPDC_SDDO_5 \ + IOMUX_PAD(0x03AC, 0x00BC, 0, 0x0000, 0, MX6SL_EPDC_PAD_CTRL) +#define MX6SL_PAD_EPDC_D5__ECSPI4_SS2 \ + IOMUX_PAD(0x03AC, 0x00BC, 1, 0x06E4, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D5__LCDIF_DAT_29 \ + IOMUX_PAD(0x03AC, 0x00BC, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D5__CSI_D_5 \ + IOMUX_PAD(0x03AC, 0x00BC, 3, 0x0644, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D5__TCON_E_DATA_5 \ + IOMUX_PAD(0x03AC, 0x00BC, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D5__GPIO_1_12 \ + IOMUX_PAD(0x03AC, 0x00BC, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D5__ANATOP_USBPHY1_TSTI_TX_HIZ \ + IOMUX_PAD(0x03AC, 0x00BC, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D5__TPSMP_HDATA_31 \ + IOMUX_PAD(0x03AC, 0x00BC, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_EPDC_D6__EPDC_SDDO_6 \ + IOMUX_PAD(0x03B0, 0x00C0, 0, 0x0000, 0, MX6SL_EPDC_PAD_CTRL) +#define MX6SL_PAD_EPDC_D6__ECSPI4_SS3 \ + IOMUX_PAD(0x03B0, 0x00C0, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D6__LCDIF_DAT_30 \ + IOMUX_PAD(0x03B0, 0x00C0, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D6__CSI_D_6 \ + IOMUX_PAD(0x03B0, 0x00C0, 3, 0x0648, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D6__TCON_E_DATA_6 \ + IOMUX_PAD(0x03B0, 0x00C0, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D6__GPIO_1_13 \ + IOMUX_PAD(0x03B0, 0x00C0, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D6__ANATOP_USBPHY2_TSTO_RX_DISCON_DET \ + IOMUX_PAD(0x03B0, 0x00C0, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D6__TPSMP_HDATA_20 \ + IOMUX_PAD(0x03B0, 0x00C0, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_EPDC_D7__EPDC_SDDO_7 \ + IOMUX_PAD(0x03B4, 0x00C4, 0, 0x0000, 0, MX6SL_EPDC_PAD_CTRL) +#define MX6SL_PAD_EPDC_D7__ECSPI4_RDY \ + IOMUX_PAD(0x03B4, 0x00C4, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D7__LCDIF_DAT_31 \ + IOMUX_PAD(0x03B4, 0x00C4, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D7__CSI_D_7 \ + IOMUX_PAD(0x03B4, 0x00C4, 3, 0x064C, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D7__TCON_E_DATA_7 \ + IOMUX_PAD(0x03B4, 0x00C4, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D7__GPIO_1_14 \ + IOMUX_PAD(0x03B4, 0x00C4, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D7__ANATOP_USBPHY2_TSTO_RX_FS_RXD \ + IOMUX_PAD(0x03B4, 0x00C4, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D7__MMDC_MMDC_DEBUG_32 \ + IOMUX_PAD(0x03B4, 0x00C4, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_EPDC_D8__EPDC_SDDO_8 \ + IOMUX_PAD(0x03B8, 0x00C8, 0, 0x0000, 0, MX6SL_EPDC_PAD_CTRL) +#define MX6SL_PAD_EPDC_D8__ECSPI3_MOSI \ + IOMUX_PAD(0x03B8, 0x00C8, 1, 0x06BC, 1, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D8__EPDC_PWRCTRL_0 \ + IOMUX_PAD(0x03B8, 0x00C8, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D8__WEIM_WEIM_A_16 \ + IOMUX_PAD(0x03B8, 0x00C8, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D8__TCON_E_DATA_8 \ + IOMUX_PAD(0x03B8, 0x00C8, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D8__GPIO_1_15 \ + IOMUX_PAD(0x03B8, 0x00C8, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D8__USDHC4_RST \ + IOMUX_PAD(0x03B8, 0x00C8, 6, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_EPDC_D8__MMDC_MMDC_DEBUG_31 \ + IOMUX_PAD(0x03B8, 0x00C8, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_EPDC_D9__EPDC_SDDO_9 \ + IOMUX_PAD(0x03BC, 0x00CC, 0, 0x0000, 0, MX6SL_EPDC_PAD_CTRL) +#define MX6SL_PAD_EPDC_D9__ECSPI3_MISO \ + IOMUX_PAD(0x03BC, 0x00CC, 1, 0x06B8, 1, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D9__EPDC_PWRCTRL_1 \ + IOMUX_PAD(0x03BC, 0x00CC, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D9__WEIM_WEIM_A_17 \ + IOMUX_PAD(0x03BC, 0x00CC, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D9__TCON_E_DATA_9 \ + IOMUX_PAD(0x03BC, 0x00CC, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D9__GPIO_1_16 \ + IOMUX_PAD(0x03BC, 0x00CC, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D9__USDHC4_VSELECT \ + IOMUX_PAD(0x03BC, 0x00CC, 6, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_EPDC_D9__MMDC_MMDC_DEBUG_30 \ + IOMUX_PAD(0x03BC, 0x00CC, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_EPDC_GDCLK__EPDC_GDCLK \ + IOMUX_PAD(0x03C0, 0x00D0, 0, 0x0000, 0, MX6SL_EPDC_PAD_CTRL) +#define MX6SL_PAD_EPDC_GDCLK__ECSPI2_SS2 \ + IOMUX_PAD(0x03C0, 0x00D0, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_GDCLK__TCON_YCKR \ + IOMUX_PAD(0x03C0, 0x00D0, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_GDCLK__CSI_PIXCLK \ + IOMUX_PAD(0x03C0, 0x00D0, 3, 0x0674, 1, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_GDCLK__TCON_YCKL \ + IOMUX_PAD(0x03C0, 0x00D0, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_GDCLK__GPIO_1_31 \ + IOMUX_PAD(0x03C0, 0x00D0, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_GDCLK__USDHC2_RST \ + IOMUX_PAD(0x03C0, 0x00D0, 6, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_EPDC_GDCLK__MMDC_MMDC_DEBUG_15 \ + IOMUX_PAD(0x03C0, 0x00D0, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_EPDC_GDOE__EPDC_GDOE \ + IOMUX_PAD(0x03C4, 0x00D4, 0, 0x0000, 0, MX6SL_EPDC_PAD_CTRL) +#define MX6SL_PAD_EPDC_GDOE__ECSPI2_SS3 \ + IOMUX_PAD(0x03C4, 0x00D4, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_GDOE__TCON_YOER \ + IOMUX_PAD(0x03C4, 0x00D4, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_GDOE__CSI_HSYNC \ + IOMUX_PAD(0x03C4, 0x00D4, 3, 0x0670, 1, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_GDOE__TCON_YOEL \ + IOMUX_PAD(0x03C4, 0x00D4, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_GDOE__GPIO_2_0 \ + IOMUX_PAD(0x03C4, 0x00D4, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_GDOE__USDHC2_VSELECT \ + IOMUX_PAD(0x03C4, 0x00D4, 6, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_EPDC_GDOE__MMDC_MMDC_DEBUG_14 \ + IOMUX_PAD(0x03C4, 0x00D4, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_EPDC_GDRL__EPDC_GDRL \ + IOMUX_PAD(0x03C8, 0x00D8, 0, 0x0000, 0, MX6SL_EPDC_PAD_CTRL) +#define MX6SL_PAD_EPDC_GDRL__ECSPI2_RDY \ + IOMUX_PAD(0x03C8, 0x00D8, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_GDRL__TCON_YDIOUR \ + IOMUX_PAD(0x03C8, 0x00D8, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_GDRL__CSI_MCLK \ + IOMUX_PAD(0x03C8, 0x00D8, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_GDRL__TCON_YDIOUL \ + IOMUX_PAD(0x03C8, 0x00D8, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_GDRL__GPIO_2_1 \ + IOMUX_PAD(0x03C8, 0x00D8, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_GDRL__USDHC2_WP \ + IOMUX_PAD(0x03C8, 0x00D8, 6, 0x0834, 1, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_EPDC_GDRL__MMDC_MMDC_DEBUG_13 \ + IOMUX_PAD(0x03C8, 0x00D8, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_EPDC_GDSP__EPDC_GDSP \ + IOMUX_PAD(0x03CC, 0x00DC, 0, 0x0000, 0, MX6SL_EPDC_PAD_CTRL) +#define MX6SL_PAD_EPDC_GDSP__PWM4_PWMO \ + IOMUX_PAD(0x03CC, 0x00DC, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_GDSP__TCON_YDIODR \ + IOMUX_PAD(0x03CC, 0x00DC, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_GDSP__CSI_VSYNC \ + IOMUX_PAD(0x03CC, 0x00DC, 3, 0x0678, 1, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_GDSP__TCON_YDIODL \ + IOMUX_PAD(0x03CC, 0x00DC, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_GDSP__GPIO_2_2 \ + IOMUX_PAD(0x03CC, 0x00DC, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_GDSP__USDHC2_CD \ + IOMUX_PAD(0x03CC, 0x00DC, 6, 0x0830, 1, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_EPDC_GDSP__MMDC_MMDC_DEBUG_12 \ + IOMUX_PAD(0x03CC, 0x00DC, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_EPDC_PWRCOM__EPDC_PWRCOM \ + IOMUX_PAD(0x03D0, 0x00E0, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRCOM__USDHC4_DAT0 \ + IOMUX_PAD(0x03D0, 0x00E0, 1, 0x085C, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRCOM__LCDIF_DAT_20 \ + IOMUX_PAD(0x03D0, 0x00E0, 2, 0x07C8, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRCOM__WEIM_WEIM_BCLK \ + IOMUX_PAD(0x03D0, 0x00E0, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRCOM__ANATOP_USBOTG1_ID \ + IOMUX_PAD(0x03D0, 0x00E0, 4, 0x05DC, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRCOM__GPIO_2_11 \ + IOMUX_PAD(0x03D0, 0x00E0, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRCOM__USDHC3_RST \ + IOMUX_PAD(0x03D0, 0x00E0, 6, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRCOM__MMDC_MMDC_DEBUG_3 \ + IOMUX_PAD(0x03D0, 0x00E0, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_EPDC_PWRCTRL0__EPDC_PWRCTRL_0 \ + IOMUX_PAD(0x03D4, 0x00E4, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRCTRL0__AUDMUX_AUD5_RXC \ + IOMUX_PAD(0x03D4, 0x00E4, 1, 0x0604, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRCTRL0__LCDIF_DAT_16 \ + IOMUX_PAD(0x03D4, 0x00E4, 2, 0x07B8, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRCTRL0__WEIM_WEIM_RW \ + IOMUX_PAD(0x03D4, 0x00E4, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRCTRL0__TCON_YCKL \ + IOMUX_PAD(0x03D4, 0x00E4, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRCTRL0__GPIO_2_7 \ + IOMUX_PAD(0x03D4, 0x00E4, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRCTRL0__USDHC4_RST \ + IOMUX_PAD(0x03D4, 0x00E4, 6, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRCTRL0__MMDC_MMDC_DEBUG_7 \ + IOMUX_PAD(0x03D4, 0x00E4, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_EPDC_PWRCTRL1__EPDC_PWRCTRL_1 \ + IOMUX_PAD(0x03D8, 0x00E8, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRCTRL1__AUDMUX_AUD5_TXFS \ + IOMUX_PAD(0x03D8, 0x00E8, 1, 0x0610, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRCTRL1__LCDIF_DAT_17 \ + IOMUX_PAD(0x03D8, 0x00E8, 2, 0x07BC, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRCTRL1__WEIM_WEIM_OE \ + IOMUX_PAD(0x03D8, 0x00E8, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRCTRL1__TCON_YOEL \ + IOMUX_PAD(0x03D8, 0x00E8, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRCTRL1__GPIO_2_8 \ + IOMUX_PAD(0x03D8, 0x00E8, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRCTRL1__USDHC4_VSELECT \ + IOMUX_PAD(0x03D8, 0x00E8, 6, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRCTRL1__MMDC_MMDC_DEBUG_6 \ + IOMUX_PAD(0x03D8, 0x00E8, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_EPDC_PWRCTRL2__EPDC_PWRCTRL_2 \ + IOMUX_PAD(0x03DC, 0x00EC, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRCTRL2__AUDMUX_AUD5_TXD \ + IOMUX_PAD(0x03DC, 0x00EC, 1, 0x0600, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRCTRL2__LCDIF_DAT_18 \ + IOMUX_PAD(0x03DC, 0x00EC, 2, 0x07C0, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRCTRL2__WEIM_WEIM_CS_0 \ + IOMUX_PAD(0x03DC, 0x00EC, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRCTRL2__TCON_YDIOUL \ + IOMUX_PAD(0x03DC, 0x00EC, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRCTRL2__GPIO_2_9 \ + IOMUX_PAD(0x03DC, 0x00EC, 5, 0x0000, 0, MX6SL_FLOAT_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRCTRL2__GPIO_2_9_PUINT \ + IOMUX_PAD(0x03DC, 0x00EC, 5, 0x0000, 0, PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) +#define MX6SL_PAD_EPDC_PWRCTRL2__USDHC4_WP \ + IOMUX_PAD(0x03DC, 0x00EC, 6, 0x087C, 1, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRCTRL2__MMDC_MMDC_DEBUG_5 \ + IOMUX_PAD(0x03DC, 0x00EC, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_EPDC_PWRCTRL3__EPDC_PWRCTRL_3 \ + IOMUX_PAD(0x03E0, 0x00F0, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRCTRL3__AUDMUX_AUD5_TXC \ + IOMUX_PAD(0x03E0, 0x00F0, 1, 0x060C, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRCTRL3__LCDIF_DAT_19 \ + IOMUX_PAD(0x03E0, 0x00F0, 2, 0x07C4, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRCTRL3__WEIM_WEIM_CS_1 \ + IOMUX_PAD(0x03E0, 0x00F0, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRCTRL3__TCON_YDIODL \ + IOMUX_PAD(0x03E0, 0x00F0, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRCTRL3__GPIO_2_10 \ + IOMUX_PAD(0x03E0, 0x00F0, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRCTRL3__USDHC4_CD \ + IOMUX_PAD(0x03E0, 0x00F0, 6, 0x0854, 1, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRCTRL3__MMDC_MMDC_DEBUG_4 \ + IOMUX_PAD(0x03E0, 0x00F0, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_EPDC_PWRINT__EPDC_PWRIRQ \ + IOMUX_PAD(0x03E4, 0x00F4, 0, 0x06E8, 1, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRINT__USDHC4_DAT1 \ + IOMUX_PAD(0x03E4, 0x00F4, 1, 0x0860, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRINT__LCDIF_DAT_21 \ + IOMUX_PAD(0x03E4, 0x00F4, 2, 0x07CC, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRINT__WEIM_ACLK_FREERUN \ + IOMUX_PAD(0x03E4, 0x00F4, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRINT__ANATOP_USBOTG2_ID \ + IOMUX_PAD(0x03E4, 0x00F4, 4, 0x05E0, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRINT__GPIO_2_12 \ + IOMUX_PAD(0x03E4, 0x00F4, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRINT__USDHC3_VSELECT \ + IOMUX_PAD(0x03E4, 0x00F4, 6, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRINT__MMDC_MMDC_DEBUG_2 \ + IOMUX_PAD(0x03E4, 0x00F4, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_EPDC_PWRSTAT__EPDC_PWRSTAT \ + IOMUX_PAD(0x03E8, 0x00F8, 0, 0x06EC, 1, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRSTAT__USDHC4_DAT2 \ + IOMUX_PAD(0x03E8, 0x00F8, 1, 0x0864, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRSTAT__LCDIF_DAT_22 \ + IOMUX_PAD(0x03E8, 0x00F8, 2, 0x07D0, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRSTAT__WEIM_WEIM_WAIT \ + IOMUX_PAD(0x03E8, 0x00F8, 3, 0x0884, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRSTAT__KITTEN_EVENTI \ + IOMUX_PAD(0x03E8, 0x00F8, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRSTAT__GPIO_2_13 \ + IOMUX_PAD(0x03E8, 0x00F8, 5, 0x0000, 0, MX6SL_FLOAT_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRSTAT__GPIO_2_13_PUINT \ + IOMUX_PAD(0x03E8, 0x00F8, 5, 0x0000, 0, PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) +#define MX6SL_PAD_EPDC_PWRSTAT__USDHC3_WP \ + IOMUX_PAD(0x03E8, 0x00F8, 6, 0x084C, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRSTAT__MMDC_MMDC_DEBUG_1 \ + IOMUX_PAD(0x03E8, 0x00F8, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_EPDC_PWRWAKEUP__EPDC_PWRWAKE \ + IOMUX_PAD(0x03EC, 0x00FC, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRWAKEUP__USDHC4_DAT3 \ + IOMUX_PAD(0x03EC, 0x00FC, 1, 0x0868, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRWAKEUP__LCDIF_DAT_23 \ + IOMUX_PAD(0x03EC, 0x00FC, 2, 0x07D4, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRWAKEUP__WEIM_WEIM_DTACK_B \ + IOMUX_PAD(0x03EC, 0x00FC, 3, 0x0880, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRWAKEUP__KITTEN_EVENTO \ + IOMUX_PAD(0x03EC, 0x00FC, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRWAKEUP__GPIO_2_14 \ + IOMUX_PAD(0x03EC, 0x00FC, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRWAKEUP__USDHC3_CD \ + IOMUX_PAD(0x03EC, 0x00FC, 6, 0x0838, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRWAKEUP__MMDC_MMDC_DEBUG_0 \ + IOMUX_PAD(0x03EC, 0x00FC, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_EPDC_SDCE0__EPDC_SDCE_0 \ + IOMUX_PAD(0x03F0, 0x0100, 0, 0x0000, 0, MX6SL_EPDC_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDCE0__ECSPI2_SS1 \ + IOMUX_PAD(0x03F0, 0x0100, 1, 0x06AC, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDCE0__PWM3_PWMO \ + IOMUX_PAD(0x03F0, 0x0100, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDCE0__WEIM_WEIM_CS_2 \ + IOMUX_PAD(0x03F0, 0x0100, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDCE0__TCON_YCKR \ + IOMUX_PAD(0x03F0, 0x0100, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDCE0__GPIO_1_27 \ + IOMUX_PAD(0x03F0, 0x0100, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDCE0__ANATOP_USBPHY1_TSTO_PLL_CLK20DIV \ + IOMUX_PAD(0x03F0, 0x0100, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDCE0__MMDC_MMDC_DEBUG_19 \ + IOMUX_PAD(0x03F0, 0x0100, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_EPDC_SDCE1__EPDC_SDCE_1 \ + IOMUX_PAD(0x03F4, 0x0104, 0, 0x0000, 0, MX6SL_EPDC_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDCE1__WDOG2_WDOG_B \ + IOMUX_PAD(0x03F4, 0x0104, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDCE1__PWM4_PWMO \ + IOMUX_PAD(0x03F4, 0x0104, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDCE1__WEIM_WEIM_LBA \ + IOMUX_PAD(0x03F4, 0x0104, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDCE1__TCON_YOER \ + IOMUX_PAD(0x03F4, 0x0104, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDCE1__GPIO_1_28 \ + IOMUX_PAD(0x03F4, 0x0104, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDCE1__ANATOP_USBPHY1_TSTO_RX_FS_RXD \ + IOMUX_PAD(0x03F4, 0x0104, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDCE1__MMDC_MMDC_DEBUG_18 \ + IOMUX_PAD(0x03F4, 0x0104, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_EPDC_SDCE2__EPDC_SDCE_2 \ + IOMUX_PAD(0x03F8, 0x0108, 0, 0x0000, 0, MX6SL_EPDC_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDCE2__I2C3_SCL \ + IOMUX_PAD(0x03F8, 0x0108, 1 | IOMUX_CONFIG_SION, 0x072C, 1, MX6SL_I2C_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDCE2__PWM1_PWMO \ + IOMUX_PAD(0x03F8, 0x0108, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDCE2__WEIM_WEIM_EB_0 \ + IOMUX_PAD(0x03F8, 0x0108, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDCE2__TCON_YDIOUR \ + IOMUX_PAD(0x03F8, 0x0108, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDCE2__GPIO_1_29 \ + IOMUX_PAD(0x03F8, 0x0108, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDCE2__ANATOP_USBPHY1_TSTO_RX_HS_RXD \ + IOMUX_PAD(0x03F8, 0x0108, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDCE2__MMDC_MMDC_DEBUG_17 \ + IOMUX_PAD(0x03F8, 0x0108, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_EPDC_SDCE3__EPDC_SDCE_3 \ + IOMUX_PAD(0x03FC, 0x010C, 0, 0x0000, 0, MX6SL_EPDC_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDCE3__I2C3_SDA \ + IOMUX_PAD(0x03FC, 0x010C, 1 | IOMUX_CONFIG_SION, 0x0730, 1, MX6SL_I2C_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDCE3__PWM2_PWMO \ + IOMUX_PAD(0x03FC, 0x010C, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDCE3__WEIM_WEIM_EB_1 \ + IOMUX_PAD(0x03FC, 0x010C, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDCE3__TCON_YDIODR \ + IOMUX_PAD(0x03FC, 0x010C, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDCE3__GPIO_1_30 \ + IOMUX_PAD(0x03FC, 0x010C, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDCE3__ANATOP_USBPHY1_TSTO_RX_SQUELCH \ + IOMUX_PAD(0x03FC, 0x010C, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDCE3__MMDC_MMDC_DEBUG_16 \ + IOMUX_PAD(0x03FC, 0x010C, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_EPDC_SDCLK__EPDC_SDCLK \ + IOMUX_PAD(0x0400, 0x0110, 0, 0x0000, 0, MX6SL_EPDC_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDCLK__ECSPI2_MOSI \ + IOMUX_PAD(0x0400, 0x0110, 1, 0x06A4, 1, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDCLK__I2C2_SCL \ + IOMUX_PAD(0x0400, 0x0110, 2 | IOMUX_CONFIG_SION, 0x0724, 0, MX6SL_I2C_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDCLK__CSI_D_8 \ + IOMUX_PAD(0x0400, 0x0110, 3, 0x0650, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDCLK__TCON_CL \ + IOMUX_PAD(0x0400, 0x0110, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDCLK__GPIO_1_23 \ + IOMUX_PAD(0x0400, 0x0110, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDCLK__ANATOP_USBPHY2_TSTO_RX_HS_RXD \ + IOMUX_PAD(0x0400, 0x0110, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDCLK__MMDC_MMDC_DEBUG_23 \ + IOMUX_PAD(0x0400, 0x0110, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_EPDC_SDLE__EPDC_SDLE \ + IOMUX_PAD(0x0404, 0x0114, 0, 0x0000, 0, MX6SL_EPDC_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDLE__ECSPI2_MISO \ + IOMUX_PAD(0x0404, 0x0114, 1, 0x06A0, 1, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDLE__I2C2_SDA \ + IOMUX_PAD(0x0404, 0x0114, 2 | IOMUX_CONFIG_SION, 0x0728, 0, MX6SL_I2C_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDLE__CSI_D_9 \ + IOMUX_PAD(0x0404, 0x0114, 3, 0x0654, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDLE__TCON_LD \ + IOMUX_PAD(0x0404, 0x0114, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDLE__GPIO_1_24 \ + IOMUX_PAD(0x0404, 0x0114, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDLE__ANATOP_USBPHY2_TSTO_RX_SQUELCH \ + IOMUX_PAD(0x0404, 0x0114, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDLE__MMDC_MMDC_DEBUG_22 \ + IOMUX_PAD(0x0404, 0x0114, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_EPDC_SDOE__EPDC_SDOE \ + IOMUX_PAD(0x0408, 0x0118, 0, 0x0000, 0, MX6SL_EPDC_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDOE__ECSPI2_SS0 \ + IOMUX_PAD(0x0408, 0x0118, 1, 0x06A8, 1, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDOE__TCON_XDIOR \ + IOMUX_PAD(0x0408, 0x0118, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDOE__CSI_D_10 \ + IOMUX_PAD(0x0408, 0x0118, 3, 0x0658, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDOE__TCON_XDIOL \ + IOMUX_PAD(0x0408, 0x0118, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDOE__GPIO_1_25 \ + IOMUX_PAD(0x0408, 0x0118, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDOE__ANATOP_USBPHY2_TSTO_PLL_CLK20DIV \ + IOMUX_PAD(0x0408, 0x0118, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDOE__MMDC_MMDC_DEBUG_21 \ + IOMUX_PAD(0x0408, 0x0118, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_EPDC_SDSHR__EPDC_SDSHR \ + IOMUX_PAD(0x040C, 0x011C, 0, 0x0000, 0, MX6SL_EPDC_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDSHR__ECSPI2_SCLK \ + IOMUX_PAD(0x040C, 0x011C, 1, 0x069C, 1, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDSHR__EPDC_SDCE_4 \ + IOMUX_PAD(0x040C, 0x011C, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDSHR__CSI_D_11 \ + IOMUX_PAD(0x040C, 0x011C, 3, 0x065C, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDSHR__TCON_XDIOR \ + IOMUX_PAD(0x040C, 0x011C, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDSHR__GPIO_1_26 \ + IOMUX_PAD(0x040C, 0x011C, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDSHR__ANATOP_USBPHY1_TSTO_RX_DISCON_DET \ + IOMUX_PAD(0x040C, 0x011C, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDSHR__MMDC_MMDC_DEBUG_20 \ + IOMUX_PAD(0x040C, 0x011C, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_EPDC_VCOM0__EPDC_VCOM_0 \ + IOMUX_PAD(0x0410, 0x0120, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_VCOM0__AUDMUX_AUD5_RXFS \ + IOMUX_PAD(0x0410, 0x0120, 1, 0x0608, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_VCOM0__UART3_TXD \ + IOMUX_PAD(0x0410, 0x0120, 2, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_EPDC_VCOM0__UART3_RXD \ + IOMUX_PAD(0x0410, 0x0120, 2, 0x080C, 4, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_EPDC_VCOM0__WEIM_WEIM_A_24 \ + IOMUX_PAD(0x0410, 0x0120, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_VCOM0__TCON_VCOM_0 \ + IOMUX_PAD(0x0410, 0x0120, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_VCOM0__GPIO_2_3 \ + IOMUX_PAD(0x0410, 0x0120, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_VCOM0__EPDC_SDCE_5 \ + IOMUX_PAD(0x0410, 0x0120, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_VCOM0__MMDC_MMDC_DEBUG_11 \ + IOMUX_PAD(0x0410, 0x0120, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_EPDC_VCOM1__EPDC_VCOM_1 \ + IOMUX_PAD(0x0414, 0x0124, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_VCOM1__AUDMUX_AUD5_RXD \ + IOMUX_PAD(0x0414, 0x0124, 1, 0x05FC, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_VCOM1__UART3_TXD \ + IOMUX_PAD(0x0414, 0x0124, 2, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_EPDC_VCOM1__UART3_RXD \ + IOMUX_PAD(0x0414, 0x0124, 2, 0x080C, 5, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_EPDC_VCOM1__WEIM_WEIM_A_25 \ + IOMUX_PAD(0x0414, 0x0124, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_VCOM1__TCON_VCOM_1 \ + IOMUX_PAD(0x0414, 0x0124, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_VCOM1__GPIO_2_4 \ + IOMUX_PAD(0x0414, 0x0124, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_VCOM1__EPDC_SDCE_6 \ + IOMUX_PAD(0x0414, 0x0124, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_VCOM1__MMDC_MMDC_DEBUG_10 \ + IOMUX_PAD(0x0414, 0x0124, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_FEC_CRS_DV__FEC_RX_DV \ + IOMUX_PAD(0x0418, 0x0128, 0, 0x0704, 1, MX6SL_ENET_PAD_CTRL) +#define MX6SL_PAD_FEC_CRS_DV__USDHC4_DAT1 \ + IOMUX_PAD(0x0418, 0x0128, 1, 0x0860, 1, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_FEC_CRS_DV__AUDMUX_AUD6_TXC \ + IOMUX_PAD(0x0418, 0x0128, 2, 0x0624, 0, NO_PAD_CTRL) +#define MX6SL_PAD_FEC_CRS_DV__ECSPI4_MISO \ + IOMUX_PAD(0x0418, 0x0128, 3, 0x06D4, 1, NO_PAD_CTRL) +#define MX6SL_PAD_FEC_CRS_DV__GPT_CMPOUT2 \ + IOMUX_PAD(0x0418, 0x0128, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_FEC_CRS_DV__GPIO_4_25 \ + IOMUX_PAD(0x0418, 0x0128, 5, 0x0000, 0, MX6SL_FLOAT_PAD_CTRL) +#define MX6SL_PAD_FEC_CRS_DV__KITTEN_TRACE_31 \ + IOMUX_PAD(0x0418, 0x0128, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_FEC_CRS_DV__PL301_SIM_MX6SL_PER1_HADDR_3 \ + IOMUX_PAD(0x0418, 0x0128, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_FEC_MDC__FEC_MDC \ + IOMUX_PAD(0x041C, 0x012C, 0, 0x0000, 0, MX6SL_ENET_PAD_CTRL) +#define MX6SL_PAD_FEC_MDC__USDHC4_DAT4 \ + IOMUX_PAD(0x041C, 0x012C, 1, 0x086C, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_FEC_MDC__AUDMUX_AUDIO_CLK_OUT \ + IOMUX_PAD(0x041C, 0x012C, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_FEC_MDC__USDHC1_RST \ + IOMUX_PAD(0x041C, 0x012C, 3, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_FEC_MDC__USDHC3_RST \ + IOMUX_PAD(0x041C, 0x012C, 4, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_FEC_MDC__GPIO_4_23 \ + IOMUX_PAD(0x041C, 0x012C, 5, 0x0000, 0, MX6SL_FLOAT_PAD_CTRL) +#define MX6SL_PAD_FEC_MDC__KITTEN_TRACE_29 \ + IOMUX_PAD(0x041C, 0x012C, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_FEC_MDC__PL301_SIM_MX6SL_PER1_HADDR_8 \ + IOMUX_PAD(0x041C, 0x012C, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_FEC_MDIO__FEC_MDIO \ + IOMUX_PAD(0x0420, 0x0130, 0, 0x06F4, 1, MX6SL_ENET_PAD_CTRL) +#define MX6SL_PAD_FEC_MDIO__USDHC4_CLK \ + IOMUX_PAD(0x0420, 0x0130, 1, 0x0850, 1, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_FEC_MDIO__AUDMUX_AUD6_RXFS \ + IOMUX_PAD(0x0420, 0x0130, 2, 0x0620, 0, NO_PAD_CTRL) +#define MX6SL_PAD_FEC_MDIO__ECSPI4_SS0 \ + IOMUX_PAD(0x0420, 0x0130, 3, 0x06DC, 1, NO_PAD_CTRL) +#define MX6SL_PAD_FEC_MDIO__GPT_CAPIN1 \ + IOMUX_PAD(0x0420, 0x0130, 4, 0x0710, 0, NO_PAD_CTRL) +#define MX6SL_PAD_FEC_MDIO__GPIO_4_20 \ + IOMUX_PAD(0x0420, 0x0130, 5, 0x0000, 0, MX6SL_FLOAT_PAD_CTRL) +#define MX6SL_PAD_FEC_MDIO__KITTEN_TRACE_26 \ + IOMUX_PAD(0x0420, 0x0130, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_FEC_MDIO__PL301_SIM_MX6SL_PER1_HADDR_15 \ + IOMUX_PAD(0x0420, 0x0130, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_FEC_REF_CLK__FEC_REF_OUT \ + IOMUX_PAD(0x0424, 0x0134, 0x10, 0x0000, 0, MX6SL_ENET_PAD_CTRL) +#define MX6SL_PAD_FEC_REF_CLK__USDHC4_RST \ + IOMUX_PAD(0x0424, 0x0134, 1, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_FEC_REF_CLK__WDOG1_WDOG_B \ + IOMUX_PAD(0x0424, 0x0134, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_FEC_REF_CLK__PWM4_PWMO \ + IOMUX_PAD(0x0424, 0x0134, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_FEC_REF_CLK__CCM_PMIC_RDY \ + IOMUX_PAD(0x0424, 0x0134, 4, 0x062C, 0, NO_PAD_CTRL) +#define MX6SL_PAD_FEC_REF_CLK__GPIO_4_26 \ + IOMUX_PAD(0x0424, 0x0134, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_FEC_REF_CLK__GPIO_4_26_PULLHIGH \ + IOMUX_PAD(0x0424, 0x0134, 5, 0x0000, 0, PAD_CTL_PUS_47K_UP) +#define MX6SL_PAD_FEC_REF_CLK__SPDIF_SPDIF_EXT_CLK \ + IOMUX_PAD(0x0424, 0x0134, 6, 0x07F4, 2, NO_PAD_CTRL) +#define MX6SL_PAD_FEC_REF_CLK__PL301_SIM_MX6SL_PER1_HADDR_0 \ + IOMUX_PAD(0x0424, 0x0134, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_FEC_RX_ER__GPIO_4_19 \ + IOMUX_PAD(0x0428, 0x0138, 5, 0x0000, 0, MX6SL_FLOAT_PAD_CTRL) +#define MX6SL_PAD_FEC_RX_ER__KITTEN_TRACE_25 \ + IOMUX_PAD(0x0428, 0x0138, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_FEC_RX_ER__PL301_SIM_MX6SL_PER1_HADDR_5 \ + IOMUX_PAD(0x0428, 0x0138, 7, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_FEC_RX_ER__FEC_RX_ER \ + IOMUX_PAD(0x0428, 0x0138, 0, 0x0708, 1, MX6SL_ENET_PAD_CTRL) +#define MX6SL_PAD_FEC_RX_ER__USDHC4_DAT0 \ + IOMUX_PAD(0x0428, 0x0138, 1, 0x085C, 1, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_FEC_RX_ER__AUDMUX_AUD6_RXD \ + IOMUX_PAD(0x0428, 0x0138, 2, 0x0614, 0, NO_PAD_CTRL) +#define MX6SL_PAD_FEC_RX_ER__ECSPI4_MOSI \ + IOMUX_PAD(0x0428, 0x0138, 3, 0x06D8, 1, NO_PAD_CTRL) +#define MX6SL_PAD_FEC_RX_ER__GPT_CMPOUT1 \ + IOMUX_PAD(0x0428, 0x0138, 4, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_FEC_RXD0__FEC_RDATA_0 \ + IOMUX_PAD(0x042C, 0x013C, 0, 0x06F8, 0, MX6SL_ENET_PAD_CTRL) +#define MX6SL_PAD_FEC_RXD0__USDHC4_DAT5 \ + IOMUX_PAD(0x042C, 0x013C, 1, 0x0870, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_FEC_RXD0__ANATOP_USBOTG1_ID \ + IOMUX_PAD(0x042C, 0x013C, 2, 0x05DC, 1, NO_PAD_CTRL) +#define MX6SL_PAD_FEC_RXD0__USDHC1_VSELECT \ + IOMUX_PAD(0x042C, 0x013C, 3, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_FEC_RXD0__USDHC3_VSELECT \ + IOMUX_PAD(0x042C, 0x013C, 4, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_FEC_RXD0__GPIO_4_17 \ + IOMUX_PAD(0x042C, 0x013C, 5, 0x0000, 0, MX6SL_FLOAT_PAD_CTRL) +#define MX6SL_PAD_FEC_RXD0__KITTEN_TRACE_24 \ + IOMUX_PAD(0x042C, 0x013C, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_FEC_RXD0__PL301_SIM_MX6SL_PER1_HADDR_7 \ + IOMUX_PAD(0x042C, 0x013C, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_FEC_RXD1__FEC_RDATA_1 \ + IOMUX_PAD(0x0430, 0x0140, 0, 0x06FC, 1, MX6SL_ENET_PAD_CTRL) +#define MX6SL_PAD_FEC_RXD1__USDHC4_DAT2 \ + IOMUX_PAD(0x0430, 0x0140, 1, 0x0864, 1, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_FEC_RXD1__AUDMUX_AUD6_TXFS \ + IOMUX_PAD(0x0430, 0x0140, 2, 0x0628, 0, NO_PAD_CTRL) +#define MX6SL_PAD_FEC_RXD1__ECSPI4_SS1 \ + IOMUX_PAD(0x0430, 0x0140, 3, 0x06E0, 1, NO_PAD_CTRL) +#define MX6SL_PAD_FEC_RXD1__GPT_CMPOUT3 \ + IOMUX_PAD(0x0430, 0x0140, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_FEC_RXD1__GPIO_4_18 \ + IOMUX_PAD(0x0430, 0x0140, 5, 0x0000, 0, MX6SL_FLOAT_PAD_CTRL) +#define MX6SL_PAD_FEC_RXD1__FEC_COL \ + IOMUX_PAD(0x0430, 0x0140, 6, 0x06F0, 0, NO_PAD_CTRL) +#define MX6SL_PAD_FEC_RXD1__PL301_SIM_MX6SL_PER1_HADDR_9 \ + IOMUX_PAD(0x0430, 0x0140, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_FEC_TX_CLK__FEC_TX_CLK \ + IOMUX_PAD(0x0434, 0x0144, 0, 0x070C, 1, NO_PAD_CTRL) +#define MX6SL_PAD_FEC_TX_CLK__USDHC4_CMD \ + IOMUX_PAD(0x0434, 0x0144, 1, 0x0858, 1, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_FEC_TX_CLK__AUDMUX_AUD6_RXC \ + IOMUX_PAD(0x0434, 0x0144, 2, 0x061C, 0, NO_PAD_CTRL) +#define MX6SL_PAD_FEC_TX_CLK__ECSPI4_SCLK \ + IOMUX_PAD(0x0434, 0x0144, 3, 0x06D0, 1, NO_PAD_CTRL) +#define MX6SL_PAD_FEC_TX_CLK__GPT_CAPIN2 \ + IOMUX_PAD(0x0434, 0x0144, 4, 0x0714, 0, NO_PAD_CTRL) +#define MX6SL_PAD_FEC_TX_CLK__GPIO_4_21 \ + IOMUX_PAD(0x0434, 0x0144, 5, 0x0000, 0, MX6SL_FLOAT_PAD_CTRL) +#define MX6SL_PAD_FEC_TX_CLK__KITTEN_TRACE_27 \ + IOMUX_PAD(0x0434, 0x0144, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_FEC_TX_CLK__PL301_SIM_MX6SL_PER1_HADDR_4 \ + IOMUX_PAD(0x0434, 0x0144, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_FEC_TX_EN__FEC_TX_EN \ + IOMUX_PAD(0x0438, 0x0148, 0, 0x0000, 0, MX6SL_ENET_PAD_CTRL) +#define MX6SL_PAD_FEC_TX_EN__USDHC4_DAT6 \ + IOMUX_PAD(0x0438, 0x0148, 1, 0x0874, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_FEC_TX_EN__SPDIF_IN1 \ + IOMUX_PAD(0x0438, 0x0148, 2, 0x07F0, 0, NO_PAD_CTRL) +#define MX6SL_PAD_FEC_TX_EN__USDHC1_WP \ + IOMUX_PAD(0x0438, 0x0148, 3, 0x082C, 1, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_FEC_TX_EN__USDHC3_WP \ + IOMUX_PAD(0x0438, 0x0148, 4, 0x084C, 1, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_FEC_TX_EN__GPIO_4_22 \ + IOMUX_PAD(0x0438, 0x0148, 5, 0x0000, 0, MX6SL_FLOAT_PAD_CTRL) +#define MX6SL_PAD_FEC_TX_EN__KITTEN_TRACE_28 \ + IOMUX_PAD(0x0438, 0x0148, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_FEC_TX_EN__PL301_SIM_MX6SL_PER1_HADDR_1 \ + IOMUX_PAD(0x0438, 0x0148, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_FEC_TXD0__FEC_TDATA_0 \ + IOMUX_PAD(0x043C, 0x014C, 0, 0x0000, 0, MX6SL_ENET_PAD_CTRL) +#define MX6SL_PAD_FEC_TXD0__USDHC4_DAT3 \ + IOMUX_PAD(0x043C, 0x014C, 1, 0x0868, 1, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_FEC_TXD0__AUDMUX_AUD6_TXD \ + IOMUX_PAD(0x043C, 0x014C, 2, 0x0618, 0, NO_PAD_CTRL) +#define MX6SL_PAD_FEC_TXD0__ECSPI4_SS2 \ + IOMUX_PAD(0x043C, 0x014C, 3, 0x06E4, 1, NO_PAD_CTRL) +#define MX6SL_PAD_FEC_TXD0__GPT_CLKIN \ + IOMUX_PAD(0x043C, 0x014C, 4, 0x0718, 0, NO_PAD_CTRL) +#define MX6SL_PAD_FEC_TXD0__GPIO_4_24 \ + IOMUX_PAD(0x043C, 0x014C, 5, 0x0000, 0, MX6SL_FLOAT_PAD_CTRL) +#define MX6SL_PAD_FEC_TXD0__KITTEN_TRACE_30 \ + IOMUX_PAD(0x043C, 0x014C, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_FEC_TXD0__PL301_SIM_MX6SL_PER1_HADDR_2 \ + IOMUX_PAD(0x043C, 0x014C, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_FEC_TXD1__FEC_TDATA_1 \ + IOMUX_PAD(0x0440, 0x0150, 0, 0x0000, 0, MX6SL_ENET_PAD_CTRL) +#define MX6SL_PAD_FEC_TXD1__USDHC4_DAT7 \ + IOMUX_PAD(0x0440, 0x0150, 1, 0x0878, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_FEC_TXD1__SPDIF_OUT1 \ + IOMUX_PAD(0x0440, 0x0150, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_FEC_TXD1__USDHC1_CD \ + IOMUX_PAD(0x0440, 0x0150, 3, 0x0828, 1, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_FEC_TXD1__USDHC3_CD \ + IOMUX_PAD(0x0440, 0x0150, 4, 0x0838, 1, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_FEC_TXD1__GPIO_4_16 \ + IOMUX_PAD(0x0440, 0x0150, 5, 0x0000, 0, MX6SL_FLOAT_PAD_CTRL) +#define MX6SL_PAD_FEC_TXD1__FEC_RX_CLK \ + IOMUX_PAD(0x0440, 0x0150, 6, 0x0700, 0, NO_PAD_CTRL) +#define MX6SL_PAD_FEC_TXD1__PL301_SIM_MX6SL_PER1_HADDR_6 \ + IOMUX_PAD(0x0440, 0x0150, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_HSIC_DAT__USB_H_DATA \ + IOMUX_PAD(0x0444, 0x0154, 0, 0x0000, 0, MX6SL_USB_HSIC_PAD_CTRL) +#define MX6SL_PAD_HSIC_DAT__I2C1_SCL \ + IOMUX_PAD(0x0444, 0x0154, 1 | IOMUX_CONFIG_SION, 0x071C, 1, MX6SL_I2C_PAD_CTRL) +#define MX6SL_PAD_HSIC_DAT__PWM1_PWMO \ + IOMUX_PAD(0x0444, 0x0154, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_HSIC_DAT__ANATOP_ANATOP_24M_OUT \ + IOMUX_PAD(0x0444, 0x0154, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_HSIC_DAT__OSC32K_32K_OUT \ + IOMUX_PAD(0x0444, 0x0154, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_HSIC_DAT__GPIO_3_19 \ + IOMUX_PAD(0x0444, 0x0154, 5, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_HSIC_STROBE__USB_H_STROBE \ + IOMUX_PAD(0x0448, 0x0158, 0, 0x0000, 0, MX6SL_USB_HSIC_PAD_CTRL) +#define MX6SL_PAD_HSIC_STROBE__USB_H_STROBE_START \ + IOMUX_PAD(0x0448, 0x0158, 0, 0x0000, 0, MX6SL_USB_HSIC_PAD_CTRL | PAD_CTL_PUS_47K_UP) +#define MX6SL_PAD_HSIC_STROBE__I2C1_SDA \ + IOMUX_PAD(0x0448, 0x0158, 1 | IOMUX_CONFIG_SION, 0x0720, 1, MX6SL_I2C_PAD_CTRL) +#define MX6SL_PAD_HSIC_STROBE__PWM2_PWMO \ + IOMUX_PAD(0x0448, 0x0158, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_HSIC_STROBE__ANATOP_ANATOP_32K_OUT \ + IOMUX_PAD(0x0448, 0x0158, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_HSIC_STROBE__GPIO_3_20 \ + IOMUX_PAD(0x0448, 0x0158, 5, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_I2C1_SCL__I2C1_SCL \ + IOMUX_PAD(0x044C, 0x015C, 0 | IOMUX_CONFIG_SION, 0x071C, 2, MX6SL_I2C_PAD_CTRL) +#define MX6SL_PAD_I2C1_SCL__UART1_CTS \ + IOMUX_PAD(0x044C, 0x015C, 1, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_I2C1_SCL__UART1_RTS \ + IOMUX_PAD(0x044C, 0x015C, 1, 0x07F8, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_I2C1_SCL__ECSPI3_SS2 \ + IOMUX_PAD(0x044C, 0x015C, 2, 0x06C8, 1, NO_PAD_CTRL) +#define MX6SL_PAD_I2C1_SCL__FEC_RDATA_0 \ + IOMUX_PAD(0x044C, 0x015C, 3, 0x06F8, 1, NO_PAD_CTRL) +#define MX6SL_PAD_I2C1_SCL__USDHC3_RST \ + IOMUX_PAD(0x044C, 0x015C, 4, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_I2C1_SCL__GPIO_3_12 \ + IOMUX_PAD(0x044C, 0x015C, 5, 0x0000, 0, MX6SL_FLOAT_PAD_CTRL) +#define MX6SL_PAD_I2C1_SCL__ECSPI1_SS1 \ + IOMUX_PAD(0x044C, 0x015C, 6, 0x0690, 0, NO_PAD_CTRL) +#define MX6SL_PAD_I2C1_SCL__PL301_SIM_MX6SL_PER1_HSIZE_0 \ + IOMUX_PAD(0x044C, 0x015C, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_I2C1_SDA__I2C1_SDA \ + IOMUX_PAD(0x0450, 0x0160, 0 | IOMUX_CONFIG_SION, 0x0720, 2, MX6SL_I2C_PAD_CTRL) +#define MX6SL_PAD_I2C1_SDA__UART1_CTS \ + IOMUX_PAD(0x0450, 0x0160, 1, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_I2C1_SDA__UART1_RTS \ + IOMUX_PAD(0x0450, 0x0160, 1, 0x07F8, 1, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_I2C1_SDA__ECSPI3_SS3 \ + IOMUX_PAD(0x0450, 0x0160, 2, 0x06CC, 1, NO_PAD_CTRL) +#define MX6SL_PAD_I2C1_SDA__FEC_TX_EN \ + IOMUX_PAD(0x0450, 0x0160, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_I2C1_SDA__USDHC3_VSELECT \ + IOMUX_PAD(0x0450, 0x0160, 4, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_I2C1_SDA__GPIO_3_13 \ + IOMUX_PAD(0x0450, 0x0160, 5, 0x0000, 0, MX6SL_FLOAT_PAD_CTRL) +#define MX6SL_PAD_I2C1_SDA__ECSPI1_SS2 \ + IOMUX_PAD(0x0450, 0x0160, 6, 0x0694, 0, NO_PAD_CTRL) +#define MX6SL_PAD_I2C1_SDA__PL301_SIM_MX6SL_PER1_HSIZE_1 \ + IOMUX_PAD(0x0450, 0x0160, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_I2C2_SCL__I2C2_SCL \ + IOMUX_PAD(0x0454, 0x0164, 0 | IOMUX_CONFIG_SION, 0x0724, 1, MX6SL_I2C_PAD_CTRL) +#define MX6SL_PAD_I2C2_SCL__AUDMUX_AUD4_RXFS \ + IOMUX_PAD(0x0454, 0x0164, 1, 0x05F0, 0, NO_PAD_CTRL) +#define MX6SL_PAD_I2C2_SCL__SPDIF_IN1 \ + IOMUX_PAD(0x0454, 0x0164, 2, 0x07F0, 1, NO_PAD_CTRL) +#define MX6SL_PAD_I2C2_SCL__FEC_TDATA_1 \ + IOMUX_PAD(0x0454, 0x0164, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_I2C2_SCL__USDHC3_WP \ + IOMUX_PAD(0x0454, 0x0164, 4, 0x084C, 2, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_I2C2_SCL__GPIO_3_14 \ + IOMUX_PAD(0x0454, 0x0164, 5, 0x0000, 0, MX6SL_FLOAT_PAD_CTRL) +#define MX6SL_PAD_I2C2_SCL__ECSPI1_RDY \ + IOMUX_PAD(0x0454, 0x0164, 6, 0x0680, 0, NO_PAD_CTRL) +#define MX6SL_PAD_I2C2_SCL__PL301_SIM_MX6SL_PER1_HSIZE_2 \ + IOMUX_PAD(0x0454, 0x0164, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_I2C2_SDA__I2C2_SDA \ + IOMUX_PAD(0x0458, 0x0168, 0 | IOMUX_CONFIG_SION, 0x0728, 1, MX6SL_I2C_PAD_CTRL) +#define MX6SL_PAD_I2C2_SDA__AUDMUX_AUD4_RXC \ + IOMUX_PAD(0x0458, 0x0168, 1, 0x05EC, 0, NO_PAD_CTRL) +#define MX6SL_PAD_I2C2_SDA__SPDIF_OUT1 \ + IOMUX_PAD(0x0458, 0x0168, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_I2C2_SDA__FEC_REF_OUT \ + IOMUX_PAD(0x0458, 0x0168, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_I2C2_SDA__USDHC3_CD \ + IOMUX_PAD(0x0458, 0x0168, 4, 0x0838, 2, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_I2C2_SDA__GPIO_3_15 \ + IOMUX_PAD(0x0458, 0x0168, 5, 0x0000, 0, MX6SL_FLOAT_PAD_CTRL) +#define MX6SL_PAD_I2C2_SDA__ANATOP_ANATOP_TESTO_0 \ + IOMUX_PAD(0x0458, 0x0168, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_I2C2_SDA__PL301_SIM_MX6SL_PER1_HWRITE \ + IOMUX_PAD(0x0458, 0x0168, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_JTAG_MOD__SJC_MOD \ + IOMUX_PAD(0x045C, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_JTAG_TCK__SJC_TCK \ + IOMUX_PAD(0x0460, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_JTAG_TDI__SJC_TDI \ + IOMUX_PAD(0x0464, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_JTAG_TDO__SJC_TDO \ + IOMUX_PAD(0x0468, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_JTAG_TMS__SJC_TMS \ + IOMUX_PAD(0x046C, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_JTAG_TRSTB__SJC_TRSTB \ + IOMUX_PAD(0x0470, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_KEY_COL0__KPP_COL_0 \ + IOMUX_PAD(0x0474, 0x016C, 0, 0x0734, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_COL0__I2C2_SCL \ + IOMUX_PAD(0x0474, 0x016C, 1 | IOMUX_CONFIG_SION, 0x0724, 2, MX6SL_I2C_PAD_CTRL) +#define MX6SL_PAD_KEY_COL0__LCDIF_DAT_0 \ + IOMUX_PAD(0x0474, 0x016C, 2, 0x0778, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_COL0__WEIM_WEIM_DA_A_0 \ + IOMUX_PAD(0x0474, 0x016C, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_COL0__USDHC1_CD \ + IOMUX_PAD(0x0474, 0x016C, 4, 0x0828, 2, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_KEY_COL0__GPIO_3_24 \ + IOMUX_PAD(0x0474, 0x016C, 5, 0x0000, 0, MX6SL_KEYPAD_CTRL) +#define MX6SL_PAD_KEY_COL0__MSHC_SCLK \ + IOMUX_PAD(0x0474, 0x016C, 6, 0x07E8, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_COL0__TPSMP_HDATA_0 \ + IOMUX_PAD(0x0474, 0x016C, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_KEY_COL1__KPP_COL_1 \ + IOMUX_PAD(0x0478, 0x0170, 0, 0x0738, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_COL1__ECSPI4_MOSI \ + IOMUX_PAD(0x0478, 0x0170, 1, 0x06D8, 2, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_COL1__LCDIF_DAT_2 \ + IOMUX_PAD(0x0478, 0x0170, 2, 0x0780, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_COL1__WEIM_WEIM_DA_A_2 \ + IOMUX_PAD(0x0478, 0x0170, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_COL1__USDHC3_DAT4 \ + IOMUX_PAD(0x0478, 0x0170, 4, 0x083C, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_KEY_COL1__GPIO_3_26 \ + IOMUX_PAD(0x0478, 0x0170, 5, 0x0000, 0, NO_PAD_I) +#define MX6SL_PAD_KEY_COL1__MSHC_DATA_0 \ + IOMUX_PAD(0x0478, 0x0170, 6, 0x07D8, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_COL1__TPSMP_HDATA_2 \ + IOMUX_PAD(0x0478, 0x0170, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_KEY_COL2__KPP_COL_2 \ + IOMUX_PAD(0x047C, 0x0174, 0, 0x073C, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_COL2__ECSPI4_SS0 \ + IOMUX_PAD(0x047C, 0x0174, 1, 0x06DC, 2, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_COL2__LCDIF_DAT_4 \ + IOMUX_PAD(0x047C, 0x0174, 2, 0x0788, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_COL2__WEIM_WEIM_DA_A_4 \ + IOMUX_PAD(0x047C, 0x0174, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_COL2__USDHC3_DAT6 \ + IOMUX_PAD(0x047C, 0x0174, 4, 0x0844, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_KEY_COL2__GPIO_3_28 \ + IOMUX_PAD(0x047C, 0x0174, 5, 0x0000, 0, MX6SL_KEYPAD_CTRL) +#define MX6SL_PAD_KEY_COL2__MSHC_DATA_2 \ + IOMUX_PAD(0x047C, 0x0174, 6, 0x07E0, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_COL2__TPSMP_HDATA_4 \ + IOMUX_PAD(0x047C, 0x0174, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_KEY_COL3__KPP_COL_3 \ + IOMUX_PAD(0x0480, 0x0178, 0, 0x0740, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_COL3__AUDMUX_AUD6_RXFS \ + IOMUX_PAD(0x0480, 0x0178, 1, 0x0620, 1, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_COL3__LCDIF_DAT_6 \ + IOMUX_PAD(0x0480, 0x0178, 2, 0x0790, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_COL3__WEIM_WEIM_DA_A_6 \ + IOMUX_PAD(0x0480, 0x0178, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_COL3__USDHC4_DAT6 \ + IOMUX_PAD(0x0480, 0x0178, 4, 0x0874, 1, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_KEY_COL3__GPIO_3_30 \ + IOMUX_PAD(0x0480, 0x0178, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_COL3__USDHC1_RST \ + IOMUX_PAD(0x0480, 0x0178, 6, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_KEY_COL3__TPSMP_HDATA_6 \ + IOMUX_PAD(0x0480, 0x0178, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_KEY_COL4__KPP_COL_4 \ + IOMUX_PAD(0x0484, 0x017C, 0, 0x0744, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_COL4__AUDMUX_AUD6_RXD \ + IOMUX_PAD(0x0484, 0x017C, 1, 0x0614, 1, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_COL4__LCDIF_DAT_8 \ + IOMUX_PAD(0x0484, 0x017C, 2, 0x0798, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_COL4__WEIM_WEIM_DA_A_8 \ + IOMUX_PAD(0x0484, 0x017C, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_COL4__USDHC4_CLK \ + IOMUX_PAD(0x0484, 0x017C, 4, 0x0850, 2, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_KEY_COL4__GPIO_4_0 \ + IOMUX_PAD(0x0484, 0x017C, 5, 0x0000, 0, MX6SL_TOUCH_CTRL) +#define MX6SL_PAD_KEY_COL4__USB_USBOTG1_PWR \ + IOMUX_PAD(0x0484, 0x017C, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_COL4__TPSMP_HDATA_8 \ + IOMUX_PAD(0x0484, 0x017C, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_KEY_COL5__KPP_COL_5 \ + IOMUX_PAD(0x0488, 0x0180, 0, 0x0748, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_COL5__AUDMUX_AUD6_TXFS \ + IOMUX_PAD(0x0488, 0x0180, 1, 0x0628, 1, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_COL5__LCDIF_DAT_10 \ + IOMUX_PAD(0x0488, 0x0180, 2, 0x07A0, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_COL5__WEIM_WEIM_DA_A_10 \ + IOMUX_PAD(0x0488, 0x0180, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_COL5__USDHC4_DAT0 \ + IOMUX_PAD(0x0488, 0x0180, 4, 0x085C, 2, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_KEY_COL5__GPIO_4_2 \ + IOMUX_PAD(0x0488, 0x0180, 5, 0x0000, 0, MX6SL_TOUCH_CTRL) +#define MX6SL_PAD_KEY_COL5__USB_USBOTG2_PWR \ + IOMUX_PAD(0x0488, 0x0180, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_COL5__TPSMP_HDATA_10 \ + IOMUX_PAD(0x0488, 0x0180, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_KEY_COL6__KPP_COL_6 \ + IOMUX_PAD(0x048C, 0x0184, 0, 0x074C, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_COL6__UART4_TXD \ + IOMUX_PAD(0x048C, 0x0184, 1, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_KEY_COL6__UART4_RXD \ + IOMUX_PAD(0x048C, 0x0184, 1, 0x0814, 2, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_KEY_COL6__LCDIF_DAT_12 \ + IOMUX_PAD(0x048C, 0x0184, 2, 0x07A8, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_COL6__WEIM_WEIM_DA_A_12 \ + IOMUX_PAD(0x048C, 0x0184, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_COL6__USDHC4_DAT2 \ + IOMUX_PAD(0x048C, 0x0184, 4, 0x0864, 2, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_KEY_COL6__GPIO_4_4 \ + IOMUX_PAD(0x048C, 0x0184, 5, 0x0000, 0, NO_PAD_I) +#define MX6SL_PAD_KEY_COL6__USDHC3_RST \ + IOMUX_PAD(0x048C, 0x0184, 6, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_KEY_COL6__TPSMP_HDATA_12 \ + IOMUX_PAD(0x048C, 0x0184, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_KEY_COL7__KPP_COL_7 \ + IOMUX_PAD(0x0490, 0x0188, 0, 0x0750, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_COL7__UART4_CTS \ + IOMUX_PAD(0x0490, 0x0188, 1, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_KEY_COL7__UART4_RTS \ + IOMUX_PAD(0x0490, 0x0188, 1, 0x0810, 2, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_KEY_COL7__LCDIF_DAT_14 \ + IOMUX_PAD(0x0490, 0x0188, 2, 0x07B0, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_COL7__WEIM_WEIM_DA_A_14 \ + IOMUX_PAD(0x0490, 0x0188, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_COL7__USDHC4_DAT4 \ + IOMUX_PAD(0x0490, 0x0188, 4, 0x086C, 1, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_KEY_COL7__GPIO_4_6 \ + IOMUX_PAD(0x0490, 0x0188, 5, 0x0000, 0, NO_PAD_I) +#define MX6SL_PAD_KEY_COL7__USDHC1_WP \ + IOMUX_PAD(0x0490, 0x0188, 6, 0x082C, 2, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_KEY_COL7__TPSMP_HDATA_14 \ + IOMUX_PAD(0x0490, 0x0188, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_KEY_ROW0__KPP_ROW_0 \ + IOMUX_PAD(0x0494, 0x018C, 0, 0x0754, 0, MX6SL_KEYPAD_CTRL) +#define MX6SL_PAD_KEY_ROW0__I2C2_SDA \ + IOMUX_PAD(0x0494, 0x018C, 1 | IOMUX_CONFIG_SION, 0x0728, 2, MX6SL_I2C_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW0__LCDIF_DAT_1 \ + IOMUX_PAD(0x0494, 0x018C, 2, 0x077C, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW0__WEIM_WEIM_DA_A_1 \ + IOMUX_PAD(0x0494, 0x018C, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW0__USDHC1_WP \ + IOMUX_PAD(0x0494, 0x018C, 4, 0x082C, 3, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW0__GPIO_3_25 \ + IOMUX_PAD(0x0494, 0x018C, 5, 0x0000, 0, (PAD_CTL_HYS|PAD_CTL_PKE)) +#define MX6SL_PAD_KEY_ROW0__MSHC_BS \ + IOMUX_PAD(0x0494, 0x018C, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW0__TPSMP_HDATA_1 \ + IOMUX_PAD(0x0494, 0x018C, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_KEY_ROW1__KPP_ROW_1 \ + IOMUX_PAD(0x0498, 0x0190, 0, 0x0758, 0, MX6SL_KEYPAD_CTRL) +#define MX6SL_PAD_KEY_ROW1__ECSPI4_MISO \ + IOMUX_PAD(0x0498, 0x0190, 1, 0x06D4, 2, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW1__LCDIF_DAT_3 \ + IOMUX_PAD(0x0498, 0x0190, 2, 0x0784, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW1__WEIM_WEIM_DA_A_3 \ + IOMUX_PAD(0x0498, 0x0190, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW1__USDHC3_DAT5 \ + IOMUX_PAD(0x0498, 0x0190, 4, 0x0840, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW1__GPIO_3_27 \ + IOMUX_PAD(0x0498, 0x0190, 5, 0x0000, 0, (PAD_CTL_HYS|PAD_CTL_PKE)) +#define MX6SL_PAD_KEY_ROW1__MSHC_DATA_1 \ + IOMUX_PAD(0x0498, 0x0190, 6, 0x07DC, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW1__TPSMP_HDATA_3 \ + IOMUX_PAD(0x0498, 0x0190, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_KEY_ROW2__KPP_ROW_2 \ + IOMUX_PAD(0x049C, 0x0194, 0, 0x075C, 0, MX6SL_KEYPAD_CTRL) +#define MX6SL_PAD_KEY_ROW2__ECSPI4_SCLK \ + IOMUX_PAD(0x049C, 0x0194, 1, 0x06D0, 2, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW2__LCDIF_DAT_5 \ + IOMUX_PAD(0x049C, 0x0194, 2, 0x078C, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW2__WEIM_WEIM_DA_A_5 \ + IOMUX_PAD(0x049C, 0x0194, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW2__USDHC3_DAT7 \ + IOMUX_PAD(0x049C, 0x0194, 4, 0x0848, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW2__GPIO_3_29 \ + IOMUX_PAD(0x049C, 0x0194, 5, 0x0000, 0, (PAD_CTL_HYS|PAD_CTL_PKE)) +#define MX6SL_PAD_KEY_ROW2__MSHC_DATA_3 \ + IOMUX_PAD(0x049C, 0x0194, 6, 0x07E4, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW2__TPSMP_HDATA_5 \ + IOMUX_PAD(0x049C, 0x0194, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_KEY_ROW3__KPP_ROW_3 \ + IOMUX_PAD(0x04A0, 0x0198, 0, 0x0760, 0, MX6SL_KEYPAD_CTRL) +#define MX6SL_PAD_KEY_ROW3__AUDMUX_AUD6_RXC \ + IOMUX_PAD(0x04A0, 0x0198, 1, 0x061C, 1, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW3__LCDIF_DAT_7 \ + IOMUX_PAD(0x04A0, 0x0198, 2, 0x0794, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW3__WEIM_WEIM_DA_A_7 \ + IOMUX_PAD(0x04A0, 0x0198, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW3__USDHC4_DAT7 \ + IOMUX_PAD(0x04A0, 0x0198, 4, 0x0878, 1, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW3__GPIO_3_31 \ + IOMUX_PAD(0x04A0, 0x0198, 5, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW3__USDHC1_VSELECT \ + IOMUX_PAD(0x04A0, 0x0198, 6, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW3__TPSMP_HDATA_7 \ + IOMUX_PAD(0x04A0, 0x0198, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_KEY_ROW4__KPP_ROW_4 \ + IOMUX_PAD(0x04A4, 0x019C, 0, 0x0764, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW4__AUDMUX_AUD6_TXC \ + IOMUX_PAD(0x04A4, 0x019C, 1, 0x0624, 1, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW4__LCDIF_DAT_9 \ + IOMUX_PAD(0x04A4, 0x019C, 2, 0x079C, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW4__WEIM_WEIM_DA_A_9 \ + IOMUX_PAD(0x04A4, 0x019C, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW4__USDHC4_CMD \ + IOMUX_PAD(0x04A4, 0x019C, 4, 0x0858, 2, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW4__GPIO_4_1 \ + IOMUX_PAD(0x04A4, 0x019C, 5, 0x0000, 0, MX6SL_INTR_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW4__USB_USBOTG1_OC \ + IOMUX_PAD(0x04A4, 0x019C, 6, 0x0824, 1, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW4__TPSMP_HDATA_9 \ + IOMUX_PAD(0x04A4, 0x019C, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_KEY_ROW5__KPP_ROW_5 \ + IOMUX_PAD(0x04A8, 0x01A0, 0, 0x0768, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW5__AUDMUX_AUD6_TXD \ + IOMUX_PAD(0x04A8, 0x01A0, 1, 0x0618, 1, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW5__LCDIF_DAT_11 \ + IOMUX_PAD(0x04A8, 0x01A0, 2, 0x07A4, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW5__WEIM_WEIM_DA_A_11 \ + IOMUX_PAD(0x04A8, 0x01A0, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW5__USDHC4_DAT1 \ + IOMUX_PAD(0x04A8, 0x01A0, 4, 0x0860, 2, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW5__GPIO_4_3 \ + IOMUX_PAD(0x04A8, 0x01A0, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW5__USB_USBOTG2_OC \ + IOMUX_PAD(0x04A8, 0x01A0, 6, 0x0820, 2, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW5__TPSMP_HDATA_11 \ + IOMUX_PAD(0x04A8, 0x01A0, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_KEY_ROW6__KPP_ROW_6 \ + IOMUX_PAD(0x04AC, 0x01A4, 0, 0x076C, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW6__UART4_TXD \ + IOMUX_PAD(0x04AC, 0x01A4, 1, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW6__UART4_RXD \ + IOMUX_PAD(0x04AC, 0x01A4, 1, 0x0814, 3, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW6__LCDIF_DAT_13 \ + IOMUX_PAD(0x04AC, 0x01A4, 2, 0x07AC, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW6__WEIM_WEIM_DA_A_13 \ + IOMUX_PAD(0x04AC, 0x01A4, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW6__USDHC4_DAT3 \ + IOMUX_PAD(0x04AC, 0x01A4, 4, 0x0868, 2, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW6__GPIO_4_5 \ + IOMUX_PAD(0x04AC, 0x01A4, 5, 0x0000, 0, NO_PAD_I) +#define MX6SL_PAD_KEY_ROW6__USDHC3_VSELECT \ + IOMUX_PAD(0x04AC, 0x01A4, 6, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW6__TPSMP_HDATA_13 \ + IOMUX_PAD(0x04AC, 0x01A4, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_KEY_ROW7__KPP_ROW_7 \ + IOMUX_PAD(0x04B0, 0x01A8, 0, 0x0770, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW7__UART4_CTS \ + IOMUX_PAD(0x04B0, 0x01A8, 1, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW7__UART4_RTS \ + IOMUX_PAD(0x04B0, 0x01A8, 1, 0x0810, 3, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW7__LCDIF_DAT_15 \ + IOMUX_PAD(0x04B0, 0x01A8, 2, 0x07B4, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW7__WEIM_WEIM_DA_A_15 \ + IOMUX_PAD(0x04B0, 0x01A8, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW7__USDHC4_DAT5 \ + IOMUX_PAD(0x04B0, 0x01A8, 4, 0x0870, 1, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW7__GPIO_4_7 \ + IOMUX_PAD(0x04B0, 0x01A8, 5, 0x0000, 0, NO_PAD_I) +#define MX6SL_PAD_KEY_ROW7__USDHC1_CD \ + IOMUX_PAD(0x04B0, 0x01A8, 6, 0x0828, 3, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW7__TPSMP_HDATA_15 \ + IOMUX_PAD(0x04B0, 0x01A8, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_LCD_CLK__LCDIF_CLK \ + IOMUX_PAD(0x04B4, 0x01AC, 0, 0x0000, 0, MX6SL_LCDIF_PAD_CTRL) +#define MX6SL_PAD_LCD_CLK__USDHC4_DAT4 \ + IOMUX_PAD(0x04B4, 0x01AC, 1, 0x086C, 2, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_LCD_CLK__LCDIF_WR_RWN \ + IOMUX_PAD(0x04B4, 0x01AC, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_CLK__WEIM_WEIM_RW \ + IOMUX_PAD(0x04B4, 0x01AC, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_CLK__PWM4_PWMO \ + IOMUX_PAD(0x04B4, 0x01AC, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_CLK__GPIO_2_15 \ + IOMUX_PAD(0x04B4, 0x01AC, 5, 0x0000, 0, MX6SL_FLOAT_PAD_CTRL) +#define MX6SL_PAD_LCD_CLK__SRC_EARLY_RST \ + IOMUX_PAD(0x04B4, 0x01AC, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_CLK__TPSMP_HTRANS_0 \ + IOMUX_PAD(0x04B4, 0x01AC, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_LCD_DAT0__LCDIF_DAT_0 \ + IOMUX_PAD(0x04B8, 0x01B0, 0, 0x0778, 1, MX6SL_LCDIF_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT0__ECSPI1_MOSI \ + IOMUX_PAD(0x04B8, 0x01B0, 1, 0x0688, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT0__ANATOP_USBOTG2_ID \ + IOMUX_PAD(0x04B8, 0x01B0, 2, 0x05E0, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT0__PWM1_PWMO \ + IOMUX_PAD(0x04B8, 0x01B0, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT0__UART5_DTR \ + IOMUX_PAD(0x04B8, 0x01B0, 4, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT0__GPIO_2_20 \ + IOMUX_PAD(0x04B8, 0x01B0, 5, 0x0000, 0, MX6SL_FLOAT_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT0__KITTEN_TRACE_0 \ + IOMUX_PAD(0x04B8, 0x01B0, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT0__SRC_BT_CFG_0 \ + IOMUX_PAD(0x04B8, 0x01B0, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_LCD_DAT1__LCDIF_DAT_1 \ + IOMUX_PAD(0x04BC, 0x01B4, 0, 0x077C, 1, MX6SL_LCDIF_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT1__ECSPI1_MISO \ + IOMUX_PAD(0x04BC, 0x01B4, 1, 0x0684, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT1__ANATOP_USBOTG1_ID \ + IOMUX_PAD(0x04BC, 0x01B4, 2, 0x05DC, 2, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT1__PWM2_PWMO \ + IOMUX_PAD(0x04BC, 0x01B4, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT1__AUDMUX_AUD4_RXFS \ + IOMUX_PAD(0x04BC, 0x01B4, 4, 0x05F0, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT1__GPIO_2_21 \ + IOMUX_PAD(0x04BC, 0x01B4, 5, 0x0000, 0, MX6SL_FLOAT_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT1__KITTEN_TRACE_1 \ + IOMUX_PAD(0x04BC, 0x01B4, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT1__SRC_BT_CFG_1 \ + IOMUX_PAD(0x04BC, 0x01B4, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_LCD_DAT10__LCDIF_DAT_10 \ + IOMUX_PAD(0x04C0, 0x01B8, 0, 0x07A0, 1, MX6SL_LCDIF_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT10__KPP_COL_1 \ + IOMUX_PAD(0x04C0, 0x01B8, 1, 0x0738, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT10__CSI_D_7 \ + IOMUX_PAD(0x04C0, 0x01B8, 2, 0x064C, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT10__WEIM_WEIM_D_4 \ + IOMUX_PAD(0x04C0, 0x01B8, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT10__ECSPI2_MISO \ + IOMUX_PAD(0x04C0, 0x01B8, 4, 0x06A0, 2, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT10__GPIO_2_30 \ + IOMUX_PAD(0x04C0, 0x01B8, 5, 0x0000, 0, MX6SL_FLOAT_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT10__KITTEN_TRACE_10 \ + IOMUX_PAD(0x04C0, 0x01B8, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT10__SRC_BT_CFG_10 \ + IOMUX_PAD(0x04C0, 0x01B8, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_LCD_DAT11__LCDIF_DAT_11 \ + IOMUX_PAD(0x04C4, 0x01BC, 0, 0x07A4, 1, MX6SL_LCDIF_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT11__KPP_ROW_1 \ + IOMUX_PAD(0x04C4, 0x01BC, 1, 0x0758, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT11__CSI_D_6 \ + IOMUX_PAD(0x04C4, 0x01BC, 2, 0x0648, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT11__WEIM_WEIM_D_5 \ + IOMUX_PAD(0x04C4, 0x01BC, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT11__ECSPI2_SS1 \ + IOMUX_PAD(0x04C4, 0x01BC, 4, 0x06AC, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT11__GPIO_2_31 \ + IOMUX_PAD(0x04C4, 0x01BC, 5, 0x0000, 0, MX6SL_FLOAT_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT11__KITTEN_TRACE_11 \ + IOMUX_PAD(0x04C4, 0x01BC, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT11__SRC_BT_CFG_11 \ + IOMUX_PAD(0x04C4, 0x01BC, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_LCD_DAT12__LCDIF_DAT_12 \ + IOMUX_PAD(0x04C8, 0x01C0, 0, 0x07A8, 1, MX6SL_LCDIF_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT12__KPP_COL_2 \ + IOMUX_PAD(0x04C8, 0x01C0, 1, 0x073C, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT12__CSI_D_5 \ + IOMUX_PAD(0x04C8, 0x01C0, 2, 0x0644, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT12__WEIM_WEIM_D_6 \ + IOMUX_PAD(0x04C8, 0x01C0, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT12__UART5_CTS \ + IOMUX_PAD(0x04C8, 0x01C0, 4, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT12__UART5_RTS \ + IOMUX_PAD(0x04C8, 0x01C0, 4, 0x0818, 2, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT12__GPIO_3_0 \ + IOMUX_PAD(0x04C8, 0x01C0, 5, 0x0000, 0, MX6SL_FLOAT_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT12__KITTEN_TRACE_12 \ + IOMUX_PAD(0x04C8, 0x01C0, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT12__SRC_BT_CFG_12 \ + IOMUX_PAD(0x04C8, 0x01C0, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_LCD_DAT13__LCDIF_DAT_13 \ + IOMUX_PAD(0x04CC, 0x01C4, 0, 0x07AC, 1, MX6SL_LCDIF_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT13__KPP_ROW_2 \ + IOMUX_PAD(0x04CC, 0x01C4, 1, 0x075C, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT13__CSI_D_4 \ + IOMUX_PAD(0x04CC, 0x01C4, 2, 0x0640, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT13__WEIM_WEIM_D_7 \ + IOMUX_PAD(0x04CC, 0x01C4, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT13__UART5_CTS \ + IOMUX_PAD(0x04CC, 0x01C4, 4, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT13__UART5_RTS \ + IOMUX_PAD(0x04CC, 0x01C4, 4, 0x0818, 3, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT13__GPIO_3_1 \ + IOMUX_PAD(0x04CC, 0x01C4, 5, 0x0000, 0, MX6SL_FLOAT_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT13__KITTEN_TRACE_13 \ + IOMUX_PAD(0x04CC, 0x01C4, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT13__SRC_BT_CFG_13 \ + IOMUX_PAD(0x04CC, 0x01C4, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_LCD_DAT14__LCDIF_DAT_14 \ + IOMUX_PAD(0x04D0, 0x01C8, 0, 0x07B0, 1, MX6SL_LCDIF_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT14__KPP_COL_3 \ + IOMUX_PAD(0x04D0, 0x01C8, 1, 0x0740, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT14__CSI_D_3 \ + IOMUX_PAD(0x04D0, 0x01C8, 2, 0x063C, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT14__WEIM_WEIM_D_8 \ + IOMUX_PAD(0x04D0, 0x01C8, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT14__UART5_TXD \ + IOMUX_PAD(0x04D0, 0x01C8, 4, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT14__UART5_RXD \ + IOMUX_PAD(0x04D0, 0x01C8, 4, 0x081C, 2, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT14__GPIO_3_2 \ + IOMUX_PAD(0x04D0, 0x01C8, 5, 0x0000, 0, MX6SL_FLOAT_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT14__KITTEN_TRACE_14 \ + IOMUX_PAD(0x04D0, 0x01C8, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT14__SRC_BT_CFG_14 \ + IOMUX_PAD(0x04D0, 0x01C8, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_LCD_DAT15__LCDIF_DAT_15 \ + IOMUX_PAD(0x04D4, 0x01CC, 0, 0x07B4, 1, MX6SL_LCDIF_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT15__KPP_ROW_3 \ + IOMUX_PAD(0x04D4, 0x01CC, 1, 0x0760, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT15__CSI_D_2 \ + IOMUX_PAD(0x04D4, 0x01CC, 2, 0x0638, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT15__WEIM_WEIM_D_9 \ + IOMUX_PAD(0x04D4, 0x01CC, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT15__UART5_TXD \ + IOMUX_PAD(0x04D4, 0x01CC, 4, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT15__UART5_RXD \ + IOMUX_PAD(0x04D4, 0x01CC, 4, 0x081C, 3, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT15__GPIO_3_3 \ + IOMUX_PAD(0x04D4, 0x01CC, 5, 0x0000, 0, MX6SL_FLOAT_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT15__KITTEN_TRACE_15 \ + IOMUX_PAD(0x04D4, 0x01CC, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT15__SRC_BT_CFG_15 \ + IOMUX_PAD(0x04D4, 0x01CC, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_LCD_DAT16__LCDIF_DAT_16 \ + IOMUX_PAD(0x04D8, 0x01D0, 0, 0x07B8, 1, MX6SL_LCDIF_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT16__KPP_COL_4 \ + IOMUX_PAD(0x04D8, 0x01D0, 1, 0x0744, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT16__CSI_D_1 \ + IOMUX_PAD(0x04D8, 0x01D0, 2, 0x0634, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT16__WEIM_WEIM_D_10 \ + IOMUX_PAD(0x04D8, 0x01D0, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT16__I2C2_SCL \ + IOMUX_PAD(0x04D8, 0x01D0, 4 | IOMUX_CONFIG_SION, 0x0724, 3, MX6SL_I2C_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT16__GPIO_3_4 \ + IOMUX_PAD(0x04D8, 0x01D0, 5, 0x0000, 0, MX6SL_FLOAT_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT16__KITTEN_TRACE_16 \ + IOMUX_PAD(0x04D8, 0x01D0, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT16__SRC_BT_CFG_24 \ + IOMUX_PAD(0x04D8, 0x01D0, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_LCD_DAT17__LCDIF_DAT_17 \ + IOMUX_PAD(0x04DC, 0x01D4, 0, 0x07BC, 1, MX6SL_LCDIF_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT17__KPP_ROW_4 \ + IOMUX_PAD(0x04DC, 0x01D4, 1, 0x0764, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT17__CSI_D_0 \ + IOMUX_PAD(0x04DC, 0x01D4, 2, 0x0630, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT17__WEIM_WEIM_D_11 \ + IOMUX_PAD(0x04DC, 0x01D4, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT17__I2C2_SDA \ + IOMUX_PAD(0x04DC, 0x01D4, 4 | IOMUX_CONFIG_SION, 0x0728, 3, MX6SL_I2C_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT17__GPIO_3_5 \ + IOMUX_PAD(0x04DC, 0x01D4, 5, 0x0000, 0, MX6SL_FLOAT_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT17__KITTEN_TRACE_17 \ + IOMUX_PAD(0x04DC, 0x01D4, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT17__SRC_BT_CFG_25 \ + IOMUX_PAD(0x04DC, 0x01D4, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_LCD_DAT18__LCDIF_DAT_18 \ + IOMUX_PAD(0x04E0, 0x01D8, 0, 0x07C0, 1, MX6SL_LCDIF_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT18__KPP_COL_5 \ + IOMUX_PAD(0x04E0, 0x01D8, 1, 0x0748, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT18__CSI_D_15 \ + IOMUX_PAD(0x04E0, 0x01D8, 2, 0x066C, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT18__WEIM_WEIM_D_12 \ + IOMUX_PAD(0x04E0, 0x01D8, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT18__GPT_CAPIN1 \ + IOMUX_PAD(0x04E0, 0x01D8, 4, 0x0710, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT18__GPIO_3_6 \ + IOMUX_PAD(0x04E0, 0x01D8, 5, 0x0000, 0, MX6SL_FLOAT_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT18__KITTEN_TRACE_18 \ + IOMUX_PAD(0x04E0, 0x01D8, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT18__SRC_BT_CFG_26 \ + IOMUX_PAD(0x04E0, 0x01D8, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_LCD_DAT19__LCDIF_DAT_19 \ + IOMUX_PAD(0x04E4, 0x01DC, 0, 0x07C4, 1, MX6SL_LCDIF_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT19__KPP_ROW_5 \ + IOMUX_PAD(0x04E4, 0x01DC, 1, 0x0768, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT19__CSI_D_14 \ + IOMUX_PAD(0x04E4, 0x01DC, 2, 0x0668, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT19__WEIM_WEIM_D_13 \ + IOMUX_PAD(0x04E4, 0x01DC, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT19__GPT_CAPIN2 \ + IOMUX_PAD(0x04E4, 0x01DC, 4, 0x0714, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT19__GPIO_3_7 \ + IOMUX_PAD(0x04E4, 0x01DC, 5, 0x0000, 0, MX6SL_FLOAT_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT19__KITTEN_TRACE_19 \ + IOMUX_PAD(0x04E4, 0x01DC, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT19__SRC_BT_CFG_27 \ + IOMUX_PAD(0x04E4, 0x01DC, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_LCD_DAT2__LCDIF_DAT_2 \ + IOMUX_PAD(0x04E8, 0x01E0, 0, 0x0780, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT2__ECSPI1_SS0 \ + IOMUX_PAD(0x04E8, 0x01E0, 1, 0x068C, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT2__EPIT2_EPITO \ + IOMUX_PAD(0x04E8, 0x01E0, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT2__PWM3_PWMO \ + IOMUX_PAD(0x04E8, 0x01E0, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT2__AUDMUX_AUD4_RXC \ + IOMUX_PAD(0x04E8, 0x01E0, 4, 0x05EC, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT2__GPIO_2_22 \ + IOMUX_PAD(0x04E8, 0x01E0, 5, 0x0000, 0, MX6SL_FLOAT_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT2__KITTEN_TRACE_2 \ + IOMUX_PAD(0x04E8, 0x01E0, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT2__SRC_BT_CFG_2 \ + IOMUX_PAD(0x04E8, 0x01E0, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_LCD_DAT20__LCDIF_DAT_20 \ + IOMUX_PAD(0x04EC, 0x01E4, 0, 0x07C8, 1, MX6SL_LCDIF_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT20__KPP_COL_6 \ + IOMUX_PAD(0x04EC, 0x01E4, 1, 0x074C, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT20__CSI_D_13 \ + IOMUX_PAD(0x04EC, 0x01E4, 2, 0x0664, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT20__WEIM_WEIM_D_14 \ + IOMUX_PAD(0x04EC, 0x01E4, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT20__GPT_CMPOUT1 \ + IOMUX_PAD(0x04EC, 0x01E4, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT20__GPIO_3_8 \ + IOMUX_PAD(0x04EC, 0x01E4, 5, 0x0000, 0, MX6SL_FLOAT_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT20__KITTEN_TRACE_20 \ + IOMUX_PAD(0x04EC, 0x01E4, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT20__SRC_BT_CFG_28 \ + IOMUX_PAD(0x04EC, 0x01E4, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_LCD_DAT21__LCDIF_DAT_21 \ + IOMUX_PAD(0x04F0, 0x01E8, 0, 0x07CC, 1, MX6SL_LCDIF_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT21__KPP_ROW_6 \ + IOMUX_PAD(0x04F0, 0x01E8, 1, 0x076C, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT21__CSI_D_12 \ + IOMUX_PAD(0x04F0, 0x01E8, 2, 0x0660, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT21__WEIM_WEIM_D_15 \ + IOMUX_PAD(0x04F0, 0x01E8, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT21__GPT_CMPOUT2 \ + IOMUX_PAD(0x04F0, 0x01E8, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT21__GPIO_3_9 \ + IOMUX_PAD(0x04F0, 0x01E8, 5, 0x0000, 0, MX6SL_FLOAT_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT21__KITTEN_TRACE_21 \ + IOMUX_PAD(0x04F0, 0x01E8, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT21__SRC_BT_CFG_29 \ + IOMUX_PAD(0x04F0, 0x01E8, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_LCD_DAT22__LCDIF_DAT_22 \ + IOMUX_PAD(0x04F4, 0x01EC, 0, 0x07D0, 1, MX6SL_LCDIF_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT22__KPP_COL_7 \ + IOMUX_PAD(0x04F4, 0x01EC, 1, 0x0750, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT22__CSI_D_11 \ + IOMUX_PAD(0x04F4, 0x01EC, 2, 0x065C, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT22__WEIM_WEIM_EB_3 \ + IOMUX_PAD(0x04F4, 0x01EC, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT22__GPT_CMPOUT3 \ + IOMUX_PAD(0x04F4, 0x01EC, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT22__GPIO_3_10 \ + IOMUX_PAD(0x04F4, 0x01EC, 5, 0x0000, 0, MX6SL_FLOAT_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT22__KITTEN_TRACE_22 \ + IOMUX_PAD(0x04F4, 0x01EC, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT22__SRC_BT_CFG_30 \ + IOMUX_PAD(0x04F4, 0x01EC, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_LCD_DAT23__LCDIF_DAT_23 \ + IOMUX_PAD(0x04F8, 0x01F0, 0, 0x07D4, 1, MX6SL_LCDIF_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT23__KPP_ROW_7 \ + IOMUX_PAD(0x04F8, 0x01F0, 1, 0x0770, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT23__CSI_D_10 \ + IOMUX_PAD(0x04F8, 0x01F0, 2, 0x0658, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT23__WEIM_WEIM_EB_2 \ + IOMUX_PAD(0x04F8, 0x01F0, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT23__GPT_CLKIN \ + IOMUX_PAD(0x04F8, 0x01F0, 4, 0x0718, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT23__GPIO_3_11 \ + IOMUX_PAD(0x04F8, 0x01F0, 5, 0x0000, 0, MX6SL_FLOAT_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT23__KITTEN_TRACE_23 \ + IOMUX_PAD(0x04F8, 0x01F0, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT23__SRC_BT_CFG_31 \ + IOMUX_PAD(0x04F8, 0x01F0, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_LCD_DAT3__LCDIF_DAT_3 \ + IOMUX_PAD(0x04FC, 0x01F4, 0, 0x0784, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT3__ECSPI1_SCLK \ + IOMUX_PAD(0x04FC, 0x01F4, 1, 0x067C, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT3__UART5_DSR \ + IOMUX_PAD(0x04FC, 0x01F4, 2, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT3__PWM4_PWMO \ + IOMUX_PAD(0x04FC, 0x01F4, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT3__AUDMUX_AUD4_RXD \ + IOMUX_PAD(0x04FC, 0x01F4, 4, 0x05E4, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT3__GPIO_2_23 \ + IOMUX_PAD(0x04FC, 0x01F4, 5, 0x0000, 0, MX6SL_FLOAT_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT3__KITTEN_TRACE_3 \ + IOMUX_PAD(0x04FC, 0x01F4, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT3__SRC_BT_CFG_3 \ + IOMUX_PAD(0x04FC, 0x01F4, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_LCD_DAT4__LCDIF_DAT_4 \ + IOMUX_PAD(0x0500, 0x01F8, 0, 0x0788, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT4__ECSPI1_SS1 \ + IOMUX_PAD(0x0500, 0x01F8, 1, 0x0690, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT4__CSI_VSYNC \ + IOMUX_PAD(0x0500, 0x01F8, 2, 0x0678, 2, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT4__WDOG2_WDOG_RST_B_DEB \ + IOMUX_PAD(0x0500, 0x01F8, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT4__AUDMUX_AUD4_TXC \ + IOMUX_PAD(0x0500, 0x01F8, 4, 0x05F4, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT4__GPIO_2_24 \ + IOMUX_PAD(0x0500, 0x01F8, 5, 0x0000, 0, MX6SL_FLOAT_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT4__KITTEN_TRACE_4 \ + IOMUX_PAD(0x0500, 0x01F8, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT4__SRC_BT_CFG_4 \ + IOMUX_PAD(0x0500, 0x01F8, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_LCD_DAT5__LCDIF_DAT_5 \ + IOMUX_PAD(0x0504, 0x01FC, 0, 0x078C, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT5__ECSPI1_SS2 \ + IOMUX_PAD(0x0504, 0x01FC, 1, 0x0694, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT5__CSI_HSYNC \ + IOMUX_PAD(0x0504, 0x01FC, 2, 0x0670, 2, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT5__WEIM_WEIM_CS_3 \ + IOMUX_PAD(0x0504, 0x01FC, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT5__AUDMUX_AUD4_TXFS \ + IOMUX_PAD(0x0504, 0x01FC, 4, 0x05F8, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT5__GPIO_2_25 \ + IOMUX_PAD(0x0504, 0x01FC, 5, 0x0000, 0, MX6SL_FLOAT_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT5__KITTEN_TRACE_5 \ + IOMUX_PAD(0x0504, 0x01FC, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT5__SRC_BT_CFG_5 \ + IOMUX_PAD(0x0504, 0x01FC, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_LCD_DAT6__LCDIF_DAT_6 \ + IOMUX_PAD(0x0508, 0x0200, 0, 0x0790, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT6__ECSPI1_SS3 \ + IOMUX_PAD(0x0508, 0x0200, 1, 0x0698, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT6__CSI_PIXCLK \ + IOMUX_PAD(0x0508, 0x0200, 2, 0x0674, 2, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT6__WEIM_WEIM_D_0 \ + IOMUX_PAD(0x0508, 0x0200, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT6__AUDMUX_AUD4_TXD \ + IOMUX_PAD(0x0508, 0x0200, 4, 0x05E8, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT6__GPIO_2_26 \ + IOMUX_PAD(0x0508, 0x0200, 5, 0x0000, 0, MX6SL_FLOAT_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT6__KITTEN_TRACE_6 \ + IOMUX_PAD(0x0508, 0x0200, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT6__SRC_BT_CFG_6 \ + IOMUX_PAD(0x0508, 0x0200, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_LCD_DAT7__LCDIF_DAT_7 \ + IOMUX_PAD(0x050C, 0x0204, 0, 0x0794, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT7__ECSPI1_RDY \ + IOMUX_PAD(0x050C, 0x0204, 1, 0x0680, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT7__CSI_MCLK \ + IOMUX_PAD(0x050C, 0x0204, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT7__WEIM_WEIM_D_1 \ + IOMUX_PAD(0x050C, 0x0204, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT7__AUDMUX_AUDIO_CLK_OUT \ + IOMUX_PAD(0x050C, 0x0204, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT7__GPIO_2_27 \ + IOMUX_PAD(0x050C, 0x0204, 5, 0x0000, 0, MX6SL_FLOAT_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT7__KITTEN_TRACE_7 \ + IOMUX_PAD(0x050C, 0x0204, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT7__SRC_BT_CFG_7 \ + IOMUX_PAD(0x050C, 0x0204, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_LCD_DAT8__LCDIF_DAT_8 \ + IOMUX_PAD(0x0510, 0x0208, 0, 0x0798, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT8__KPP_COL_0 \ + IOMUX_PAD(0x0510, 0x0208, 1, 0x0734, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT8__CSI_D_9 \ + IOMUX_PAD(0x0510, 0x0208, 2, 0x0654, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT8__WEIM_WEIM_D_2 \ + IOMUX_PAD(0x0510, 0x0208, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT8__ECSPI2_SCLK \ + IOMUX_PAD(0x0510, 0x0208, 4, 0x069C, 2, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT8__GPIO_2_28 \ + IOMUX_PAD(0x0510, 0x0208, 5, 0x0000, 0, MX6SL_FLOAT_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT8__KITTEN_TRACE_8 \ + IOMUX_PAD(0x0510, 0x0208, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT8__SRC_BT_CFG_8 \ + IOMUX_PAD(0x0510, 0x0208, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_LCD_DAT9__LCDIF_DAT_9 \ + IOMUX_PAD(0x0514, 0x020C, 0, 0x079C, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT9__KPP_ROW_0 \ + IOMUX_PAD(0x0514, 0x020C, 1, 0x0754, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT9__CSI_D_8 \ + IOMUX_PAD(0x0514, 0x020C, 2, 0x0650, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT9__WEIM_WEIM_D_3 \ + IOMUX_PAD(0x0514, 0x020C, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT9__ECSPI2_MOSI \ + IOMUX_PAD(0x0514, 0x020C, 4, 0x06A4, 2, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT9__GPIO_2_29 \ + IOMUX_PAD(0x0514, 0x020C, 5, 0x0000, 0, MX6SL_FLOAT_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT9__KITTEN_TRACE_9 \ + IOMUX_PAD(0x0514, 0x020C, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT9__SRC_BT_CFG_9 \ + IOMUX_PAD(0x0514, 0x020C, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_LCD_ENABLE__LCDIF_ENABLE \ + IOMUX_PAD(0x0518, 0x0210, 0, 0x0000, 0, MX6SL_LCDIF_PAD_CTRL) +#define MX6SL_PAD_LCD_ENABLE__USDHC4_DAT5 \ + IOMUX_PAD(0x0518, 0x0210, 1, 0x0870, 2, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_LCD_ENABLE__LCDIF_RD_E \ + IOMUX_PAD(0x0518, 0x0210, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_ENABLE__WEIM_WEIM_OE \ + IOMUX_PAD(0x0518, 0x0210, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_ENABLE__UART2_TXD \ + IOMUX_PAD(0x0518, 0x0210, 4, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_LCD_ENABLE__UART2_RXD \ + IOMUX_PAD(0x0518, 0x0210, 4, 0x0804, 2, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_LCD_ENABLE__GPIO_2_16 \ + IOMUX_PAD(0x0518, 0x0210, 5, 0x0000, 0, MX6SL_FLOAT_PAD_CTRL) +#define MX6SL_PAD_LCD_ENABLE__OCOTP_CTRL_WRAPPER_FUSE_LATCHED \ + IOMUX_PAD(0x0518, 0x0210, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_ENABLE__TPSMP_HTRANS_1 \ + IOMUX_PAD(0x0518, 0x0210, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_LCD_HSYNC__LCDIF_HSYNC \ + IOMUX_PAD(0x051C, 0x0214, 0, 0x0774, 0, MX6SL_LCDIF_PAD_CTRL) +#define MX6SL_PAD_LCD_HSYNC__USDHC4_DAT6 \ + IOMUX_PAD(0x051C, 0x0214, 1, 0x0874, 2, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_LCD_HSYNC__LCDIF_CS \ + IOMUX_PAD(0x051C, 0x0214, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_HSYNC__WEIM_WEIM_CS_0 \ + IOMUX_PAD(0x051C, 0x0214, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_HSYNC__UART2_TXD \ + IOMUX_PAD(0x051C, 0x0214, 4, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_LCD_HSYNC__UART2_RXD \ + IOMUX_PAD(0x051C, 0x0214, 4, 0x0804, 3, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_LCD_HSYNC__GPIO_2_17 \ + IOMUX_PAD(0x051C, 0x0214, 5, 0x0000, 0, MX6SL_FLOAT_PAD_CTRL) +#define MX6SL_PAD_LCD_HSYNC__KITTEN_TRCLK \ + IOMUX_PAD(0x051C, 0x0214, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_HSYNC__TPSMP_HDATA_16 \ + IOMUX_PAD(0x051C, 0x0214, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_LCD_RESET__LCDIF_RESET \ + IOMUX_PAD(0x0520, 0x0218, 0, 0x0000, 0, MX6SL_LCDIF_PAD_CTRL) +#define MX6SL_PAD_LCD_RESET__WEIM_WEIM_DTACK_B \ + IOMUX_PAD(0x0520, 0x0218, 1, 0x0880, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_RESET__LCDIF_BUSY \ + IOMUX_PAD(0x0520, 0x0218, 2, 0x0774, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_RESET__WEIM_WEIM_WAIT \ + IOMUX_PAD(0x0520, 0x0218, 3, 0x0884, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_RESET__UART2_CTS \ + IOMUX_PAD(0x0520, 0x0218, 4, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_LCD_RESET__UART2_RTS \ + IOMUX_PAD(0x0520, 0x0218, 4, 0x0800, 2, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_LCD_RESET__GPIO_2_19 \ + IOMUX_PAD(0x0520, 0x0218, 5, 0x0000, 0, MX6SL_FLOAT_PAD_CTRL) +#define MX6SL_PAD_LCD_RESET__CCM_PMIC_RDY \ + IOMUX_PAD(0x0520, 0x0218, 6, 0x062C, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_RESET__TPSMP_HDATA_DIR \ + IOMUX_PAD(0x0520, 0x0218, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_LCD_VSYNC__LCDIF_VSYNC \ + IOMUX_PAD(0x0524, 0x021C, 0, 0x0000, 0, MX6SL_LCDIF_PAD_CTRL) +#define MX6SL_PAD_LCD_VSYNC__USDHC4_DAT7 \ + IOMUX_PAD(0x0524, 0x021C, 1, 0x0878, 2, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_LCD_VSYNC__LCDIF_RS \ + IOMUX_PAD(0x0524, 0x021C, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_VSYNC__WEIM_WEIM_CS_1 \ + IOMUX_PAD(0x0524, 0x021C, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_VSYNC__UART2_CTS \ + IOMUX_PAD(0x0524, 0x021C, 4, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_LCD_VSYNC__UART2_RTS \ + IOMUX_PAD(0x0524, 0x021C, 4, 0x0800, 3, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_LCD_VSYNC__GPIO_2_18 \ + IOMUX_PAD(0x0524, 0x021C, 5, 0x0000, 0, MX6SL_FLOAT_PAD_CTRL) +#define MX6SL_PAD_LCD_VSYNC__KITTEN_TRCTL \ + IOMUX_PAD(0x0524, 0x021C, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_VSYNC__TPSMP_HDATA_17 \ + IOMUX_PAD(0x0524, 0x021C, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_PMIC_ON_REQ__SNVS_LP_WRAPPER_SNVS_WAKEUP_ALARM \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_PMIC_STBY_REQ__CCM_PMIC_VSTBY_REQ \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_POR_B__SRC_POR_B \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_PWM1__PWM1_PWMO \ + IOMUX_PAD(0x0528, 0x0220, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_PWM1__CCM_CLKO \ + IOMUX_PAD(0x0528, 0x0220, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_PWM1__AUDMUX_AUDIO_CLK_OUT \ + IOMUX_PAD(0x0528, 0x0220, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_PWM1__FEC_REF_OUT \ + IOMUX_PAD(0x0528, 0x0220, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_PWM1__CSI_MCLK \ + IOMUX_PAD(0x0528, 0x0220, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_PWM1__GPIO_3_23 \ + IOMUX_PAD(0x0528, 0x0220, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_PWM1__EPIT1_EPITO \ + IOMUX_PAD(0x0528, 0x0220, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_PWM1__OBSERVE_MUX_OUT_4 \ + IOMUX_PAD(0x0528, 0x0220, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_REF_CLK_24M__ANATOP_ANATOP_24M_OUT \ + IOMUX_PAD(0x052C, 0x0224, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_REF_CLK_24M__I2C3_SCL \ + IOMUX_PAD(0x052C, 0x0224, 1 | IOMUX_CONFIG_SION, 0x072C, 2, MX6SL_I2C_PAD_CTRL) +#define MX6SL_PAD_REF_CLK_24M__PWM3_PWMO \ + IOMUX_PAD(0x052C, 0x0224, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_REF_CLK_24M__ANATOP_USBOTG2_ID \ + IOMUX_PAD(0x052C, 0x0224, 3, 0x05E0, 2, NO_PAD_CTRL) +#define MX6SL_PAD_REF_CLK_24M__CCM_PMIC_RDY \ + IOMUX_PAD(0x052C, 0x0224, 4, 0x062C, 2, NO_PAD_CTRL) +#define MX6SL_PAD_REF_CLK_24M__GPIO_3_21 \ + IOMUX_PAD(0x052C, 0x0224, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_REF_CLK_24M__USDHC3_WP \ + IOMUX_PAD(0x052C, 0x0224, 6, 0x084C, 3, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_REF_CLK_24M__TPSMP_HDATA_19 \ + IOMUX_PAD(0x052C, 0x0224, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_REF_CLK_32K__ANATOP_ANATOP_32K_OUT \ + IOMUX_PAD(0x0530, 0x0228, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_REF_CLK_32K__I2C3_SDA \ + IOMUX_PAD(0x0530, 0x0228, 1 | IOMUX_CONFIG_SION, 0x0730, 2, MX6SL_I2C_PAD_CTRL) +#define MX6SL_PAD_REF_CLK_32K__PWM4_PWMO \ + IOMUX_PAD(0x0530, 0x0228, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_REF_CLK_32K__ANATOP_USBOTG1_ID \ + IOMUX_PAD(0x0530, 0x0228, 3, 0x05DC, 3, NO_PAD_CTRL) +#define MX6SL_PAD_REF_CLK_32K__USDHC1_LCTL \ + IOMUX_PAD(0x0530, 0x0228, 4, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_REF_CLK_32K__GPIO_3_22 \ + IOMUX_PAD(0x0530, 0x0228, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_REF_CLK_32K__USDHC3_CD \ + IOMUX_PAD(0x0530, 0x0228, 6, 0x0838, 3, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_REF_CLK_32K__OBSERVE_MUX_OUT_3 \ + IOMUX_PAD(0x0530, 0x0228, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_RESET_IN_B__SRC_RESET_B \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_SD1_CLK__USDHC1_CLK_50MHZ \ + IOMUX_PAD(0x0534, 0x022C, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_SD1_CLK__USDHC1_CLK_100MHZ \ + IOMUX_PAD(0x0534, 0x022C, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_100MHZ) +#define MX6SL_PAD_SD1_CLK__USDHC1_CLK_200MHZ \ + IOMUX_PAD(0x0534, 0x022C, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_200MHZ) +#define MX6SL_PAD_SD1_CLK__FEC_MDIO \ + IOMUX_PAD(0x0534, 0x022C, 1, 0x06F4, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_CLK__KPP_COL_0 \ + IOMUX_PAD(0x0534, 0x022C, 2, 0x0734, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_CLK__EPDC_SDCE_4 \ + IOMUX_PAD(0x0534, 0x022C, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_CLK__MSHC_SCLK \ + IOMUX_PAD(0x0534, 0x022C, 4, 0x07E8, 1, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_CLK__GPIO_5_15 \ + IOMUX_PAD(0x0534, 0x022C, 5, 0x0000, 0, MX6SL_CHG_PAD_CTRL) +#define MX6SL_PAD_SD1_CLK__ANATOP_ANATOP_TESTO_2 \ + IOMUX_PAD(0x0534, 0x022C, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_CLK__PL301_SIM_MX6SL_PER1_HADDR_25 \ + IOMUX_PAD(0x0534, 0x022C, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_SD1_CMD__USDHC1_CMD_50MHZ \ + IOMUX_PAD(0x0538, 0x0230, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_SD1_CMD__USDHC1_CMD_100MHZ \ + IOMUX_PAD(0x0538, 0x0230, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_100MHZ) +#define MX6SL_PAD_SD1_CMD__USDHC1_CMD_200MHZ \ + IOMUX_PAD(0x0538, 0x0230, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_200MHZ) +#define MX6SL_PAD_SD1_CMD__FEC_TX_CLK \ + IOMUX_PAD(0x0538, 0x0230, 1, 0x070C, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_CMD__KPP_ROW_0 \ + IOMUX_PAD(0x0538, 0x0230, 2, 0x0754, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_CMD__EPDC_SDCE_5 \ + IOMUX_PAD(0x0538, 0x0230, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_CMD__MSHC_BS \ + IOMUX_PAD(0x0538, 0x0230, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_CMD__GPIO_5_14 \ + IOMUX_PAD(0x0538, 0x0230, 5, 0x0000, 0, MX6SL_FLOAT_PAD_CTRL) +#define MX6SL_PAD_SD1_CMD__ANATOP_ANATOP_TESTO_3 \ + IOMUX_PAD(0x0538, 0x0230, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_CMD__PL301_SIM_MX6SL_PER1_HADDR_26 \ + IOMUX_PAD(0x0538, 0x0230, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_SD1_DAT0__USDHC1_DAT0_50MHZ \ + IOMUX_PAD(0x053C, 0x0234, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT0__USDHC1_DAT0_100MHZ \ + IOMUX_PAD(0x053C, 0x0234, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_100MHZ) +#define MX6SL_PAD_SD1_DAT0__USDHC1_DAT0_200MHZ \ + IOMUX_PAD(0x053C, 0x0234, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_200MHZ) +#define MX6SL_PAD_SD1_DAT0__FEC_RX_ER \ + IOMUX_PAD(0x053C, 0x0234, 1, 0x0708, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT0__KPP_COL_1 \ + IOMUX_PAD(0x053C, 0x0234, 2, 0x0738, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT0__EPDC_SDCE_6 \ + IOMUX_PAD(0x053C, 0x0234, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT0__MSHC_DATA_0 \ + IOMUX_PAD(0x053C, 0x0234, 4, 0x07D8, 1, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT0__GPIO_5_11 \ + IOMUX_PAD(0x053C, 0x0234, 5, 0x0000, 0, MX6SL_CHG_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT0__ANATOP_ANATOP_TESTO_4 \ + IOMUX_PAD(0x053C, 0x0234, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT0__PL301_SIM_MX6SL_PER1_HADDR_27 \ + IOMUX_PAD(0x053C, 0x0234, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_SD1_DAT1__USDHC1_DAT1_50MHZ \ + IOMUX_PAD(0x0540, 0x0238, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT1__USDHC1_DAT1_100MHZ \ + IOMUX_PAD(0x0540, 0x0238, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_100MHZ) +#define MX6SL_PAD_SD1_DAT1__USDHC1_DAT1_200MHZ \ + IOMUX_PAD(0x0540, 0x0238, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_200MHZ) +#define MX6SL_PAD_SD1_DAT1__FEC_RX_DV \ + IOMUX_PAD(0x0540, 0x0238, 1, 0x0704, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT1__KPP_ROW_1 \ + IOMUX_PAD(0x0540, 0x0238, 2, 0x0758, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT1__EPDC_SDCE_7 \ + IOMUX_PAD(0x0540, 0x0238, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT1__MSHC_DATA_1 \ + IOMUX_PAD(0x0540, 0x0238, 4, 0x07DC, 1, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT1__GPIO_5_8 \ + IOMUX_PAD(0x0540, 0x0238, 5, 0x0000, 0, MX6SL_FLOAT_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT1__ANATOP_ANATOP_TESTO_5 \ + IOMUX_PAD(0x0540, 0x0238, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT1__PL301_SIM_MX6SL_PER1_HADDR_28 \ + IOMUX_PAD(0x0540, 0x0238, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_SD1_DAT2__USDHC1_DAT2_50MHZ \ + IOMUX_PAD(0x0544, 0x023C, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT2__USDHC1_DAT2_100MHZ \ + IOMUX_PAD(0x0544, 0x023C, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_100MHZ) +#define MX6SL_PAD_SD1_DAT2__USDHC1_DAT2_200MHZ \ + IOMUX_PAD(0x0544, 0x023C, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_200MHZ) +#define MX6SL_PAD_SD1_DAT2__FEC_RDATA_1 \ + IOMUX_PAD(0x0544, 0x023C, 1, 0x06FC, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT2__KPP_COL_2 \ + IOMUX_PAD(0x0544, 0x023C, 2, 0x073C, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT2__EPDC_SDCE_8 \ + IOMUX_PAD(0x0544, 0x023C, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT2__MSHC_DATA_2 \ + IOMUX_PAD(0x0544, 0x023C, 4, 0x07E0, 1, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT2__GPIO_5_13 \ + IOMUX_PAD(0x0544, 0x023C, 5, 0x0000, 0, MX6SL_FLOAT_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT2__GPIO_5_13_PULLHIGH \ + IOMUX_PAD(0x0544, 0x023C, 5, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT2__ANATOP_ANATOP_TESTO_6 \ + IOMUX_PAD(0x0544, 0x023C, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT2__PL301_SIM_MX6SL_PER1_HADDR_29 \ + IOMUX_PAD(0x0544, 0x023C, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_SD1_DAT3__USDHC1_DAT3_50MHZ \ + IOMUX_PAD(0x0548, 0x0240, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT3__USDHC1_DAT3_100MHZ \ + IOMUX_PAD(0x0548, 0x0240, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_100MHZ) +#define MX6SL_PAD_SD1_DAT3__USDHC1_DAT3_200MHZ \ + IOMUX_PAD(0x0548, 0x0240, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_200MHZ) +#define MX6SL_PAD_SD1_DAT3__FEC_TDATA_0 \ + IOMUX_PAD(0x0548, 0x0240, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT3__KPP_ROW_2 \ + IOMUX_PAD(0x0548, 0x0240, 2, 0x075C, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT3__EPDC_SDCE_9 \ + IOMUX_PAD(0x0548, 0x0240, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT3__MSHC_DATA_3 \ + IOMUX_PAD(0x0548, 0x0240, 4, 0x07E4, 1, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT3__GPIO_5_6 \ + IOMUX_PAD(0x0548, 0x0240, 5, 0x0000, 0, MX6SL_FLOAT_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT3__ANATOP_ANATOP_TESTO_7 \ + IOMUX_PAD(0x0548, 0x0240, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT3__PL301_SIM_MX6SL_PER1_HADDR_30 \ + IOMUX_PAD(0x0548, 0x0240, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_SD1_DAT4__USDHC1_DAT4_50MHZ \ + IOMUX_PAD(0x054C, 0x0244, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT4__USDHC1_DAT4_100MHZ \ + IOMUX_PAD(0x054C, 0x0244, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_100MHZ) +#define MX6SL_PAD_SD1_DAT4__USDHC1_DAT4_200MHZ \ + IOMUX_PAD(0x054C, 0x0244, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_200MHZ) +#define MX6SL_PAD_SD1_DAT4__FEC_MDC \ + IOMUX_PAD(0x054C, 0x0244, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT4__KPP_COL_3 \ + IOMUX_PAD(0x054C, 0x0244, 2, 0x0740, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT4__EPDC_SDCLKN \ + IOMUX_PAD(0x054C, 0x0244, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT4__UART4_TXD \ + IOMUX_PAD(0x054C, 0x0244, 4, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT4__UART4_RXD \ + IOMUX_PAD(0x054C, 0x0244, 4, 0x0814, 4, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT4__GPIO_5_12 \ + IOMUX_PAD(0x054C, 0x0244, 5, 0x0000, 0, MX6SL_FLOAT_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT4__ANATOP_ANATOP_TESTO_8 \ + IOMUX_PAD(0x054C, 0x0244, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT4__PL301_SIM_MX6SL_PER1_HADDR_31 \ + IOMUX_PAD(0x054C, 0x0244, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_SD1_DAT5__USDHC1_DAT5_50MHZ \ + IOMUX_PAD(0x0550, 0x0248, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT5__USDHC1_DAT5_100MHZ \ + IOMUX_PAD(0x0550, 0x0248, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_100MHZ) +#define MX6SL_PAD_SD1_DAT5__USDHC1_DAT5_200MHZ \ + IOMUX_PAD(0x0550, 0x0248, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_200MHZ) +#define MX6SL_PAD_SD1_DAT5__FEC_RDATA_0 \ + IOMUX_PAD(0x0550, 0x0248, 1, 0x06F8, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT5__KPP_ROW_3 \ + IOMUX_PAD(0x0550, 0x0248, 2, 0x0760, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT5__EPDC_SDOED \ + IOMUX_PAD(0x0550, 0x0248, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT5__UART4_TXD \ + IOMUX_PAD(0x0550, 0x0248, 4, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT5__UART4_RXD \ + IOMUX_PAD(0x0550, 0x0248, 4, 0x0814, 5, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT5__GPIO_5_9 \ + IOMUX_PAD(0x0550, 0x0248, 5, 0x0000, 0, MX6SL_FLOAT_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT5__ANATOP_ANATOP_TESTO_9 \ + IOMUX_PAD(0x0550, 0x0248, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT5__PL301_SIM_MX6SL_PER1_HPROT_3 \ + IOMUX_PAD(0x0550, 0x0248, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_SD1_DAT6__USDHC1_DAT6_50MHZ \ + IOMUX_PAD(0x0554, 0x024C, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT6__USDHC1_DAT6_100MHZ \ + IOMUX_PAD(0x0554, 0x024C, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_100MHZ) +#define MX6SL_PAD_SD1_DAT6__USDHC1_DAT6_200MHZ \ + IOMUX_PAD(0x0554, 0x024C, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_200MHZ) +#define MX6SL_PAD_SD1_DAT6__FEC_TX_EN \ + IOMUX_PAD(0x0554, 0x024C, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT6__KPP_COL_4 \ + IOMUX_PAD(0x0554, 0x024C, 2, 0x0744, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT6__EPDC_SDOEZ \ + IOMUX_PAD(0x0554, 0x024C, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT6__UART4_CTS \ + IOMUX_PAD(0x0554, 0x024C, 4, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT6__UART4_RTS \ + IOMUX_PAD(0x0554, 0x024C, 4, 0x0810, 4, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT6__GPIO_5_7 \ + IOMUX_PAD(0x0554, 0x024C, 5, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT6__ANATOP_ANATOP_TESTO_10 \ + IOMUX_PAD(0x0554, 0x024C, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT6__PL301_SIM_MX6SL_PER1_HPROT_2 \ + IOMUX_PAD(0x0554, 0x024C, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_SD1_DAT7__USDHC1_DAT7_50MHZ \ + IOMUX_PAD(0x0558, 0x0250, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT7__USDHC1_DAT7_100MHZ \ + IOMUX_PAD(0x0558, 0x0250, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_100MHZ) +#define MX6SL_PAD_SD1_DAT7__USDHC1_DAT7_200MHZ \ + IOMUX_PAD(0x0558, 0x0250, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_200MHZ) +#define MX6SL_PAD_SD1_DAT7__FEC_TDATA_1 \ + IOMUX_PAD(0x0558, 0x0250, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT7__KPP_ROW_4 \ + IOMUX_PAD(0x0558, 0x0250, 2, 0x0764, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT7__CCM_PMIC_RDY \ + IOMUX_PAD(0x0558, 0x0250, 3, 0x062C, 3, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT7__UART4_CTS \ + IOMUX_PAD(0x0558, 0x0250, 4, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT7__UART4_RTS \ + IOMUX_PAD(0x0558, 0x0250, 4, 0x0810, 5, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT7__GPIO_5_10 \ + IOMUX_PAD(0x0558, 0x0250, 5, 0x0000, 0, MX6SL_FLOAT_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT7__GPIO_5_10_OUPUT \ + IOMUX_PAD(0x0558, 0x0250, 5, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT7__ANATOP_ANATOP_TESTO_11 \ + IOMUX_PAD(0x0558, 0x0250, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT7__PL301_SIM_MX6SL_PER1_HMASTLOCK \ + IOMUX_PAD(0x0558, 0x0250, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_SD2_CLK__USDHC2_CLK_50MHZ \ + IOMUX_PAD(0x055C, 0x0254, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_SD2_CLK__USDHC2_CLK_100MHZ \ + IOMUX_PAD(0x055C, 0x0254, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_100MHZ) +#define MX6SL_PAD_SD2_CLK__USDHC2_CLK_200MHZ \ + IOMUX_PAD(0x055C, 0x0254, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_200MHZ) +#define MX6SL_PAD_SD2_CLK__AUDMUX_AUD4_RXFS \ + IOMUX_PAD(0x055C, 0x0254, 1, 0x05F0, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_CLK__ECSPI3_SCLK \ + IOMUX_PAD(0x055C, 0x0254, 2, 0x06B0, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_CLK__CSI_D_0 \ + IOMUX_PAD(0x055C, 0x0254, 3, 0x0630, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_CLK__OSC32K_32K_OUT \ + IOMUX_PAD(0x055C, 0x0254, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_CLK__GPIO_5_5 \ + IOMUX_PAD(0x055C, 0x0254, 5, 0x0000, 0, MX6SL_FLOAT_PAD_CTRL) +#define MX6SL_PAD_SD2_CLK__ANATOP_ANATOP_TESTO_13 \ + IOMUX_PAD(0x055C, 0x0254, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_CLK__PL301_SIM_MX6SL_PER1_HPROT_1 \ + IOMUX_PAD(0x055C, 0x0254, 7, 0x07EC, 1, NO_PAD_CTRL) + +#define MX6SL_PAD_SD2_CMD__USDHC2_CMD_50MHZ \ + IOMUX_PAD(0x0560, 0x0258, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_SD2_CMD__USDHC2_CMD_100MHZ \ + IOMUX_PAD(0x0560, 0x0258, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_100MHZ) +#define MX6SL_PAD_SD2_CMD__USDHC2_CMD_200MHZ \ + IOMUX_PAD(0x0560, 0x0258, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_200MHZ) +#define MX6SL_PAD_SD2_CMD__AUDMUX_AUD4_RXC \ + IOMUX_PAD(0x0560, 0x0258, 1, 0x05EC, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_CMD__ECSPI3_SS0 \ + IOMUX_PAD(0x0560, 0x0258, 2, 0x06C0, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_CMD__CSI_D_1 \ + IOMUX_PAD(0x0560, 0x0258, 3, 0x0634, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_CMD__EPIT1_EPITO \ + IOMUX_PAD(0x0560, 0x0258, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_CMD__GPIO_5_4 \ + IOMUX_PAD(0x0560, 0x0258, 5, 0x0000, 0, MX6SL_FLOAT_PAD_CTRL) +#define MX6SL_PAD_SD2_CMD__ANATOP_ANATOP_TESTO_14 \ + IOMUX_PAD(0x0560, 0x0258, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_CMD__PL301_SIM_MX6SL_PER1_HADDR_21 \ + IOMUX_PAD(0x0560, 0x0258, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_SD2_DAT0__USDHC2_DAT0_50MHZ \ + IOMUX_PAD(0x0564, 0x025C, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT0__USDHC2_DAT0_100MHZ \ + IOMUX_PAD(0x0564, 0x025C, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_100MHZ) +#define MX6SL_PAD_SD2_DAT0__USDHC2_DAT0_200MHZ \ + IOMUX_PAD(0x0564, 0x025C, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_200MHZ) +#define MX6SL_PAD_SD2_DAT0__AUDMUX_AUD4_RXD \ + IOMUX_PAD(0x0564, 0x025C, 1, 0x05E4, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT0__ECSPI3_MOSI \ + IOMUX_PAD(0x0564, 0x025C, 2, 0x06BC, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT0__CSI_D_2 \ + IOMUX_PAD(0x0564, 0x025C, 3, 0x0638, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT0__UART5_CTS \ + IOMUX_PAD(0x0564, 0x025C, 4, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT0__UART5_RTS \ + IOMUX_PAD(0x0564, 0x025C, 4, 0x0818, 4, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT0__GPIO_5_1 \ + IOMUX_PAD(0x0564, 0x025C, 5, 0x0000, 0, MX6SL_FLOAT_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT0__ANATOP_ANATOP_TESTO_15 \ + IOMUX_PAD(0x0564, 0x025C, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT0__PL301_SIM_MX6SL_PER1_HPROT_0 \ + IOMUX_PAD(0x0564, 0x025C, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_SD2_DAT1__USDHC2_DAT1_50MHZ \ + IOMUX_PAD(0x0568, 0x0260, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT1__USDHC2_DAT1_100MHZ \ + IOMUX_PAD(0x0568, 0x0260, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_100MHZ) +#define MX6SL_PAD_SD2_DAT1__USDHC2_DAT1_200MHZ \ + IOMUX_PAD(0x0568, 0x0260, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_200MHZ) +#define MX6SL_PAD_SD2_DAT1__AUDMUX_AUD4_TXC \ + IOMUX_PAD(0x0568, 0x0260, 1, 0x05F4, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT1__ECSPI3_MISO \ + IOMUX_PAD(0x0568, 0x0260, 2, 0x06B8, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT1__CSI_D_3 \ + IOMUX_PAD(0x0568, 0x0260, 3, 0x063C, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT1__UART5_CTS \ + IOMUX_PAD(0x0568, 0x0260, 4, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT1__UART5_RTS \ + IOMUX_PAD(0x0568, 0x0260, 4, 0x0818, 5, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT1__GPIO_4_30 \ + IOMUX_PAD(0x0568, 0x0260, 5, 0x0000, 0, MX6SL_FLOAT_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT1__MMDC_MMDC_DEBUG_39 \ + IOMUX_PAD(0x0568, 0x0260, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT1__PL301_SIM_MX6SL_PER1_HBURST_1 \ + IOMUX_PAD(0x0568, 0x0260, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_SD2_DAT2__USDHC2_DAT2_50MHZ \ + IOMUX_PAD(0x056C, 0x0264, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT2__USDHC2_DAT2_100MHZ \ + IOMUX_PAD(0x056C, 0x0264, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_100MHZ) +#define MX6SL_PAD_SD2_DAT2__USDHC2_DAT2_200MHZ \ + IOMUX_PAD(0x056C, 0x0264, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_200MHZ) +#define MX6SL_PAD_SD2_DAT2__AUDMUX_AUD4_TXFS \ + IOMUX_PAD(0x056C, 0x0264, 1, 0x05F8, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT2__FEC_COL \ + IOMUX_PAD(0x056C, 0x0264, 2, 0x06F0, 1, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT2__CSI_D_4 \ + IOMUX_PAD(0x056C, 0x0264, 3, 0x0640, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT2__UART5_TXD \ + IOMUX_PAD(0x056C, 0x0264, 4, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT2__UART5_RXD \ + IOMUX_PAD(0x056C, 0x0264, 4, 0x081C, 4, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT2__GPIO_5_3 \ + IOMUX_PAD(0x056C, 0x0264, 5, 0x0000, 0, MX6SL_FLOAT_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT2__MMDC_MMDC_DEBUG_38 \ + IOMUX_PAD(0x056C, 0x0264, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT2__PL301_SIM_MX6SL_PER1_HADDR_22 \ + IOMUX_PAD(0x056C, 0x0264, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_SD2_DAT3__USDHC2_DAT3_50MHZ \ + IOMUX_PAD(0x0570, 0x0268, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT3__USDHC2_DAT3_100MHZ \ + IOMUX_PAD(0x0570, 0x0268, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_100MHZ) +#define MX6SL_PAD_SD2_DAT3__USDHC2_DAT3_200MHZ \ + IOMUX_PAD(0x0570, 0x0268, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_200MHZ) +#define MX6SL_PAD_SD2_DAT3__AUDMUX_AUD4_TXD \ + IOMUX_PAD(0x0570, 0x0268, 1, 0x05E8, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT3__FEC_RX_CLK \ + IOMUX_PAD(0x0570, 0x0268, 2, 0x0700, 1, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT3__CSI_D_5 \ + IOMUX_PAD(0x0570, 0x0268, 3, 0x0644, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT3__UART5_TXD \ + IOMUX_PAD(0x0570, 0x0268, 4, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT3__UART5_RXD \ + IOMUX_PAD(0x0570, 0x0268, 4, 0x081C, 5, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT3__GPIO_4_28 \ + IOMUX_PAD(0x0570, 0x0268, 5, 0x0000, 0, MX6SL_FLOAT_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT3__MMDC_MMDC_DEBUG_37 \ + IOMUX_PAD(0x0570, 0x0268, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT3__PL301_SIM_MX6SL_PER1_HBURST_0 \ + IOMUX_PAD(0x0570, 0x0268, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_SD2_DAT4__USDHC2_DAT4_50MHZ \ + IOMUX_PAD(0x0574, 0x026C, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT4__USDHC2_DAT4_100MHZ \ + IOMUX_PAD(0x0574, 0x026C, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_100MHZ) +#define MX6SL_PAD_SD2_DAT4__USDHC2_DAT4_200MHZ \ + IOMUX_PAD(0x0574, 0x026C, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_200MHZ) +#define MX6SL_PAD_SD2_DAT4__USDHC3_DAT4 \ + IOMUX_PAD(0x0574, 0x026C, 1, 0x083C, 1, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT4__UART2_TXD \ + IOMUX_PAD(0x0574, 0x026C, 2, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT4__UART2_RXD \ + IOMUX_PAD(0x0574, 0x026C, 2, 0x0804, 4, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT4__CSI_D_6 \ + IOMUX_PAD(0x0574, 0x026C, 3, 0x0648, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT4__SPDIF_OUT1 \ + IOMUX_PAD(0x0574, 0x026C, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT4__GPIO_5_2 \ + IOMUX_PAD(0x0574, 0x026C, 5, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT4__MMDC_MMDC_DEBUG_36 \ + IOMUX_PAD(0x0574, 0x026C, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT4__PL301_SIM_MX6SL_PER1_HADDR_10 \ + IOMUX_PAD(0x0574, 0x026C, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_SD2_DAT5__USDHC2_DAT5_50MHZ \ + IOMUX_PAD(0x0578, 0x0270, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT5__USDHC2_DAT5_100MHZ \ + IOMUX_PAD(0x0578, 0x0270, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_100MHZ) +#define MX6SL_PAD_SD2_DAT5__USDHC2_DAT5_200MHZ \ + IOMUX_PAD(0x0578, 0x0270, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_200MHZ) +#define MX6SL_PAD_SD2_DAT5__USDHC3_DAT5 \ + IOMUX_PAD(0x0578, 0x0270, 1, 0x0840, 1, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT5__UART2_TXD \ + IOMUX_PAD(0x0578, 0x0270, 2, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT5__UART2_RXD \ + IOMUX_PAD(0x0578, 0x0270, 2, 0x0804, 5, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT5__CSI_D_7 \ + IOMUX_PAD(0x0578, 0x0270, 3, 0x064C, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT5__SPDIF_IN1 \ + IOMUX_PAD(0x0578, 0x0270, 4, 0x07F0, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT5__GPIO_4_31 \ + IOMUX_PAD(0x0578, 0x0270, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT5__GPIO_4_31_INPUT \ + IOMUX_PAD(0x0578, 0x0270, 5, 0x0000, 0, NO_PAD_I) +#define MX6SL_PAD_SD2_DAT5__MMDC_MMDC_DEBUG_35 \ + IOMUX_PAD(0x0578, 0x0270, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT5__PL301_SIM_MX6SL_PER1_HADDR_20 \ + IOMUX_PAD(0x0578, 0x0270, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_SD2_DAT6__USDHC2_DAT6_50MHZ \ + IOMUX_PAD(0x057C, 0x0274, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT6__USDHC2_DAT6_100MHZ \ + IOMUX_PAD(0x057C, 0x0274, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_100MHZ) +#define MX6SL_PAD_SD2_DAT6__USDHC2_DAT6_200MHZ \ + IOMUX_PAD(0x057C, 0x0274, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_200MHZ) +#define MX6SL_PAD_SD2_DAT6__USDHC3_DAT6 \ + IOMUX_PAD(0x057C, 0x0274, 1, 0x0844, 1, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT6__UART2_CTS \ + IOMUX_PAD(0x057C, 0x0274, 2, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT6__UART2_RTS \ + IOMUX_PAD(0x057C, 0x0274, 2, 0x0800, 4, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT6__CSI_D_8 \ + IOMUX_PAD(0x057C, 0x0274, 3, 0x0650, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT6__USDHC2_WP \ + IOMUX_PAD(0x057C, 0x0274, 4, 0x0834, 2, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT6__GPIO_4_29 \ + IOMUX_PAD(0x057C, 0x0274, 5, 0x0000, 0, NO_PAD_I) +#define MX6SL_PAD_SD2_DAT6__GPIO_4_29_OUTPUT \ + IOMUX_PAD(0x057C, 0x0274, 5, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT6__MMDC_MMDC_DEBUG_34 \ + IOMUX_PAD(0x057C, 0x0274, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT6__PL301_SIM_MX6SL_PER1_HADDR_19 \ + IOMUX_PAD(0x057C, 0x0274, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_SD2_DAT7__USDHC2_DAT7_50MHZ \ + IOMUX_PAD(0x0580, 0x0278, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT7__USDHC2_DAT7_100MHZ \ + IOMUX_PAD(0x0580, 0x0278, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_100MHZ) +#define MX6SL_PAD_SD2_DAT7__USDHC2_DAT7_200MHZ \ + IOMUX_PAD(0x0580, 0x0278, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_200MHZ) +#define MX6SL_PAD_SD2_DAT7__USDHC3_DAT7 \ + IOMUX_PAD(0x0580, 0x0278, 1, 0x0848, 1, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT7__UART2_CTS \ + IOMUX_PAD(0x0580, 0x0278, 2, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT7__UART2_RTS \ + IOMUX_PAD(0x0580, 0x0278, 2, 0x0800, 5, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT7__CSI_D_9 \ + IOMUX_PAD(0x0580, 0x0278, 3, 0x0654, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT7__USDHC2_CD \ + IOMUX_PAD(0x0580, 0x0278, 4, 0x0830, 2, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT7__GPIO_5_0 \ + IOMUX_PAD(0x0580, 0x0278, 5, 0x0000, 0, MX6SL_FLOAT_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT7__MMDC_MMDC_DEBUG_33 \ + IOMUX_PAD(0x0580, 0x0278, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT7__PL301_SIM_MX6SL_PER1_HADDR_16 \ + IOMUX_PAD(0x0580, 0x0278, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_SD2_RST__USDHC2_RST \ + IOMUX_PAD(0x0584, 0x027C, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_SD2_RST__FEC_REF_OUT \ + IOMUX_PAD(0x0584, 0x027C, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_RST__WDOG2_WDOG_B \ + IOMUX_PAD(0x0584, 0x027C, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_RST__SPDIF_OUT1 \ + IOMUX_PAD(0x0584, 0x027C, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_RST__CSI_MCLK \ + IOMUX_PAD(0x0584, 0x027C, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_RST__GPIO_4_27 \ + IOMUX_PAD(0x0584, 0x027C, 5, 0x0000, 0, MX6SL_FLOAT_PAD_CTRL/*NO_PAD_CTRL*/) +#define MX6SL_PAD_SD2_RST__ANATOP_ANATOP_TESTO_12 \ + IOMUX_PAD(0x0584, 0x027C, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_RST__PL301_SIM_MX6SL_PER1_HBURST_2 \ + IOMUX_PAD(0x0584, 0x027C, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_SD3_CLK__USDHC3_CLK_50MHZ \ + IOMUX_PAD(0x0588, 0x0280, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_SD3_CLK__USDHC3_CLK_100MHZ \ + IOMUX_PAD(0x0588, 0x0280, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_100MHZ) +#define MX6SL_PAD_SD3_CLK__USDHC3_CLK_200MHZ \ + IOMUX_PAD(0x0588, 0x0280, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_200MHZ) +#define MX6SL_PAD_SD3_CLK__AUDMUX_AUD5_RXFS \ + IOMUX_PAD(0x0588, 0x0280, 1, 0x0608, 1, NO_PAD_CTRL) +#define MX6SL_PAD_SD3_CLK__KPP_COL_5 \ + IOMUX_PAD(0x0588, 0x0280, 2, 0x0748, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD3_CLK__CSI_D_10 \ + IOMUX_PAD(0x0588, 0x0280, 3, 0x0658, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD3_CLK__WDOG1_WDOG_RST_B_DEB \ + IOMUX_PAD(0x0588, 0x0280, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD3_CLK__GPIO_5_18 \ + IOMUX_PAD(0x0588, 0x0280, 5, 0x0000, 0, MX6SL_FLOAT_PAD_CTRL) +#define MX6SL_PAD_SD3_CLK__USB_USBOTG1_PWR \ + IOMUX_PAD(0x0588, 0x0280, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD3_CLK__PL301_SIM_MX6SL_PER1_HADDR_13 \ + IOMUX_PAD(0x0588, 0x0280, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_SD3_CMD__USDHC3_CMD_50MHZ \ + IOMUX_PAD(0x058C, 0x0284, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_SD3_CMD__USDHC3_CMD_100MHZ \ + IOMUX_PAD(0x058C, 0x0284, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_100MHZ) +#define MX6SL_PAD_SD3_CMD__USDHC3_CMD_200MHZ \ + IOMUX_PAD(0x058C, 0x0284, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_200MHZ) +#define MX6SL_PAD_SD3_CMD__AUDMUX_AUD5_RXC \ + IOMUX_PAD(0x058C, 0x0284, 1, 0x0604, 1, NO_PAD_CTRL) +#define MX6SL_PAD_SD3_CMD__KPP_ROW_5 \ + IOMUX_PAD(0x058C, 0x0284, 2, 0x0768, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD3_CMD__CSI_D_11 \ + IOMUX_PAD(0x058C, 0x0284, 3, 0x065C, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD3_CMD__ANATOP_USBOTG2_ID \ + IOMUX_PAD(0x058C, 0x0284, 4, 0x05E0, 3, NO_PAD_CTRL) +#define MX6SL_PAD_SD3_CMD__GPIO_5_21 \ + IOMUX_PAD(0x058C, 0x0284, 5, 0x0000, 0, MX6SL_FLOAT_PAD_CTRL) +#define MX6SL_PAD_SD3_CMD__USB_USBOTG2_PWR \ + IOMUX_PAD(0x058C, 0x0284, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD3_CMD__PL301_SIM_MX6SL_PER1_HADDR_18 \ + IOMUX_PAD(0x058C, 0x0284, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_SD3_DAT0__USDHC3_DAT0_50MHZ \ + IOMUX_PAD(0x0590, 0x0288, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_SD3_DAT0__USDHC3_DAT0_100MHZ \ + IOMUX_PAD(0x0590, 0x0288, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_100MHZ) +#define MX6SL_PAD_SD3_DAT0__USDHC3_DAT0_200MHZ \ + IOMUX_PAD(0x0590, 0x0288, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_200MHZ) +#define MX6SL_PAD_SD3_DAT0__AUDMUX_AUD5_RXD \ + IOMUX_PAD(0x0590, 0x0288, 1, 0x05FC, 1, NO_PAD_CTRL) +#define MX6SL_PAD_SD3_DAT0__KPP_COL_6 \ + IOMUX_PAD(0x0590, 0x0288, 2, 0x074C, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD3_DAT0__CSI_D_12 \ + IOMUX_PAD(0x0590, 0x0288, 3, 0x0660, 1, NO_PAD_CTRL) +#define MX6SL_PAD_SD3_DAT0__ANATOP_USBOTG1_ID \ + IOMUX_PAD(0x0590, 0x0288, 4, 0x05DC, 4, NO_PAD_CTRL) +#define MX6SL_PAD_SD3_DAT0__GPIO_5_19 \ + IOMUX_PAD(0x0590, 0x0288, 5, 0x0000, 0, MX6SL_FLOAT_PAD_CTRL) +#define MX6SL_PAD_SD3_DAT0__SJC_JTAG_ACT \ + IOMUX_PAD(0x0590, 0x0288, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD3_DAT0__PL301_SIM_MX6SL_PER1_HADDR_11 \ + IOMUX_PAD(0x0590, 0x0288, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_SD3_DAT1__USDHC3_DAT1_50MHZ \ + IOMUX_PAD(0x0594, 0x028C, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_SD3_DAT1__USDHC3_DAT1_100MHZ \ + IOMUX_PAD(0x0594, 0x028C, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_100MHZ) +#define MX6SL_PAD_SD3_DAT1__USDHC3_DAT1_200MHZ \ + IOMUX_PAD(0x0594, 0x028C, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_200MHZ) +#define MX6SL_PAD_SD3_DAT1__AUDMUX_AUD5_TXC \ + IOMUX_PAD(0x0594, 0x028C, 1, 0x060C, 1, NO_PAD_CTRL) +#define MX6SL_PAD_SD3_DAT1__KPP_ROW_6 \ + IOMUX_PAD(0x0594, 0x028C, 2, 0x076C, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD3_DAT1__CSI_D_13 \ + IOMUX_PAD(0x0594, 0x028C, 3, 0x0664, 1, NO_PAD_CTRL) +#define MX6SL_PAD_SD3_DAT1__USDHC1_VSELECT \ + IOMUX_PAD(0x0594, 0x028C, 4, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_SD3_DAT1__GPIO_5_20 \ + IOMUX_PAD(0x0594, 0x028C, 5, 0x0000, 0, MX6SL_FLOAT_PAD_CTRL) +#define MX6SL_PAD_SD3_DAT1__SJC_DE_B \ + IOMUX_PAD(0x0594, 0x028C, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD3_DAT1__PL301_SIM_MX6SL_PER1_HADDR_17 \ + IOMUX_PAD(0x0594, 0x028C, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_SD3_DAT2__USDHC3_DAT2_50MHZ \ + IOMUX_PAD(0x0598, 0x0290, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_SD3_DAT2__USDHC3_DAT2_100MHZ \ + IOMUX_PAD(0x0598, 0x0290, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_100MHZ) +#define MX6SL_PAD_SD3_DAT2__USDHC3_DAT2_200MHZ \ + IOMUX_PAD(0x0598, 0x0290, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_200MHZ) +#define MX6SL_PAD_SD3_DAT2__AUDMUX_AUD5_TXFS \ + IOMUX_PAD(0x0598, 0x0290, 1, 0x0610, 1, NO_PAD_CTRL) +#define MX6SL_PAD_SD3_DAT2__KPP_COL_7 \ + IOMUX_PAD(0x0598, 0x0290, 2, 0x0750, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD3_DAT2__CSI_D_14 \ + IOMUX_PAD(0x0598, 0x0290, 3, 0x0668, 1, NO_PAD_CTRL) +#define MX6SL_PAD_SD3_DAT2__EPIT1_EPITO \ + IOMUX_PAD(0x0598, 0x0290, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD3_DAT2__GPIO_5_16 \ + IOMUX_PAD(0x0598, 0x0290, 5, 0x0000, 0, MX6SL_FLOAT_PAD_CTRL) +#define MX6SL_PAD_SD3_DAT2__USB_USBOTG2_OC \ + IOMUX_PAD(0x0598, 0x0290, 6, 0x0820, 3, NO_PAD_CTRL) +#define MX6SL_PAD_SD3_DAT2__PL301_SIM_MX6SL_PER1_HADDR_14 \ + IOMUX_PAD(0x0598, 0x0290, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_SD3_DAT3__USDHC3_DAT3_50MHZ \ + IOMUX_PAD(0x059C, 0x0294, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_SD3_DAT3__USDHC3_DAT3_100MHZ \ + IOMUX_PAD(0x059C, 0x0294, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_100MHZ) +#define MX6SL_PAD_SD3_DAT3__USDHC3_DAT3_200MHZ \ + IOMUX_PAD(0x059C, 0x0294, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_200MHZ) +#define MX6SL_PAD_SD3_DAT3__AUDMUX_AUD5_TXD \ + IOMUX_PAD(0x059C, 0x0294, 1, 0x0600, 1, NO_PAD_CTRL) +#define MX6SL_PAD_SD3_DAT3__KPP_ROW_7 \ + IOMUX_PAD(0x059C, 0x0294, 2, 0x0770, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD3_DAT3__CSI_D_15 \ + IOMUX_PAD(0x059C, 0x0294, 3, 0x066C, 1, NO_PAD_CTRL) +#define MX6SL_PAD_SD3_DAT3__EPIT2_EPITO \ + IOMUX_PAD(0x059C, 0x0294, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD3_DAT3__GPIO_5_17 \ + IOMUX_PAD(0x059C, 0x0294, 5, 0x0000, 0, MX6SL_FLOAT_PAD_CTRL) +#define MX6SL_PAD_SD3_DAT3__USB_USBOTG1_OC \ + IOMUX_PAD(0x059C, 0x0294, 6, 0x0824, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD3_DAT3__PL301_SIM_MX6SL_PER1_HADDR_12 \ + IOMUX_PAD(0x059C, 0x0294, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_TAMPER__SNVS_LP_WRAPPER_SNVS_TD1 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_TEST_MODE__TCU_TEST_MODE \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_UART1_RXD__UART1_TXD \ + IOMUX_PAD(0x05A0, 0x0298, 0, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_UART1_RXD__UART1_RXD \ + IOMUX_PAD(0x05A0, 0x0298, 0, 0x07FC, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_UART1_RXD__PWM1_PWMO \ + IOMUX_PAD(0x05A0, 0x0298, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_UART1_RXD__UART4_TXD \ + IOMUX_PAD(0x05A0, 0x0298, 2, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_UART1_RXD__UART4_RXD \ + IOMUX_PAD(0x05A0, 0x0298, 2, 0x0814, 6, NO_PAD_CTRL) +#define MX6SL_PAD_UART1_RXD__FEC_COL \ + IOMUX_PAD(0x05A0, 0x0298, 3, 0x06F0, 2, NO_PAD_CTRL) +#define MX6SL_PAD_UART1_RXD__UART5_TXD \ + IOMUX_PAD(0x05A0, 0x0298, 4, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_UART1_RXD__UART5_RXD \ + IOMUX_PAD(0x05A0, 0x0298, 4, 0x081C, 6, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_UART1_RXD__GPIO_3_16 \ + IOMUX_PAD(0x05A0, 0x0298, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_UART1_RXD__ANATOP_ANATOP_TESTI_2 \ + IOMUX_PAD(0x05A0, 0x0298, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_UART1_RXD__TPSMP_CLK \ + IOMUX_PAD(0x05A0, 0x0298, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_UART1_TXD__UART1_TXD \ + IOMUX_PAD(0x05A4, 0x029C, 0, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_UART1_TXD__UART1_RXD \ + IOMUX_PAD(0x05A4, 0x029C, 0, 0x07FC, 1, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_UART1_TXD__PWM2_PWMO \ + IOMUX_PAD(0x05A4, 0x029C, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_UART1_TXD__UART4_TXD \ + IOMUX_PAD(0x05A4, 0x029C, 2, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_UART1_TXD__UART4_RXD \ + IOMUX_PAD(0x05A4, 0x029C, 2, 0x0814, 7, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_UART1_TXD__FEC_RX_CLK \ + IOMUX_PAD(0x05A4, 0x029C, 3, 0x0700, 2, NO_PAD_CTRL) +#define MX6SL_PAD_UART1_TXD__UART5_TXD \ + IOMUX_PAD(0x05A4, 0x029C, 4, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_UART1_TXD__UART5_RXD \ + IOMUX_PAD(0x05A4, 0x029C, 4, 0x081C, 7, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_UART1_TXD__GPIO_3_17 \ + IOMUX_PAD(0x05A4, 0x029C, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_UART1_TXD__ANATOP_ANATOP_TESTI_3 \ + IOMUX_PAD(0x05A4, 0x029C, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_UART1_TXD__UART5_DCD \ + IOMUX_PAD(0x05A4, 0x029C, 7, 0x0000, 0, MX6SL_UART_PAD_CTRL) + +#define MX6SL_PAD_WDOG_B__WDOG1_WDOG_B \ + IOMUX_PAD(0x05A8, 0x02A0, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_WDOG_B__WDOG1_WDOG_RST_B_DEB \ + IOMUX_PAD(0x05A8, 0x02A0, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_WDOG_B__UART5_RI \ + IOMUX_PAD(0x05A8, 0x02A0, 2, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_WDOG_B__GPIO_3_18 \ + IOMUX_PAD(0x05A8, 0x02A0, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_WDOG_B__OBSERVE_MUX_OUT_2 \ + IOMUX_PAD(0x05A8, 0x02A0, 7, 0x0000, 0, NO_PAD_CTRL) + +#endif /* __MACH_IOMUX_MX6SL_H__*/ diff --git a/arch/arm/plat-mxc/include/mach/iomux-v1.h b/arch/arm/plat-mxc/include/mach/iomux-v1.h new file mode 100644 index 00000000..c07d3021 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/iomux-v1.h @@ -0,0 +1,105 @@ +/* + * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> + * Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ +#ifndef __MACH_IOMUX_V1_H__ +#define __MACH_IOMUX_V1_H__ + +/* +* GPIO Module and I/O Multiplexer +* x = 0..3 for reg_A, reg_B, reg_C, reg_D +*/ +#define MXC_DDIR(x) (0x00 + ((x) << 8)) +#define MXC_OCR1(x) (0x04 + ((x) << 8)) +#define MXC_OCR2(x) (0x08 + ((x) << 8)) +#define MXC_ICONFA1(x) (0x0c + ((x) << 8)) +#define MXC_ICONFA2(x) (0x10 + ((x) << 8)) +#define MXC_ICONFB1(x) (0x14 + ((x) << 8)) +#define MXC_ICONFB2(x) (0x18 + ((x) << 8)) +#define MXC_DR(x) (0x1c + ((x) << 8)) +#define MXC_GIUS(x) (0x20 + ((x) << 8)) +#define MXC_SSR(x) (0x24 + ((x) << 8)) +#define MXC_ICR1(x) (0x28 + ((x) << 8)) +#define MXC_ICR2(x) (0x2c + ((x) << 8)) +#define MXC_IMR(x) (0x30 + ((x) << 8)) +#define MXC_ISR(x) (0x34 + ((x) << 8)) +#define MXC_GPR(x) (0x38 + ((x) << 8)) +#define MXC_SWR(x) (0x3c + ((x) << 8)) +#define MXC_PUEN(x) (0x40 + ((x) << 8)) + +#define MX1_NUM_GPIO_PORT 4 +#define MX21_NUM_GPIO_PORT 6 +#define MX27_NUM_GPIO_PORT 6 + +#define GPIO_PIN_MASK 0x1f + +#define GPIO_PORT_SHIFT 5 +#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT) + +#define GPIO_PORTA (0 << GPIO_PORT_SHIFT) +#define GPIO_PORTB (1 << GPIO_PORT_SHIFT) +#define GPIO_PORTC (2 << GPIO_PORT_SHIFT) +#define GPIO_PORTD (3 << GPIO_PORT_SHIFT) +#define GPIO_PORTE (4 << GPIO_PORT_SHIFT) +#define GPIO_PORTF (5 << GPIO_PORT_SHIFT) + +#define GPIO_OUT (1 << 8) +#define GPIO_IN (0 << 8) +#define GPIO_PUEN (1 << 9) + +#define GPIO_PF (1 << 10) +#define GPIO_AF (1 << 11) + +#define GPIO_OCR_SHIFT 12 +#define GPIO_OCR_MASK (3 << GPIO_OCR_SHIFT) +#define GPIO_AIN (0 << GPIO_OCR_SHIFT) +#define GPIO_BIN (1 << GPIO_OCR_SHIFT) +#define GPIO_CIN (2 << GPIO_OCR_SHIFT) +#define GPIO_GPIO (3 << GPIO_OCR_SHIFT) + +#define GPIO_AOUT_SHIFT 14 +#define GPIO_AOUT_MASK (3 << GPIO_AOUT_SHIFT) +#define GPIO_AOUT (0 << GPIO_AOUT_SHIFT) +#define GPIO_AOUT_ISR (1 << GPIO_AOUT_SHIFT) +#define GPIO_AOUT_0 (2 << GPIO_AOUT_SHIFT) +#define GPIO_AOUT_1 (3 << GPIO_AOUT_SHIFT) + +#define GPIO_BOUT_SHIFT 16 +#define GPIO_BOUT_MASK (3 << GPIO_BOUT_SHIFT) +#define GPIO_BOUT (0 << GPIO_BOUT_SHIFT) +#define GPIO_BOUT_ISR (1 << GPIO_BOUT_SHIFT) +#define GPIO_BOUT_0 (2 << GPIO_BOUT_SHIFT) +#define GPIO_BOUT_1 (3 << GPIO_BOUT_SHIFT) + +/* decode irq number to use with IMR(x), ISR(x) and friends */ +#define IRQ_TO_REG(irq) ((irq - MXC_INTERNAL_IRQS) >> 5) + +#define IRQ_GPIOA(x) (MXC_GPIO_IRQ_START + x) +#define IRQ_GPIOB(x) (IRQ_GPIOA(32) + x) +#define IRQ_GPIOC(x) (IRQ_GPIOB(32) + x) +#define IRQ_GPIOD(x) (IRQ_GPIOC(32) + x) +#define IRQ_GPIOE(x) (IRQ_GPIOD(32) + x) +#define IRQ_GPIOF(x) (IRQ_GPIOE(32) + x) + +extern int mxc_gpio_mode(int gpio_mode); +extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count, + const char *label); +extern void mxc_gpio_release_multiple_pins(const int *pin_list, int count); + +extern int __init imx_iomuxv1_init(void __iomem *base, int numports); + +#endif /* __MACH_IOMUX_V1_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/iomux-v3.h b/arch/arm/plat-mxc/include/mach/iomux-v3.h new file mode 100644 index 00000000..55350c5b --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/iomux-v3.h @@ -0,0 +1,193 @@ +/* + * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH, + * <armlinux@phytec.de> + * + * Copyright (C) 2012 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#ifndef __MACH_IOMUX_V3_H__ +#define __MACH_IOMUX_V3_H__ + +/* + * build IOMUX_PAD structure + * + * This iomux scheme is based around pads, which are the physical balls + * on the processor. + * + * - Each pad has a pad control register (IOMUXC_SW_PAD_CTRL_x) which controls + * things like driving strength and pullup/pulldown. + * - Each pad can have but not necessarily does have an output routing register + * (IOMUXC_SW_MUX_CTL_PAD_x). + * - Each pad can have but not necessarily does have an input routing register + * (IOMUXC_x_SELECT_INPUT) + * + * The three register sets do not have a fixed offset to each other, + * hence we order this table by pad control registers (which all pads + * have) and put the optional i/o routing registers into additional + * fields. + * + * The naming convention for the pad modes is MX35_PAD_<padname>__<padmode> + * If <padname> or <padmode> refers to a GPIO, it is named + * GPIO_<unit>_<num> + * + * IOMUX/PAD Bit field definitions + * + * MUX_CTRL_OFS: 0..11 (12) + * PAD_CTRL_OFS: 12..23 (12) + * SEL_INPUT_OFS: 24..35 (12) + * MUX_MODE + SION: 36..40 (5) + * PAD_CTRL + NO_PAD_CTRL: 41..58 (18) + * SEL_INP: 59..62 (4) + * reserved: 63 (1) +*/ + +typedef u64 iomux_v3_cfg_t; + +#define MUX_CTRL_OFS_SHIFT 0 +#define MUX_CTRL_OFS_MASK ((iomux_v3_cfg_t)0xfff << MUX_CTRL_OFS_SHIFT) +#define MUX_PAD_CTRL_OFS_SHIFT 12 +#define MUX_PAD_CTRL_OFS_MASK ((iomux_v3_cfg_t)0xfff << MUX_PAD_CTRL_OFS_SHIFT) +#define MUX_SEL_INPUT_OFS_SHIFT 24 +#define MUX_SEL_INPUT_OFS_MASK ((iomux_v3_cfg_t)0xfff << MUX_SEL_INPUT_OFS_SHIFT) + +#define MUX_MODE_SHIFT 36 +#define MUX_MODE_MASK ((iomux_v3_cfg_t)0x1f << MUX_MODE_SHIFT) +#define MUX_PAD_CTRL_SHIFT 41 +//#define MUX_PAD_CTRL_MASK ((iomux_v3_cfg_t)0x3ffff << MUX_PAD_CTRL_SHIFT) +#define MUX_PAD_CTRL_MASK ((iomux_v3_cfg_t)0x43ffff << MUX_PAD_CTRL_SHIFT) +#define MUX_SEL_INPUT_SHIFT 59 +#define MUX_SEL_INPUT_MASK ((iomux_v3_cfg_t)0xf << MUX_SEL_INPUT_SHIFT) + +#define MUX_PAD_CTRL(x) ((iomux_v3_cfg_t)(x) << MUX_PAD_CTRL_SHIFT) + +#define IOMUX_PAD(_pad_ctrl_ofs, _mux_ctrl_ofs, _mux_mode, _sel_input_ofs, \ + _sel_input, _pad_ctrl) \ + (((iomux_v3_cfg_t)(_mux_ctrl_ofs) << MUX_CTRL_OFS_SHIFT) | \ + ((iomux_v3_cfg_t)(_mux_mode) << MUX_MODE_SHIFT) | \ + ((iomux_v3_cfg_t)(_pad_ctrl_ofs) << MUX_PAD_CTRL_OFS_SHIFT) | \ + ((iomux_v3_cfg_t)(_pad_ctrl) << MUX_PAD_CTRL_SHIFT) | \ + ((iomux_v3_cfg_t)(_sel_input_ofs) << MUX_SEL_INPUT_OFS_SHIFT) | \ + ((iomux_v3_cfg_t)(_sel_input) << MUX_SEL_INPUT_SHIFT)) + +#define NEW_PAD_CTRL(cfg, pad) (((cfg) & ~MUX_PAD_CTRL_MASK) | \ + MUX_PAD_CTRL(pad)) +/* + * Use to set PAD control + */ +#define NO_PAD_CTRL (1 << 17) +#define NO_PAD_I 0 +#define NO_MUX_I 0 +#ifdef CONFIG_SOC_IMX6Q +#define PAD_CTL_LVE (1 << 22) +#define PAD_CTL_LVE_MASK (1 << 22) +#define PAD_CTL_DDR_SEL_LPDDR2 (2 << 18) +#define PAD_CTL_DDR_SEL_DDR3 (3 << 18) +#define PAD_CTL_DDR_SEL_MASK (3 << 18) +#define PAD_CTL_HYS (1 << 16) + +#define PAD_CTL_PUS_100K_DOWN (0 << 14) +#define PAD_CTL_PUS_47K_UP (1 << 14) +#define PAD_CTL_PUS_100K_UP (2 << 14) +#define PAD_CTL_PUS_22K_UP (3 << 14) + +#define PAD_CTL_PUE (1 << 13) +#define PAD_CTL_PKE (1 << 12) +#define PAD_CTL_ODE (1 << 11) + +#define PAD_CTL_SPEED_LOW (1 << 6) +#define PAD_CTL_SPEED_MED (2 << 6) +#define PAD_CTL_SPEED_HIGH (3 << 6) + +#define PAD_CTL_DSE_DISABLE (0 << 3) +#define PAD_CTL_DSE_240ohm (1 << 3) +#define PAD_CTL_DSE_120ohm (2 << 3) +#define PAD_CTL_DSE_80ohm (3 << 3) +#define PAD_CTL_DSE_60ohm (4 << 3) +#define PAD_CTL_DSE_48ohm (5 << 3) +#define PAD_CTL_DSE_40ohm (6 << 3) +#define PAD_CTL_DSE_34ohm (7 << 3) + +#define PAD_CTL_SRE_FAST (1 << 0) +#define PAD_CTL_SRE_SLOW (0 << 0) + +#else +#define PAD_CTL_DVS (1 << 13) +#define PAD_CTL_HYS (1 << 8) + +#define PAD_CTL_PKE (1 << 7) +#define PAD_CTL_PUE (1 << 6 | PAD_CTL_PKE) +#define PAD_CTL_PUS_100K_DOWN (0 << 4 | PAD_CTL_PUE) +#define PAD_CTL_PUS_47K_UP (1 << 4 | PAD_CTL_PUE) +#define PAD_CTL_PUS_100K_UP (2 << 4 | PAD_CTL_PUE) +#define PAD_CTL_PUS_22K_UP (3 << 4 | PAD_CTL_PUE) + +#define PAD_CTL_ODE (1 << 3) + +#define PAD_CTL_DSE_LOW (0 << 1) +#define PAD_CTL_DSE_MED (1 << 1) +#define PAD_CTL_DSE_HIGH (2 << 1) +#define PAD_CTL_DSE_MAX (3 << 1) + +#define PAD_CTL_SRE_FAST (1 << 0) +#define PAD_CTL_SRE_SLOW (0 << 0) +#endif +#define IOMUX_CONFIG_SION (0x1 << 4) + +#define MX51_NUM_GPIO_PORT 4 + +#define GPIO_PIN_MASK 0x1f + +#define GPIO_PORT_SHIFT 5 +#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT) + +#define GPIO_PORTA (0 << GPIO_PORT_SHIFT) +#define GPIO_PORTB (1 << GPIO_PORT_SHIFT) +#define GPIO_PORTC (2 << GPIO_PORT_SHIFT) +#define GPIO_PORTD (3 << GPIO_PORT_SHIFT) +#define GPIO_PORTE (4 << GPIO_PORT_SHIFT) +#define GPIO_PORTF (5 << GPIO_PORT_SHIFT) + +/* + * read/write a single pad in the iomuxer + */ +int mxc_iomux_v3_get_pad(iomux_v3_cfg_t *pad); +int mxc_iomux_v3_setup_pad(iomux_v3_cfg_t pad); + +/* + * read/write mutliple pads + * convenient way to call the above function with tables + */ + int mxc_iomux_v3_get_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count); +int mxc_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count); + +/* + * Initialise the iomux controller + */ +void mxc_iomux_v3_init(void __iomem *iomux_v3_base); + +/* + * Set bits for general purpose registers + */ +void mxc_iomux_set_gpr_register(int group, int start_bit, int num_bits, int value); + +/* + * Set special bits for iomux registers, such as LVE bit, DDR_SEL bits + */ +void mxc_iomux_set_specialbits_register(u32 pad_addr, u32 value, u32 mask); + +#endif /* __MACH_IOMUX_V3_H__*/ + diff --git a/arch/arm/plat-mxc/include/mach/iomux.h b/arch/arm/plat-mxc/include/mach/iomux.h new file mode 100644 index 00000000..3d226d7e --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/iomux.h @@ -0,0 +1,26 @@ +/* + * Copyright (C) 2010 Uwe Kleine-Koenig, Pengutronix + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + */ +#ifndef __MACH_IOMUX_H__ +#define __MACH_IOMUX_H__ + +/* This file will go away, please include mach/iomux-mx... directly */ + +#ifdef CONFIG_ARCH_MX1 +#include <mach/iomux-mx1.h> +#endif +#ifdef CONFIG_ARCH_MX2 +#include <mach/iomux-mx2x.h> +#ifdef CONFIG_MACH_MX21 +#include <mach/iomux-mx21.h> +#endif +#ifdef CONFIG_MACH_MX27 +#include <mach/iomux-mx27.h> +#endif +#endif + +#endif /* __MACH_IOMUX_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/ipu-v3.h b/arch/arm/plat-mxc/include/mach/ipu-v3.h new file mode 100755 index 00000000..e2265d40 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/ipu-v3.h @@ -0,0 +1,765 @@ +/* + * Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de> + * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#ifndef __MACH_IPU_V3_H_ +#define __MACH_IPU_V3_H_ + +#include <linux/ipu.h> + +/* IPU Driver channels definitions. */ +/* Note these are different from IDMA channels */ +#define IPU_MAX_CH 32 +#define _MAKE_CHAN(num, v_in, g_in, a_in, out) \ + ((num << 24) | (v_in << 18) | (g_in << 12) | (a_in << 6) | out) +#define _MAKE_ALT_CHAN(ch) (ch | (IPU_MAX_CH << 24)) +#define IPU_CHAN_ID(ch) (ch >> 24) +#define IPU_CHAN_ALT(ch) (ch & 0x02000000) +#define IPU_CHAN_ALPHA_IN_DMA(ch) ((uint32_t) (ch >> 6) & 0x3F) +#define IPU_CHAN_GRAPH_IN_DMA(ch) ((uint32_t) (ch >> 12) & 0x3F) +#define IPU_CHAN_VIDEO_IN_DMA(ch) ((uint32_t) (ch >> 18) & 0x3F) +#define IPU_CHAN_OUT_DMA(ch) ((uint32_t) (ch & 0x3F)) +#define NO_DMA 0x3F +#define ALT 1 +/*! + * Enumeration of IPU logical channels. An IPU logical channel is defined as a + * combination of an input (memory to IPU), output (IPU to memory), and/or + * secondary input IDMA channels and in some cases an Image Converter task. + * Some channels consist of only an input or output. + */ +typedef enum { + CHAN_NONE = -1, + MEM_ROT_ENC_MEM = _MAKE_CHAN(1, 45, NO_DMA, NO_DMA, 48), + MEM_ROT_VF_MEM = _MAKE_CHAN(2, 46, NO_DMA, NO_DMA, 49), + MEM_ROT_PP_MEM = _MAKE_CHAN(3, 47, NO_DMA, NO_DMA, 50), + + MEM_PRP_ENC_MEM = _MAKE_CHAN(4, 12, 14, 17, 20), + MEM_PRP_VF_MEM = _MAKE_CHAN(5, 12, 14, 17, 21), + MEM_PP_MEM = _MAKE_CHAN(6, 11, 15, 18, 22), + + MEM_DC_SYNC = _MAKE_CHAN(7, 28, NO_DMA, NO_DMA, NO_DMA), + MEM_DC_ASYNC = _MAKE_CHAN(8, 41, NO_DMA, NO_DMA, NO_DMA), + MEM_BG_SYNC = _MAKE_CHAN(9, 23, NO_DMA, 51, NO_DMA), + MEM_FG_SYNC = _MAKE_CHAN(10, 27, NO_DMA, 31, NO_DMA), + + MEM_BG_ASYNC0 = _MAKE_CHAN(11, 24, NO_DMA, 52, NO_DMA), + MEM_FG_ASYNC0 = _MAKE_CHAN(12, 29, NO_DMA, 33, NO_DMA), + MEM_BG_ASYNC1 = _MAKE_ALT_CHAN(MEM_BG_ASYNC0), + MEM_FG_ASYNC1 = _MAKE_ALT_CHAN(MEM_FG_ASYNC0), + + DIRECT_ASYNC0 = _MAKE_CHAN(13, NO_DMA, NO_DMA, NO_DMA, NO_DMA), + DIRECT_ASYNC1 = _MAKE_CHAN(14, NO_DMA, NO_DMA, NO_DMA, NO_DMA), + + CSI_MEM0 = _MAKE_CHAN(15, NO_DMA, NO_DMA, NO_DMA, 0), + CSI_MEM1 = _MAKE_CHAN(16, NO_DMA, NO_DMA, NO_DMA, 1), + CSI_MEM2 = _MAKE_CHAN(17, NO_DMA, NO_DMA, NO_DMA, 2), + CSI_MEM3 = _MAKE_CHAN(18, NO_DMA, NO_DMA, NO_DMA, 3), + + CSI_MEM = CSI_MEM0, + + CSI_PRP_ENC_MEM = _MAKE_CHAN(19, NO_DMA, NO_DMA, NO_DMA, 20), + CSI_PRP_VF_MEM = _MAKE_CHAN(20, NO_DMA, NO_DMA, NO_DMA, 21), + + /* for vdi mem->vdi->ic->mem , add graphics plane and alpha*/ + MEM_VDI_PRP_VF_MEM_P = _MAKE_CHAN(21, 8, 14, 17, 21), + MEM_VDI_PRP_VF_MEM = _MAKE_CHAN(22, 9, 14, 17, 21), + MEM_VDI_PRP_VF_MEM_N = _MAKE_CHAN(23, 10, 14, 17, 21), + + /* for vdi mem->vdi->mem */ + MEM_VDI_MEM_P = _MAKE_CHAN(24, 8, NO_DMA, NO_DMA, 5), + MEM_VDI_MEM = _MAKE_CHAN(25, 9, NO_DMA, NO_DMA, 5), + MEM_VDI_MEM_N = _MAKE_CHAN(26, 10, NO_DMA, NO_DMA, 5), + + /* fake channel for vdoa to link with IPU */ + MEM_VDOA_MEM = _MAKE_CHAN(27, NO_DMA, NO_DMA, NO_DMA, NO_DMA), + + MEM_PP_ADC = CHAN_NONE, + ADC_SYS2 = CHAN_NONE, + +} ipu_channel_t; + +/*! + * Enumeration of types of buffers for a logical channel. + */ +typedef enum { + IPU_OUTPUT_BUFFER = 0, /*!< Buffer for output from IPU */ + IPU_ALPHA_IN_BUFFER = 1, /*!< Buffer for input to IPU */ + IPU_GRAPH_IN_BUFFER = 2, /*!< Buffer for input to IPU */ + IPU_VIDEO_IN_BUFFER = 3, /*!< Buffer for input to IPU */ + IPU_INPUT_BUFFER = IPU_VIDEO_IN_BUFFER, + IPU_SEC_INPUT_BUFFER = IPU_GRAPH_IN_BUFFER, +} ipu_buffer_t; + +#define IPU_PANEL_SERIAL 1 +#define IPU_PANEL_PARALLEL 2 + +/*! + * Enumeration of ADC channel operation mode. + */ +typedef enum { + Disable, + WriteTemplateNonSeq, + ReadTemplateNonSeq, + WriteTemplateUnCon, + ReadTemplateUnCon, + WriteDataWithRS, + WriteDataWoRS, + WriteCmd +} mcu_mode_t; + +/*! + * Enumeration of ADC channel addressing mode. + */ +typedef enum { + FullWoBE, + FullWithBE, + XY +} display_addressing_t; + +/*! + * Union of initialization parameters for a logical channel. + */ +typedef union { + struct { + uint32_t csi; + uint32_t mipi_id; + uint32_t mipi_vc; + bool mipi_en; + bool interlaced; + } csi_mem; + struct { + uint32_t in_width; + uint32_t in_height; + uint32_t in_pixel_fmt; + uint32_t out_width; + uint32_t out_height; + uint32_t out_pixel_fmt; + uint32_t outh_resize_ratio; + uint32_t outv_resize_ratio; + uint32_t csi; + uint32_t mipi_id; + uint32_t mipi_vc; + bool mipi_en; + } csi_prp_enc_mem; + struct { + uint32_t in_width; + uint32_t in_height; + uint32_t in_pixel_fmt; + uint32_t out_width; + uint32_t out_height; + uint32_t out_pixel_fmt; + uint32_t outh_resize_ratio; + uint32_t outv_resize_ratio; + } mem_prp_enc_mem; + struct { + uint32_t in_width; + uint32_t in_height; + uint32_t in_pixel_fmt; + uint32_t out_width; + uint32_t out_height; + uint32_t out_pixel_fmt; + } mem_rot_enc_mem; + struct { + uint32_t in_width; + uint32_t in_height; + uint32_t in_pixel_fmt; + uint32_t out_width; + uint32_t out_height; + uint32_t out_pixel_fmt; + uint32_t outh_resize_ratio; + uint32_t outv_resize_ratio; + bool graphics_combine_en; + bool global_alpha_en; + bool key_color_en; + uint32_t in_g_pixel_fmt; + uint8_t alpha; + uint32_t key_color; + bool alpha_chan_en; + ipu_motion_sel motion_sel; + enum v4l2_field field_fmt; + uint32_t csi; + uint32_t mipi_id; + uint32_t mipi_vc; + bool mipi_en; + } csi_prp_vf_mem; + struct { + uint32_t in_width; + uint32_t in_height; + uint32_t in_pixel_fmt; + uint32_t out_width; + uint32_t out_height; + uint32_t out_pixel_fmt; + bool graphics_combine_en; + bool global_alpha_en; + bool key_color_en; + display_port_t disp; + uint32_t out_left; + uint32_t out_top; + } csi_prp_vf_adc; + struct { + uint32_t in_width; + uint32_t in_height; + uint32_t in_pixel_fmt; + uint32_t out_width; + uint32_t out_height; + uint32_t out_pixel_fmt; + uint32_t outh_resize_ratio; + uint32_t outv_resize_ratio; + bool graphics_combine_en; + bool global_alpha_en; + bool key_color_en; + uint32_t in_g_pixel_fmt; + uint8_t alpha; + uint32_t key_color; + bool alpha_chan_en; + ipu_motion_sel motion_sel; + enum v4l2_field field_fmt; + } mem_prp_vf_mem; + struct { + uint32_t temp; + } mem_prp_vf_adc; + struct { + uint32_t temp; + } mem_rot_vf_mem; + struct { + uint32_t in_width; + uint32_t in_height; + uint32_t in_pixel_fmt; + uint32_t out_width; + uint32_t out_height; + uint32_t out_pixel_fmt; + uint32_t outh_resize_ratio; + uint32_t outv_resize_ratio; + bool graphics_combine_en; + bool global_alpha_en; + bool key_color_en; + uint32_t in_g_pixel_fmt; + uint8_t alpha; + uint32_t key_color; + bool alpha_chan_en; + } mem_pp_mem; + struct { + uint32_t temp; + } mem_rot_mem; + struct { + uint32_t in_width; + uint32_t in_height; + uint32_t in_pixel_fmt; + uint32_t out_width; + uint32_t out_height; + uint32_t out_pixel_fmt; + bool graphics_combine_en; + bool global_alpha_en; + bool key_color_en; + display_port_t disp; + uint32_t out_left; + uint32_t out_top; + } mem_pp_adc; + struct { + uint32_t di; + bool interlaced; + uint32_t in_pixel_fmt; + uint32_t out_pixel_fmt; + } mem_dc_sync; + struct { + uint32_t temp; + } mem_sdc_fg; + struct { + uint32_t di; + bool interlaced; + uint32_t in_pixel_fmt; + uint32_t out_pixel_fmt; + bool alpha_chan_en; + } mem_dp_bg_sync; + struct { + uint32_t temp; + } mem_sdc_bg; + struct { + uint32_t di; + bool interlaced; + uint32_t in_pixel_fmt; + uint32_t out_pixel_fmt; + bool alpha_chan_en; + } mem_dp_fg_sync; + struct { + uint32_t di; + } direct_async; + struct { + display_port_t disp; + mcu_mode_t ch_mode; + uint32_t out_left; + uint32_t out_top; + } adc_sys1; + struct { + display_port_t disp; + mcu_mode_t ch_mode; + uint32_t out_left; + uint32_t out_top; + } adc_sys2; +} ipu_channel_params_t; + +/* + * IPU_IRQF_ONESHOT - Interrupt is not reenabled after the irq handler finished. + */ +#define IPU_IRQF_NONE 0x00000000 +#define IPU_IRQF_ONESHOT 0x00000001 + +/*! + * Enumeration of IPU interrupt sources. + */ +enum ipu_irq_line { + IPU_IRQ_CSI0_OUT_EOF = 0, + IPU_IRQ_CSI1_OUT_EOF = 1, + IPU_IRQ_CSI2_OUT_EOF = 2, + IPU_IRQ_CSI3_OUT_EOF = 3, + IPU_IRQ_VDIC_OUT_EOF = 5, + IPU_IRQ_VDI_P_IN_EOF = 8, + IPU_IRQ_VDI_C_IN_EOF = 9, + IPU_IRQ_VDI_N_IN_EOF = 10, + IPU_IRQ_PP_IN_EOF = 11, + IPU_IRQ_PRP_IN_EOF = 12, + IPU_IRQ_PRP_GRAPH_IN_EOF = 14, + IPU_IRQ_PP_GRAPH_IN_EOF = 15, + IPU_IRQ_PRP_ALPHA_IN_EOF = 17, + IPU_IRQ_PP_ALPHA_IN_EOF = 18, + IPU_IRQ_PRP_ENC_OUT_EOF = 20, + IPU_IRQ_PRP_VF_OUT_EOF = 21, + IPU_IRQ_PP_OUT_EOF = 22, + IPU_IRQ_BG_SYNC_EOF = 23, + IPU_IRQ_BG_ASYNC_EOF = 24, + IPU_IRQ_FG_SYNC_EOF = 27, + IPU_IRQ_DC_SYNC_EOF = 28, + IPU_IRQ_FG_ASYNC_EOF = 29, + IPU_IRQ_FG_ALPHA_SYNC_EOF = 31, + + IPU_IRQ_FG_ALPHA_ASYNC_EOF = 33, + IPU_IRQ_DC_READ_EOF = 40, + IPU_IRQ_DC_ASYNC_EOF = 41, + IPU_IRQ_DC_CMD1_EOF = 42, + IPU_IRQ_DC_CMD2_EOF = 43, + IPU_IRQ_DC_MASK_EOF = 44, + IPU_IRQ_PRP_ENC_ROT_IN_EOF = 45, + IPU_IRQ_PRP_VF_ROT_IN_EOF = 46, + IPU_IRQ_PP_ROT_IN_EOF = 47, + IPU_IRQ_PRP_ENC_ROT_OUT_EOF = 48, + IPU_IRQ_PRP_VF_ROT_OUT_EOF = 49, + IPU_IRQ_PP_ROT_OUT_EOF = 50, + IPU_IRQ_BG_ALPHA_SYNC_EOF = 51, + IPU_IRQ_BG_ALPHA_ASYNC_EOF = 52, + + IPU_IRQ_BG_SYNC_NFACK = 64 + 23, + IPU_IRQ_FG_SYNC_NFACK = 64 + 27, + IPU_IRQ_DC_SYNC_NFACK = 64 + 28, + + IPU_IRQ_DP_SF_START = 448 + 2, + IPU_IRQ_DP_SF_END = 448 + 3, + IPU_IRQ_BG_SF_END = IPU_IRQ_DP_SF_END, + IPU_IRQ_DC_FC_0 = 448 + 8, + IPU_IRQ_DC_FC_1 = 448 + 9, + IPU_IRQ_DC_FC_2 = 448 + 10, + IPU_IRQ_DC_FC_3 = 448 + 11, + IPU_IRQ_DC_FC_4 = 448 + 12, + IPU_IRQ_DC_FC_6 = 448 + 13, + IPU_IRQ_VSYNC_PRE_0 = 448 + 14, + IPU_IRQ_VSYNC_PRE_1 = 448 + 15, + + IPU_IRQ_COUNT +}; + +/*! + * Bitfield of Display Interface signal polarities. + */ +typedef struct { + unsigned datamask_en:1; + unsigned int_clk:1; + unsigned interlaced:1; + unsigned odd_field_first:1; + unsigned clksel_en:1; + unsigned clkidle_en:1; + unsigned data_pol:1; /* true = inverted */ + unsigned clk_pol:1; /* true = rising edge */ + unsigned enable_pol:1; + unsigned Hsync_pol:1; /* true = active high */ + unsigned Vsync_pol:1; +} ipu_di_signal_cfg_t; + +/*! + * Bitfield of CSI signal polarities and modes. + */ + +typedef struct { + unsigned data_width:4; + unsigned clk_mode:3; + unsigned ext_vsync:1; + unsigned Vsync_pol:1; + unsigned Hsync_pol:1; + unsigned pixclk_pol:1; + unsigned data_pol:1; + unsigned sens_clksrc:1; + unsigned pack_tight:1; + unsigned force_eof:1; + unsigned data_en_pol:1; + unsigned data_fmt; + unsigned csi; + unsigned mclk; +} ipu_csi_signal_cfg_t; + +/*! + * Enumeration of CSI data bus widths. + */ +enum { + IPU_CSI_DATA_WIDTH_4 = 0, + IPU_CSI_DATA_WIDTH_8 = 1, + IPU_CSI_DATA_WIDTH_10 = 3, + IPU_CSI_DATA_WIDTH_16 = 9, +}; + +/*! + * Enumeration of CSI clock modes. + */ +enum { + IPU_CSI_CLK_MODE_GATED_CLK, + IPU_CSI_CLK_MODE_NONGATED_CLK, + IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE, + IPU_CSI_CLK_MODE_CCIR656_INTERLACED, + IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_DDR, + IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_SDR, + IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_DDR, + IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_SDR, +}; + +enum { + IPU_CSI_MIPI_DI0, + IPU_CSI_MIPI_DI1, + IPU_CSI_MIPI_DI2, + IPU_CSI_MIPI_DI3, +}; + +typedef enum { + RGB, + YCbCr, + YUV +} ipu_color_space_t; + +/*! + * Enumeration of ADC vertical sync mode. + */ +typedef enum { + VsyncNone, + VsyncInternal, + VsyncCSI, + VsyncExternal +} vsync_t; + +typedef enum { + DAT, + CMD +} cmddata_t; + +/*! + * Enumeration of ADC display update mode. + */ +typedef enum { + IPU_ADC_REFRESH_NONE, + IPU_ADC_AUTO_REFRESH, + IPU_ADC_AUTO_REFRESH_SNOOP, + IPU_ADC_SNOOPING, +} ipu_adc_update_mode_t; + +/*! + * Enumeration of ADC display interface types (serial or parallel). + */ +enum { + IPU_ADC_IFC_MODE_SYS80_TYPE1, + IPU_ADC_IFC_MODE_SYS80_TYPE2, + IPU_ADC_IFC_MODE_SYS68K_TYPE1, + IPU_ADC_IFC_MODE_SYS68K_TYPE2, + IPU_ADC_IFC_MODE_3WIRE_SERIAL, + IPU_ADC_IFC_MODE_4WIRE_SERIAL, + IPU_ADC_IFC_MODE_5WIRE_SERIAL_CLK, + IPU_ADC_IFC_MODE_5WIRE_SERIAL_CS, +}; + +enum { + IPU_ADC_IFC_WIDTH_8, + IPU_ADC_IFC_WIDTH_16, +}; + +/*! + * Enumeration of ADC display interface burst mode. + */ +enum { + IPU_ADC_BURST_WCS, + IPU_ADC_BURST_WBLCK, + IPU_ADC_BURST_NONE, + IPU_ADC_BURST_SERIAL, +}; + +/*! + * Enumeration of ADC display interface RW signal timing modes. + */ +enum { + IPU_ADC_SER_NO_RW, + IPU_ADC_SER_RW_BEFORE_RS, + IPU_ADC_SER_RW_AFTER_RS, +}; + +/*! + * Bitfield of ADC signal polarities and modes. + */ +typedef struct { + unsigned data_pol:1; + unsigned clk_pol:1; + unsigned cs_pol:1; + unsigned rs_pol:1; + unsigned addr_pol:1; + unsigned read_pol:1; + unsigned write_pol:1; + unsigned Vsync_pol:1; + unsigned burst_pol:1; + unsigned burst_mode:2; + unsigned ifc_mode:3; + unsigned ifc_width:5; + unsigned ser_preamble_len:4; + unsigned ser_preamble:8; + unsigned ser_rw_mode:2; +} ipu_adc_sig_cfg_t; + +/*! + * Enumeration of ADC template commands. + */ +enum { + RD_DATA, + RD_ACK, + RD_WAIT, + WR_XADDR, + WR_YADDR, + WR_ADDR, + WR_CMND, + WR_DATA, +}; + +/*! + * Enumeration of ADC template command flow control. + */ +enum { + SINGLE_STEP, + PAUSE, + STOP, +}; + + +/*Define template constants*/ +#define ATM_ADDR_RANGE 0x20 /*offset address of DISP */ +#define TEMPLATE_BUF_SIZE 0x20 /*size of template */ + +/*! + * Define to create ADC template command entry. + */ +#define ipu_adc_template_gen(oc, rs, fc, dat) (((rs) << 29) | ((fc) << 27) | \ + ((oc) << 24) | (dat)) + +typedef struct { + u32 reg; + u32 value; +} ipu_lpmc_reg_t; + +#define IPU_LPMC_REG_READ 0x80000000L + +#define CSI_MCLK_VF 1 +#define CSI_MCLK_ENC 2 +#define CSI_MCLK_RAW 4 +#define CSI_MCLK_I2C 8 + +struct ipu_soc; +/* Common IPU API */ +struct ipu_soc *ipu_get_soc(int id); +int32_t ipu_init_channel(struct ipu_soc *ipu, ipu_channel_t channel, ipu_channel_params_t *params); +void ipu_uninit_channel(struct ipu_soc *ipu, ipu_channel_t channel); +void ipu_disable_hsp_clk(struct ipu_soc *ipu); + +static inline bool ipu_can_rotate_in_place(ipu_rotate_mode_t rot) +{ +#ifdef CONFIG_MXC_IPU_V3D + return (rot < IPU_ROTATE_HORIZ_FLIP); +#else + return (rot < IPU_ROTATE_90_RIGHT); +#endif +} + +int32_t ipu_init_channel_buffer(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type, + uint32_t pixel_fmt, + uint16_t width, uint16_t height, + uint32_t stride, + ipu_rotate_mode_t rot_mode, + dma_addr_t phyaddr_0, dma_addr_t phyaddr_1, + dma_addr_t phyaddr_2, + uint32_t u_offset, uint32_t v_offset); + +int32_t ipu_update_channel_buffer(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type, + uint32_t bufNum, dma_addr_t phyaddr); + +int32_t ipu_update_channel_offset(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type, + uint32_t pixel_fmt, + uint16_t width, uint16_t height, + uint32_t stride, + uint32_t u, uint32_t v, + uint32_t vertical_offset, uint32_t horizontal_offset); + +int32_t ipu_select_buffer(struct ipu_soc *ipu, ipu_channel_t channel, + ipu_buffer_t type, uint32_t bufNum); +int32_t ipu_select_multi_vdi_buffer(struct ipu_soc *ipu, uint32_t bufNum); + +int32_t ipu_link_channels(struct ipu_soc *ipu, ipu_channel_t src_ch, ipu_channel_t dest_ch); +int32_t ipu_unlink_channels(struct ipu_soc *ipu, ipu_channel_t src_ch, ipu_channel_t dest_ch); + +int32_t ipu_is_channel_busy(struct ipu_soc *ipu, ipu_channel_t channel); +int32_t ipu_check_buffer_ready(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type, + uint32_t bufNum); +void ipu_clear_buffer_ready(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type, + uint32_t bufNum); +uint32_t ipu_get_cur_buffer_idx(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type); +int32_t ipu_enable_channel(struct ipu_soc *ipu, ipu_channel_t channel); +int32_t ipu_disable_channel(struct ipu_soc *ipu, ipu_channel_t channel, bool wait_for_stop); +int32_t ipu_swap_channel(struct ipu_soc *ipu, ipu_channel_t from_ch, ipu_channel_t to_ch); +uint32_t ipu_channel_status(struct ipu_soc *ipu, ipu_channel_t channel); + +int32_t ipu_enable_csi(struct ipu_soc *ipu, uint32_t csi); +int32_t ipu_disable_csi(struct ipu_soc *ipu, uint32_t csi); + +int ipu_lowpwr_display_enable(void); +int ipu_lowpwr_display_disable(void); + +int ipu_enable_irq(struct ipu_soc *ipu, uint32_t irq); +void ipu_disable_irq(struct ipu_soc *ipu, uint32_t irq); +void ipu_clear_irq(struct ipu_soc *ipu, uint32_t irq); +int ipu_request_irq(struct ipu_soc *ipu, uint32_t irq, + irqreturn_t(*handler) (int, void *), + uint32_t irq_flags, const char *devname, void *dev_id); +void ipu_free_irq(struct ipu_soc *ipu, uint32_t irq, void *dev_id); +bool ipu_get_irq_status(struct ipu_soc *ipu, uint32_t irq); +void ipu_set_csc_coefficients(struct ipu_soc *ipu, ipu_channel_t channel, int32_t param[][3]); +int32_t ipu_set_channel_bandmode(struct ipu_soc *ipu, ipu_channel_t channel, + ipu_buffer_t type, uint32_t band_height); + +/* two stripe calculations */ +struct stripe_param{ + unsigned int input_width; /* width of the input stripe */ + unsigned int output_width; /* width of the output stripe */ + unsigned int input_column; /* the first column on the input stripe */ + unsigned int output_column; /* the first column on the output stripe */ + unsigned int idr; + /* inverse downisizing ratio parameter; expressed as a power of 2 */ + unsigned int irr; + /* inverse resizing ratio parameter; expressed as a multiple of 2^-13 */ +}; +int ipu_calc_stripes_sizes(const unsigned int input_frame_width, + unsigned int output_frame_width, + const unsigned int maximal_stripe_width, + const unsigned long long cirr, + const unsigned int equal_stripes, + u32 input_pixelformat, + u32 output_pixelformat, + struct stripe_param *left, + struct stripe_param *right); + +/* SDC API */ +int32_t ipu_init_sync_panel(struct ipu_soc *ipu, int disp, + uint32_t pixel_clk, + uint16_t width, uint16_t height, + uint32_t pixel_fmt, + uint16_t h_start_width, uint16_t h_sync_width, + uint16_t h_end_width, uint16_t v_start_width, + uint16_t v_sync_width, uint16_t v_end_width, + uint32_t v_to_h_sync, ipu_di_signal_cfg_t sig); + +void ipu_uninit_sync_panel(struct ipu_soc *ipu, int disp); + +int32_t ipu_disp_set_window_pos(struct ipu_soc *ipu, ipu_channel_t channel, int16_t x_pos, + int16_t y_pos); +int32_t ipu_disp_get_window_pos(struct ipu_soc *ipu, ipu_channel_t channel, int16_t *x_pos, + int16_t *y_pos); +int32_t ipu_disp_set_global_alpha(struct ipu_soc *ipu, ipu_channel_t channel, bool enable, + uint8_t alpha); +int32_t ipu_disp_set_color_key(struct ipu_soc *ipu, ipu_channel_t channel, bool enable, + uint32_t colorKey); +int32_t ipu_disp_set_gamma_correction(struct ipu_soc *ipu, ipu_channel_t channel, bool enable, + int constk[], int slopek[]); + +int ipu_init_async_panel(struct ipu_soc *ipu, int disp, int type, uint32_t cycle_time, + uint32_t pixel_fmt, ipu_adc_sig_cfg_t sig); +void ipu_disp_direct_write(struct ipu_soc *ipu, ipu_channel_t channel, u32 value, u32 offset); +void ipu_reset_disp_panel(struct ipu_soc *ipu); + +/* CMOS Sensor Interface API */ +int32_t ipu_csi_init_interface(struct ipu_soc *ipu, uint16_t width, uint16_t height, + uint32_t pixel_fmt, ipu_csi_signal_cfg_t sig); + +int32_t ipu_csi_get_sensor_protocol(struct ipu_soc *ipu, uint32_t csi); + +int32_t ipu_csi_enable_mclk(struct ipu_soc *ipu, int src, bool flag, bool wait); + +static inline int32_t ipu_csi_enable_mclk_if(struct ipu_soc *ipu, int src, uint32_t csi, + bool flag, bool wait) +{ + return ipu_csi_enable_mclk(ipu, csi, flag, wait); +} + +int ipu_csi_read_mclk_flag(void); + +void ipu_csi_flash_strobe(bool flag); + +void ipu_csi_get_window_size(struct ipu_soc *ipu, uint32_t *width, uint32_t *height, uint32_t csi); + +void ipu_csi_set_window_size(struct ipu_soc *ipu, uint32_t width, uint32_t height, uint32_t csi); + +void ipu_csi_set_window_pos(struct ipu_soc *ipu, uint32_t left, uint32_t top, uint32_t csi); + +uint32_t bytes_per_pixel(uint32_t fmt); + +struct ipuv3_fb_platform_data { + char disp_dev[32]; + u32 interface_pix_fmt; + char *mode_str; + int default_bpp; + bool int_clk; + + /* reserved mem */ + resource_size_t res_base[2]; + resource_size_t res_size[2]; + + /* + * Late init to avoid display channel being + * re-initialized as we've probably setup the + * channel in bootloader. + */ + bool late_init; +}; + +struct imx_ipuv3_platform_data { + int rev; + int (*init) (int); + void (*pg) (int); + + char *csi_clk[2]; + + /* + * Bypass reset to avoid display channel being + * stopped by probe since it may starts to work + * in bootloader. + */ + bool bypass_reset; +}; + +#endif /* __MACH_IPU_V3_H_ */ diff --git a/arch/arm/plat-mxc/include/mach/ipu.h b/arch/arm/plat-mxc/include/mach/ipu.h new file mode 100644 index 00000000..a9221f1c --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/ipu.h @@ -0,0 +1,181 @@ +/* + * Copyright (C) 2008 + * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de> + * + * Copyright (C) 2005-2007 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _IPU_H_ +#define _IPU_H_ + +#include <linux/types.h> +#include <linux/dmaengine.h> + +/* IPU DMA Controller channel definitions. */ +enum ipu_channel { + IDMAC_IC_0 = 0, /* IC (encoding task) to memory */ + IDMAC_IC_1 = 1, /* IC (viewfinder task) to memory */ + IDMAC_ADC_0 = 1, + IDMAC_IC_2 = 2, + IDMAC_ADC_1 = 2, + IDMAC_IC_3 = 3, + IDMAC_IC_4 = 4, + IDMAC_IC_5 = 5, + IDMAC_IC_6 = 6, + IDMAC_IC_7 = 7, /* IC (sensor data) to memory */ + IDMAC_IC_8 = 8, + IDMAC_IC_9 = 9, + IDMAC_IC_10 = 10, + IDMAC_IC_11 = 11, + IDMAC_IC_12 = 12, + IDMAC_IC_13 = 13, + IDMAC_SDC_0 = 14, /* Background synchronous display data */ + IDMAC_SDC_1 = 15, /* Foreground data (overlay) */ + IDMAC_SDC_2 = 16, + IDMAC_SDC_3 = 17, + IDMAC_ADC_2 = 18, + IDMAC_ADC_3 = 19, + IDMAC_ADC_4 = 20, + IDMAC_ADC_5 = 21, + IDMAC_ADC_6 = 22, + IDMAC_ADC_7 = 23, + IDMAC_PF_0 = 24, + IDMAC_PF_1 = 25, + IDMAC_PF_2 = 26, + IDMAC_PF_3 = 27, + IDMAC_PF_4 = 28, + IDMAC_PF_5 = 29, + IDMAC_PF_6 = 30, + IDMAC_PF_7 = 31, +}; + +/* Order significant! */ +enum ipu_channel_status { + IPU_CHANNEL_FREE, + IPU_CHANNEL_INITIALIZED, + IPU_CHANNEL_READY, + IPU_CHANNEL_ENABLED, +}; + +#define IPU_CHANNELS_NUM 32 + +enum pixel_fmt { + /* 1 byte */ + IPU_PIX_FMT_GENERIC, + IPU_PIX_FMT_RGB332, + IPU_PIX_FMT_YUV420P, + IPU_PIX_FMT_YUV422P, + IPU_PIX_FMT_YUV420P2, + IPU_PIX_FMT_YVU422P, + /* 2 bytes */ + IPU_PIX_FMT_RGB565, + IPU_PIX_FMT_RGB666, + IPU_PIX_FMT_BGR666, + IPU_PIX_FMT_YUYV, + IPU_PIX_FMT_UYVY, + /* 3 bytes */ + IPU_PIX_FMT_RGB24, + IPU_PIX_FMT_BGR24, + /* 4 bytes */ + IPU_PIX_FMT_GENERIC_32, + IPU_PIX_FMT_RGB32, + IPU_PIX_FMT_BGR32, + IPU_PIX_FMT_ABGR32, + IPU_PIX_FMT_BGRA32, + IPU_PIX_FMT_RGBA32, +}; + +enum ipu_color_space { + IPU_COLORSPACE_RGB, + IPU_COLORSPACE_YCBCR, + IPU_COLORSPACE_YUV +}; + +/* + * Enumeration of IPU rotation modes + */ +enum ipu_rotate_mode { + /* Note the enum values correspond to BAM value */ + IPU_ROTATE_NONE = 0, + IPU_ROTATE_VERT_FLIP = 1, + IPU_ROTATE_HORIZ_FLIP = 2, + IPU_ROTATE_180 = 3, + IPU_ROTATE_90_RIGHT = 4, + IPU_ROTATE_90_RIGHT_VFLIP = 5, + IPU_ROTATE_90_RIGHT_HFLIP = 6, + IPU_ROTATE_90_LEFT = 7, +}; + +struct ipu_platform_data { + unsigned int irq_base; +}; + +/* + * Enumeration of DI ports for ADC. + */ +enum display_port { + DISP0, + DISP1, + DISP2, + DISP3 +}; + +struct idmac_video_param { + unsigned short in_width; + unsigned short in_height; + uint32_t in_pixel_fmt; + unsigned short out_width; + unsigned short out_height; + uint32_t out_pixel_fmt; + unsigned short out_stride; + bool graphics_combine_en; + bool global_alpha_en; + bool key_color_en; + enum display_port disp; + unsigned short out_left; + unsigned short out_top; +}; + +/* + * Union of initialization parameters for a logical channel. So far only video + * parameters are used. + */ +union ipu_channel_param { + struct idmac_video_param video; +}; + +struct idmac_tx_desc { + struct dma_async_tx_descriptor txd; + struct scatterlist *sg; /* scatterlist for this */ + unsigned int sg_len; /* tx-descriptor. */ + struct list_head list; +}; + +struct idmac_channel { + struct dma_chan dma_chan; + dma_cookie_t completed; /* last completed cookie */ + union ipu_channel_param params; + enum ipu_channel link; /* input channel, linked to the output */ + enum ipu_channel_status status; + void *client; /* Only one client per channel */ + unsigned int n_tx_desc; + struct idmac_tx_desc *desc; /* allocated tx-descriptors */ + struct scatterlist *sg[2]; /* scatterlist elements in buffer-0 and -1 */ + struct list_head free_list; /* free tx-descriptors */ + struct list_head queue; /* queued tx-descriptors */ + spinlock_t lock; /* protects sg[0,1], queue */ + struct mutex chan_mutex; /* protects status, cookie, free_list */ + bool sec_chan_en; + int active_buffer; + unsigned int eof_irq; + char eof_name[16]; /* EOF IRQ name for request_irq() */ +}; + +#define to_tx_desc(tx) container_of(tx, struct idmac_tx_desc, txd) +#define to_idmac_chan(c) container_of(c, struct idmac_channel, dma_chan) + +#endif diff --git a/arch/arm/plat-mxc/include/mach/iram.h b/arch/arm/plat-mxc/include/mach/iram.h new file mode 100644 index 00000000..022690c3 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/iram.h @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ +#include <linux/errno.h> + +#ifdef CONFIG_IRAM_ALLOC + +int __init iram_init(unsigned long base, unsigned long size); +void __iomem *iram_alloc(unsigned int size, unsigned long *dma_addr); +void iram_free(unsigned long dma_addr, unsigned int size); + +#else + +static inline int __init iram_init(unsigned long base, unsigned long size) +{ + return -ENOMEM; +} + +static inline void __iomem *iram_alloc(unsigned int size, unsigned long *dma_addr) +{ + return NULL; +} + +static inline void iram_free(unsigned long base, unsigned long size) {} + +#endif diff --git a/arch/arm/plat-mxc/include/mach/irqs.h b/arch/arm/plat-mxc/include/mach/irqs.h new file mode 100644 index 00000000..62282a95 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/irqs.h @@ -0,0 +1,91 @@ +/* + * Copyright 2004-2013 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_MXC_IRQS_H__ +#define __ASM_ARCH_MXC_IRQS_H__ + +/* + * SoCs with TZIC interrupt controller have 128 IRQs, those with AVIC have 64 + */ +#ifdef CONFIG_MXC_TZIC +#define MXC_INTERNAL_IRQS 128 +#elif defined CONFIG_ARM_GIC +/* assuem 256 is enough for GIC */ +#define MXC_INTERNAL_IRQS 256 +#else +#define MXC_INTERNAL_IRQS 64 +#endif + +#define MXC_GPIO_IRQ_START MXC_INTERNAL_IRQS + +/* these are ordered by size to support multi-SoC kernels */ +#if defined CONFIG_SOC_IMX53 +#define MXC_GPIO_IRQS (32 * 7) +#elif defined CONFIG_ARCH_MX2 +#define MXC_GPIO_IRQS (32 * 6) +#elif defined CONFIG_SOC_IMX50 +#define MXC_GPIO_IRQS (32 * 6) +#elif defined CONFIG_ARCH_MX1 +#define MXC_GPIO_IRQS (32 * 4) +#elif defined CONFIG_ARCH_MX25 +#define MXC_GPIO_IRQS (32 * 4) +#elif defined CONFIG_SOC_IMX51 +#define MXC_GPIO_IRQS (32 * 4) +#elif defined CONFIG_ARCH_MX3 +#define MXC_GPIO_IRQS (32 * 3) +#elif defined CONFIG_ARCH_MX6 +#define MXC_GPIO_IRQS (32 * 7) +#endif + +/* + * The next 16 interrupts are for board specific purposes. Since + * the kernel can only run on one machine at a time, we can re-use + * these. If you need more, increase MXC_BOARD_IRQS, but keep it + * within sensible limits. + */ +#define MXC_BOARD_IRQ_START (MXC_INTERNAL_IRQS + MXC_GPIO_IRQS) + +#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1 +#define MXC_BOARD_IRQS 80 +#else +#define MXC_BOARD_IRQS 16 +#endif + +#define MXC_IPU_IRQ_START (MXC_BOARD_IRQ_START + MXC_BOARD_IRQS) + +#ifdef CONFIG_MX3_IPU_IRQS +#define MX3_IPU_IRQS CONFIG_MX3_IPU_IRQS +#else +#define MX3_IPU_IRQS 0 +#endif + +#ifdef CONFIG_ARCH_MX5 +#define MX5_IPU_IRQS (32*15) +#else +#define MX5_IPU_IRQS 0 +#endif + +#ifdef CONFIG_ARCH_MX6 +#define MX6_MSI_IRQS 128 +#else +#define MX6_MSI_IRQS 0 +#endif + +#define IRQ_IMX_MSI_0 (MXC_IPU_IRQ_START + MX3_IPU_IRQS + MX5_IPU_IRQS) +#define NR_IRQS (IRQ_IMX_MSI_0 + MX6_MSI_IRQS) + +extern int imx_irq_set_priority(unsigned char irq, unsigned char prio); + +/* all normal IRQs can be FIQs */ +#define FIQ_START 0 +/* switch between IRQ and FIQ */ +extern int mxc_set_irq_fiq(unsigned int irq, unsigned int type); + +#endif /* __ASM_ARCH_MXC_IRQS_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/memory.h b/arch/arm/plat-mxc/include/mach/memory.h new file mode 100755 index 00000000..350ae0f9 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/memory.h @@ -0,0 +1,79 @@ +/* + * Copyright 2004-2012 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_MXC_MEMORY_H__ +#define __ASM_ARCH_MXC_MEMORY_H__ + +#include <asm/sizes.h> +#include <asm/page.h> + +#define MX1_PHYS_OFFSET UL(0x08000000) +#define MX21_PHYS_OFFSET UL(0xc0000000) +#define MX25_PHYS_OFFSET UL(0x80000000) +#define MX27_PHYS_OFFSET UL(0xa0000000) +#define MX3x_PHYS_OFFSET UL(0x80000000) +#define MX50_PHYS_OFFSET UL(0x70000000) +#define MX51_PHYS_OFFSET UL(0x90000000) +#define MX53_PHYS_OFFSET UL(0x70000000) +#define MX6_PHYS_OFFSET UL(0x10000000) +#define MX6SL_PHYS_OFFSET UL(0x80000000) + +#if !defined(CONFIG_RUNTIME_PHYS_OFFSET) +# if defined CONFIG_ARCH_MX1 +# define PLAT_PHYS_OFFSET MX1_PHYS_OFFSET +# elif defined CONFIG_MACH_MX21 +# define PLAT_PHYS_OFFSET MX21_PHYS_OFFSET +# elif defined CONFIG_ARCH_MX25 +# define PLAT_PHYS_OFFSET MX25_PHYS_OFFSET +# elif defined CONFIG_MACH_MX27 +# define PLAT_PHYS_OFFSET MX27_PHYS_OFFSET +# elif defined CONFIG_ARCH_MX3 +# define PLAT_PHYS_OFFSET MX3x_PHYS_OFFSET +# elif defined CONFIG_ARCH_MX50 +# define PLAT_PHYS_OFFSET MX50_PHYS_OFFSET +# elif defined CONFIG_ARCH_MX51 +# define PLAT_PHYS_OFFSET MX51_PHYS_OFFSET +# elif defined CONFIG_ARCH_MX53 +# define PLAT_PHYS_OFFSET MX53_PHYS_OFFSET +# elif defined CONFIG_ARCH_MX50 +# define PLAT_PHYS_OFFSET MX50_PHYS_OFFSET +# elif defined CONFIG_ARCH_MX6 +# define PLAT_PHYS_OFFSET MX6_PHYS_OFFSET +# endif +#endif + +#if defined(CONFIG_MX3_VIDEO) +/* + * Increase size of DMA-consistent memory region. + * This is required for mx3 camera driver to capture at least two QXGA frames. + */ +#define CONSISTENT_DMA_SIZE SZ_8M + +#elif defined(CONFIG_MX1_VIDEO) || defined(CONFIG_VIDEO_MX2_HOSTSUPPORT) +/* + * Increase size of DMA-consistent memory region. + * This is required for i.MX camera driver to capture at least four VGA frames. + */ +#define CONSISTENT_DMA_SIZE SZ_4M +#else + +#ifndef CONFIG_ZONE_DMA +#define CONSISTENT_DMA_SIZE (64 * SZ_1M) +#elif defined(CONFIG_ARCH_MX5) || defined(CONFIG_ARCH_MX6) +#define ARM_DMA_ZONE_SIZE (184 * SZ_1M) +#define CONSISTENT_DMA_SIZE ARM_DMA_ZONE_SIZE +#else +#define CONSISTENT_DMA_SIZE (32 * SZ_1M) +#endif + +#endif /* CONFIG_MX1_VIDEO || CONFIG_VIDEO_MX2_HOSTSUPPORT */ + + +#endif /* __ASM_ARCH_MXC_MEMORY_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mipi_csi2.h b/arch/arm/plat-mxc/include/mach/mipi_csi2.h new file mode 100644 index 00000000..7679027a --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/mipi_csi2.h @@ -0,0 +1,121 @@ +/* + * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __INCLUDE_MIPI_CSI2_H +#define __INCLUDE_MIPI_CSI2_H + +/* mipi csi2 register */ +#define CSI2_VERSION 0x000 +#define CSI2_N_LANES (0x004/4) +#define CSI2_PHY_SHUTDOWNZ (0x008/4) +#define CSI2_DPHY_RSTZ (0x00c/4) +#define CSI2_RESETN (0x010/4) +#define CSI2_PHY_STATE (0x014/4) +#define CSI2_DATA_IDS_1 (0x018/4) +#define CSI2_DATA_IDS_2 (0x01c/4) +#define CSI2_ERR1 (0x020/4) +#define CSI2_ERR2 (0x024/4) +#define CSI2_MSK1 (0x028/4) +#define CSI2_MSK2 (0x02c/4) +#define CSI2_PHY_TST_CTRL0 (0x030/4) +#define CSI2_PHY_TST_CTRL1 (0x034/4) +#define CSI2_SFT_RESET (0xf00/4) + +/* mipi data type */ +#define MIPI_DT_YUV420 0x18 /* YYY.../UYVY.... */ +#define MIPI_DT_YUV420_LEGACY 0x1a /* UYY.../VYY... */ +#define MIPI_DT_YUV422 0x1e /* UYVY... */ +#define MIPI_DT_RGB444 0x20 +#define MIPI_DT_RGB555 0x21 +#define MIPI_DT_RGB565 0x22 +#define MIPI_DT_RGB666 0x23 +#define MIPI_DT_RGB888 0x24 +#define MIPI_DT_RAW6 0x28 +#define MIPI_DT_RAW7 0x29 +#define MIPI_DT_RAW8 0x2a +#define MIPI_DT_RAW10 0x2b +#define MIPI_DT_RAW12 0x2c +#define MIPI_DT_RAW14 0x2d + + +struct mipi_csi2_info; +/* mipi csi2 API */ +struct mipi_csi2_info *mipi_csi2_get_info(void); + +bool mipi_csi2_enable(struct mipi_csi2_info *info); + +bool mipi_csi2_disable(struct mipi_csi2_info *info); + +bool mipi_csi2_get_status(struct mipi_csi2_info *info); + +int mipi_csi2_get_bind_ipu(struct mipi_csi2_info *info); + +unsigned int mipi_csi2_get_bind_csi(struct mipi_csi2_info *info); + +unsigned int mipi_csi2_get_virtual_channel(struct mipi_csi2_info *info); + +unsigned int mipi_csi2_set_lanes(struct mipi_csi2_info *info); + +unsigned int mipi_csi2_set_datatype(struct mipi_csi2_info *info, + unsigned int datatype); + +unsigned int mipi_csi2_get_datatype(struct mipi_csi2_info *info); + +unsigned int mipi_csi2_dphy_status(struct mipi_csi2_info *info); + +unsigned int mipi_csi2_get_error1(struct mipi_csi2_info *info); + +unsigned int mipi_csi2_get_error2(struct mipi_csi2_info *info); + +int mipi_csi2_pixelclk_enable(struct mipi_csi2_info *info); + +void mipi_csi2_pixelclk_disable(struct mipi_csi2_info *info); + +int mipi_csi2_reset(struct mipi_csi2_info *info); + +/** + * struct mipi_csi2_platform_data - MIPI CSI2 driver platform data. + * + * This structure communicates platform-specific information to the + * MIPI CSI2 driver that can't be expressed as resources. + * + * @ipu_id: the id of IPUs on which this MIPI CSI2 works + * + * @csi_id: the id of IPU CSI interfaces + * + * @v_channel: mipi virtual channel num + * + * @lanes: mipi lanes + * + * @init: A pointer to a function the driver will call to + * initialize the platform (e.g., set up the pin mux). + * @exit: A pointer to a function the driver will call to + * exit the platform (e.g., free pins). + */ +struct mipi_csi2_platform_data { + int ipu_id; + unsigned int csi_id; + unsigned int v_channel; + unsigned int lanes; + char *dphy_clk; + char *pixel_clk; + int (*init)(struct platform_device *); + void (*exit)(struct platform_device *); +}; + +#endif diff --git a/arch/arm/plat-mxc/include/mach/mipi_dsi.h b/arch/arm/plat-mxc/include/mach/mipi_dsi.h new file mode 100644 index 00000000..0dd1f083 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/mipi_dsi.h @@ -0,0 +1,225 @@ +/* + * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __INCLUDE_MIPI_DSI_H +#define __INCLUDE_MIPI_DSI_H + +#define MIPI_DSI_VERSION (0x000) +#define MIPI_DSI_PWR_UP (0x004) +#define MIPI_DSI_CLKMGR_CFG (0x008) +#define MIPI_DSI_DPI_CFG (0x00c) +#define MIPI_DSI_DBI_CFG (0x010) +#define MIPI_DSI_DBIS_CMDSIZE (0x014) +#define MIPI_DSI_PCKHDL_CFG (0x018) +#define MIPI_DSI_VID_MODE_CFG (0x01c) +#define MIPI_DSI_VID_PKT_CFG (0x020) +#define MIPI_DSI_CMD_MODE_CFG (0x024) +#define MIPI_DSI_TMR_LINE_CFG (0x028) +#define MIPI_DSI_VTIMING_CFG (0x02c) +#define MIPI_DSI_PHY_TMR_CFG (0x030) +#define MIPI_DSI_GEN_HDR (0x034) +#define MIPI_DSI_GEN_PLD_DATA (0x038) +#define MIPI_DSI_CMD_PKT_STATUS (0x03c) +#define MIPI_DSI_TO_CNT_CFG (0x040) +#define MIPI_DSI_ERROR_ST0 (0x044) +#define MIPI_DSI_ERROR_ST1 (0x048) +#define MIPI_DSI_ERROR_MSK0 (0x04c) +#define MIPI_DSI_ERROR_MSK1 (0x050) +#define MIPI_DSI_PHY_RSTZ (0x054) +#define MIPI_DSI_PHY_IF_CFG (0x058) +#define MIPI_DSI_PHY_IF_CTRL (0x05c) +#define MIPI_DSI_PHY_STATUS (0x060) +#define MIPI_DSI_PHY_TST_CTRL0 (0x064) +#define MIPI_DSI_PHY_TST_CTRL1 (0x068) + +#define DSI_PWRUP_RESET (0x0 << 0) +#define DSI_PWRUP_POWERUP (0x1 << 0) + +#define DSI_DPI_CFG_VID_SHIFT (0) +#define DSI_DPI_CFG_VID_MASK (0x3) +#define DSI_DPI_CFG_COLORCODE_SHIFT (2) +#define DSI_DPI_CFG_COLORCODE_MASK (0x7) +#define DSI_DPI_CFG_DATAEN_ACT_LOW (0x1 << 5) +#define DSI_DPI_CFG_DATAEN_ACT_HIGH (0x0 << 5) +#define DSI_DPI_CFG_VSYNC_ACT_LOW (0x1 << 6) +#define DSI_DPI_CFG_VSYNC_ACT_HIGH (0x0 << 6) +#define DSI_DPI_CFG_HSYNC_ACT_LOW (0x1 << 7) +#define DSI_DPI_CFG_HSYNC_ACT_HIGH (0x0 << 7) +#define DSI_DPI_CFG_SHUTD_ACT_LOW (0x1 << 8) +#define DSI_DPI_CFG_SHUTD_ACT_HIGH (0x0 << 8) +#define DSI_DPI_CFG_COLORMODE_ACT_LOW (0x1 << 9) +#define DSI_DPI_CFG_COLORMODE_ACT_HIGH (0x0 << 9) +#define DSI_DPI_CFG_EN18LOOSELY (0x1 << 10) + +#define DSI_PCKHDL_CFG_EN_EOTP_TX (0x1 << 0) +#define DSI_PCKHDL_CFG_EN_EOTP_RX (0x1 << 1) +#define DSI_PCKHDL_CFG_EN_BTA (0x1 << 2) +#define DSI_PCKHDL_CFG_EN_ECC_RX (0x1 << 3) +#define DSI_PCKHDL_CFG_EN_CRC_RX (0x1 << 4) +#define DSI_PCKHDL_CFG_GEN_VID_RX_MASK (0x3) +#define DSI_PCKHDL_CFG_GEN_VID_RX_SHIFT (5) + +#define DSI_VID_MODE_CFG_EN (0x1 << 0) +#define DSI_VID_MODE_CFG_EN_BURSTMODE (0x3 << 1) +#define DSI_VID_MODE_CFG_TYPE_MASK (0x3) +#define DSI_VID_MODE_CFG_TYPE_SHIFT (1) +#define DSI_VID_MODE_CFG_EN_LP_VSA (0x1 << 3) +#define DSI_VID_MODE_CFG_EN_LP_VBP (0x1 << 4) +#define DSI_VID_MODE_CFG_EN_LP_VFP (0x1 << 5) +#define DSI_VID_MODE_CFG_EN_LP_VACT (0x1 << 6) +#define DSI_VID_MODE_CFG_EN_LP_HBP (0x1 << 7) +#define DSI_VID_MODE_CFG_EN_LP_HFP (0x1 << 8) +#define DSI_VID_MODE_CFG_EN_MULTI_PKT (0x1 << 9) +#define DSI_VID_MODE_CFG_EN_NULL_PKT (0x1 << 10) +#define DSI_VID_MODE_CFG_EN_FRAME_ACK (0x1 << 11) +#define DSI_VID_MODE_CFG_EN_LP_MODE (DSI_VID_MODE_CFG_EN_LP_VSA | \ + DSI_VID_MODE_CFG_EN_LP_VBP | \ + DSI_VID_MODE_CFG_EN_LP_VFP | \ + DSI_VID_MODE_CFG_EN_LP_HFP | \ + DSI_VID_MODE_CFG_EN_LP_HBP | \ + DSI_VID_MODE_CFG_EN_LP_VACT) + + + +#define DSI_VID_PKT_CFG_VID_PKT_SZ_MASK (0x7ff) +#define DSI_VID_PKT_CFG_VID_PKT_SZ_SHIFT (0) +#define DSI_VID_PKT_CFG_NUM_CHUNKS_MASK (0x3ff) +#define DSI_VID_PKT_CFG_NUM_CHUNKS_SHIFT (11) +#define DSI_VID_PKT_CFG_NULL_PKT_SZ_MASK (0x3ff) +#define DSI_VID_PKT_CFG_NULL_PKT_SZ_SHIFT (21) + +#define MIPI_DSI_CMD_MODE_CFG_EN_LOWPOWER (0x1FFF) +#define MIPI_DSI_CMD_MODE_CFG_EN_CMD_MODE (0x1 << 0) + +#define DSI_TME_LINE_CFG_HSA_TIME_MASK (0x1ff) +#define DSI_TME_LINE_CFG_HSA_TIME_SHIFT (0) +#define DSI_TME_LINE_CFG_HBP_TIME_MASK (0x1ff) +#define DSI_TME_LINE_CFG_HBP_TIME_SHIFT (9) +#define DSI_TME_LINE_CFG_HLINE_TIME_MASK (0x3fff) +#define DSI_TME_LINE_CFG_HLINE_TIME_SHIFT (18) + +#define DSI_VTIMING_CFG_VSA_LINES_MASK (0xf) +#define DSI_VTIMING_CFG_VSA_LINES_SHIFT (0) +#define DSI_VTIMING_CFG_VBP_LINES_MASK (0x3f) +#define DSI_VTIMING_CFG_VBP_LINES_SHIFT (4) +#define DSI_VTIMING_CFG_VFP_LINES_MASK (0x3f) +#define DSI_VTIMING_CFG_VFP_LINES_SHIFT (10) +#define DSI_VTIMING_CFG_V_ACT_LINES_MASK (0x7ff) +#define DSI_VTIMING_CFG_V_ACT_LINES_SHIFT (16) + +#define DSI_PHY_TMR_CFG_BTA_TIME_MASK (0xfff) +#define DSI_PHY_TMR_CFG_BTA_TIME_SHIFT (0) +#define DSI_PHY_TMR_CFG_LP2HS_TIME_MASK (0xff) +#define DSI_PHY_TMR_CFG_LP2HS_TIME_SHIFT (12) +#define DSI_PHY_TMR_CFG_HS2LP_TIME_MASK (0xff) +#define DSI_PHY_TMR_CFG_HS2LP_TIME_SHIFT (20) + +#define DSI_PHY_IF_CFG_N_LANES_MASK (0x3) +#define DSI_PHY_IF_CFG_N_LANES_SHIFT (0) +#define DSI_PHY_IF_CFG_WAIT_TIME_MASK (0xff) +#define DSI_PHY_IF_CFG_WAIT_TIME_SHIFT (2) + +#define DSI_PHY_RSTZ_EN_CLK (0x1 << 2) +#define DSI_PHY_RSTZ_DISABLE_RST (0x1 << 1) +#define DSI_PHY_RSTZ_DISABLE_SHUTDOWN (0x1 << 0) +#define DSI_PHY_RSTZ_RST (0x0) + +#define DSI_PHY_STATUS_LOCK (0x1 << 0) +#define DSI_PHY_STATUS_STOPSTATE_CLK_LANE (0x1 << 2) + +#define DSI_GEN_HDR_TYPE_MASK (0xff) +#define DSI_GEN_HDR_TYPE_SHIFT (0) +#define DSI_GEN_HDR_DATA_MASK (0xffff) +#define DSI_GEN_HDR_DATA_SHIFT (8) + +#define DSI_CMD_PKT_STATUS_GEN_CMD_EMPTY (0x1 << 0) +#define DSI_CMD_PKT_STATUS_GEN_CMD_FULL (0x1 << 1) +#define DSI_CMD_PKT_STATUS_GEN_PLD_W_EMPTY (0x1 << 2) +#define DSI_CMD_PKT_STATUS_GEN_PLD_W_FULL (0x1 << 3) +#define DSI_CMD_PKT_STATUS_GEN_PLD_R_EMPTY (0x1 << 4) +#define DSI_CMD_PKT_STATUS_GEN_RD_CMD_BUSY (0x1 << 6) + +#define DSI_ERROR_MSK0_ALL_MASK (0x1fffff) +#define DSI_ERROR_MSK1_ALL_MASK (0x3ffff) + +#define DSI_PHY_IF_CTRL_RESET (0x0) +#define DSI_PHY_IF_CTRL_TX_REQ_CLK_HS (0x1 << 0) +#define DSI_PHY_IF_CTRL_TX_REQ_CLK_ULPS (0x1 << 1) +#define DSI_PHY_IF_CTRL_TX_EXIT_CLK_ULPS (0x1 << 2) +#define DSI_PHY_IF_CTRL_TX_REQ_DATA_ULPS (0x1 << 3) +#define DSI_PHY_IF_CTRL_TX_EXIT_DATA_ULPS (0x1 << 4) +#define DSI_PHY_IF_CTRL_TX_TRIG_MASK (0xF) +#define DSI_PHY_IF_CTRL_TX_TRIG_SHIFT (5) + +#define DSI_PHY_CLK_INIT_COMMAND (0x44) +#define DSI_GEN_PLD_DATA_BUF_SIZE (0x4) +/** + * struct mipi_dsi_platform_data - MIPI DSI driver platform data. + * + * This structure communicates platform-specific information to the MIPI DSI + * driver that can't be expressed as resources. + * + * @ipu_id: the id of IPUs on which this MIPI DSI works + * + * @disp_id: the id of IPU display interfaces + * + * @lcd_panel: the supported mipi LCD panel string + * + * @init: A pointer to a function the driver will call to + * initialize the platform (e.g., set up the pin mux). + * @exit: A pointer to a function the driver will call to + * exit the platform (e.g., free pins). + * @io_regulator: io regulator name for MIPI DSI display module + * + * @core_regulator: core regulator name for MIPI DSI display module + * + * @analog_regulator: analog regulator name for MIPI DSI display module + * + * @io_volt: io regulator voltage for MIPI DSI display module + * + * @core_volt: core regulator voltage for MIPI DSI display module + * + * @analog_volt: analog regulator voltage for MIPI DSI display module + * + * @reset: A pointer to a function the driver will call to + * reset the MIPI DSI display module + * @lcd_power: A pointer to a function the drvier will call to + * configure the power of MIPI LCD panel + * @backlight_power: A pointer to a function the drvier will call to + * configure the power of MIPI LCD backlight + */ +struct mipi_dsi_platform_data { + /* SoC hardware information. */ + int ipu_id; + int disp_id; + char *lcd_panel; + int (*init)(struct platform_device *); + void (*exit)(struct platform_device *); + + /* board related information. */ + char *io_regulator; + char *core_regulator; + char *analog_regulator; + int io_volt; + int core_volt; + int analog_volt; + void (*reset) (void); + void (*lcd_power)(int); + void (*backlight_power)(int); +}; +#endif diff --git a/arch/arm/plat-mxc/include/mach/mmc.h b/arch/arm/plat-mxc/include/mach/mmc.h new file mode 100644 index 00000000..29115f40 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/mmc.h @@ -0,0 +1,39 @@ +#ifndef ASMARM_ARCH_MMC_H +#define ASMARM_ARCH_MMC_H + +#include <linux/mmc/host.h> + +struct device; + +/* board specific SDHC data, optional. + * If not present, a writable card with 3,3V is assumed. + */ +struct imxmmc_platform_data { + /* Return values for the get_ro callback should be: + * 0 for a read/write card + * 1 for a read-only card + * -ENOSYS when not supported (equal to NULL callback) + * or a negative errno value when something bad happened + */ + int (*get_ro)(struct device *); + + /* board specific hook to (de)initialize the SD slot. + * The board code can call 'handler' on a card detection + * change giving data as argument. + */ + int (*init)(struct device *dev, irq_handler_t handler, void *data); + void (*exit)(struct device *dev, void *data); + + /* available voltages. If not given, assume + * MMC_VDD_32_33 | MMC_VDD_33_34 + */ + unsigned int ocr_avail; + + /* adjust slot voltage */ + void (*setpower)(struct device *, unsigned int vdd); + + /* enable card detect using DAT3 */ + int dat3_card_detect; +}; + +#endif diff --git a/arch/arm/plat-mxc/include/mach/mx1.h b/arch/arm/plat-mxc/include/mach/mx1.h new file mode 100644 index 00000000..97b19e78 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/mx1.h @@ -0,0 +1,173 @@ +/* + * Copyright (C) 1997,1998 Russell King + * Copyright (C) 1999 ARM Limited + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (c) 2008 Paulius Zaleckas <paulius.zaleckas@teltonika.lt> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __MACH_MX1_H__ +#define __MACH_MX1_H__ + +#include <mach/vmalloc.h> + +/* + * Memory map + */ +#define MX1_IO_BASE_ADDR 0x00200000 +#define MX1_IO_SIZE SZ_1M + +#define MX1_CS0_PHYS 0x10000000 +#define MX1_CS0_SIZE 0x02000000 + +#define MX1_CS1_PHYS 0x12000000 +#define MX1_CS1_SIZE 0x01000000 + +#define MX1_CS2_PHYS 0x13000000 +#define MX1_CS2_SIZE 0x01000000 + +#define MX1_CS3_PHYS 0x14000000 +#define MX1_CS3_SIZE 0x01000000 + +#define MX1_CS4_PHYS 0x15000000 +#define MX1_CS4_SIZE 0x01000000 + +#define MX1_CS5_PHYS 0x16000000 +#define MX1_CS5_SIZE 0x01000000 + +/* + * Register BASEs, based on OFFSETs + */ +#define MX1_AIPI1_BASE_ADDR (0x00000 + MX1_IO_BASE_ADDR) +#define MX1_WDT_BASE_ADDR (0x01000 + MX1_IO_BASE_ADDR) +#define MX1_TIM1_BASE_ADDR (0x02000 + MX1_IO_BASE_ADDR) +#define MX1_TIM2_BASE_ADDR (0x03000 + MX1_IO_BASE_ADDR) +#define MX1_RTC_BASE_ADDR (0x04000 + MX1_IO_BASE_ADDR) +#define MX1_LCDC_BASE_ADDR (0x05000 + MX1_IO_BASE_ADDR) +#define MX1_UART1_BASE_ADDR (0x06000 + MX1_IO_BASE_ADDR) +#define MX1_UART2_BASE_ADDR (0x07000 + MX1_IO_BASE_ADDR) +#define MX1_PWM_BASE_ADDR (0x08000 + MX1_IO_BASE_ADDR) +#define MX1_DMA_BASE_ADDR (0x09000 + MX1_IO_BASE_ADDR) +#define MX1_AIPI2_BASE_ADDR (0x10000 + MX1_IO_BASE_ADDR) +#define MX1_SIM_BASE_ADDR (0x11000 + MX1_IO_BASE_ADDR) +#define MX1_USBD_BASE_ADDR (0x12000 + MX1_IO_BASE_ADDR) +#define MX1_CSPI1_BASE_ADDR (0x13000 + MX1_IO_BASE_ADDR) +#define MX1_MMC_BASE_ADDR (0x14000 + MX1_IO_BASE_ADDR) +#define MX1_ASP_BASE_ADDR (0x15000 + MX1_IO_BASE_ADDR) +#define MX1_BTA_BASE_ADDR (0x16000 + MX1_IO_BASE_ADDR) +#define MX1_I2C_BASE_ADDR (0x17000 + MX1_IO_BASE_ADDR) +#define MX1_SSI_BASE_ADDR (0x18000 + MX1_IO_BASE_ADDR) +#define MX1_CSPI2_BASE_ADDR (0x19000 + MX1_IO_BASE_ADDR) +#define MX1_MSHC_BASE_ADDR (0x1A000 + MX1_IO_BASE_ADDR) +#define MX1_CCM_BASE_ADDR (0x1B000 + MX1_IO_BASE_ADDR) +#define MX1_SCM_BASE_ADDR (0x1B804 + MX1_IO_BASE_ADDR) +#define MX1_GPIO_BASE_ADDR (0x1C000 + MX1_IO_BASE_ADDR) +#define MX1_GPIO1_BASE_ADDR (0x1C000 + MX1_IO_BASE_ADDR) +#define MX1_GPIO2_BASE_ADDR (0x1C100 + MX1_IO_BASE_ADDR) +#define MX1_GPIO3_BASE_ADDR (0x1C200 + MX1_IO_BASE_ADDR) +#define MX1_GPIO4_BASE_ADDR (0x1C300 + MX1_IO_BASE_ADDR) +#define MX1_EIM_BASE_ADDR (0x20000 + MX1_IO_BASE_ADDR) +#define MX1_SDRAMC_BASE_ADDR (0x21000 + MX1_IO_BASE_ADDR) +#define MX1_MMA_BASE_ADDR (0x22000 + MX1_IO_BASE_ADDR) +#define MX1_AVIC_BASE_ADDR (0x23000 + MX1_IO_BASE_ADDR) +#define MX1_CSI_BASE_ADDR (0x24000 + MX1_IO_BASE_ADDR) + +/* macro to get at IO space when running virtually */ +#define MX1_IO_P2V(x) IMX_IO_P2V(x) +#define MX1_IO_ADDRESS(x) IOMEM(MX1_IO_P2V(x)) + +/* fixed interrput numbers */ +#define MX1_INT_SOFTINT 0 +#define MX1_INT_CSI 6 +#define MX1_DSPA_MAC_INT 7 +#define MX1_DSPA_INT 8 +#define MX1_COMP_INT 9 +#define MX1_MSHC_XINT 10 +#define MX1_GPIO_INT_PORTA 11 +#define MX1_GPIO_INT_PORTB 12 +#define MX1_GPIO_INT_PORTC 13 +#define MX1_INT_LCDC 14 +#define MX1_SIM_INT 15 +#define MX1_SIM_DATA_INT 16 +#define MX1_RTC_INT 17 +#define MX1_RTC_SAMINT 18 +#define MX1_INT_UART2PFERR 19 +#define MX1_INT_UART2RTS 20 +#define MX1_INT_UART2DTR 21 +#define MX1_INT_UART2UARTC 22 +#define MX1_INT_UART2TX 23 +#define MX1_INT_UART2RX 24 +#define MX1_INT_UART1PFERR 25 +#define MX1_INT_UART1RTS 26 +#define MX1_INT_UART1DTR 27 +#define MX1_INT_UART1UARTC 28 +#define MX1_INT_UART1TX 29 +#define MX1_INT_UART1RX 30 +#define MX1_VOICE_DAC_INT 31 +#define MX1_VOICE_ADC_INT 32 +#define MX1_PEN_DATA_INT 33 +#define MX1_PWM_INT 34 +#define MX1_SDHC_INT 35 +#define MX1_INT_I2C 39 +#define MX1_INT_CSPI2 40 +#define MX1_INT_CSPI1 41 +#define MX1_SSI_TX_INT 42 +#define MX1_SSI_TX_ERR_INT 43 +#define MX1_SSI_RX_INT 44 +#define MX1_SSI_RX_ERR_INT 45 +#define MX1_TOUCH_INT 46 +#define MX1_INT_USBD0 47 +#define MX1_INT_USBD1 48 +#define MX1_INT_USBD2 49 +#define MX1_INT_USBD3 50 +#define MX1_INT_USBD4 51 +#define MX1_INT_USBD5 52 +#define MX1_INT_USBD6 53 +#define MX1_BTSYS_INT 55 +#define MX1_BTTIM_INT 56 +#define MX1_BTWUI_INT 57 +#define MX1_TIM2_INT 58 +#define MX1_TIM1_INT 59 +#define MX1_DMA_ERR 60 +#define MX1_DMA_INT 61 +#define MX1_GPIO_INT_PORTD 62 +#define MX1_WDT_INT 63 + +/* DMA */ +#define MX1_DMA_REQ_UART3_T 2 +#define MX1_DMA_REQ_UART3_R 3 +#define MX1_DMA_REQ_SSI2_T 4 +#define MX1_DMA_REQ_SSI2_R 5 +#define MX1_DMA_REQ_CSI_STAT 6 +#define MX1_DMA_REQ_CSI_R 7 +#define MX1_DMA_REQ_MSHC 8 +#define MX1_DMA_REQ_DSPA_DCT_DOUT 9 +#define MX1_DMA_REQ_DSPA_DCT_DIN 10 +#define MX1_DMA_REQ_DSPA_MAC 11 +#define MX1_DMA_REQ_EXT 12 +#define MX1_DMA_REQ_SDHC 13 +#define MX1_DMA_REQ_SPI1_R 14 +#define MX1_DMA_REQ_SPI1_T 15 +#define MX1_DMA_REQ_SSI_T 16 +#define MX1_DMA_REQ_SSI_R 17 +#define MX1_DMA_REQ_ASP_DAC 18 +#define MX1_DMA_REQ_ASP_ADC 19 +#define MX1_DMA_REQ_USP_EP(x) (20 + (x)) +#define MX1_DMA_REQ_SPI2_R 26 +#define MX1_DMA_REQ_SPI2_T 27 +#define MX1_DMA_REQ_UART2_T 28 +#define MX1_DMA_REQ_UART2_R 29 +#define MX1_DMA_REQ_UART1_T 30 +#define MX1_DMA_REQ_UART1_R 31 + +/* + * This doesn't depend on IMX_NEEDS_DEPRECATED_SYMBOLS + * to not break drivers/usb/gadget/imx_udc. Should go + * away after this driver uses the new name. + */ +#define USBD_INT0 MX1_INT_USBD0 + +#endif /* ifndef __MACH_MX1_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx1_camera.h b/arch/arm/plat-mxc/include/mach/mx1_camera.h new file mode 100644 index 00000000..4fd6c703 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/mx1_camera.h @@ -0,0 +1,35 @@ +/* + * mx1_camera.h - i.MX1/i.MXL camera driver header file + * + * Copyright (c) 2008, Paulius Zaleckas <paulius.zaleckas@teltonika.lt> + * Copyright (C) 2009, Darius Augulis <augulis.darius@gmail.com> + * + * Based on PXA camera.h file: + * Copyright (C) 2003, Intel Corporation + * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_CAMERA_H_ +#define __ASM_ARCH_CAMERA_H_ + +#define MX1_CAMERA_DATA_HIGH 1 +#define MX1_CAMERA_PCLK_RISING 2 +#define MX1_CAMERA_VSYNC_HIGH 4 + +extern unsigned char mx1_camera_sof_fiq_start, mx1_camera_sof_fiq_end; + +/** + * struct mx1_camera_pdata - i.MX1/i.MXL camera platform data + * @mclk_10khz: master clock frequency in 10kHz units + * @flags: MX1 camera platform flags + */ +struct mx1_camera_pdata { + unsigned long mclk_10khz; + unsigned long flags; +}; + +#endif /* __ASM_ARCH_CAMERA_H_ */ diff --git a/arch/arm/plat-mxc/include/mach/mx21-usbhost.h b/arch/arm/plat-mxc/include/mach/mx21-usbhost.h new file mode 100644 index 00000000..22d0b596 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/mx21-usbhost.h @@ -0,0 +1,38 @@ +/* + * Copyright (C) 2009 Martin Fuzzey <mfuzzey@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __ASM_ARCH_MX21_USBH +#define __ASM_ARCH_MX21_USBH + +enum mx21_usbh_xcvr { + /* Values below as used by hardware (HWMODE register) */ + MX21_USBXCVR_TXDIF_RXDIF = 0, + MX21_USBXCVR_TXDIF_RXSE = 1, + MX21_USBXCVR_TXSE_RXDIF = 2, + MX21_USBXCVR_TXSE_RXSE = 3, +}; + +struct mx21_usbh_platform_data { + enum mx21_usbh_xcvr host_xcvr; /* tranceiver mode host 1,2 ports */ + enum mx21_usbh_xcvr otg_xcvr; /* tranceiver mode otg (as host) port */ + u16 enable_host1:1, + enable_host2:1, + enable_otg_host:1, /* enable "OTG" port (as host) */ + host1_xcverless:1, /* traceiverless host1 port */ + host1_txenoe:1, /* output enable host1 transmit enable */ + otg_ext_xcvr:1, /* external tranceiver for OTG port */ + unused:10; +}; + +#endif /* __ASM_ARCH_MX21_USBH */ diff --git a/arch/arm/plat-mxc/include/mach/mx21.h b/arch/arm/plat-mxc/include/mach/mx21.h new file mode 100644 index 00000000..6cd049eb --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/mx21.h @@ -0,0 +1,188 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008 Juergen Beisert, kernel@pengutronix.de + * Copyright 2009 Holger Schurig, hs4233@mail.mn-solutions.de + * + * This contains i.MX21-specific hardware definitions. For those + * hardware pieces that are common between i.MX21 and i.MX27, have a + * look at mx2x.h. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#ifndef __MACH_MX21_H__ +#define __MACH_MX21_H__ + +#define MX21_AIPI_BASE_ADDR 0x10000000 +#define MX21_AIPI_SIZE SZ_1M +#define MX21_DMA_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x01000) +#define MX21_WDOG_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x02000) +#define MX21_GPT1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x03000) +#define MX21_GPT2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x04000) +#define MX21_GPT3_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x05000) +#define MX21_PWM_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x06000) +#define MX21_RTC_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x07000) +#define MX21_KPP_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x08000) +#define MX21_OWIRE_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x09000) +#define MX21_UART1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0a000) +#define MX21_UART2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0b000) +#define MX21_UART3_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0c000) +#define MX21_UART4_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0d000) +#define MX21_CSPI1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0e000) +#define MX21_CSPI2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0f000) +#define MX21_SSI1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x10000) +#define MX21_SSI2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x11000) +#define MX21_I2C_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x12000) +#define MX21_SDHC1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x13000) +#define MX21_SDHC2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x14000) +#define MX21_GPIO_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x15000) +#define MX21_GPIO1_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x000) +#define MX21_GPIO2_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x100) +#define MX21_GPIO3_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x200) +#define MX21_GPIO4_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x300) +#define MX21_GPIO5_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x400) +#define MX21_GPIO6_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x500) +#define MX21_AUDMUX_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x16000) +#define MX21_CSPI3_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x17000) +#define MX21_LCDC_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x21000) +#define MX21_SLCDC_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x22000) +#define MX21_USBOTG_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x24000) +#define MX21_EMMA_PP_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x26000) +#define MX21_EMMA_PRP_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x26400) +#define MX21_CCM_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x27000) +#define MX21_SYSCTRL_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x27800) +#define MX21_JAM_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x3e000) +#define MX21_MAX_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x3f000) + +#define MX21_AVIC_BASE_ADDR 0x10040000 + +#define MX21_SAHB1_BASE_ADDR 0x80000000 +#define MX21_SAHB1_SIZE SZ_1M +#define MX21_CSI_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x0000) + +/* Memory regions and CS */ +#define MX21_SDRAM_BASE_ADDR 0xc0000000 +#define MX21_CSD1_BASE_ADDR 0xc4000000 + +#define MX21_CS0_BASE_ADDR 0xc8000000 +#define MX21_CS1_BASE_ADDR 0xcc000000 +#define MX21_CS2_BASE_ADDR 0xd0000000 +#define MX21_CS3_BASE_ADDR 0xd1000000 +#define MX21_CS4_BASE_ADDR 0xd2000000 +#define MX21_PCMCIA_MEM_BASE_ADDR 0xd4000000 +#define MX21_CS5_BASE_ADDR 0xdd000000 + +/* NAND, SDRAM, WEIM etc controllers */ +#define MX21_X_MEMC_BASE_ADDR 0xdf000000 +#define MX21_X_MEMC_SIZE SZ_256K + +#define MX21_SDRAMC_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x0000) +#define MX21_EIM_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x1000) +#define MX21_PCMCIA_CTL_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x2000) +#define MX21_NFC_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x3000) + +#define MX21_IRAM_BASE_ADDR 0xffffe800 /* internal ram */ + +#define MX21_IO_P2V(x) IMX_IO_P2V(x) +#define MX21_IO_ADDRESS(x) IOMEM(MX21_IO_P2V(x)) + +/* fixed interrupt numbers */ +#define MX21_INT_CSPI3 6 +#define MX21_INT_GPIO 8 +#define MX21_INT_FIRI 9 +#define MX21_INT_SDHC2 10 +#define MX21_INT_SDHC1 11 +#define MX21_INT_I2C 12 +#define MX21_INT_SSI2 13 +#define MX21_INT_SSI1 14 +#define MX21_INT_CSPI2 15 +#define MX21_INT_CSPI1 16 +#define MX21_INT_UART4 17 +#define MX21_INT_UART3 18 +#define MX21_INT_UART2 19 +#define MX21_INT_UART1 20 +#define MX21_INT_KPP 21 +#define MX21_INT_RTC 22 +#define MX21_INT_PWM 23 +#define MX21_INT_GPT3 24 +#define MX21_INT_GPT2 25 +#define MX21_INT_GPT1 26 +#define MX21_INT_WDOG 27 +#define MX21_INT_PCMCIA 28 +#define MX21_INT_NFC 29 +#define MX21_INT_BMI 30 +#define MX21_INT_CSI 31 +#define MX21_INT_DMACH0 32 +#define MX21_INT_DMACH1 33 +#define MX21_INT_DMACH2 34 +#define MX21_INT_DMACH3 35 +#define MX21_INT_DMACH4 36 +#define MX21_INT_DMACH5 37 +#define MX21_INT_DMACH6 38 +#define MX21_INT_DMACH7 39 +#define MX21_INT_DMACH8 40 +#define MX21_INT_DMACH9 41 +#define MX21_INT_DMACH10 42 +#define MX21_INT_DMACH11 43 +#define MX21_INT_DMACH12 44 +#define MX21_INT_DMACH13 45 +#define MX21_INT_DMACH14 46 +#define MX21_INT_DMACH15 47 +#define MX21_INT_EMMAENC 49 +#define MX21_INT_EMMADEC 50 +#define MX21_INT_EMMAPRP 51 +#define MX21_INT_EMMAPP 52 +#define MX21_INT_USBWKUP 53 +#define MX21_INT_USBDMA 54 +#define MX21_INT_USBHOST 55 +#define MX21_INT_USBFUNC 56 +#define MX21_INT_USBMNP 57 +#define MX21_INT_USBCTRL 58 +#define MX21_INT_SLCDC 60 +#define MX21_INT_LCDC 61 + +/* fixed DMA request numbers */ +#define MX21_DMA_REQ_CSPI3_RX 1 +#define MX21_DMA_REQ_CSPI3_TX 2 +#define MX21_DMA_REQ_EXT 3 +#define MX21_DMA_REQ_FIRI_RX 4 +#define MX21_DMA_REQ_SDHC2 6 +#define MX21_DMA_REQ_SDHC1 7 +#define MX21_DMA_REQ_SSI2_RX0 8 +#define MX21_DMA_REQ_SSI2_TX0 9 +#define MX21_DMA_REQ_SSI2_RX1 10 +#define MX21_DMA_REQ_SSI2_TX1 11 +#define MX21_DMA_REQ_SSI1_RX0 12 +#define MX21_DMA_REQ_SSI1_TX0 13 +#define MX21_DMA_REQ_SSI1_RX1 14 +#define MX21_DMA_REQ_SSI1_TX1 15 +#define MX21_DMA_REQ_CSPI2_RX 16 +#define MX21_DMA_REQ_CSPI2_TX 17 +#define MX21_DMA_REQ_CSPI1_RX 18 +#define MX21_DMA_REQ_CSPI1_TX 19 +#define MX21_DMA_REQ_UART4_RX 20 +#define MX21_DMA_REQ_UART4_TX 21 +#define MX21_DMA_REQ_UART3_RX 22 +#define MX21_DMA_REQ_UART3_TX 23 +#define MX21_DMA_REQ_UART2_RX 24 +#define MX21_DMA_REQ_UART2_TX 25 +#define MX21_DMA_REQ_UART1_RX 26 +#define MX21_DMA_REQ_UART1_TX 27 +#define MX21_DMA_REQ_BMI_TX 28 +#define MX21_DMA_REQ_BMI_RX 29 +#define MX21_DMA_REQ_CSI_STAT 30 +#define MX21_DMA_REQ_CSI_RX 31 + +#endif /* ifndef __MACH_MX21_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h new file mode 100644 index 00000000..087cd7ac --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/mx25.h @@ -0,0 +1,107 @@ +#ifndef __MACH_MX25_H__ +#define __MACH_MX25_H__ + +#define MX25_AIPS1_BASE_ADDR 0x43f00000 +#define MX25_AIPS1_SIZE SZ_1M +#define MX25_AIPS2_BASE_ADDR 0x53f00000 +#define MX25_AIPS2_SIZE SZ_1M +#define MX25_AVIC_BASE_ADDR 0x68000000 +#define MX25_AVIC_SIZE SZ_1M + +#define MX25_I2C1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x80000) +#define MX25_I2C3_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x84000) +#define MX25_CAN1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x88000) +#define MX25_CAN2_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x8c000) +#define MX25_I2C2_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x98000) +#define MX25_CSPI1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xa4000) +#define MX25_IOMUXC_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xac000) + +#define MX25_CRM_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x80000) +#define MX25_GPT1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x90000) +#define MX25_GPIO4_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x9c000) +#define MX25_PWM2_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa0000) +#define MX25_GPIO3_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa4000) +#define MX25_PWM3_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa8000) +#define MX25_PWM4_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xc8000) +#define MX25_GPIO1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xcc000) +#define MX25_GPIO2_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xd0000) +#define MX25_WDOG_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xdc000) +#define MX25_PWM1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xe0000) + +#define MX25_UART1_BASE_ADDR 0x43f90000 +#define MX25_UART2_BASE_ADDR 0x43f94000 +#define MX25_AUDMUX_BASE_ADDR 0x43fb0000 +#define MX25_UART3_BASE_ADDR 0x5000c000 +#define MX25_UART4_BASE_ADDR 0x50008000 +#define MX25_UART5_BASE_ADDR 0x5002c000 + +#define MX25_CSPI3_BASE_ADDR 0x50004000 +#define MX25_CSPI2_BASE_ADDR 0x50010000 +#define MX25_FEC_BASE_ADDR 0x50038000 +#define MX25_SSI2_BASE_ADDR 0x50014000 +#define MX25_SSI1_BASE_ADDR 0x50034000 +#define MX25_NFC_BASE_ADDR 0xbb000000 +#define MX25_DRYICE_BASE_ADDR 0x53ffc000 +#define MX25_ESDHC1_BASE_ADDR 0x53fb4000 +#define MX25_ESDHC2_BASE_ADDR 0x53fb8000 +#define MX25_LCDC_BASE_ADDR 0x53fbc000 +#define MX25_KPP_BASE_ADDR 0x43fa8000 +#define MX25_SDMA_BASE_ADDR 0x53fd4000 +#define MX25_USB_BASE_ADDR 0x53ff4000 +#define MX25_USB_OTG_BASE_ADDR (MX25_USB_BASE_ADDR + 0x0000) +/* + * The reference manual (IMX25RM, Rev. 1, 06/2009) specifies an offset of 0x200 + * for the host controller. Early documentation drafts specified 0x400 and + * Freescale internal sources confirm only the latter value to work. + */ +#define MX25_USB_HS_BASE_ADDR (MX25_USB_BASE_ADDR + 0x0400) +#define MX25_CSI_BASE_ADDR 0x53ff8000 + +#define MX25_IO_P2V(x) IMX_IO_P2V(x) +#define MX25_IO_ADDRESS(x) IOMEM(MX25_IO_P2V(x)) + +#define MX25_INT_CSPI3 0 +#define MX25_INT_I2C1 3 +#define MX25_INT_I2C2 4 +#define MX25_INT_UART4 5 +#define MX25_INT_ESDHC2 8 +#define MX25_INT_ESDHC1 9 +#define MX25_INT_I2C3 10 +#define MX25_INT_SSI2 11 +#define MX25_INT_SSI1 12 +#define MX25_INT_CSPI2 13 +#define MX25_INT_CSPI1 14 +#define MX25_INT_GPIO3 16 +#define MX25_INT_CSI 17 +#define MX25_INT_UART3 18 +#define MX25_INT_GPIO4 23 +#define MX25_INT_KPP 24 +#define MX25_INT_DRYICE 25 +#define MX25_INT_PWM1 26 +#define MX25_INT_UART2 32 +#define MX25_INT_NFC 33 +#define MX25_INT_SDMA 34 +#define MX25_INT_USB_HS 35 +#define MX25_INT_PWM2 36 +#define MX25_INT_USB_OTG 37 +#define MX25_INT_LCDC 39 +#define MX25_INT_UART5 40 +#define MX25_INT_PWM3 41 +#define MX25_INT_PWM4 42 +#define MX25_INT_CAN1 43 +#define MX25_INT_CAN2 44 +#define MX25_INT_UART1 45 +#define MX25_INT_GPIO2 51 +#define MX25_INT_GPIO1 52 +#define MX25_INT_FEC 57 + +#define MX25_DMA_REQ_SSI2_RX1 22 +#define MX25_DMA_REQ_SSI2_TX1 23 +#define MX25_DMA_REQ_SSI2_RX0 24 +#define MX25_DMA_REQ_SSI2_TX0 25 +#define MX25_DMA_REQ_SSI1_RX1 26 +#define MX25_DMA_REQ_SSI1_TX1 27 +#define MX25_DMA_REQ_SSI1_RX0 28 +#define MX25_DMA_REQ_SSI1_TX0 29 + +#endif /* ifndef __MACH_MX25_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h new file mode 100644 index 00000000..1dc1c522 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/mx27.h @@ -0,0 +1,251 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008 Juergen Beisert, kernel@pengutronix.de + * + * This contains i.MX27-specific hardware definitions. For those + * hardware pieces that are common between i.MX21 and i.MX27, have a + * look at mx2x.h. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#ifndef __MACH_MX27_H__ +#define __MACH_MX27_H__ + +#ifndef __ASSEMBLER__ +#include <linux/io.h> +#endif + +#define MX27_AIPI_BASE_ADDR 0x10000000 +#define MX27_AIPI_SIZE SZ_1M +#define MX27_DMA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x01000) +#define MX27_WDOG_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x02000) +#define MX27_GPT1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x03000) +#define MX27_GPT2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x04000) +#define MX27_GPT3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x05000) +#define MX27_PWM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x06000) +#define MX27_RTC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x07000) +#define MX27_KPP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x08000) +#define MX27_OWIRE_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x09000) +#define MX27_UART1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0a000) +#define MX27_UART2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0b000) +#define MX27_UART3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0c000) +#define MX27_UART4_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0d000) +#define MX27_CSPI1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0e000) +#define MX27_CSPI2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0f000) +#define MX27_SSI1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x10000) +#define MX27_SSI2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x11000) +#define MX27_I2C1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x12000) +#define MX27_SDHC1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x13000) +#define MX27_SDHC2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x14000) +#define MX27_GPIO_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x15000) +#define MX27_GPIO1_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x000) +#define MX27_GPIO2_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x100) +#define MX27_GPIO3_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x200) +#define MX27_GPIO4_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x300) +#define MX27_GPIO5_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x400) +#define MX27_GPIO6_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x500) +#define MX27_AUDMUX_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x16000) +#define MX27_CSPI3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x17000) +#define MX27_MSHC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x18000) +#define MX27_GPT4_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x19000) +#define MX27_GPT5_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1a000) +#define MX27_UART5_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1b000) +#define MX27_UART6_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1c000) +#define MX27_I2C2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1d000) +#define MX27_SDHC3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1e000) +#define MX27_GPT6_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1f000) +#define MX27_LCDC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x21000) +#define MX27_SLCDC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x22000) +#define MX27_VPU_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x23000) +#define MX27_USB_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x24000) +#define MX27_USB_OTG_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0000) +#define MX27_USB_HS1_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0200) +#define MX27_USB_HS2_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0400) +#define MX27_SAHARA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x25000) +#define MX27_EMMAPP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26000) +#define MX27_EMMAPRP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26400) +#define MX27_CCM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x27000) +#define MX27_SYSCTRL_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x27800) +#define MX27_IIM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x28000) +#define MX27_RTIC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x2a000) +#define MX27_FEC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x2b000) +#define MX27_SCC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x2c000) +#define MX27_ETB_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3b000) +#define MX27_ETB_RAM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3c000) +#define MX27_JAM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3e000) +#define MX27_MAX_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3f000) + +#define MX27_AVIC_BASE_ADDR 0x10040000 + +/* ROM patch */ +#define MX27_ROMP_BASE_ADDR 0x10041000 + +#define MX27_SAHB1_BASE_ADDR 0x80000000 +#define MX27_SAHB1_SIZE SZ_1M +#define MX27_CSI_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x0000) +#define MX27_ATA_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x1000) + +/* Memory regions and CS */ +#define MX27_SDRAM_BASE_ADDR 0xa0000000 +#define MX27_CSD1_BASE_ADDR 0xb0000000 + +#define MX27_CS0_BASE_ADDR 0xc0000000 +#define MX27_CS1_BASE_ADDR 0xc8000000 +#define MX27_CS2_BASE_ADDR 0xd0000000 +#define MX27_CS3_BASE_ADDR 0xd2000000 +#define MX27_CS4_BASE_ADDR 0xd4000000 +#define MX27_CS5_BASE_ADDR 0xd6000000 + +/* NAND, SDRAM, WEIM, M3IF, EMI controllers */ +#define MX27_X_MEMC_BASE_ADDR 0xd8000000 +#define MX27_X_MEMC_SIZE SZ_1M +#define MX27_NFC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR) +#define MX27_SDRAMC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x1000) +#define MX27_WEIM_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x2000) +#define MX27_M3IF_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x3000) +#define MX27_PCMCIA_CTL_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x4000) + +#define MX27_WEIM_CSCRx_BASE_ADDR(cs) (MX27_WEIM_BASE_ADDR + (cs) * 0x10) +#define MX27_WEIM_CSCRxU(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs)) +#define MX27_WEIM_CSCRxL(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs) + 0x4) +#define MX27_WEIM_CSCRxA(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs) + 0x8) + +#define MX27_PCMCIA_MEM_BASE_ADDR 0xdc000000 + +/* IRAM */ +#define MX27_IRAM_BASE_ADDR 0xffff4c00 /* internal ram */ + +#define MX27_IO_P2V(x) IMX_IO_P2V(x) +#define MX27_IO_ADDRESS(x) IOMEM(MX27_IO_P2V(x)) + +#ifndef __ASSEMBLER__ +static inline void mx27_setup_weimcs(size_t cs, + unsigned upper, unsigned lower, unsigned addional) +{ + __raw_writel(upper, MX27_IO_ADDRESS(MX27_WEIM_CSCRxU(cs))); + __raw_writel(lower, MX27_IO_ADDRESS(MX27_WEIM_CSCRxL(cs))); + __raw_writel(addional, MX27_IO_ADDRESS(MX27_WEIM_CSCRxA(cs))); +} +#endif + +/* fixed interrupt numbers */ +#define MX27_INT_I2C2 1 +#define MX27_INT_GPT6 2 +#define MX27_INT_GPT5 3 +#define MX27_INT_GPT4 4 +#define MX27_INT_RTIC 5 +#define MX27_INT_CSPI3 6 +#define MX27_INT_SDHC 7 +#define MX27_INT_GPIO 8 +#define MX27_INT_SDHC3 9 +#define MX27_INT_SDHC2 10 +#define MX27_INT_SDHC1 11 +#define MX27_INT_I2C1 12 +#define MX27_INT_SSI2 13 +#define MX27_INT_SSI1 14 +#define MX27_INT_CSPI2 15 +#define MX27_INT_CSPI1 16 +#define MX27_INT_UART4 17 +#define MX27_INT_UART3 18 +#define MX27_INT_UART2 19 +#define MX27_INT_UART1 20 +#define MX27_INT_KPP 21 +#define MX27_INT_RTC 22 +#define MX27_INT_PWM 23 +#define MX27_INT_GPT3 24 +#define MX27_INT_GPT2 25 +#define MX27_INT_GPT1 26 +#define MX27_INT_WDOG 27 +#define MX27_INT_PCMCIA 28 +#define MX27_INT_NFC 29 +#define MX27_INT_ATA 30 +#define MX27_INT_CSI 31 +#define MX27_INT_DMACH0 32 +#define MX27_INT_DMACH1 33 +#define MX27_INT_DMACH2 34 +#define MX27_INT_DMACH3 35 +#define MX27_INT_DMACH4 36 +#define MX27_INT_DMACH5 37 +#define MX27_INT_DMACH6 38 +#define MX27_INT_DMACH7 39 +#define MX27_INT_DMACH8 40 +#define MX27_INT_DMACH9 41 +#define MX27_INT_DMACH10 42 +#define MX27_INT_DMACH11 43 +#define MX27_INT_DMACH12 44 +#define MX27_INT_DMACH13 45 +#define MX27_INT_DMACH14 46 +#define MX27_INT_DMACH15 47 +#define MX27_INT_UART6 48 +#define MX27_INT_UART5 49 +#define MX27_INT_FEC 50 +#define MX27_INT_EMMAPRP 51 +#define MX27_INT_EMMAPP 52 +#define MX27_INT_VPU 53 +#define MX27_INT_USB_HS1 54 +#define MX27_INT_USB_HS2 55 +#define MX27_INT_USB_OTG 56 +#define MX27_INT_SCC_SMN 57 +#define MX27_INT_SCC_SCM 58 +#define MX27_INT_SAHARA 59 +#define MX27_INT_SLCDC 60 +#define MX27_INT_LCDC 61 +#define MX27_INT_IIM 62 +#define MX27_INT_CCM 63 + +/* fixed DMA request numbers */ +#define MX27_DMA_REQ_CSPI3_RX 1 +#define MX27_DMA_REQ_CSPI3_TX 2 +#define MX27_DMA_REQ_EXT 3 +#define MX27_DMA_REQ_MSHC 4 +#define MX27_DMA_REQ_SDHC2 6 +#define MX27_DMA_REQ_SDHC1 7 +#define MX27_DMA_REQ_SSI2_RX0 8 +#define MX27_DMA_REQ_SSI2_TX0 9 +#define MX27_DMA_REQ_SSI2_RX1 10 +#define MX27_DMA_REQ_SSI2_TX1 11 +#define MX27_DMA_REQ_SSI1_RX0 12 +#define MX27_DMA_REQ_SSI1_TX0 13 +#define MX27_DMA_REQ_SSI1_RX1 14 +#define MX27_DMA_REQ_SSI1_TX1 15 +#define MX27_DMA_REQ_CSPI2_RX 16 +#define MX27_DMA_REQ_CSPI2_TX 17 +#define MX27_DMA_REQ_CSPI1_RX 18 +#define MX27_DMA_REQ_CSPI1_TX 19 +#define MX27_DMA_REQ_UART4_RX 20 +#define MX27_DMA_REQ_UART4_TX 21 +#define MX27_DMA_REQ_UART3_RX 22 +#define MX27_DMA_REQ_UART3_TX 23 +#define MX27_DMA_REQ_UART2_RX 24 +#define MX27_DMA_REQ_UART2_TX 25 +#define MX27_DMA_REQ_UART1_RX 26 +#define MX27_DMA_REQ_UART1_TX 27 +#define MX27_DMA_REQ_ATA_TX 28 +#define MX27_DMA_REQ_ATA_RCV 29 +#define MX27_DMA_REQ_CSI_STAT 30 +#define MX27_DMA_REQ_CSI_RX 31 +#define MX27_DMA_REQ_UART5_TX 32 +#define MX27_DMA_REQ_UART5_RX 33 +#define MX27_DMA_REQ_UART6_TX 34 +#define MX27_DMA_REQ_UART6_RX 35 +#define MX27_DMA_REQ_SDHC3 36 +#define MX27_DMA_REQ_NFC 37 + +#ifndef __ASSEMBLY__ +extern int mx27_revision(void); +#endif + +#endif /* ifndef __MACH_MX27_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx2_cam.h b/arch/arm/plat-mxc/include/mach/mx2_cam.h new file mode 100644 index 00000000..3c080a32 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/mx2_cam.h @@ -0,0 +1,46 @@ +/* + * mx2-cam.h - i.MX27/i.MX25 camera driver header file + * + * Copyright (C) 2003, Intel Corporation + * Copyright (C) 2008, Sascha Hauer <s.hauer@pengutronix.de> + * Copyright (C) 2010, Baruch Siach <baruch@tkos.co.il> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __MACH_MX2_CAM_H_ +#define __MACH_MX2_CAM_H_ + +#define MX2_CAMERA_SWAP16 (1 << 0) +#define MX2_CAMERA_EXT_VSYNC (1 << 1) +#define MX2_CAMERA_CCIR (1 << 2) +#define MX2_CAMERA_CCIR_INTERLACE (1 << 3) +#define MX2_CAMERA_HSYNC_HIGH (1 << 4) +#define MX2_CAMERA_GATED_CLOCK (1 << 5) +#define MX2_CAMERA_INV_DATA (1 << 6) +#define MX2_CAMERA_PCLK_SAMPLE_RISING (1 << 7) +#define MX2_CAMERA_PACK_DIR_MSB (1 << 8) + +/** + * struct mx2_camera_platform_data - optional platform data for mx2_camera + * @flags: any combination of MX2_CAMERA_* + * @clk: clock rate of the csi block / 2 + */ +struct mx2_camera_platform_data { + unsigned long flags; + unsigned long clk; +}; + +#endif /* __MACH_MX2_CAM_H_ */ diff --git a/arch/arm/plat-mxc/include/mach/mx2x.h b/arch/arm/plat-mxc/include/mach/mx2x.h new file mode 100644 index 00000000..6d07839f --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/mx2x.h @@ -0,0 +1,144 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008 Juergen Beisert, kernel@pengutronix.de + * + * This contains hardware definitions that are common between i.MX21 and + * i.MX27. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#ifndef __MACH_MX2x_H__ +#define __MACH_MX2x_H__ + +/* The following addresses are common between i.MX21 and i.MX27 */ + +/* Register offsets */ +#define MX2x_AIPI_BASE_ADDR 0x10000000 +#define MX2x_AIPI_SIZE SZ_1M +#define MX2x_DMA_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x01000) +#define MX2x_WDOG_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x02000) +#define MX2x_GPT1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x03000) +#define MX2x_GPT2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x04000) +#define MX2x_GPT3_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x05000) +#define MX2x_PWM_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x06000) +#define MX2x_RTC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x07000) +#define MX2x_KPP_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x08000) +#define MX2x_OWIRE_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x09000) +#define MX2x_UART1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0a000) +#define MX2x_UART2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0b000) +#define MX2x_UART3_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0c000) +#define MX2x_UART4_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0d000) +#define MX2x_CSPI1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0e000) +#define MX2x_CSPI2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0f000) +#define MX2x_SSI1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x10000) +#define MX2x_SSI2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x11000) +#define MX2x_I2C_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x12000) +#define MX2x_SDHC1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x13000) +#define MX2x_SDHC2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x14000) +#define MX2x_GPIO_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x15000) +#define MX2x_AUDMUX_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x16000) +#define MX2x_CSPI3_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x17000) +#define MX2x_LCDC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x21000) +#define MX2x_SLCDC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x22000) +#define MX2x_USBOTG_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x24000) +#define MX2x_EMMA_PP_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x26000) +#define MX2x_EMMA_PRP_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x26400) +#define MX2x_CCM_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x27000) +#define MX2x_SYSCTRL_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x27800) +#define MX2x_JAM_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x3e000) +#define MX2x_MAX_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x3f000) + +#define MX2x_AVIC_BASE_ADDR 0x10040000 + +#define MX2x_SAHB1_BASE_ADDR 0x80000000 +#define MX2x_SAHB1_SIZE SZ_1M +#define MX2x_CSI_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x0000) + +/* fixed interrupt numbers */ +#define MX2x_INT_CSPI3 6 +#define MX2x_INT_GPIO 8 +#define MX2x_INT_SDHC2 10 +#define MX2x_INT_SDHC1 11 +#define MX2x_INT_I2C 12 +#define MX2x_INT_SSI2 13 +#define MX2x_INT_SSI1 14 +#define MX2x_INT_CSPI2 15 +#define MX2x_INT_CSPI1 16 +#define MX2x_INT_UART4 17 +#define MX2x_INT_UART3 18 +#define MX2x_INT_UART2 19 +#define MX2x_INT_UART1 20 +#define MX2x_INT_KPP 21 +#define MX2x_INT_RTC 22 +#define MX2x_INT_PWM 23 +#define MX2x_INT_GPT3 24 +#define MX2x_INT_GPT2 25 +#define MX2x_INT_GPT1 26 +#define MX2x_INT_WDOG 27 +#define MX2x_INT_PCMCIA 28 +#define MX2x_INT_NANDFC 29 +#define MX2x_INT_CSI 31 +#define MX2x_INT_DMACH0 32 +#define MX2x_INT_DMACH1 33 +#define MX2x_INT_DMACH2 34 +#define MX2x_INT_DMACH3 35 +#define MX2x_INT_DMACH4 36 +#define MX2x_INT_DMACH5 37 +#define MX2x_INT_DMACH6 38 +#define MX2x_INT_DMACH7 39 +#define MX2x_INT_DMACH8 40 +#define MX2x_INT_DMACH9 41 +#define MX2x_INT_DMACH10 42 +#define MX2x_INT_DMACH11 43 +#define MX2x_INT_DMACH12 44 +#define MX2x_INT_DMACH13 45 +#define MX2x_INT_DMACH14 46 +#define MX2x_INT_DMACH15 47 +#define MX2x_INT_EMMAPRP 51 +#define MX2x_INT_EMMAPP 52 +#define MX2x_INT_SLCDC 60 +#define MX2x_INT_LCDC 61 + +/* fixed DMA request numbers */ +#define MX2x_DMA_REQ_CSPI3_RX 1 +#define MX2x_DMA_REQ_CSPI3_TX 2 +#define MX2x_DMA_REQ_EXT 3 +#define MX2x_DMA_REQ_SDHC2 6 +#define MX2x_DMA_REQ_SDHC1 7 +#define MX2x_DMA_REQ_SSI2_RX0 8 +#define MX2x_DMA_REQ_SSI2_TX0 9 +#define MX2x_DMA_REQ_SSI2_RX1 10 +#define MX2x_DMA_REQ_SSI2_TX1 11 +#define MX2x_DMA_REQ_SSI1_RX0 12 +#define MX2x_DMA_REQ_SSI1_TX0 13 +#define MX2x_DMA_REQ_SSI1_RX1 14 +#define MX2x_DMA_REQ_SSI1_TX1 15 +#define MX2x_DMA_REQ_CSPI2_RX 16 +#define MX2x_DMA_REQ_CSPI2_TX 17 +#define MX2x_DMA_REQ_CSPI1_RX 18 +#define MX2x_DMA_REQ_CSPI1_TX 19 +#define MX2x_DMA_REQ_UART4_RX 20 +#define MX2x_DMA_REQ_UART4_TX 21 +#define MX2x_DMA_REQ_UART3_RX 22 +#define MX2x_DMA_REQ_UART3_TX 23 +#define MX2x_DMA_REQ_UART2_RX 24 +#define MX2x_DMA_REQ_UART2_TX 25 +#define MX2x_DMA_REQ_UART1_RX 26 +#define MX2x_DMA_REQ_UART1_TX 27 +#define MX2x_DMA_REQ_CSI_STAT 30 +#define MX2x_DMA_REQ_CSI_RX 31 + +#endif /* ifndef __MACH_MX2x_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h new file mode 100644 index 00000000..79e7fc01 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/mx31.h @@ -0,0 +1,206 @@ +#ifndef __MACH_MX31_H__ +#define __MACH_MX31_H__ + +#ifndef __ASSEMBLER__ +#include <linux/io.h> +#endif + +/* + * IRAM + */ +#define MX31_IRAM_BASE_ADDR 0x1ffc0000 /* internal ram */ +#define MX31_IRAM_SIZE SZ_16K + +#define MX31_L2CC_BASE_ADDR 0x30000000 +#define MX31_L2CC_SIZE SZ_1M + +#define MX31_AIPS1_BASE_ADDR 0x43f00000 +#define MX31_AIPS1_SIZE SZ_1M +#define MX31_MAX_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x04000) +#define MX31_EVTMON_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x08000) +#define MX31_CLKCTL_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x0c000) +#define MX31_ETB_SLOT4_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x10000) +#define MX31_ETB_SLOT5_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x14000) +#define MX31_ECT_CTIO_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x18000) +#define MX31_I2C1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x80000) +#define MX31_I2C3_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x84000) +#define MX31_USB_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x88000) +#define MX31_USB_OTG_BASE_ADDR (MX31_USB_BASE_ADDR + 0x0000) +#define MX31_USB_HS1_BASE_ADDR (MX31_USB_BASE_ADDR + 0x0200) +#define MX31_USB_HS2_BASE_ADDR (MX31_USB_BASE_ADDR + 0x0400) +#define MX31_ATA_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x8c000) +#define MX31_UART1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x90000) +#define MX31_UART2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x94000) +#define MX31_I2C2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x98000) +#define MX31_OWIRE_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x9c000) +#define MX31_SSI1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xa0000) +#define MX31_CSPI1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xa4000) +#define MX31_KPP_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xa8000) +#define MX31_IOMUXC_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xac000) +#define MX31_UART4_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xb0000) +#define MX31_UART5_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xb4000) +#define MX31_ECT_IP1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xb8000) +#define MX31_ECT_IP2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xbc000) + +#define MX31_SPBA0_BASE_ADDR 0x50000000 +#define MX31_SPBA0_SIZE SZ_1M +#define MX31_SDHC1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x04000) +#define MX31_SDHC2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x08000) +#define MX31_UART3_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x0c000) +#define MX31_CSPI2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x10000) +#define MX31_SSI2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x14000) +#define MX31_SIM1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x18000) +#define MX31_IIM_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x1c000) +#define MX31_ATA_DMA_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x20000) +#define MX31_MSHC1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x24000) +#define MX31_SPBA_CTRL_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x3c000) + +#define MX31_AIPS2_BASE_ADDR 0x53f00000 +#define MX31_AIPS2_SIZE SZ_1M +#define MX31_CCM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x80000) +#define MX31_CSPI3_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x84000) +#define MX31_FIRI_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x8c000) +#define MX31_GPT1_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x90000) +#define MX31_EPIT1_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x94000) +#define MX31_EPIT2_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x98000) +#define MX31_GPIO3_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xa4000) +#define MX31_SCC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xac000) +#define MX31_SCM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xae000) +#define MX31_SMN_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xaf000) +#define MX31_RNGA_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xb0000) +#define MX31_IPU_CTRL_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xc0000) +#define MX31_AUDMUX_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xc4000) +#define MX31_MPEG4_ENC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xc8000) +#define MX31_GPIO1_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xcc000) +#define MX31_GPIO2_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xd0000) +#define MX31_SDMA_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xd4000) +#define MX31_RTC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xd8000) +#define MX31_WDOG_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xdc000) +#define MX31_PWM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xe0000) +#define MX31_RTIC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xec000) + +#define MX31_ROMP_BASE_ADDR 0x60000000 +#define MX31_ROMP_BASE_ADDR_VIRT 0xfc500000 +#define MX31_ROMP_SIZE SZ_1M + +#define MX31_AVIC_BASE_ADDR 0x68000000 +#define MX31_AVIC_SIZE SZ_1M + +#define MX31_IPU_MEM_BASE_ADDR 0x70000000 +#define MX31_CSD0_BASE_ADDR 0x80000000 +#define MX31_CSD1_BASE_ADDR 0x90000000 + +#define MX31_CS0_BASE_ADDR 0xa0000000 +#define MX31_CS1_BASE_ADDR 0xa8000000 +#define MX31_CS2_BASE_ADDR 0xb0000000 +#define MX31_CS3_BASE_ADDR 0xb2000000 + +#define MX31_CS4_BASE_ADDR 0xb4000000 +#define MX31_CS4_BASE_ADDR_VIRT 0xf6000000 +#define MX31_CS4_SIZE SZ_32M + +#define MX31_CS5_BASE_ADDR 0xb6000000 +#define MX31_CS5_BASE_ADDR_VIRT 0xf8000000 +#define MX31_CS5_SIZE SZ_32M + +#define MX31_X_MEMC_BASE_ADDR 0xb8000000 +#define MX31_X_MEMC_SIZE SZ_64K +#define MX31_NFC_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x0000) +#define MX31_ESDCTL_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x1000) +#define MX31_WEIM_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x2000) +#define MX31_M3IF_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x3000) +#define MX31_EMI_CTL_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x4000) +#define MX31_PCMCIA_CTL_BASE_ADDR MX31_EMI_CTL_BASE_ADDR + +#define MX31_WEIM_CSCRx_BASE_ADDR(cs) (MX31_WEIM_BASE_ADDR + (cs) * 0x10) +#define MX31_WEIM_CSCRxU(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs)) +#define MX31_WEIM_CSCRxL(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs) + 0x4) +#define MX31_WEIM_CSCRxA(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs) + 0x8) + +#define MX31_PCMCIA_MEM_BASE_ADDR 0xbc000000 + +#define MX31_IO_P2V(x) IMX_IO_P2V(x) +#define MX31_IO_ADDRESS(x) IOMEM(MX31_IO_P2V(x)) + +#ifndef __ASSEMBLER__ +static inline void mx31_setup_weimcs(size_t cs, + unsigned upper, unsigned lower, unsigned addional) +{ + __raw_writel(upper, MX31_IO_ADDRESS(MX31_WEIM_CSCRxU(cs))); + __raw_writel(lower, MX31_IO_ADDRESS(MX31_WEIM_CSCRxL(cs))); + __raw_writel(addional, MX31_IO_ADDRESS(MX31_WEIM_CSCRxA(cs))); +} +#endif + +#define MX31_INT_I2C3 3 +#define MX31_INT_I2C2 4 +#define MX31_INT_MPEG4_ENCODER 5 +#define MX31_INT_RTIC 6 +#define MX31_INT_FIRI 7 +#define MX31_INT_SDHC2 8 +#define MX31_INT_SDHC1 9 +#define MX31_INT_I2C1 10 +#define MX31_INT_SSI2 11 +#define MX31_INT_SSI1 12 +#define MX31_INT_CSPI2 13 +#define MX31_INT_CSPI1 14 +#define MX31_INT_ATA 15 +#define MX31_INT_MBX 16 +#define MX31_INT_CSPI3 17 +#define MX31_INT_UART3 18 +#define MX31_INT_IIM 19 +#define MX31_INT_SIM2 20 +#define MX31_INT_SIM1 21 +#define MX31_INT_RNGA 22 +#define MX31_INT_EVTMON 23 +#define MX31_INT_KPP 24 +#define MX31_INT_RTC 25 +#define MX31_INT_PWM 26 +#define MX31_INT_EPIT2 27 +#define MX31_INT_EPIT1 28 +#define MX31_INT_GPT 29 +#define MX31_INT_POWER_FAIL 30 +#define MX31_INT_CCM_DVFS 31 +#define MX31_INT_UART2 32 +#define MX31_INT_NFC 33 +#define MX31_INT_SDMA 34 +#define MX31_INT_USB_HS1 35 +#define MX31_INT_USB_HS2 36 +#define MX31_INT_USB_OTG 37 +#define MX31_INT_MSHC1 39 +#define MX31_INT_MSHC2 40 +#define MX31_INT_IPU_ERR 41 +#define MX31_INT_IPU_SYN 42 +#define MX31_INT_UART1 45 +#define MX31_INT_UART4 46 +#define MX31_INT_UART5 47 +#define MX31_INT_ECT 48 +#define MX31_INT_SCC_SCM 49 +#define MX31_INT_SCC_SMN 50 +#define MX31_INT_GPIO2 51 +#define MX31_INT_GPIO1 52 +#define MX31_INT_CCM 53 +#define MX31_INT_PCMCIA 54 +#define MX31_INT_WDOG 55 +#define MX31_INT_GPIO3 56 +#define MX31_INT_EXT_POWER 58 +#define MX31_INT_EXT_TEMPER 59 +#define MX31_INT_EXT_SENSOR60 60 +#define MX31_INT_EXT_SENSOR61 61 +#define MX31_INT_EXT_WDOG 62 +#define MX31_INT_EXT_TV 63 + +#define MX31_DMA_REQ_SDHC1 20 +#define MX31_DMA_REQ_SDHC2 21 +#define MX31_DMA_REQ_SSI2_RX1 22 +#define MX31_DMA_REQ_SSI2_TX1 23 +#define MX31_DMA_REQ_SSI2_RX0 24 +#define MX31_DMA_REQ_SSI2_TX0 25 +#define MX31_DMA_REQ_SSI1_RX1 26 +#define MX31_DMA_REQ_SSI1_TX1 27 +#define MX31_DMA_REQ_SSI1_RX0 28 +#define MX31_DMA_REQ_SSI1_TX0 29 + +#define MX31_PROD_SIGNATURE 0x1 /* For MX31 */ + +#endif /* ifndef __MACH_MX31_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx35.h b/arch/arm/plat-mxc/include/mach/mx35.h new file mode 100644 index 00000000..d13dbfee --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/mx35.h @@ -0,0 +1,189 @@ +#ifndef __MACH_MX35_H__ +#define __MACH_MX35_H__ + +/* + * IRAM + */ +#define MX35_IRAM_BASE_ADDR 0x10000000 /* internal ram */ +#define MX35_IRAM_SIZE SZ_128K + +#define MX35_L2CC_BASE_ADDR 0x30000000 +#define MX35_L2CC_SIZE SZ_1M + +#define MX35_AIPS1_BASE_ADDR 0x43f00000 +#define MX35_AIPS1_SIZE SZ_1M +#define MX35_MAX_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x04000) +#define MX35_EVTMON_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x08000) +#define MX35_CLKCTL_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x0c000) +#define MX35_ETB_SLOT4_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x10000) +#define MX35_ETB_SLOT5_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x14000) +#define MX35_ECT_CTIO_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x18000) +#define MX35_I2C1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x80000) +#define MX35_I2C3_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x84000) +#define MX35_UART1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x90000) +#define MX35_UART2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x94000) +#define MX35_I2C2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x98000) +#define MX35_OWIRE_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x9c000) +#define MX35_SSI1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xa0000) +#define MX35_CSPI1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xa4000) +#define MX35_KPP_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xa8000) +#define MX35_IOMUXC_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xac000) +#define MX35_ECT_IP1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xb8000) +#define MX35_ECT_IP2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xbc000) + +#define MX35_SPBA0_BASE_ADDR 0x50000000 +#define MX35_SPBA0_SIZE SZ_1M +#define MX35_UART3_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x0c000) +#define MX35_CSPI2_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x10000) +#define MX35_SSI2_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x14000) +#define MX35_ATA_DMA_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x20000) +#define MX35_MSHC1_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x24000) +#define MX35_FEC_BASE_ADDR 0x50038000 +#define MX35_SPBA_CTRL_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x3c000) + +#define MX35_AIPS2_BASE_ADDR 0x53f00000 +#define MX35_AIPS2_SIZE SZ_1M +#define MX35_CCM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x80000) +#define MX35_GPT1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x90000) +#define MX35_EPIT1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x94000) +#define MX35_EPIT2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x98000) +#define MX35_GPIO3_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xa4000) +#define MX35_SCC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xac000) +#define MX35_RNGA_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xb0000) +#define MX35_ESDHC1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xb4000) +#define MX35_ESDHC2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xb8000) +#define MX35_ESDHC3_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xbc000) +#define MX35_IPU_CTRL_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xc0000) +#define MX35_AUDMUX_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xc4000) +#define MX35_GPIO1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xcc000) +#define MX35_GPIO2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xd0000) +#define MX35_SDMA_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xd4000) +#define MX35_RTC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xd8000) +#define MX35_WDOG_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xdc000) +#define MX35_PWM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe0000) +#define MX35_CAN1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe4000) +#define MX35_CAN2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe8000) +#define MX35_RTIC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xec000) +#define MX35_IIM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xf0000) +#define MX35_USB_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xf4000) +#define MX35_USB_OTG_BASE_ADDR (MX35_USB_BASE_ADDR + 0x0000) +/* + * The Reference Manual (IMX35RM, Rev. 2, 3/2009) claims an offset of 0x200 for + * HS. When host support was implemented only a preliminary document was + * available, which told 0x400. This works fine. + */ +#define MX35_USB_HS_BASE_ADDR (MX35_USB_BASE_ADDR + 0x0400) + +#define MX35_ROMP_BASE_ADDR 0x60000000 +#define MX35_ROMP_SIZE SZ_1M + +#define MX35_AVIC_BASE_ADDR 0x68000000 +#define MX35_AVIC_SIZE SZ_1M + +/* + * Memory regions and CS + */ +#define MX35_IPU_MEM_BASE_ADDR 0x70000000 +#define MX35_CSD0_BASE_ADDR 0x80000000 +#define MX35_CSD1_BASE_ADDR 0x90000000 + +#define MX35_CS0_BASE_ADDR 0xa0000000 +#define MX35_CS1_BASE_ADDR 0xa8000000 +#define MX35_CS2_BASE_ADDR 0xb0000000 +#define MX35_CS3_BASE_ADDR 0xb2000000 + +#define MX35_CS4_BASE_ADDR 0xb4000000 +#define MX35_CS4_BASE_ADDR_VIRT 0xf6000000 +#define MX35_CS4_SIZE SZ_32M + +#define MX35_CS5_BASE_ADDR 0xb6000000 +#define MX35_CS5_BASE_ADDR_VIRT 0xf8000000 +#define MX35_CS5_SIZE SZ_32M + +/* + * NAND, SDRAM, WEIM, M3IF, EMI controllers + */ +#define MX35_X_MEMC_BASE_ADDR 0xb8000000 +#define MX35_X_MEMC_SIZE SZ_64K +#define MX35_ESDCTL_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x1000) +#define MX35_WEIM_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x2000) +#define MX35_M3IF_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x3000) +#define MX35_EMI_CTL_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x4000) +#define MX35_PCMCIA_CTL_BASE_ADDR MX35_EMI_CTL_BASE_ADDR + +#define MX35_NFC_BASE_ADDR 0xbb000000 +#define MX35_PCMCIA_MEM_BASE_ADDR 0xbc000000 + +#define MX35_IO_P2V(x) IMX_IO_P2V(x) +#define MX35_IO_ADDRESS(x) IOMEM(MX35_IO_P2V(x)) + +/* + * Interrupt numbers + */ +#define MX35_INT_OWIRE 2 +#define MX35_INT_I2C3 3 +#define MX35_INT_I2C2 4 +#define MX35_INT_RTIC 6 +#define MX35_INT_ESDHC1 7 +#define MX35_INT_ESDHC2 8 +#define MX35_INT_ESDHC3 9 +#define MX35_INT_I2C1 10 +#define MX35_INT_SSI1 11 +#define MX35_INT_SSI2 12 +#define MX35_INT_CSPI2 13 +#define MX35_INT_CSPI1 14 +#define MX35_INT_ATA 15 +#define MX35_INT_GPU2D 16 +#define MX35_INT_ASRC 17 +#define MX35_INT_UART3 18 +#define MX35_INT_IIM 19 +#define MX35_INT_RNGA 22 +#define MX35_INT_EVTMON 23 +#define MX35_INT_KPP 24 +#define MX35_INT_RTC 25 +#define MX35_INT_PWM 26 +#define MX35_INT_EPIT2 27 +#define MX35_INT_EPIT1 28 +#define MX35_INT_GPT 29 +#define MX35_INT_POWER_FAIL 30 +#define MX35_INT_UART2 32 +#define MX35_INT_NFC 33 +#define MX35_INT_SDMA 34 +#define MX35_INT_USB_HS 35 +#define MX35_INT_USB_OTG 37 +#define MX35_INT_MSHC1 39 +#define MX35_INT_ESAI 40 +#define MX35_INT_IPU_ERR 41 +#define MX35_INT_IPU_SYN 42 +#define MX35_INT_CAN1 43 +#define MX35_INT_CAN2 44 +#define MX35_INT_UART1 45 +#define MX35_INT_MLB 46 +#define MX35_INT_SPDIF 47 +#define MX35_INT_ECT 48 +#define MX35_INT_SCC_SCM 49 +#define MX35_INT_SCC_SMN 50 +#define MX35_INT_GPIO2 51 +#define MX35_INT_GPIO1 52 +#define MX35_INT_WDOG 55 +#define MX35_INT_GPIO3 56 +#define MX35_INT_FEC 57 +#define MX35_INT_EXT_POWER 58 +#define MX35_INT_EXT_TEMPER 59 +#define MX35_INT_EXT_SENSOR60 60 +#define MX35_INT_EXT_SENSOR61 61 +#define MX35_INT_EXT_WDOG 62 +#define MX35_INT_EXT_TV 63 + +#define MX35_DMA_REQ_SSI2_RX1 22 +#define MX35_DMA_REQ_SSI2_TX1 23 +#define MX35_DMA_REQ_SSI2_RX0 24 +#define MX35_DMA_REQ_SSI2_TX0 25 +#define MX35_DMA_REQ_SSI1_RX1 26 +#define MX35_DMA_REQ_SSI1_TX1 27 +#define MX35_DMA_REQ_SSI1_RX0 28 +#define MX35_DMA_REQ_SSI1_TX0 29 + +#define MX35_PROD_SIGNATURE 0x1 /* For MX31 */ + +#endif /* ifndef __MACH_MX35_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx3_camera.h b/arch/arm/plat-mxc/include/mach/mx3_camera.h new file mode 100644 index 00000000..f226ee37 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/mx3_camera.h @@ -0,0 +1,48 @@ +/* + * mx3_camera.h - i.MX3x camera driver header file + * + * Copyright (C) 2008, Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _MX3_CAMERA_H_ +#define _MX3_CAMERA_H_ + +#include <linux/device.h> + +#define MX3_CAMERA_CLK_SRC 1 +#define MX3_CAMERA_EXT_VSYNC 2 +#define MX3_CAMERA_DP 4 +#define MX3_CAMERA_PCP 8 +#define MX3_CAMERA_HSP 0x10 +#define MX3_CAMERA_VSP 0x20 +#define MX3_CAMERA_DATAWIDTH_4 0x40 +#define MX3_CAMERA_DATAWIDTH_8 0x80 +#define MX3_CAMERA_DATAWIDTH_10 0x100 +#define MX3_CAMERA_DATAWIDTH_15 0x200 + +#define MX3_CAMERA_DATAWIDTH_MASK (MX3_CAMERA_DATAWIDTH_4 | MX3_CAMERA_DATAWIDTH_8 | \ + MX3_CAMERA_DATAWIDTH_10 | MX3_CAMERA_DATAWIDTH_15) + +/** + * struct mx3_camera_pdata - i.MX3x camera platform data + * @flags: MX3_CAMERA_* flags + * @mclk_10khz: master clock frequency in 10kHz units + * @dma_dev: IPU DMA device to match against in channel allocation + */ +struct mx3_camera_pdata { + unsigned long flags; + unsigned long mclk_10khz; + struct device *dma_dev; +}; + +#endif diff --git a/arch/arm/plat-mxc/include/mach/mx3fb.h b/arch/arm/plat-mxc/include/mach/mx3fb.h new file mode 100644 index 00000000..ac24c5c4 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/mx3fb.h @@ -0,0 +1,38 @@ +/* + * Copyright (C) 2008 + * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_MX3FB_H__ +#define __ASM_ARCH_MX3FB_H__ + +#include <linux/device.h> +#include <linux/fb.h> + +/* Proprietary FB_SYNC_ flags */ +#define FB_SYNC_OE_ACT_HIGH 0x80000000 +#define FB_SYNC_CLK_INVERT 0x40000000 +#define FB_SYNC_DATA_INVERT 0x20000000 +#define FB_SYNC_CLK_IDLE_EN 0x10000000 +#define FB_SYNC_SHARP_MODE 0x08000000 +#define FB_SYNC_SWAP_RGB 0x04000000 +#define FB_SYNC_CLK_SEL_EN 0x02000000 + +/** + * struct mx3fb_platform_data - mx3fb platform data + * + * @dma_dev: pointer to the dma-device, used for dma-slave connection + * @mode: pointer to a platform-provided per mxc_register_fb() videomode + */ +struct mx3fb_platform_data { + struct device *dma_dev; + const char *name; + const struct fb_videomode *mode; + int num_modes; +}; + +#endif diff --git a/arch/arm/plat-mxc/include/mach/mx3x.h b/arch/arm/plat-mxc/include/mach/mx3x.h new file mode 100644 index 00000000..388a407d --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/mx3x.h @@ -0,0 +1,208 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __MACH_MX3x_H__ +#define __MACH_MX3x_H__ + +/* + * MX31 memory map: + * + * Virt Phys Size What + * --------------------------------------------------------------------------- + * FC000000 43F00000 1M AIPS 1 + * FC100000 50000000 1M SPBA + * FC200000 53F00000 1M AIPS 2 + * FC500000 60000000 128M ROMPATCH + * FC400000 68000000 128M AVIC + * 70000000 256M IPU (MAX M2) + * 80000000 256M CSD0 SDRAM/DDR + * 90000000 256M CSD1 SDRAM/DDR + * A0000000 128M CS0 Flash + * A8000000 128M CS1 Flash + * B0000000 32M CS2 + * B2000000 32M CS3 + * F4000000 B4000000 32M CS4 + * B6000000 32M CS5 + * FC320000 B8000000 64K NAND, SDRAM, WEIM, M3IF, EMI controllers + * C0000000 64M PCMCIA/CF + */ + +/* + * L2CC + */ +#define MX3x_L2CC_BASE_ADDR 0x30000000 +#define MX3x_L2CC_SIZE SZ_1M + +/* + * AIPS 1 + */ +#define MX3x_AIPS1_BASE_ADDR 0x43f00000 +#define MX3x_AIPS1_SIZE SZ_1M +#define MX3x_MAX_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x04000) +#define MX3x_EVTMON_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x08000) +#define MX3x_CLKCTL_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x0c000) +#define MX3x_ETB_SLOT4_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x10000) +#define MX3x_ETB_SLOT5_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x14000) +#define MX3x_ECT_CTIO_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x18000) +#define MX3x_I2C_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x80000) +#define MX3x_I2C3_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x84000) +#define MX3x_UART1_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x90000) +#define MX3x_UART2_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x94000) +#define MX3x_I2C2_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x98000) +#define MX3x_OWIRE_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x9c000) +#define MX3x_SSI1_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xa0000) +#define MX3x_CSPI1_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xa4000) +#define MX3x_KPP_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xa8000) +#define MX3x_IOMUXC_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xac000) +#define MX3x_ECT_IP1_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xb8000) +#define MX3x_ECT_IP2_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xbc000) + +/* + * SPBA global module enabled #0 + */ +#define MX3x_SPBA0_BASE_ADDR 0x50000000 +#define MX3x_SPBA0_SIZE SZ_1M +#define MX3x_UART3_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x0c000) +#define MX3x_CSPI2_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x10000) +#define MX3x_SSI2_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x14000) +#define MX3x_ATA_DMA_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x20000) +#define MX3x_MSHC1_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x24000) +#define MX3x_SPBA_CTRL_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x3c000) + +/* + * AIPS 2 + */ +#define MX3x_AIPS2_BASE_ADDR 0x53f00000 +#define MX3x_AIPS2_SIZE SZ_1M +#define MX3x_CCM_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x80000) +#define MX3x_GPT1_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x90000) +#define MX3x_EPIT1_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x94000) +#define MX3x_EPIT2_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x98000) +#define MX3x_GPIO3_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xa4000) +#define MX3x_SCC_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xac000) +#define MX3x_RNGA_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xb0000) +#define MX3x_IPU_CTRL_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xc0000) +#define MX3x_AUDMUX_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xc4000) +#define MX3x_GPIO1_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xcc000) +#define MX3x_GPIO2_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xd0000) +#define MX3x_SDMA_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xd4000) +#define MX3x_RTC_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xd8000) +#define MX3x_WDOG_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xdc000) +#define MX3x_PWM_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xe0000) +#define MX3x_RTIC_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xec000) + +/* + * ROMP and AVIC + */ +#define MX3x_ROMP_BASE_ADDR 0x60000000 +#define MX3x_ROMP_SIZE SZ_1M + +#define MX3x_AVIC_BASE_ADDR 0x68000000 +#define MX3x_AVIC_SIZE SZ_1M + +/* + * Memory regions and CS + */ +#define MX3x_IPU_MEM_BASE_ADDR 0x70000000 +#define MX3x_CSD0_BASE_ADDR 0x80000000 +#define MX3x_CSD1_BASE_ADDR 0x90000000 + +#define MX3x_CS0_BASE_ADDR 0xa0000000 +#define MX3x_CS1_BASE_ADDR 0xa8000000 +#define MX3x_CS2_BASE_ADDR 0xb0000000 +#define MX3x_CS3_BASE_ADDR 0xb2000000 + +#define MX3x_CS4_BASE_ADDR 0xb4000000 +#define MX3x_CS4_BASE_ADDR_VIRT 0xf6000000 +#define MX3x_CS4_SIZE SZ_32M + +#define MX3x_CS5_BASE_ADDR 0xb6000000 +#define MX3x_CS5_BASE_ADDR_VIRT 0xf8000000 +#define MX3x_CS5_SIZE SZ_32M + +/* + * NAND, SDRAM, WEIM, M3IF, EMI controllers + */ +#define MX3x_X_MEMC_BASE_ADDR 0xb8000000 +#define MX3x_X_MEMC_SIZE SZ_64K +#define MX3x_ESDCTL_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x1000) +#define MX3x_WEIM_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x2000) +#define MX3x_M3IF_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x3000) +#define MX3x_EMI_CTL_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x4000) +#define MX3x_PCMCIA_CTL_BASE_ADDR MX3x_EMI_CTL_BASE_ADDR + +#define MX3x_PCMCIA_MEM_BASE_ADDR 0xbc000000 + +/* + * Interrupt numbers + */ +#define MX3x_INT_I2C3 3 +#define MX3x_INT_I2C2 4 +#define MX3x_INT_RTIC 6 +#define MX3x_INT_I2C 10 +#define MX3x_INT_CSPI2 13 +#define MX3x_INT_CSPI1 14 +#define MX3x_INT_ATA 15 +#define MX3x_INT_UART3 18 +#define MX3x_INT_IIM 19 +#define MX3x_INT_RNGA 22 +#define MX3x_INT_EVTMON 23 +#define MX3x_INT_KPP 24 +#define MX3x_INT_RTC 25 +#define MX3x_INT_PWM 26 +#define MX3x_INT_EPIT2 27 +#define MX3x_INT_EPIT1 28 +#define MX3x_INT_GPT 29 +#define MX3x_INT_POWER_FAIL 30 +#define MX3x_INT_UART2 32 +#define MX3x_INT_NANDFC 33 +#define MX3x_INT_SDMA 34 +#define MX3x_INT_MSHC1 39 +#define MX3x_INT_IPU_ERR 41 +#define MX3x_INT_IPU_SYN 42 +#define MX3x_INT_UART1 45 +#define MX3x_INT_ECT 48 +#define MX3x_INT_SCC_SCM 49 +#define MX3x_INT_SCC_SMN 50 +#define MX3x_INT_GPIO2 51 +#define MX3x_INT_GPIO1 52 +#define MX3x_INT_WDOG 55 +#define MX3x_INT_GPIO3 56 +#define MX3x_INT_EXT_POWER 58 +#define MX3x_INT_EXT_TEMPER 59 +#define MX3x_INT_EXT_SENSOR60 60 +#define MX3x_INT_EXT_SENSOR61 61 +#define MX3x_INT_EXT_WDOG 62 +#define MX3x_INT_EXT_TV 63 + +#define MX3x_PROD_SIGNATURE 0x1 /* For MX31 */ + +/* Mandatory defines used globally */ + +#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) + +extern unsigned int mx31_cpu_rev; +extern void mx31_read_cpu_rev(void); + +static inline int mx31_revision(void) +{ + return mx31_cpu_rev; +} + +extern unsigned int mx35_cpu_rev; +extern void mx35_read_cpu_rev(void); + +static inline int mx35_revision(void) +{ + return mx35_cpu_rev; +} +#endif + +#endif /* ifndef __MACH_MX3x_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx50.h b/arch/arm/plat-mxc/include/mach/mx50.h new file mode 100755 index 00000000..ec37ab16 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/mx50.h @@ -0,0 +1,352 @@ +/* + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __MACH_MX50_H__ +#define __MACH_MX50_H__ + +/* + * IROM + */ +#define MX50_IROM_BASE_ADDR 0x0 +#define MX50_IROM_SIZE SZ_64K + +/* TZIC */ +#define MX50_TZIC_BASE_ADDR 0x0fffc000 +#define MX50_TZIC_SIZE SZ_16K + +/* + * IRAM + */ +#define MX50_IRAM_BASE_ADDR 0xf8000000 /* internal ram */ +#define MX50_IRAM_PARTITIONS 16 +#define MX50_IRAM_SIZE (MX50_IRAM_PARTITIONS * SZ_8K) /* 128KB */ + +/* + * Databahn + */ +#define MX50_DATABAHN_BASE_ADDR 0x14000000 +#define DATABAHN_CTL_REG19 0x4c +#define DATABAHN_CTL_REG20 0x50 +#define DATABAHN_CTL_REG21 0x54 +#define DATABAHN_CTL_REG22 0x58 +#define DATABAHN_CTL_REG23 0x5c +#define DATABAHN_CTL_REG42 0xa8 +#define DATABAHN_CTL_REG43 0xac +#define DATABAHN_CTL_REG55 0xdc +#define DATABAHN_CTL_REG63 0xFC +#define DATABAHN_CTL_REG73 0x124 +#define DATABAHN_CTL_REG74 0x128 +#define DATABAHN_CTL_REG75 0x12C +#define DATABAHN_CTL_REG83 0x14C +#define LOWPOWER_CONTROL_MASK 0x1F +#define LOWPOWER_AUTOENABLE_MASK 0x1F +#define LOWPOWER_EXTERNAL_CNT_MASK (0xFFFF << 16) +#define LOWPOWER_EXTERNAL_CNT_OFFSET 16 +#define LOWPOWER_INTERNAL_CNT_MASK (0xFFFF << 8) +#define LOWPOWER_INTERNAL_CNT_OFFSET 8 +#define LOWPOWER_REFRESH_ENABLE_MASK (3 << 16) +#define LOWPOWER_REFRESH_ENABLE_OFFSET 16 +#define LOWPOWER_REFRESH_HOLD_MASK 0xFFFF +#define LOWPOWER_REFRESH_HOLD_OFFSET 0 +#define MX50_LPDDR2 (0x5 << 8) +#define MX50_MDDR (0x1 << 8) + + +/* + * Graphics Memory of GPU + */ +#define MX50_GPU2D_BASE_ADDR 0x20000000 + +#define MX50_DEBUG_BASE_ADDR 0x40000000 +#define MX50_DEBUG_SIZE SZ_1M +#define MX50_ETB_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00001000) +#define MX50_ETM_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00002000) +#define MX50_TPIU_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00003000) +#define MX50_CTI0_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00004000) +#define MX50_CTI1_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00005000) +#define MX50_CTI2_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00006000) +#define MX50_CTI3_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00007000) +#define MX50_CORTEX_DBG_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00008000) + +#define MX50_APBHDMA_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01000000) +#define MX50_OCOTP_CTRL_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01002000) +#define MX50_DIGCTL_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01004000) +#define MX50_GPMI_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01006000) +#define MX50_BCH_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01008000) +#define MX50_ELCDIF_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x0100a000) +#define MX50_EPXP_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x0100c000) +#define MX50_DCP_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x0100e000) +#define MX50_EPDC_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01010000) +#define MX50_QOSC_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01012000) +#define MX50_PERFMON_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01014000) +#define MX50_SSP_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01016000) +#define MX50_ANATOP_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01018000) +#define MX50_NIC_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x08000000) + +/* + * SPBA global module enabled #0 + */ +#define MX50_SPBA0_BASE_ADDR 0x50000000 +#define MX50_SPBA0_SIZE SZ_1M + +#define MX50_ESDHC1_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00004000) +#define MX50_ESDHC2_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00008000) +#define MX50_UART3_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x0000c000) +#define MX50_CSPI1_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00010000) +#define MX50_SSI2_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00014000) +#define MX50_ESDHC3_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00020000) +#define MX50_ESDHC4_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00024000) + +/* + * AIPS 1 + */ +#define MX50_AIPS1_BASE_ADDR 0x53f00000 +#define MX50_AIPS1_SIZE SZ_1M + +#define MX50_OTG_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00080000) +#define MX50_GPIO1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00084000) +#define MX50_GPIO2_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00088000) +#define MX50_GPIO3_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x0008c000) +#define MX50_GPIO4_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00090000) +#define MX50_KPP_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00094000) +#define MX50_WDOG_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00098000) +#define MX50_GPT1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000a0000) +#define MX50_SRTC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000a4000) +#define MX50_IOMUXC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000a8000) +#define MX50_EPIT1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000ac000) +#define MX50_PWM1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000b4000) +#define MX50_PWM2_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000b8000) +#define MX50_UART1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000bc000) +#define MX50_UART2_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000c0000) +#define MX50_SRC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000d0000) +#define MX50_CCM_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000d4000) +#define MX50_GPC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000d8000) +#define MX50_GPIO5_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000dc000) +#define MX50_GPIO6_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000e0000) +#define MX50_I2C3_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000ec000) +#define MX50_UART4_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000f0000) + +#define MX50_MSHC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000f4000) +#define MX50_RNGB_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000f8000) +#define MX50_DVFSCORE_BASE_ADDR (MX50_GPC_BASE_ADDR + 0x180) + +/* GPC offsets */ +#define MXC_GPC_CNTR_OFFSET 0x0 +#define MXC_GPC_PGR_OFFSET 0x4 +#define MXC_GPC_VCR_OFFSET 0x8 + +/* + * AIPS 2 + */ +#define MX50_AIPS2_BASE_ADDR 0x63f00000 +#define MX50_AIPS2_SIZE SZ_1M + +#define MX50_PLL1_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00080000) +#define MX50_PLL2_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00084000) +#define MX50_PLL3_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00088000) +#define MX50_UART5_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00090000) +#define MX50_AHBMAX_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00094000) +#define MX50_ARM_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000a0000) +#define MX50_OWIRE_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000a4000) +#define MX50_CSPI2_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000ac000) +#define MX50_SDMA_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000b0000) +#define MX50_ROMCP_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000b8000) +#define MX50_CSPI3_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000c0000) +#define MX50_I2C2_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000c4000) +#define MX50_I2C1_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000c8000) +#define MX50_SSI1_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000cc000) +#define MX50_AUDMUX_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000d0000) +#define MX50_WEIM_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000d8000) +#define MX50_FEC_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000ec000) + +/* + * Memory regions and CS + */ +#define MX50_CSD0_BASE_ADDR 0x70000000 +#define MX50_CSD1_BASE_ADDR 0xb0000000 +#define MX50_CS0_BASE_ADDR 0xf0000000 + +#define MX50_IO_P2V(x) IMX_IO_P2V(x) +#define MX50_IO_ADDRESS(x) IOMEM(MX50_IO_P2V(x)) + +/* + * defines for SPBA modules + */ +#define MX50_SPBA_SDHC1 0x04 +#define MX50_SPBA_SDHC2 0x08 +#define MX50_SPBA_UART3 0x0c +#define MX50_SPBA_CSPI1 0x10 +#define MX50_SPBA_SSI2 0x14 +#define MX50_SPBA_SDHC3 0x20 +#define MX50_SPBA_SDHC4 0x24 +#define MX50_SPBA_SPDIF 0x28 +#define MX50_SPBA_ATA 0x30 +#define MX50_SPBA_SLIM 0x34 +#define MX50_SPBA_HSI2C 0x38 +#define MX50_SPBA_CTRL 0x3c + +/* + * DMA request assignments + */ +#define MX50_DMA_REQ_GPC 1 +#define MX50_DMA_REQ_ATA_UART4_RX 2 +#define MX50_DMA_REQ_ATA_UART4_TX 3 +#define MX50_DMA_REQ_CSPI1_RX 6 +#define MX50_DMA_REQ_CSPI1_TX 7 +#define MX50_DMA_REQ_CSPI2_RX 8 +#define MX50_DMA_REQ_CSPI2_TX 9 +#define MX50_DMA_REQ_I2C3_SDHC3 10 +#define MX50_DMA_REQ_SDHC4 11 +#define MX50_DMA_REQ_UART2_FIRI_RX 12 +#define MX50_DMA_REQ_UART2_FIRI_TX 13 +#define MX50_DMA_REQ_EXT0 14 +#define MX50_DMA_REQ_EXT1 15 +#define MX50_DMA_REQ_UART5_RX 16 +#define MX50_DMA_REQ_UART5_TX 17 +#define MX50_DMA_REQ_UART1_RX 18 +#define MX50_DMA_REQ_UART1_TX 19 +#define MX50_DMA_REQ_I2C1_SDHC1 20 +#define MX50_DMA_REQ_I2C2_SDHC2 21 +#define MX50_DMA_REQ_SSI2_RX2 22 +#define MX50_DMA_REQ_SSI2_TX2 23 +#define MX50_DMA_REQ_SSI2_RX1 24 +#define MX50_DMA_REQ_SSI2_TX1 25 +#define MX50_DMA_REQ_SSI1_RX2 26 +#define MX50_DMA_REQ_SSI1_TX2 27 +#define MX50_DMA_REQ_SSI1_RX1 28 +#define MX50_DMA_REQ_SSI1_TX1 29 +#define MX50_DMA_REQ_CSPI_RX 38 +#define MX50_DMA_REQ_CSPI_TX 39 +#define MX50_DMA_REQ_UART3_RX 42 +#define MX50_DMA_REQ_UART3_TX 43 + +/* + * Interrupt numbers + */ +#define MX50_INT_ESDHC1 1 +#define MX50_INT_ESDHC2 2 +#define MX50_INT_ESDHC3 3 +#define MX50_INT_ESDHC4 4 +#define MX50_INT_DAP 5 +#define MX50_INT_SDMA 6 +#define MX50_INT_IOMUX 7 +#define MX50_INT_UART4 13 +#define MX50_INT_USB_H1 14 +#define MX50_INT_USB_OTG 18 +#define MX50_INT_DATABAHN 19 +#define MX50_INT_ELCDIF 20 +#define MX50_INT_EPXP 21 +#define MX50_INT_SRTC_NTZ 24 +#define MX50_INT_SRTC_TZ 25 +#define MX50_INT_EPDC 27 +#define MX50_INT_NIC 28 +#define MX50_INT_SSI1 29 +#define MX50_INT_SSI2 30 +#define MX50_INT_UART1 31 +#define MX50_INT_UART2 32 +#define MX50_INT_UART3 33 +#define MX50_INT_RESV34 34 +#define MX50_INT_RESV35 35 +/* eCSPI interrupts */ +#define MX50_INT_CSPI1 36 +#define MX50_INT_CSPI2 37 +/* CSPI interrupt */ +#define MX50_INT_CSPI3 38 +#define MX50_INT_GPT 39 +#define MX50_INT_EPIT1 40 +#define MX50_INT_GPIO1_INT7 42 +#define MX50_INT_GPIO1_INT6 43 +#define MX50_INT_GPIO1_INT5 44 +#define MX50_INT_GPIO1_INT4 45 +#define MX50_INT_GPIO1_INT3 46 +#define MX50_INT_GPIO1_INT2 47 +#define MX50_INT_GPIO1_INT1 48 +#define MX50_INT_GPIO1_INT0 49 +#define MX50_INT_GPIO1_LOW 50 +#define MX50_INT_GPIO1_HIGH 51 +#define MX50_INT_GPIO2_LOW 52 +#define MX50_INT_GPIO2_HIGH 53 +#define MX50_INT_GPIO3_LOW 54 +#define MX50_INT_GPIO3_HIGH 55 +#define MX50_INT_GPIO4_LOW 56 +#define MX50_INT_GPIO4_HIGH 57 +#define MX50_INT_WDOG1 58 +#define MX50_INT_KPP 60 +#define MX50_INT_PWM1 61 +#define MX50_INT_I2C1 62 +#define MX50_INT_I2C2 63 +#define MX50_INT_I2C3 64 +#define MX50_INT_RESV65 65 +#define MX50_INT_DCDC 66 +#define MX50_INT_THERMAL_ALARM 67 +#define MX50_INT_ANA3 68 +#define MX50_INT_ANA4 69 +#define MX50_INT_CCM1 71 +#define MX50_INT_CCM2 72 +#define MX50_INT_GPC1 73 +#define MX50_INT_GPC2 74 +#define MX50_INT_SRC 75 +#define MX50_INT_NM 76 +#define MX50_INT_PMU 77 +#define MX50_INT_CTI_IRQ 78 +#define MX50_INT_CTI1_TG0 79 +#define MX50_INT_CTI1_TG1 80 +#define MX50_INT_GPU2_IRQ 84 +#define MX50_INT_GPU2_BUSY 85 +#define MX50_INT_UART5 86 +#define MX50_INT_FEC 87 +#define MX50_INT_OWIRE 88 +#define MX50_INT_CTI1_TG2 89 +#define MX50_INT_SJC 90 +#define MX50_INT_DCP_CHAN1_3 91 +#define MX50_INT_DCP_CHAN0 92 +#define MX50_INT_PWM2 94 +#define MX50_INT_RNGB 97 +#define MX50_INT_CTI1_TG3 98 +#define MX50_INT_RAWNAND_BCH 100 +#define MX50_INT_RAWNAND_GPMI 102 +#define MX50_INT_GPIO5_LOW 103 +#define MX50_INT_GPIO5_HIGH 104 +#define MX50_INT_GPIO6_LOW 105 +#define MX50_INT_GPIO6_HIGH 106 +#define MX50_INT_MSHC 109 +#define MX50_INT_APBHDMA_CHAN0 110 +#define MX50_INT_APBHDMA_CHAN1 111 +#define MX50_INT_APBHDMA_CHAN2 112 +#define MX50_INT_APBHDMA_CHAN3 113 +#define MX50_INT_APBHDMA_CHAN4 114 +#define MX50_INT_APBHDMA_CHAN5 115 +#define MX50_INT_APBHDMA_CHAN6 116 +#define MX50_INT_APBHDMA_CHAN7 117 + +/* DMA */ +#define MX50_DMA_CHANNEL_AHB_APBH_GPMI0 0 +#define MX50_DMA_CHANNEL_AHB_APBH_GPMI1 1 +#define MX50_DMA_CHANNEL_AHB_APBH_GPMI2 2 +#define MX50_DMA_CHANNEL_AHB_APBH_GPMI3 3 +#define MX50_DMA_CHANNEL_AHB_APBH_GPMI4 4 +#define MX50_DMA_CHANNEL_AHB_APBH_GPMI5 5 +#define MX50_DMA_CHANNEL_AHB_APBH_GPMI6 6 +#define MX50_DMA_CHANNEL_AHB_APBH_GPMI7 7 +#define MX50_DMA_CHANNEL_AHB_APBH_SSP 8 + +#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) +extern int mx50_revision(void); +#endif + +#endif /* ifndef __MACH_MX50_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx51.h b/arch/arm/plat-mxc/include/mach/mx51.h new file mode 100755 index 00000000..9db86a19 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/mx51.h @@ -0,0 +1,382 @@ +#ifndef __MACH_MX51_H__ +#define __MACH_MX51_H__ + +/* + * IROM + */ +#define MX51_IROM_BASE_ADDR 0x0 +#define MX51_IROM_SIZE SZ_64K + +/* + * IRAM + */ +#define MX51_IRAM_BASE_ADDR 0x1ffe0000 /* internal ram */ +#define MX51_IRAM_PARTITIONS 16 +#define MX51_IRAM_SIZE (MX51_IRAM_PARTITIONS * SZ_8K) /* 128KB */ + +/* + * SCC RAM: shares IRAM space + */ +#define MX51_SCC_RAM_BASE_ADDR MX51_IRAM_BASE_ADDR + +#if defined(CONFIG_MXC_SECURITY_SCC2) \ + || defined(CONFIG_MXC_SECURITY_SCC2_MODULE) +#define MX51_SCC_RAM_SIZE SZ_16K /* 2 partitions of 8 KB from IRAM */ +#else +#define MX51_SCC_RAM_SIZE 0 +#endif + +#define MX51_GPU_GMEM_BASE_ADDR 0x20000000 +#define MX51_GPU_GMEM_SIZE SZ_128K +#define MX51_GPU_BASE_ADDR 0x30000000 +#define MX51_IPU_CTRL_BASE_ADDR 0x40000000 + +#define MX51_DEBUG_BASE_ADDR 0x60000000 +#define MX51_DEBUG_SIZE SZ_1M + +#define MX51_ETB_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x01000) +#define MX51_ETM_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x02000) +#define MX51_TPIU_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x03000) +#define MX51_CTI0_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x04000) +#define MX51_CTI1_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x05000) +#define MX51_CTI2_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x06000) +#define MX51_CTI3_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x07000) +#define MX51_CORTEX_DBG_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x08000) + +/* + * SPBA global module enabled #0 + */ +#define MX51_SPBA0_BASE_ADDR 0x70000000 +#define MX51_SPBA0_SIZE SZ_1M + +#define MX51_ESDHC1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x04000) +#define MX51_ESDHC2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x08000) +#define MX51_UART3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x0c000) +#define MX51_ECSPI1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x10000) +#define MX51_SSI2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x14000) +#define MX51_ESDHC3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x20000) +#define MX51_ESDHC4_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x24000) +#define MX51_SPDIF_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x28000) +#define MX51_ATA_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x30000) +#define MX51_SLIM_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x34000) +#define MX51_HSI2C_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x38000) +#define MX51_SPBA_CTRL_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x3c000) + +/* + * AIPS 1 + */ +#define MX51_AIPS1_BASE_ADDR 0x73f00000 +#define MX51_AIPS1_SIZE SZ_1M + +#define MX51_OTG_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x80000) +#define MX51_GPIO1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x84000) +#define MX51_GPIO2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x88000) +#define MX51_GPIO3_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x8c000) +#define MX51_GPIO4_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x90000) +#define MX51_KPP_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x94000) +#define MX51_WDOG1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x98000) +#define MX51_WDOG2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x9c000) +#define MX51_GPT1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xa0000) +#define MX51_SRTC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xa4000) +#define MX51_IOMUXC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xa8000) +#define MX51_EPIT1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xac000) +#define MX51_EPIT2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xb0000) +#define MX51_PWM1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xb4000) +#define MX51_PWM2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xb8000) +#define MX51_UART1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xbc000) +#define MX51_UART2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xc0000) +#define MX51_SRC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xd0000) +#define MX51_CCM_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xd4000) +#define MX51_GPC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xd8000) +#define MX51_DVFSCORE_BASE_ADDR (MX51_GPC_BASE_ADDR + 0x180) + +/* + * AIPS 2 + */ +#define MX51_AIPS2_BASE_ADDR 0x83f00000 +#define MX51_AIPS2_SIZE SZ_1M + +#define MX51_PLL1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x80000) +#define MX51_PLL2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x84000) +#define MX51_PLL3_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x88000) +#define MX51_AHBMAX_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x94000) +#define MX51_IIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x98000) +#define MX51_CSU_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x9c000) +#define MX51_ARM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xa0000) +#define MX51_OWIRE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xa4000) +#define MX51_FIRI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xa8000) +#define MX51_ECSPI2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xac000) +#define MX51_SDMA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xb0000) +#define MX51_SCC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xb4000) +#define MX51_ROMCP_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xb8000) +#define MX51_RTIC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xbc000) +#define MX51_CSPI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xc0000) +#define MX51_I2C2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xc4000) +#define MX51_I2C1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xc8000) +#define MX51_SSI1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xcc000) +#define MX51_AUDMUX_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xd0000) +#define MX51_M4IF_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xd8000) +#define MX51_ESDCTL_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xd9000) +#define MX51_WEIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xda000) +#define MX51_NFC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xdb000) +#define MX51_EMI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xdbf00) +#define MX51_MIPI_HSC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xdc000) +#define MX51_ATA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe0000) +#define MX51_SIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe4000) +#define MX51_SSI3_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe8000) +#define MX51_FEC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xec000) +#define MX51_TVE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xf0000) +#define MX51_VPU_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xf4000) +#define MX51_SAHARA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xf8000) + +#define MX51_CSD0_BASE_ADDR 0x90000000 +#define MX51_CSD1_BASE_ADDR 0xa0000000 +#define MX51_CS0_BASE_ADDR 0xb0000000 +#define MX51_CS1_BASE_ADDR 0xb8000000 +#define MX51_CS2_BASE_ADDR 0xc0000000 +#define MX51_CS3_BASE_ADDR 0xc8000000 +#define MX51_CS4_BASE_ADDR 0xcc000000 +#define MX51_CS5_BASE_ADDR 0xce000000 + +/* + * NFC + */ +#define MX51_NFC_AXI_BASE_ADDR 0xcfff0000 /* NAND flash AXI */ +#define MX51_NFC_AXI_SIZE SZ_64K + +#define MX51_GPU2D_BASE_ADDR 0xd0000000 +#define MX51_TZIC_BASE_ADDR 0xe0000000 + +#define MX51_IO_P2V(x) IMX_IO_P2V(x) +#define MX51_IO_ADDRESS(x) IOMEM(MX51_IO_P2V(x)) + +/* PGC */ +#define MX51_GPC_BASE (MX51_IO_ADDRESS(MX51_GPC_BASE_ADDR)) +#define MX51_PGC_IPU_BASE (MX51_GPC_BASE + 0x220) +#define MX51_PGC_VPU_BASE (MX51_GPC_BASE + 0x240) +#define MX51_PGC_GPU_BASE (MX51_GPC_BASE + 0x260) +#define MX51_PGC_IPU_PGCR (MX51_PGC_IPU_BASE + 0x0) +#define MX51_PGC_IPU_PGSR (MX51_PGC_IPU_BASE + 0xC) +#define MX51_PGC_VPU_PGCR (MX51_PGC_VPU_BASE + 0x0) +#define MX51_PGC_VPU_PGSR (MX51_PGC_VPU_BASE + 0xC) +#define MX51_PGC_GPU_PGCR (MX51_PGC_GPU_BASE + 0x0) +#define MX51_PGC_GPU_PGSR (MX51_PGC_GPU_BASE + 0xC) + +/* + * defines for SPBA modules + */ +#define MX51_SPBA_SDHC1 0x04 +#define MX51_SPBA_SDHC2 0x08 +#define MX51_SPBA_UART3 0x0c +#define MX51_SPBA_CSPI1 0x10 +#define MX51_SPBA_SSI2 0x14 +#define MX51_SPBA_SDHC3 0x20 +#define MX51_SPBA_SDHC4 0x24 +#define MX51_SPBA_SPDIF 0x28 +#define MX51_SPBA_ATA 0x30 +#define MX51_SPBA_SLIM 0x34 +#define MX51_SPBA_HSI2C 0x38 +#define MX51_SPBA_CTRL 0x3c + +/* + * Defines for modules using static and dynamic DMA channels + */ +#define MX51_MXC_DMA_CHANNEL_IRAM 30 +#define MX51_MXC_DMA_CHANNEL_SPDIF_TX MXC_DMA_DYNAMIC_CHANNEL +#define MX51_MXC_DMA_CHANNEL_UART1_RX MXC_DMA_DYNAMIC_CHANNEL +#define MX51_MXC_DMA_CHANNEL_UART1_TX MXC_DMA_DYNAMIC_CHANNEL +#define MX51_MXC_DMA_CHANNEL_UART2_RX MXC_DMA_DYNAMIC_CHANNEL +#define MX51_MXC_DMA_CHANNEL_UART2_TX MXC_DMA_DYNAMIC_CHANNEL +#define MX51_MXC_DMA_CHANNEL_UART3_RX MXC_DMA_DYNAMIC_CHANNEL +#define MX51_MXC_DMA_CHANNEL_UART3_TX MXC_DMA_DYNAMIC_CHANNEL +#define MX51_MXC_DMA_CHANNEL_MMC1 MXC_DMA_DYNAMIC_CHANNEL +#define MX51_MXC_DMA_CHANNEL_MMC2 MXC_DMA_DYNAMIC_CHANNEL +#define MX51_MXC_DMA_CHANNEL_SSI1_RX MXC_DMA_DYNAMIC_CHANNEL +#define MX51_MXC_DMA_CHANNEL_SSI1_TX MXC_DMA_DYNAMIC_CHANNEL +#define MX51_MXC_DMA_CHANNEL_SSI2_RX MXC_DMA_DYNAMIC_CHANNEL +#ifdef CONFIG_SDMA_IRAM +#define MX51_MXC_DMA_CHANNEL_SSI2_TX (MX51_MXC_DMA_CHANNEL_IRAM + 1) +#else /*CONFIG_SDMA_IRAM */ +#define MX51_MXC_DMA_CHANNEL_SSI2_TX MXC_DMA_DYNAMIC_CHANNEL +#endif /*CONFIG_SDMA_IRAM */ +#define MX51_MXC_DMA_CHANNEL_CSPI1_RX MXC_DMA_DYNAMIC_CHANNEL +#define MX51_MXC_DMA_CHANNEL_CSPI1_TX MXC_DMA_DYNAMIC_CHANNEL +#define MX51_MXC_DMA_CHANNEL_CSPI2_RX MXC_DMA_DYNAMIC_CHANNEL +#define MX51_MXC_DMA_CHANNEL_CSPI2_TX MXC_DMA_DYNAMIC_CHANNEL +#define MX51_MXC_DMA_CHANNEL_CSPI3_RX MXC_DMA_DYNAMIC_CHANNEL +#define MX51_MXC_DMA_CHANNEL_CSPI3_TX MXC_DMA_DYNAMIC_CHANNEL +#define MX51_MXC_DMA_CHANNEL_ATA_RX MXC_DMA_DYNAMIC_CHANNEL +#define MX51_MXC_DMA_CHANNEL_ATA_TX MXC_DMA_DYNAMIC_CHANNEL +#define MX51_MXC_DMA_CHANNEL_MEMORY MXC_DMA_DYNAMIC_CHANNEL + +#define MX51_IS_MEM_DEVICE_NONSHARED(x) 0 + +/* + * DMA request assignments + */ +#define MX51_DMA_REQ_VPU 0 +#define MX51_DMA_REQ_GPC 1 +#define MX51_DMA_REQ_ATA_RX 2 +#define MX51_DMA_REQ_ATA_TX 3 +#define MX51_DMA_REQ_ATA_TX_END 4 +#define MX51_DMA_REQ_SLIM_B 5 +#define MX51_DMA_REQ_CSPI1_RX 6 +#define MX51_DMA_REQ_CSPI1_TX 7 +#define MX51_DMA_REQ_CSPI2_RX 8 +#define MX51_DMA_REQ_CSPI2_TX 9 +#define MX51_DMA_REQ_HS_I2C_TX 10 +#define MX51_DMA_REQ_HS_I2C_RX 11 +#define MX51_DMA_REQ_FIRI_RX 12 +#define MX51_DMA_REQ_FIRI_TX 13 +#define MX51_DMA_REQ_EXTREQ1 14 +#define MX51_DMA_REQ_GPU 15 +#define MX51_DMA_REQ_UART2_RX 16 +#define MX51_DMA_REQ_UART2_TX 17 +#define MX51_DMA_REQ_UART1_RX 18 +#define MX51_DMA_REQ_UART1_TX 19 +#define MX51_DMA_REQ_SDHC1 20 +#define MX51_DMA_REQ_SDHC2 21 +#define MX51_DMA_REQ_SSI2_RX1 22 +#define MX51_DMA_REQ_SSI2_TX1 23 +#define MX51_DMA_REQ_SSI2_RX0 24 +#define MX51_DMA_REQ_SSI2_TX0 25 +#define MX51_DMA_REQ_SSI1_RX1 26 +#define MX51_DMA_REQ_SSI1_TX1 27 +#define MX51_DMA_REQ_SSI1_RX0 28 +#define MX51_DMA_REQ_SSI1_TX0 29 +#define MX51_DMA_REQ_EMI_RD 30 +#define MX51_DMA_REQ_CTI2_0 31 +#define MX51_DMA_REQ_EMI_WR 32 +#define MX51_DMA_REQ_CTI2_1 33 +#define MX51_DMA_REQ_EPIT2 34 +#define MX51_DMA_REQ_SSI3_RX1 35 +#define MX51_DMA_REQ_IPU 36 +#define MX51_DMA_REQ_SSI3_TX1 37 +#define MX51_DMA_REQ_CSPI_RX 38 +#define MX51_DMA_REQ_CSPI_TX 39 +#define MX51_DMA_REQ_SDHC3 40 +#define MX51_DMA_REQ_SDHC4 41 +#define MX51_DMA_REQ_SLIM_B_TX 42 +#define MX51_DMA_REQ_UART3_RX 43 +#define MX51_DMA_REQ_UART3_TX 44 +#define MX51_DMA_REQ_SPDIF 45 +#define MX51_DMA_REQ_SSI3_RX0 46 +#define MX51_DMA_REQ_SSI3_TX0 47 + +/* + * Interrupt numbers + */ +#define MX51_MXC_INT_BASE 0 +#define MX51_MXC_INT_RESV0 0 +#define MX51_INT_ESDHC1 1 +#define MX51_INT_ESDHC2 2 +#define MX51_INT_ESDHC3 3 +#define MX51_INT_ESDHC4 4 +#define MX51_MXC_INT_RESV5 5 +#define MX51_INT_SDMA 6 +#define MX51_MXC_INT_IOMUX 7 +#define MX51_INT_NFC 8 +#define MX51_INT_VPU 9 +#define MX51_INT_IPU_ERR 10 +#define MX51_INT_IPU_SYN 11 +#define MX51_INT_GPU 12 +#define MX51_MXC_INT_RESV13 13 +#define MX51_MXC_INT_USB_H1 14 +#define MX51_MXC_INT_EMI 15 +#define MX51_MXC_INT_USB_H2 16 +#define MX51_MXC_INT_USB_H3 17 +#define MX51_MXC_INT_USB_OTG 18 +#define MX51_MXC_INT_SAHARA_H0 19 +#define MX51_MXC_INT_SAHARA_H1 20 +#define MX51_INT_SCC_SMN 21 +#define MX51_INT_SCC_STZ 22 +#define MX51_INT_SCC_SCM 23 +#define MX51_INT_SRTC_NTZ 24 +#define MX51_INT_SRTC_TZ 25 +#define MX51_MXC_INT_RTIC 26 +#define MX51_MXC_INT_CSU 27 +#define MX51_MXC_INT_SLIM_B 28 +#define MX51_INT_SSI1 29 +#define MX51_INT_SSI2 30 +#define MX51_INT_UART1 31 +#define MX51_INT_UART2 32 +#define MX51_INT_UART3 33 +#define MX51_MXC_INT_RESV34 34 +#define MX51_MXC_INT_RESV35 35 +#define MX51_INT_ECSPI1 36 +#define MX51_INT_ECSPI2 37 +#define MX51_INT_CSPI 38 +#define MX51_MXC_INT_GPT 39 +#define MX51_MXC_INT_EPIT1 40 +#define MX51_MXC_INT_EPIT2 41 +#define MX51_MXC_INT_GPIO1_INT7 42 +#define MX51_MXC_INT_GPIO1_INT6 43 +#define MX51_MXC_INT_GPIO1_INT5 44 +#define MX51_MXC_INT_GPIO1_INT4 45 +#define MX51_MXC_INT_GPIO1_INT3 46 +#define MX51_MXC_INT_GPIO1_INT2 47 +#define MX51_MXC_INT_GPIO1_INT1 48 +#define MX51_MXC_INT_GPIO1_INT0 49 +#define MX51_MXC_INT_GPIO1_LOW 50 +#define MX51_MXC_INT_GPIO1_HIGH 51 +#define MX51_MXC_INT_GPIO2_LOW 52 +#define MX51_MXC_INT_GPIO2_HIGH 53 +#define MX51_MXC_INT_GPIO3_LOW 54 +#define MX51_MXC_INT_GPIO3_HIGH 55 +#define MX51_MXC_INT_GPIO4_LOW 56 +#define MX51_MXC_INT_GPIO4_HIGH 57 +#define MX51_MXC_INT_WDOG1 58 +#define MX51_MXC_INT_WDOG2 59 +#define MX51_INT_KPP 60 +#define MX51_INT_PWM1 61 +#define MX51_INT_I2C1 62 +#define MX51_INT_I2C2 63 +#define MX51_MXC_INT_HS_I2C 64 +#define MX51_MXC_INT_RESV65 65 +#define MX51_MXC_INT_RESV66 66 +#define MX51_MXC_INT_SIM_IPB 67 +#define MX51_MXC_INT_SIM_DAT 68 +#define MX51_INT_IIM 69 +#define MX51_MXC_INT_ATA 70 +#define MX51_MXC_INT_CCM1 71 +#define MX51_MXC_INT_CCM2 72 +#define MX51_INT_GPC1 73 +#define MX51_INT_GPC2 74 +#define MX51_MXC_INT_SRC 75 +#define MX51_MXC_INT_NM 76 +#define MX51_MXC_INT_PMU 77 +#define MX51_MXC_INT_CTI_IRQ 78 +#define MX51_MXC_INT_CTI1_TG0 79 +#define MX51_MXC_INT_CTI1_TG1 80 +#define MX51_MXC_INT_MCG_ERR 81 +#define MX51_MXC_INT_MCG_TMR 82 +#define MX51_MXC_INT_MCG_FUNC 83 +#define MX51_INT_GPU2_IRQ 84 +#define MX51_MXC_INT_GPU2_BUSY 85 +#define MX51_MXC_INT_RESV86 86 +#define MX51_INT_FEC 87 +#define MX51_MXC_INT_OWIRE 88 +#define MX51_MXC_INT_CTI1_TG2 89 +#define MX51_MXC_INT_SJC 90 +#define MX51_INT_SPDIF 91 +#define MX51_INT_TVE 92 +#define MX51_MXC_INT_FIRI 93 +#define MX51_INT_PWM2 94 +#define MX51_MXC_INT_SLIM_EXP 95 +#define MX51_INT_SSI3 96 +#define MX51_MXC_INT_EMI_BOOT 97 +#define MX51_MXC_INT_CTI1_TG3 98 +#define MX51_MXC_INT_SMC_RX 99 +#define MX51_MXC_INT_VPU_IDLE 100 +#define MX51_MXC_INT_EMI_NFC 101 +#define MX51_MXC_INT_GPU_IDLE 102 + +#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) +extern int mx51_revision(void); +extern void mx51_display_revision(void); +#endif + +/* tape-out 1 defines */ +#define MX51_TZIC_BASE_ADDR_TO1 0x8fffc000 + +#endif /* ifndef __MACH_MX51_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx53.h b/arch/arm/plat-mxc/include/mach/mx53.h new file mode 100755 index 00000000..1bcddd63 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/mx53.h @@ -0,0 +1,392 @@ +#ifndef __MACH_MX53_H__ +#define __MACH_MX53_H__ + +/* + * IROM + */ +#define MX53_IROM_BASE_ADDR 0x0 +#define MX53_IROM_SIZE SZ_64K + +/* TZIC */ +#define MX53_TZIC_BASE_ADDR 0x0FFFC000 + +/* + * AHCI SATA + */ +#define MX53_SATA_BASE_ADDR 0x10000000 + +/* + * NFC + */ +#define MX53_NFC_AXI_BASE_ADDR 0xF7FF0000 /* NAND flash AXI */ +#define MX53_NFC_AXI_SIZE SZ_64K + +/* + * IRAM + */ +#define MX53_IRAM_BASE_ADDR 0xF8000000 /* internal ram */ +#define MX53_IRAM_PARTITIONS 16 +#define MX53_IRAM_SIZE (MX53_IRAM_PARTITIONS * SZ_8K) /* 128KB */ + +/* + * SCC RAM + */ +#define MX53_SCC_RAM_BASE_ADDR 0x07000000 +#define MX53_SCC_RAM_PARTITIONS 4 + /* 16 KB */ +#define MX53_SCC_RAM_SIZE (MX53_SCC_RAM_PARTITIONS * SZ_4K) + +#ifdef CONFIG_MXC_VPU_IRAM +#define VPU_IRAM_SIZE 0x14000 +#else +#define VPU_IRAM_SIZE 0 +#endif + +/* + * Graphics Memory of GPU + */ +#define MX53_IPU_CTRL_BASE_ADDR 0x18000000 +#define MX53_GPU2D_BASE_ADDR 0x20000000 +#define MX53_GPU_BASE_ADDR 0x30000000 +#define MX53_GPU_GMEM_BASE_ADDR 0xF8020000 +#define MX53_GPU_GMEM_SIZE SZ_256K + +#define MX53_DEBUG_BASE_ADDR 0x40000000 +#define MX53_DEBUG_SIZE SZ_1M +#define MX53_ETB_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00001000) +#define MX53_ETM_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00002000) +#define MX53_TPIU_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00003000) +#define MX53_CTI0_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00004000) +#define MX53_CTI1_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00005000) +#define MX53_CTI2_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00006000) +#define MX53_CTI3_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00007000) +#define MX53_CORTEX_DBG_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00008000) + +/* + * SPBA global module enabled #0 + */ +#define MX53_SPBA0_BASE_ADDR 0x50000000 +#define MX53_SPBA0_SIZE SZ_1M + +#define MX53_ESDHC1_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00004000) +#define MX53_ESDHC2_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00008000) +#define MX53_UART3_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x0000C000) +#define MX53_ECSPI1_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00010000) +#define MX53_SSI2_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00014000) +#define MX53_ESAI_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00018000) +#define MX53_ESDHC3_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00020000) +#define MX53_ESDHC4_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00024000) +#define MX53_SPDIF_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00028000) +#define MX53_ASRC_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x0002C000) +#define MX53_ATA_DMA_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00030000) +#define MX53_SLIM_DMA_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00034000) +#define MX53_HSI2C_DMA_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00038000) +#define MX53_SPBA_CTRL_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x0003C000) + +/* + * AIPS 1 + */ +#define MX53_AIPS1_BASE_ADDR 0x53F00000 +#define MX53_AIPS1_SIZE SZ_1M + +#define MX53_OTG_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00080000) +#define MX53_GPIO1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00084000) +#define MX53_GPIO2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00088000) +#define MX53_GPIO3_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x0008C000) +#define MX53_GPIO4_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00090000) +#define MX53_KPP_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00094000) +#define MX53_WDOG1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00098000) +#define MX53_WDOG2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x0009C000) +#define MX53_GPT1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000A0000) +#define MX53_SRTC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000A4000) +#define MX53_IOMUXC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000A8000) +#define MX53_EPIT1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000AC000) +#define MX53_EPIT2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000B0000) +#define MX53_PWM1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000B4000) +#define MX53_PWM2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000B8000) +#define MX53_UART1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000BC000) +#define MX53_UART2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000C0000) +#define MX53_SRC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000D0000) +#define MX53_CCM_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000D4000) +#define MX53_GPC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000D8000) +#define MX53_GPIO5_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000DC000) +#define MX53_GPIO6_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000E0000) +#define MX53_GPIO7_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000E4000) +#define MX53_ATA_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000E8000) +#define MX53_I2C3_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000EC000) +#define MX53_UART4_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000F0000) +#define MX53_DVFSCORE_BASE_ADDR (MX53_GPC_BASE_ADDR + 0x180) + +/* + * AIPS 2 + */ +#define MX53_AIPS2_BASE_ADDR 0x63F00000 +#define MX53_AIPS2_SIZE SZ_1M + +#define MX53_PLL1_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00080000) +#define MX53_PLL2_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00084000) +#define MX53_PLL3_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00088000) +#define MX53_PLL4_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x0008C000) +#define MX53_UART5_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00090000) +#define MX53_AHBMAX_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00094000) +#define MX53_IIM_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00098000) +#define MX53_CSU_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x0009C000) +#define MX53_ARM_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A0000) +#define MX53_OWIRE_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A4000) +#define MX53_FIRI_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A8000) +#define MX53_ECSPI2_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000AC000) +#define MX53_SDMA_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B0000) +#define MX53_SCC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B4000) +#define MX53_ROMCP_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B8000) +#define MX53_RTIC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000BC000) +#define MX53_CSPI_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C0000) +#define MX53_I2C2_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C4000) +#define MX53_I2C1_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C8000) +#define MX53_SSI1_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000CC000) +#define MX53_AUDMUX_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000D0000) +#define MX53_RTC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000D4000) +#define MX53_M4IF_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000D8000) +#define MX53_ESDCTL_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000D9000) +#define MX53_WEIM_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DA000) +#define MX53_NFC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DB000) +#define MX53_EMI_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DBF00) +#define MX53_MIPI_HSC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DC000) +#define MX53_MLB_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000E4000) +#define MX53_SSI3_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000E8000) +#define MX53_FEC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000EC000) +#define MX53_TVE_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000F0000) +#define MX53_VPU_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000F4000) +#define MX53_SAHARA_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000F8000) +#define MX53_PTP_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000FC000) + +/* + * Memory regions and CS + */ +#define MX53_CSD0_BASE_ADDR 0x90000000 +#define MX53_CSD1_BASE_ADDR 0xA0000000 +#define MX53_CS0_BASE_ADDR 0xF0000000 +#define MX53_CS1_BASE_ADDR 0xF4000000 +#define MX53_CS2_BASE_ADDR 0xC0000000 +#define MX53_CS3_BASE_ADDR 0xC8000000 +#define MX53_CS4_BASE_ADDR 0xCC000000 +#define MX53_CS5_BASE_ADDR 0xCE000000 + +#define MX53_IO_P2V(x) IMX_IO_P2V(x) +#define MX53_IO_ADDRESS(x) IOMEM(MX53_IO_P2V(x)) + +/* PGC */ +#define MX53_GPC_BASE (MX53_IO_ADDRESS(MX53_GPC_BASE_ADDR)) +#define MX53_PGC_IPU_BASE (MX53_GPC_BASE + 0x220) +#define MX53_PGC_VPU_BASE (MX53_GPC_BASE + 0x240) +#define MX53_PGC_GPU_BASE (MX53_GPC_BASE + 0x260) +#define MX53_PGC_IPU_PGCR (MX53_PGC_IPU_BASE + 0x0) +#define MX53_PGC_IPU_PGSR (MX53_PGC_IPU_BASE + 0xC) +#define MX53_PGC_VPU_PGCR (MX53_PGC_VPU_BASE + 0x0) +#define MX53_PGC_VPU_PGSR (MX53_PGC_VPU_BASE + 0xC) +#define MX53_PGC_GPU_PGCR (MX53_PGC_GPU_BASE + 0x0) +#define MX53_PGC_GPU_PGSR (MX53_PGC_GPU_BASE + 0xC) + +/* + * defines for SPBA modules + */ +#define MX53_SPBA_SDHC1 0x04 +#define MX53_SPBA_SDHC2 0x08 +#define MX53_SPBA_UART3 0x0C +#define MX53_SPBA_CSPI1 0x10 +#define MX53_SPBA_SSI2 0x14 +#define MX53_SPBA_SDHC3 0x20 +#define MX53_SPBA_SDHC4 0x24 +#define MX53_SPBA_SPDIF 0x28 +#define MX53_SPBA_ATA 0x30 +#define MX53_SPBA_SLIM 0x34 +#define MX53_SPBA_HSI2C 0x38 +#define MX53_SPBA_CTRL 0x3C + +/* + * DMA request assignments + */ +#define MX53_DMA_REQ_SSI3_TX0 47 +#define MX53_DMA_REQ_SSI3_RX0 46 +#define MX53_DMA_REQ_SSI3_TX1 45 +#define MX53_DMA_REQ_SSI3_RX1 44 +#define MX53_DMA_REQ_UART3_TX 43 +#define MX53_DMA_REQ_UART3_RX 42 +#define MX53_DMA_REQ_ESAI_TX 41 +#define MX53_DMA_REQ_ESAI_RX 40 +#define MX53_DMA_REQ_CSPI_TX 39 +#define MX53_DMA_REQ_CSPI_RX 38 +#define MX53_DMA_REQ_ASRC_DMA6 37 +#define MX53_DMA_REQ_ASRC_DMA5 36 +#define MX53_DMA_REQ_ASRC_DMA4 35 +#define MX53_DMA_REQ_ASRC_DMA3 34 +#define MX53_DMA_REQ_ASRC_DMA2 33 +#define MX53_DMA_REQ_ASRC_DMA1 32 +#define MX53_DMA_REQ_EMI_WR 31 +#define MX53_DMA_REQ_EMI_RD 30 +#define MX53_DMA_REQ_SSI1_TX0 29 +#define MX53_DMA_REQ_SSI1_RX0 28 +#define MX53_DMA_REQ_SSI1_TX1 27 +#define MX53_DMA_REQ_SSI1_RX1 26 +#define MX53_DMA_REQ_SSI2_TX0 25 +#define MX53_DMA_REQ_SSI2_RX0 24 +#define MX53_DMA_REQ_SSI2_TX1 23 +#define MX53_DMA_REQ_SSI2_RX1 22 +#define MX53_DMA_REQ_I2C2_SDHC2 21 +#define MX53_DMA_REQ_I2C1_SDHC1 20 +#define MX53_DMA_REQ_UART1_TX 19 +#define MX53_DMA_REQ_UART1_RX 18 +#define MX53_DMA_REQ_UART5_TX 17 +#define MX53_DMA_REQ_UART5_RX 16 +#define MX53_DMA_REQ_SPDIF_TX 15 +#define MX53_DMA_REQ_SPDIF_RX 14 +#define MX53_DMA_REQ_UART2_FIRI_TX 13 +#define MX53_DMA_REQ_UART2_FIRI_RX 12 +#define MX53_DMA_REQ_SDHC4 11 +#define MX53_DMA_REQ_I2C3_SDHC3 10 +#define MX53_DMA_REQ_CSPI2_TX 9 +#define MX53_DMA_REQ_CSPI2_RX 8 +#define MX53_DMA_REQ_CSPI1_TX 7 +#define MX53_DMA_REQ_CSPI1_RX 6 +#define MX53_DMA_REQ_IPU 5 +#define MX53_DMA_REQ_ATA_TX_END 4 +#define MX53_DMA_REQ_ATA_UART4_TX 3 +#define MX53_DMA_REQ_ATA_UART4_RX 2 +#define MX53_DMA_REQ_GPC 1 +#define MX53_DMA_REQ_VPU 0 + +/* + * Interrupt numbers + */ +#define MX53_INT_RESV0 0 +#define MX53_INT_ESDHC1 1 +#define MX53_INT_ESDHC2 2 +#define MX53_INT_ESDHC3 3 +#define MX53_INT_ESDHC4 4 +#define MX53_INT_RESV5 5 +#define MX53_INT_SDMA 6 +#define MX53_INT_IOMUX 7 +#define MX53_INT_NFC 8 +#define MX53_INT_VPU 9 +#define MX53_INT_IPU_ERR 10 +#define MX53_INT_IPU_SYN 11 +#define MX53_INT_GPU 12 +#define MX53_INT_RESV13 13 +#define MX53_INT_USB_H1 14 +#define MX53_INT_EMI 15 +#define MX53_INT_USB_H2 16 +#define MX53_INT_USB_H3 17 +#define MX53_INT_USB_OTG 18 +#define MX53_INT_SAHARA_H0 19 +#define MX53_INT_SAHARA_H1 20 +#define MX53_INT_SCC_SMN 21 +#define MX53_INT_SCC_STZ 22 +#define MX53_INT_SCC_SCM 23 +#define MX53_INT_SRTC_NTZ 24 +#define MX53_INT_SRTC_TZ 25 +#define MX53_INT_RTIC 26 +#define MX53_INT_CSU 27 +#define MX53_INT_SATA 28 +#define MX53_INT_SSI1 29 +#define MX53_INT_SSI2 30 +#define MX53_INT_UART1 31 +#define MX53_INT_UART2 32 +#define MX53_INT_UART3 33 +#define MX53_INT_RESV34 34 +#define MX53_INT_RESV35 35 +#define MX53_INT_ECSPI1 36 +#define MX53_INT_ECSPI2 37 +#define MX53_INT_CSPI 38 +#define MX53_INT_GPT 39 +#define MX53_INT_EPIT1 40 +#define MX53_INT_EPIT2 41 +#define MX53_INT_GPIO1_INT7 42 +#define MX53_INT_GPIO1_INT6 43 +#define MX53_INT_GPIO1_INT5 44 +#define MX53_INT_GPIO1_INT4 45 +#define MX53_INT_GPIO1_INT3 46 +#define MX53_INT_GPIO1_INT2 47 +#define MX53_INT_GPIO1_INT1 48 +#define MX53_INT_GPIO1_INT0 49 +#define MX53_INT_GPIO1_LOW 50 +#define MX53_INT_GPIO1_HIGH 51 +#define MX53_INT_GPIO2_LOW 52 +#define MX53_INT_GPIO2_HIGH 53 +#define MX53_INT_GPIO3_LOW 54 +#define MX53_INT_GPIO3_HIGH 55 +#define MX53_INT_GPIO4_LOW 56 +#define MX53_INT_GPIO4_HIGH 57 +#define MX53_INT_WDOG1 58 +#define MX53_INT_WDOG2 59 +#define MX53_INT_KPP 60 +#define MX53_INT_PWM1 61 +#define MX53_INT_I2C1 62 +#define MX53_INT_I2C2 63 +#define MX53_INT_I2C3 64 +#define MX53_INT_RESV65 65 +#define MX53_INT_RESV66 66 +#define MX53_INT_SPDIF 67 +#define MX53_INT_SIM_DAT 68 +#define MX53_INT_IIM 69 +#define MX53_INT_ATA 70 +#define MX53_INT_CCM1 71 +#define MX53_INT_CCM2 72 +#define MX53_INT_GPC1 73 +#define MX53_INT_GPC2 74 +#define MX53_INT_SRC 75 +#define MX53_INT_NM 76 +#define MX53_INT_PMU 77 +#define MX53_INT_CTI_IRQ 78 +#define MX53_INT_CTI1_TG0 79 +#define MX53_INT_CTI1_TG1 80 +#define MX53_INT_ESAI 81 +#define MX53_INT_CAN1 82 +#define MX53_INT_CAN2 83 +#define MX53_INT_GPU2_IRQ 84 +#define MX53_INT_GPU2_BUSY 85 +#define MX53_INT_RESV86 86 +#define MX53_INT_FEC 87 +#define MX53_INT_OWIRE 88 +#define MX53_INT_CTI1_TG2 89 +#define MX53_INT_SJC 90 +#define MX53_INT_TVE 92 +#define MX53_INT_FIRI 93 +#define MX53_INT_PWM2 94 +#define MX53_INT_SLIM_EXP 95 +#define MX53_INT_SSI3 96 +#define MX53_INT_EMI_BOOT 97 +#define MX53_INT_CTI1_TG3 98 +#define MX53_INT_SMC_RX 99 +#define MX53_INT_VPU_IDLE 100 +#define MX53_INT_EMI_NFC 101 +#define MX53_INT_GPU_IDLE 102 +#define MX53_INT_GPIO5_LOW 103 +#define MX53_INT_GPIO5_HIGH 104 +#define MX53_INT_GPIO6_LOW 105 +#define MX53_INT_GPIO6_HIGH 106 +#define MX53_INT_GPIO7_LOW 107 +#define MX53_INT_GPIO7_HIGH 108 + +/* silicon revisions specific to i.MX53 */ +#define MX53_CHIP_REV_1_0 0x10 +#define MX53_CHIP_REV_1_1 0x11 +#define MX53_CHIP_REV_1_2 0x12 +#define MX53_CHIP_REV_1_3 0x13 +#define MX53_CHIP_REV_2_0 0x20 +#define MX53_CHIP_REV_2_1 0x21 +#define MX53_CHIP_REV_2_2 0x22 +#define MX53_CHIP_REV_2_3 0x23 +#define MX53_CHIP_REV_3_0 0x30 +#define MX53_CHIP_REV_3_1 0x31 +#define MX53_CHIP_REV_3_2 0x32 + +/*! + * IIM bank info + */ +#define MXC_IIM_MX51_BANK_START_ADDR 0x0800 +#define MXC_IIM_MX51_BANK_END_ADDR 0x147c +#define MXC_IIM_MX53_BANK_START_ADDR 0x0800 +#define MXC_IIM_MX53_BANK_END_ADDR 0x183c +#define MXC_IIM_MX53_BANK_AREA_1_OFFSET 0xc00 +#define MXC_IIM_MX53_MAC_ADDR_OFFSET 0x24 + +#endif /* ifndef __MACH_MX53_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx6.h b/arch/arm/plat-mxc/include/mach/mx6.h new file mode 100644 index 00000000..50c2d5a7 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/mx6.h @@ -0,0 +1,594 @@ +/* + * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ASM_ARCH_MXC_MX6_H__ +#define __ASM_ARCH_MXC_MX6_H__ + +#ifndef __ASM_ARCH_MXC_HARDWARE_H__ +#error "Do not include directly." +#endif + +/*! + * @file arch-mxc/mx6.h + * @brief This file contains register definitions. + * + * @ingroup MSL_MX6 + */ + +/*! + * Register an interrupt handler for the SMN as well as the SCC. In some + * implementations, the SMN is not connected at all, and in others, it is + * on the same interrupt line as the SCM. Comment this line out accordingly + */ +#define USE_SMN_INTERRUPT + +/*! + * This option is used to set or clear the RXDMUXSEL bit in control reg 3. + * Certain platforms need this bit to be set in order to receive Irda data. + */ +#define MXC_UART_IR_RXDMUX 0x0004 +/*! + * This option is used to set or clear the RXDMUXSEL bit in control reg 3. + * Certain platforms need this bit to be set in order to receive UART data. + */ +#define MXC_UART_RXDMUX 0x0004 + +/*! + * The maximum frequency that the pixel clock can be at so as to + * activate DVFS-PER. + */ +#define DVFS_MAX_PIX_CLK 54000000 + +/* IROM + */ +#define IROM_BASE_ADDR 0x0 +#define IROM_SIZE SZ_64K + +/* CPU Memory Map */ +#define MMDC0_ARB_BASE_ADDR 0x10000000 +#define MMDC0_ARB_END_ADDR 0x7FFFFFFF +#define MMDC1_ARB_BASE_ADDR 0x80000000 +#define MMDC1_ARB_END_ADDR 0xFFFFFFFF +#define MX6SL_MMDC0_ARB_BASE_ADDR 0x80000000 /* only MX6SL */ +#define MX6SL_MMDC0_ARB_END_ADDR 0xFFFFFFFF +#define OCRAM_ARB_BASE_ADDR 0x00900000 +#define OCRAM_ARB_END_ADDR 0x009FFFFF +#define IRAM_BASE_ADDR OCRAM_ARB_BASE_ADDR +#define PCIE_ARB_BASE_ADDR 0x01000000 +#define PCIE_ARB_END_ADDR 0x01FFFFFF + +/* + * IRAM page table setup. + * The size defined here includes the code size plus the memory + * needed to store DDR IOMUX pad settings and the ARM SRPG registers. + */ +#define MX6_IRAM_TLB_BASE_ADDR IRAM_BASE_ADDR +#define MX6_IRAM_TLB_SIZE SZ_16K +#define TT_ATTRIB_NON_CACHEABLE_1M 0x802 +#define MX6Q_IRAM_BASE_ADDR (IRAM_BASE_ADDR + MX6_IRAM_TLB_SIZE) +#define MX6_SUSPEND_IRAM_CODE IRAM_BASE_ADDR +#define MX6_SUSPEND_CODE_SIZE 0x1400 +#define MX6_DDR_FREQ_IRAM_CODE (MX6_SUSPEND_IRAM_CODE + MX6_SUSPEND_CODE_SIZE) +#define MX6SL_DDR_FREQ_CODE_SIZE 0x500 +#define MX6SL_WFI_IRAM_CODE (MX6_DDR_FREQ_IRAM_CODE + MX6SL_DDR_FREQ_CODE_SIZE) +#define MX6SL_WFI_IRAM_CODE_SIZE SZ_8K - MX6_SUSPEND_CODE_SIZE - MX6SL_DDR_FREQ_CODE_SIZE + +/* The last 4K is for cpu hotplug to workaround wdog issue*/ +#define MX6Q_IRAM_SIZE (SZ_256K - SZ_4K) +#define MX6DL_MX6SL_IRAM_SIZE (SZ_128K - SZ_4K - MX6_IRAM_TLB_SIZE) + +/* Blocks connected via pl301periph */ +#define ROMCP_ARB_BASE_ADDR 0x00000000 +#define ROMCP_ARB_END_ADDR 0x000FFFFF +#define BOOT_ROM_BASE_ADDR ROMCP_ARB_BASE_ADDR +#define CAAM_SECMEM_BASE_ADDR 0x00100000 +#define CAAM_SECMEM_END_ADDR 0x00103FFF +#define APBH_DMA_ARB_BASE_ADDR 0x00110000 +#define APBH_DMA_ARB_END_ADDR 0x00117FFF +#define MX6Q_HDMI_ARB_BASE_ADDR 0x00120000 +#define MX6Q_HDMI_ARB_END_ADDR 0x00128FFF +#define GPU_3D_ARB_BASE_ADDR 0x00130000 +#define GPU_3D_ARB_END_ADDR 0x00133FFF +#define GPU_2D_ARB_BASE_ADDR 0x00134000 +#define GPU_2D_ARB_END_ADDR 0x00137FFF +#define MX6SL_GPU_2D_ARB_BASE_ADDR 0x02200000 /* MX6SL */ +#define MX6SL_GPU_2D_ARB_END_ADDR 0x02203FFF /* MX6SL */ +#define DTCP_ARB_BASE_ADDR 0x00138000 +#define DTCP_ARB_END_ADDR 0x0013BFFF + +/* GPV - PL301 configuration ports */ +#define GPV0_BASE_ADDR 0x00B00000 +#define GPV1_BASE_ADDR 0x00C00000 +#define GPV2_BASE_ADDR 0x00200000 +#define MX6SL_GPV2_BASE_ADDR 0x00D00000 /* GPV0-2 for MX6SL */ +#define GPV3_BASE_ADDR 0x00300000 +#define GPV4_BASE_ADDR 0x00800000 + +#define AIPS1_ARB_BASE_ADDR 0x02000000 +#define AIPS1_ARB_END_ADDR 0x020FFFFF +#define AIPS2_ARB_BASE_ADDR 0x02100000 +#define AIPS2_ARB_END_ADDR 0x021FFFFF +#define MX6Q_SATA_BASE_ADDR 0x02200000 +#define MX6Q_SATA_ARB_END_ADDR 0x02203FFF +#define OPENVG_ARB_BASE_ADDR 0x02204000 +#define OPENVG_ARB_END_ADDR 0x02207FFF +#define HSI_ARB_BASE_ADDR 0x02208000 +#define HSI_ARB_END_ADDR 0x0220BFFF +#define MX6Q_IPU1_ARB_BASE_ADDR 0x02400000 +#define MX6Q_IPU1_ARB_END_ADDR 0x027FFFFF +#define MX6Q_IPU2_ARB_BASE_ADDR 0x02800000 +#define MX6Q_IPU2_ARB_END_ADDR 0x02BFFFFF +#define WEIM_ARB_BASE_ADDR 0x08000000 +#define WEIM_ARB_END_ADDR 0x0FFFFFFF + +/* Legacy Defines */ +#define CSD0_DDR_BASE_ADDR MMDC0_ARB_BASE_ADDR +#define CSD1_DDR_BASE_ADDR MMDC1_ARB_BASE_ADDR +#define CS0_BASE_ADDR WEIM_ARB_BASE_ADDR +#define NAND_FLASH_BASE_ADDR APBH_DMA_ARB_BASE_ADDR +#define MX6Q_GPMI_BASE_ADDR (APBH_DMA_ARB_BASE_ADDR + 0x02000) +#define MX6Q_BCH_BASE_ADDR (APBH_DMA_ARB_BASE_ADDR + 0x04000) + +/* Defines for Blocks connected via AIPS (SkyBlue) */ +#define ATZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR +#define ATZ2_BASE_ADDR AIPS2_ARB_BASE_ADDR + +/* slots 0,7 of SDMA reserved, therefore left unused in IPMUX3 */ +#define MX6Q_SPDIF_BASE_ADDR (ATZ1_BASE_ADDR + 0x04000) /* slot 1 */ +#define MX6Q_ECSPI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x08000) /* slot 2 */ +#define MX6Q_ECSPI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x0C000) /* slot 3 */ +#define MX6Q_ECSPI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x10000) /* slot 4 */ +#define MX6Q_ECSPI4_BASE_ADDR (ATZ1_BASE_ADDR + 0x14000) /* slot 5 */ +#define MX6Q_ECSPI5_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000) /* slot 6 */ +#define MX6SL_UART5_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000) /* MX6SL */ +#define UART1_BASE_ADDR (ATZ1_BASE_ADDR + 0x20000) /* slot 8 */ +#define ESAI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000) /* slot 9 */ +#define MX6SL_UART1_BASE_ADDR (ATZ1_BASE_ADDR + 0x20000) /* MX6SL */ +#define MX6SL_UART2_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000) /* MX6SL */ +#define MX6Q_SSI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000) /* slot 10 */ +#define MX6Q_SSI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000) /* slot 11 */ +#define MX6Q_SSI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000) /* slot 12 */ +#define MX6Q_ASRC_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000) /* slot 13 */ +#define MX6SL_UART3_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000) /* MX6SL */ +#define MX6SL_UART4_BASE_ADDR (ATZ1_BASE_ADDR + 0x38000) /* MX6SL */ +#define SPBA_BASE_ADDR (ATZ1_BASE_ADDR + 0x3C000) /* slot 15 */ +#define MX6Q_VPU_BASE_ADDR (ATZ1_BASE_ADDR + 0x40000) /* slot 33, + global en[1], til 0x7BFFF */ + +/* ATZ#1- On Platform */ +#define AIPS1_ON_BASE_ADDR (ATZ1_BASE_ADDR + 0x7C000) + +/* ATZ#1- Off Platform */ +#define AIPS1_OFF_BASE_ADDR (ATZ1_BASE_ADDR + 0x80000) + +#define MX6Q_PWM1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x0000) +#define MX6Q_PWM2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4000) +#define MX6Q_PWM3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x8000) +#define MX6Q_PWM4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0xC000) +#define MX6Q_CAN1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x10000) +#define MX6SL_DBGMON_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x10000) +#define MX6Q_CAN2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x14000) +#define MX6SL_QOSC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x14000) +#define GPT_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x18000) +#define GPIO1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x1C000) +#define GPIO2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x20000) +#define GPIO3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x24000) +#define GPIO4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x28000) +#define GPIO5_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x2C000) +#define GPIO6_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x30000) +#define GPIO7_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000) +#define MX6SL_KPP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x38000) +#define MX6Q_WDOG1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x3C000) +#define MX6Q_WDOG2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x40000) +#define CCM_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x44000) +#define ANATOP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x48000) +#define USB_PHY0_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x49000) +#define USB_PHY1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4a000) +#define MX6Q_SNVS_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4C000) +#define EPIT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x50000) +#define EPIT2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x54000) +#define SRC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x58000) +#define GPC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x5C000) +#define MX6Q_IOMUXC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x60000) +#define DCIC1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000) +#define MX6SL_CSI_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000) +#define DCIC2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) +#define MX6SL_SIPIX_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) +#define MX6Q_SDMA_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) +#define MX6DL_EPXP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x70000) +#define MX6DL_EPDC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x74000) +#define MX6DL_ELCDIF_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x78000) +#define MX6SL_DCP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x7C000) +#define MX6Q_DVFSCORE_BASE_ADDR (GPC_BASE_ADDR + 0x180) + +/* ATZ#2- On Platform */ +#define AIPS2_ON_BASE_ADDR (ATZ2_BASE_ADDR + 0x7C000) + +/* ATZ#2- Off Platform */ +#define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000) + +/* ATZ#2 - Global enable (0) */ +#define CAAM_BASE_ADDR ATZ2_BASE_ADDR +#define ARM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000) + +/* ARM Cortex A9 MPCore Platform */ +#define MX6Q_A9_PLATFRM_BASE (ARM_BASE_ADDR + 0x20000) + +/* ARM Cortex A9 PTM */ +#define MX6Q_PTM0_BASE_ADDR 0x0215C000 +#define MX6Q_PTM1_BASE_ADDR 0x0215D000 +#define MX6Q_PTM2_BASE_ADDR 0x0215E000 +#define MX6Q_PTM3_BASE_ADDR 0x0215F000 +#define MX6Q_FUNNEL_BASE_ADDR 0x02144000 +#define MX6Q_ETB_BASE_ADDR 0x02141000 + +#define MX6Q_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000) +#define MX6Q_USB_OTG_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000) +#define MX6Q_USB_HS1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4200) +#define MX6Q_USB_HS2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4400) +#define MX6Q_USB_HS3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4600) +#define MX6SL_USB_HS1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4200) +#define MX6SL_USB_HS2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4400) +#define MX6SL_USB_HS3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4600) +#define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x8000) +#define MLB_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0xC000) +#define MX6SL_MSHC_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0xC000) + +#define MXC_CAAM_BASE_ADDR (AIPS2_ARB_BASE_ADDR + 0x00000) + +#define MX6Q_USDHC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x10000) +#define MX6Q_USDHC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x14000) +#define MX6Q_USDHC3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x18000) +#define MX6Q_USDHC4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x1C000) +#define MX6Q_I2C1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x20000) +#define MX6Q_I2C2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x24000) +#define MX6Q_I2C3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x28000) +#define MX6SL_I2C4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000) +#define ROMCP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x2C000) +#define MMDC_P0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x30000) +#define MMDC_P1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000) +#define MX6SL_RNGB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000) +#define WEIM_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x38000) +#define OCOTP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x3C000) +#define CSU_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x40000) +#define IP2APB_PERFMON1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000) +#define IP2APB_PERFMON2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000) +#define IP2APB_PERFMON3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000) +#define IP2APB_TZASC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x50000) +#define IP2APB_TZASC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000) +#define MX6Q_AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000) +#define MIPI_CSI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000) +#define MIPI_DSI_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000) +#define VDOA_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000) +#define UART2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x68000) +#define UART3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x6C000) +#define UART4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x70000) +#define UART5_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x74000) +#define MX6DL_I2C4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000) + +/* Cortex-A9 MPCore private memory region */ +#define ARM_PERIPHBASE 0x00A00000 +#define SCU_BASE_ADDR ARM_PERIPHBASE +#define LOCAL_TWD_ADDR (SCU_BASE_ADDR + 0x600) +#define IC_INTERFACES_BASE_ADDR (ARM_PERIPHBASE + 0x0100) +#define GLOBAL_TIMER_BASE_ADDR (ARM_PERIPHBASE + 0x0200) +#define PRIVATE_TIMERS_WD_BASE_ADDR (ARM_PERIPHBASE + 0x0600) +#define IC_DISTRIBUTOR_BASE_ADDR (ARM_PERIPHBASE + 0x1000) +#define L2_BASE_ADDR (ARM_PERIPHBASE + 0x2000) + + +#define MX6Q_UART1_BASE_ADDR UART1_BASE_ADDR +#define MX6Q_UART2_BASE_ADDR UART2_BASE_ADDR +#define MX6Q_UART3_BASE_ADDR UART3_BASE_ADDR +#define MX6Q_UART4_BASE_ADDR UART4_BASE_ADDR +#define MX6Q_UART5_BASE_ADDR UART5_BASE_ADDR + +#define MX6Q_FEC_BASE_ADDR ENET_BASE_ADDR +#define MX6DL_FEC_BASE_ADDR ENET_BASE_ADDR +#define MX6Q_MIPI_DSI_BASE_ADDR MIPI_DSI_BASE_ADDR +#define MX6Q_MIPI_CSI2_BASE_ADDR MIPI_CSI2_BASE_ADDR + +/* define virtual address */ +#define PERIPBASE_VIRT 0xF2000000 +#define BOOT_ROM_BASE_ADDR_VIRT (PERIPBASE_VIRT + BOOT_ROM_BASE_ADDR) +#define AIPS1_BASE_ADDR_VIRT (PERIPBASE_VIRT + AIPS1_ARB_BASE_ADDR) +#define AIPS2_BASE_ADDR_VIRT (PERIPBASE_VIRT + AIPS2_ARB_BASE_ADDR) +#define ARM_PERIPHBASE_VIRT (PERIPBASE_VIRT + ARM_PERIPHBASE) +#define IRAM_BASE_ADDR_VIRT (PERIPBASE_VIRT + IRAM_BASE_ADDR) +#define L2_BASE_ADDR_VIRT (PERIPBASE_VIRT + L2_BASE_ADDR) +#define ROMCP_SIZE SZ_1M +#define AIPS1_SIZE SZ_1M +#define AIPS2_SIZE SZ_1M +#define ARM_PERIPHBASE_SIZE (SZ_8K + SZ_4K) +#define IRAM_VIRT_SIZE SZ_1M + +#define SRC_GPR9 0x40 +#define SRC_GPR10 0x44 + +#define SNVS_LPGPR 0x68 + +/* GPC offsets */ +#define MXC_GPC_CNTR_OFFSET 0x0 + +#define MX6_IO_ADDRESS(x) (void __force __iomem *)((x) + PERIPBASE_VIRT) + +/*! + * This macro defines the physical to virtual address mapping for all the + * peripheral modules. It is used by passing in the physical address as x + * and returning the virtual address. If the physical address is not mapped, + * it returns 0xDEADBEEF + */ +#define IO_ADDRESS(x) \ + (((((x) >= (unsigned long)AIPS1_ARB_BASE_ADDR) && \ + ((x) <= (unsigned long)AIPS2_ARB_END_ADDR)) || \ + ((x) >= (unsigned long)ARM_PERIPHBASE && \ + ((x) <= (unsigned long)(ARM_PERIPHBASE + ARM_PERIPHBASE_SIZE)))) ? \ + MX6_IO_ADDRESS(x) : (void __force __iomem *)0xDEADBEEF) + +/* + * Interrupt numbers + */ +#define MXC_INT_START 32 +#define MXC_INT_GPR 32 +#define MXC_INT_CHEETAH_CSYSPWRUPREQ 33 +#define MX6Q_INT_SDMA 34 +#define MX6Q_INT_VPU_JPG 35 +#define MX6DL_INT_MSHC 35 +#define MXC_INT_INTERRUPT_36_NUM 36 +#define MX6Q_INT_IPU1_ERR 37 +#define MX6SL_INT_RNGB 37 +#define MX6Q_INT_IPU1_SYN 38 +#define MX6SL_INT_SPDC 38 +#define MX6Q_INT_IPU2_ERR 39 +#define MX6DL_INT_CSI 39 +#define MX6SL_INT_CSI 39 +#define MX6Q_INT_IPU2_SYN 40 +#define MXC_INT_GPU3D_IRQ 41 +#define MXC_INT_GPU2D_IRQ 42 +#define MXC_INT_OPENVG_XAQ2 43 +#define MX6Q_INT_VPU_IPI 44 +#define MXC_INT_APBHDMA_DMA 45 +#define MXC_INT_WEIM 46 +#define MXC_INT_RAWNAND_BCH 47 +#define MXC_INT_RAWNAND_GPMI 48 +#define MXC_INT_DTCP 49 +#define MXC_INT_VDOA 50 +#define MX6Q_INT_SNVS 51 +#define MXC_INT_SNVS_SEC 52 +#define MXC_INT_CSU 53 +#define MX6Q_INT_USDHC1 54 +#define MX6Q_INT_USDHC2 55 +#define MX6Q_INT_USDHC3 56 +#define MX6Q_INT_USDHC4 57 +#define MXC_INT_UART1_ANDED 58 +#define MXC_INT_UART2_ANDED 59 +#define MXC_INT_UART3_ANDED 60 +#define MXC_INT_UART4_ANDED 61 +#define MXC_INT_UART5_ANDED 62 +#define MX6Q_INT_ECSPI1 63 +#define MX6Q_INT_ECSPI2 64 +#define MX6Q_INT_ECSPI3 65 +#define MX6Q_INT_ECSPI4 66 +#define MX6Q_INT_ECSPI5 67 +#define MX6DL_INT_I2C4 67 +#define MX6Q_INT_I2C1 68 +#define MX6Q_INT_I2C2 69 +#define MX6Q_INT_I2C3 70 +#define MX6Q_INT_SATA 71 +#define MX6DL_INT_ELCDIF 71 +#define MX6Q_INT_USB_HS1 72 +#define MX6SL_INT_USB_HS1 74 +#define MX6Q_INT_USB_HS2 73 +#define MX6SL_INT_USB_HS2 72 +#define MX6Q_INT_USB_HS3 74 +#define MX6SL_INT_USB_HS3 73 +#define MX6Q_INT_USB_OTG 75 +#define MX6Q_INT_USB_PHY0 76 +#define MX6Q_INT_USB_PHY1 77 +#define MX6SL_INT_USB_PHY0 76 +#define MX6SL_INT_USB_PHY1 77 +/* + * MX6Q_INT_USB_PHY2, MX6Q_INT_USB_PHY3 are dummy interrupts + * In order to compile pass for platform device's definition + */ +#define MX6Q_INT_USB_PHY2 73 +#define MX6Q_INT_USB_PHY3 74 +#define MX6SL_INT_USB_PHY2 72 +#define MX6SL_INT_USB_PHY3 73 +#define MX6Q_INT_SSI1 78 +#define MX6Q_INT_SSI2 79 +#define MX6Q_INT_SSI3 80 +#define MXC_INT_ANATOP_TEMPSNSR 81 +#define MX6Q_INT_ASRC 82 +#define MXC_INT_ESAI 83 +#define MX6Q_INT_SPDIF 84 +#define MXC_INT_MLB 85 +#define MXC_INT_ANATOP_ANA1 86 +#define MXDL_INT_PMU 86 +#define MXC_INT_GPT 87 +#define MXC_INT_EPIT1 88 +#define MXC_INT_EPIT2 89 +#define MXC_INT_GPIO1_INT7_NUM 90 +#define MXC_INT_GPIO1_INT6_NUM 91 +#define MXC_INT_GPIO1_INT5_NUM 92 +#define MXC_INT_GPIO1_INT4_NUM 93 +#define MXC_INT_GPIO1_INT3_NUM 94 +#define MXC_INT_GPIO1_INT2_NUM 95 +#define MXC_INT_GPIO1_INT1_NUM 96 +#define MXC_INT_GPIO1_INT0_NUM 97 +#define MXC_INT_GPIO1_INT15_0_NUM 98 +#define MXC_INT_GPIO1_INT31_16_NUM 99 +#define MXC_INT_GPIO2_INT15_0_NUM 100 +#define MXC_INT_GPIO2_INT31_16_NUM 101 +#define MXC_INT_GPIO3_INT15_0_NUM 102 +#define MXC_INT_GPIO3_INT31_16_NUM 103 +#define MXC_INT_GPIO4_INT15_0_NUM 104 +#define MXC_INT_GPIO4_INT31_16_NUM 105 +#define MXC_INT_GPIO5_INT15_0_NUM 106 +#define MXC_INT_GPIO5_INT31_16_NUM 107 +#define MXC_INT_GPIO6_INT15_0_NUM 108 +#define MXC_INT_GPIO6_INT31_16_NUM 109 +#define MXC_INT_GPIO7_INT15_0_NUM 110 +#define MXC_INT_GPIO7_INT31_16_NUM 111 +#define MX6Q_INT_WDOG1 112 +#define MX6Q_INT_WDOG2 113 +#define MXC_INT_KPP 114 +#define MX6SL_INT_KPP 114 +#define MX6Q_INT_PWM1 115 +#define MX6Q_INT_PWM2 116 +#define MX6Q_INT_PWM3 117 +#define MX6Q_INT_PWM4 118 +#define MXC_INT_CCM_INT1_NUM 119 +#define MXC_INT_CCM_INT2_NUM 120 +#define MX6Q_INT_GPC1 121 +#define MXC_INT_GPC_INT2_NUM 122 +#define MXC_INT_SRC 123 +#define MXC_INT_CHEETAH_L2 124 +#define MXC_INT_CHEETAH_PARITY 125 +#define MXC_INT_CHEETAH_PERFORM 126 +#define MXC_INT_CHEETAH_TRIGGER 127 +#define MXC_INT_SRC_CPU_WDOG 128 +#define MX6DL_INT_EPDC 129 +#define MX6DL_INT_EPXP 130 +#define MXC_INT_INTERRUPT_131_NUM 131 +#define MX6SL_INT_DCP_GEN 131 +#define MX6SL_INT_DCP_CH0 132 +#define MX6SL_INT_DCP_SEC 133 +#define MXC_INT_CSI_INTR1 132 +#define MXC_INT_CSI_INTR2 133 +#define MXC_INT_DSI 134 +#define MXC_INT_HSI 135 +#define MXC_INT_SJC 136 +#define MXC_INT_CAAM_INT0_NUM 137 +#define MXC_INT_CAAM_INT1_NUM 138 +#define MXC_INT_INTERRUPT_139_NUM 139 +#define MXC_INT_TZASC1 140 +#define MXC_INT_TZASC2 141 +#define MX6Q_INT_CAN1 142 +#define MX6Q_INT_CAN2 143 +#define MX6Q_INT_PERFMON1 144 +#define MX6Q_INT_PERFMON2 145 +#define MX6Q_INT_PERFMON3 146 +#define MX6DL_INT_FEC 146 +#define MX6Q_INT_HDMI_TX 147 +#define MX6Q_INT_HDMI_TX_WAKEUP 148 +#define MXC_INT_MLB_AHB0 149 +#define MXC_INT_ENET1 150 +#define MXC_INT_ENET2 151 +#define MXC_INT_PCIE_0 152 +#define MXC_INT_PCIE_1 153 +#define MXC_INT_PCIE_2 154 +#define MXC_INT_PCIE_3 155 +#define MXC_INT_DCIC1 156 +#define MXC_INT_DCIC2 157 +#define MXC_INT_MLB_AHB1 158 +#define MXC_INT_ANATOP_ANA2 159 +#define MXC_INT_END 159 + +#define MX6Q_INT_UART1 MXC_INT_UART1_ANDED +#define MX6Q_INT_UART2 MXC_INT_UART2_ANDED +#define MX6Q_INT_UART3 MXC_INT_UART3_ANDED +#define MX6Q_INT_UART4 MXC_INT_UART4_ANDED +#define MX6Q_INT_UART5 MXC_INT_UART5_ANDED +#define MX6SL_INT_UART1 MXC_INT_UART1_ANDED +#define MX6SL_INT_UART2 MXC_INT_UART2_ANDED +#define MX6SL_INT_UART3 MXC_INT_UART3_ANDED +#define MX6SL_INT_UART4 MXC_INT_UART4_ANDED +#define MX6SL_INT_UART5 MXC_INT_UART5_ANDED +#define MX6Q_INT_FEC MXC_INT_ENET1 +#define MX6Q_INT_DSI MXC_INT_DSI + +#define IRQ_LOCALTIMER 29 + +/* APBH-DMA */ +#define MX6Q_DMA_CHANNEL_AHB_APBH_GPMI0 0 +#define MX6Q_DMA_CHANNEL_AHB_APBH_GPMI1 1 +#define MX6Q_DMA_CHANNEL_AHB_APBH_GPMI2 2 +#define MX6Q_DMA_CHANNEL_AHB_APBH_GPMI3 3 +#define MX6Q_DMA_CHANNEL_AHB_APBH_GPMI4 4 +#define MX6Q_DMA_CHANNEL_AHB_APBH_GPMI5 5 +#define MX6Q_DMA_CHANNEL_AHB_APBH_GPMI6 6 +#define MX6Q_DMA_CHANNEL_AHB_APBH_GPMI7 7 + +/* + * DMA request assignments + */ +#define MX6Q_DMA_REQ_VPU 0 +#define MX6Q_DMA_REQ_GPC 1 +#define MX6Q_DMA_REQ_IPU1 2 +#define MX6Q_DMA_REQ_EXT_DMA_REQ_0 2 +#define MX6Q_DMA_REQ_CSPI1_RX 3 +#define MX6Q_DMA_REQ_I2C3_A 3 +#define MX6Q_DMA_REQ_CSPI1_TX 4 +#define MX6Q_DMA_REQ_I2C2_A 4 +#define MX6Q_DMA_REQ_CSPI2_RX 5 +#define MX6Q_DMA_REQ_I2C1_A 5 +#define MX6Q_DMA_REQ_CSPI2_TX 6 +#define MX6Q_DMA_REQ_CSPI3_RX 7 +#define MX6Q_DMA_REQ_CSPI3_TX 8 +#define MX6Q_DMA_REQ_CSPI4_RX 9 +#define MX6Q_DMA_REQ_EPIT2 9 +#define MX6Q_DMA_REQ_CSPI4_TX 10 +#define MX6Q_DMA_REQ_I2C1_B 10 +#define MX6Q_DMA_REQ_CSPI5_RX 11 +#define MX6Q_DMA_REQ_CSPI5_TX 12 +#define MX6Q_DMA_REQ_GPT 13 +#define MX6Q_DMA_REQ_SPDIF_RX 14 +#define MX6Q_DMA_REQ_EXT_DMA_REQ_1 14 +#define MX6Q_DMA_REQ_SPDIF_TX 15 +#define MX6Q_DMA_REQ_EPIT1 16 +#define MX6Q_DMA_REQ_ASRC_RX1 17 +#define MX6Q_DMA_REQ_ASRC_RX2 18 +#define MX6Q_DMA_REQ_ASRC_RX3 19 +#define MX6Q_DMA_REQ_ASRC_TX1 20 +#define MX6Q_DMA_REQ_ASRC_TX2 21 +#define MX6Q_DMA_REQ_ASRC_TX3 22 +#define MX6Q_DMA_REQ_ESAI_RX 23 +#define MX6Q_DMA_REQ_I2C3_B 23 +#define MX6Q_DMA_REQ_ESAI_TX 24 +#define MX6Q_DMA_REQ_UART1_RX 25 +#define MX6Q_DMA_REQ_UART1_TX 26 +#define MX6Q_DMA_REQ_UART2_RX 27 +#define MX6Q_DMA_REQ_UART2_TX 28 +#define MX6Q_DMA_REQ_UART3_RX 29 +#define MX6Q_DMA_REQ_UART3_TX 30 +#define MX6Q_DMA_REQ_UART4_RX 31 +#define MX6Q_DMA_REQ_UART4_TX 32 +#define MX6Q_DMA_REQ_UART5_RX 33 +#define MX6Q_DMA_REQ_UART5_TX 34 +#define MX6Q_DMA_REQ_SSI1_RX1 35 +#define MX6Q_DMA_REQ_SSI1_TX1 36 +#define MX6Q_DMA_REQ_SSI1_RX0 37 +#define MX6Q_DMA_REQ_SSI1_TX0 38 +#define MX6Q_DMA_REQ_SSI2_RX1 39 +#define MX6Q_DMA_REQ_SSI2_TX1 40 +#define MX6Q_DMA_REQ_SSI2_RX0 41 +#define MX6Q_DMA_REQ_SSI2_TX0 42 +#define MX6Q_DMA_REQ_SSI3_RX1 43 +#define MX6Q_DMA_REQ_SSI3_TX1 44 +#define MX6Q_DMA_REQ_SSI3_RX0 45 +#define MX6Q_DMA_REQ_SSI3_TX0 46 +#define MX6Q_DMA_REQ_DTCP 47 + +#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) +extern int mx6q_revision(void); +extern int mx6dl_revision(void); +extern int mx6sl_revision(void); +#endif + +#endif /* __ASM_ARCH_MXC_MX6_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h new file mode 100755 index 00000000..75b99aff --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/mxc.h @@ -0,0 +1,318 @@ +/* + * Copyright 2004-2007, 2011-2013 Freescale Semiconductor, Inc. + * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#ifndef __ASM_ARCH_MXC_H__ +#define __ASM_ARCH_MXC_H__ + +#include <linux/types.h> + +#ifndef __ASM_ARCH_MXC_HARDWARE_H__ +#error "Do not include directly." +#endif + +#define MXC_CPU_MX1 1 +#define MXC_CPU_MX21 21 +#define MXC_CPU_MX25 25 +#define MXC_CPU_MX27 27 +#define MXC_CPU_MX31 31 +#define MXC_CPU_MX35 35 +#define MXC_CPU_MX37 37 +#define MXC_CPU_MX50 50 +#define MXC_CPU_MX51 51 +#define MXC_CPU_MX53 53 +#define MXC_CPU_MX6Q 63 +#define MXC_CPU_MX6DL 61 +#define MXC_CPU_MX6SL 60 + +#define IMX_CHIP_REVISION_1_0 0x10 +#define IMX_CHIP_REVISION_1_1 0x11 +#define IMX_CHIP_REVISION_1_2 0x12 +#define IMX_CHIP_REVISION_1_3 0x13 +#define IMX_CHIP_REVISION_2_0 0x20 +#define IMX_CHIP_REVISION_2_1 0x21 +#define IMX_CHIP_REVISION_2_2 0x22 +#define IMX_CHIP_REVISION_2_3 0x23 +#define IMX_CHIP_REVISION_3_0 0x30 +#define IMX_CHIP_REVISION_3_1 0x31 +#define IMX_CHIP_REVISION_3_2 0x32 +#define IMX_CHIP_REVISION_3_3 0x33 +#define IMX_CHIP_REVISION_UNKNOWN 0xff + +#define IMX_CHIP_REVISION_1_0_STRING "1.0" +#define IMX_CHIP_REVISION_1_1_STRING "1.1" +#define IMX_CHIP_REVISION_1_2_STRING "1.2" +#define IMX_CHIP_REVISION_1_3_STRING "1.3" +#define IMX_CHIP_REVISION_2_0_STRING "2.0" +#define IMX_CHIP_REVISION_2_1_STRING "2.1" +#define IMX_CHIP_REVISION_2_2_STRING "2.2" +#define IMX_CHIP_REVISION_2_3_STRING "2.3" +#define IMX_CHIP_REVISION_3_0_STRING "3.0" +#define IMX_CHIP_REVISION_3_1_STRING "3.1" +#define IMX_CHIP_REVISION_3_2_STRING "3.2" +#define IMX_CHIP_REVISION_3_3_STRING "3.3" +#define IMX_CHIP_REVISION_UNKNOWN_STRING "unknown" +#define IMX_BOARD_REV_1 0x000 +#define IMX_BOARD_REV_2 0x100 +#define IMX_BOARD_REV_3 0x200 +#define IMX_BOARD_REV_4 0x300 + +#ifndef __ASSEMBLY__ +extern unsigned int system_rev; +#define board_is_rev(rev) (((system_rev & 0x0F00) == rev) ? 1 : 0) +#define imx_cpu_ver() (system_rev & 0xFF) + +#endif + +#ifdef CONFIG_ARCH_MX5 +#define board_is_mx53_loco_mc34708() (cpu_is_mx53() && \ + (board_is_rev(IMX_BOARD_REV_2) || board_is_rev(IMX_BOARD_REV_4))) +#define board_is_mx53_arm2() (cpu_is_mx53() && board_is_rev(IMX_BOARD_REV_2)) +#define board_is_mx53_evk_a() (cpu_is_mx53() && board_is_rev(IMX_BOARD_REV_1)) +#define board_is_mx53_evk_b() (cpu_is_mx53() && board_is_rev(IMX_BOARD_REV_3)) +#endif + +#ifdef CONFIG_SOC_IMX6Q +#define board_is_mx6q_arm2() (cpu_is_mx6q() && \ + board_is_rev(IMX_BOARD_REV_1)) +#define board_is_mx6q_sabre_lite() (cpu_is_mx6q() && \ + board_is_rev(IMX_BOARD_REV_2)) +#define board_is_mx6q_sabre_auto() (cpu_is_mx6q() && \ + board_is_rev(IMX_BOARD_REV_3)) +#define board_is_mx6sl_evk() (cpu_is_mx6sl() && \ + board_is_rev(IMX_BOARD_REV_3)) + +#define board_is_mx6_unknown() \ + board_is_rev(IMX_BOARD_REV_1) +#define board_is_mx6_reva() \ + board_is_rev(IMX_BOARD_REV_2) +#define board_is_mx6_revb() \ + board_is_rev(IMX_BOARD_REV_3) +#define board_is_mx6_revc() \ + board_is_rev(IMX_BOARD_REV_4) +#endif + +#ifndef __ASSEMBLY__ +extern unsigned int __mxc_cpu_type; +#endif + +#ifdef CONFIG_ARCH_MX1 +# ifdef mxc_cpu_type +# undef mxc_cpu_type +# define mxc_cpu_type __mxc_cpu_type +# else +# define mxc_cpu_type MXC_CPU_MX1 +# endif +# define cpu_is_mx1() (mxc_cpu_type == MXC_CPU_MX1) +#else +# define cpu_is_mx1() (0) +#endif + +#ifdef CONFIG_MACH_MX21 +# ifdef mxc_cpu_type +# undef mxc_cpu_type +# define mxc_cpu_type __mxc_cpu_type +# else +# define mxc_cpu_type MXC_CPU_MX21 +# endif +# define cpu_is_mx21() (mxc_cpu_type == MXC_CPU_MX21) +#else +# define cpu_is_mx21() (0) +#endif + +#ifdef CONFIG_ARCH_MX25 +# ifdef mxc_cpu_type +# undef mxc_cpu_type +# define mxc_cpu_type __mxc_cpu_type +# else +# define mxc_cpu_type MXC_CPU_MX25 +# endif +# define cpu_is_mx25() (mxc_cpu_type == MXC_CPU_MX25) +#else +# define cpu_is_mx25() (0) +#endif + +#ifdef CONFIG_MACH_MX27 +# ifdef mxc_cpu_type +# undef mxc_cpu_type +# define mxc_cpu_type __mxc_cpu_type +# else +# define mxc_cpu_type MXC_CPU_MX27 +# endif +# define cpu_is_mx27() (mxc_cpu_type == MXC_CPU_MX27) +#else +# define cpu_is_mx27() (0) +#endif + +#ifdef CONFIG_SOC_IMX31 +# ifdef mxc_cpu_type +# undef mxc_cpu_type +# define mxc_cpu_type __mxc_cpu_type +# else +# define mxc_cpu_type MXC_CPU_MX31 +# endif +# define cpu_is_mx31() (mxc_cpu_type == MXC_CPU_MX31) +#else +# define cpu_is_mx31() (0) +#endif + +# define cpu_is_mx32() (0) + +#ifdef CONFIG_SOC_IMX35 +# ifdef mxc_cpu_type +# undef mxc_cpu_type +# define mxc_cpu_type __mxc_cpu_type +# else +# define mxc_cpu_type MXC_CPU_MX35 +# endif +# define cpu_is_mx35() (mxc_cpu_type == MXC_CPU_MX35) +#else +# define cpu_is_mx35() (0) +#endif + +#ifdef CONFIG_SOC_IMX37 +# ifdef mxc_cpu_type +# undef mxc_cpu_type +# define mxc_cpu_type __mxc_cpu_type +# else +# define mxc_cpu_type MXC_CPU_MX37 +# endif +# define cpu_is_mx37() (mxc_cpu_type == MXC_CPU_MX37) +#else +# define cpu_is_mx37() (0) +#endif + +#ifdef CONFIG_SOC_IMX50 +# ifdef mxc_cpu_type +# undef mxc_cpu_type +# define mxc_cpu_type __mxc_cpu_type +# else +# define mxc_cpu_type MXC_CPU_MX50 +# endif +# define cpu_is_mx50() (mxc_cpu_type == MXC_CPU_MX50) +#else +# define cpu_is_mx50() (0) +#endif + +#ifdef CONFIG_SOC_IMX51 +# ifdef mxc_cpu_type +# undef mxc_cpu_type +# define mxc_cpu_type __mxc_cpu_type +# else +# define mxc_cpu_type MXC_CPU_MX51 +# endif +# define cpu_is_mx51() (mxc_cpu_type == MXC_CPU_MX51) +#else +# define cpu_is_mx51() (0) +#endif + +#ifdef CONFIG_SOC_IMX53 +# ifdef mxc_cpu_type +# undef mxc_cpu_type +# define mxc_cpu_type __mxc_cpu_type +# else +# define mxc_cpu_type MXC_CPU_MX53 +# endif +# define cpu_is_mx53() (mxc_cpu_type == MXC_CPU_MX53) +#else +# define cpu_is_mx53() (0) +#endif + +#ifdef CONFIG_SOC_IMX6Q +# define mxc_cpu_type __mxc_cpu_type +# define cpu_is_mx6q() (mxc_cpu_type == MXC_CPU_MX6Q) +# define cpu_is_mx6dl() (mxc_cpu_type == MXC_CPU_MX6DL) +# define cpu_is_mx6sl() (mxc_cpu_type == MXC_CPU_MX6SL) +#else +# define cpu_is_mx6q() (0) +# define cpu_is_mx6dl() (0) +# define cpu_is_mx6sl() (0) +#endif + +#ifndef __ASSEMBLY__ + +struct cpu_op { + u32 pll_reg; + u32 pll_rate; + u32 pll_lpm_rate; + u32 cpu_rate; + u32 pdr0_reg; + u32 pdf; + u32 mfi; + u32 mfd; + u32 mfn; + u32 pu_voltage; + u32 soc_voltage; + u32 cpu_voltage; + u32 cpu_podf; +}; + +enum mxc_cpu_pwr_mode { + WAIT_CLOCKED, /* wfi only */ + WAIT_UNCLOCKED, /* WAIT */ + WAIT_UNCLOCKED_POWER_OFF, /* WAIT + SRPG */ + STOP_XTAL_ON, /* STOP + SRPG + XTAL_ON*/ + STOP_POWER_OFF, /* STOP + XTAL_OFF */ + ARM_POWER_OFF, /* STOP + SRPG + ARM power off */ +}; + +int tzic_enable_wake(int is_idle); + +extern void mxc_cpu_lp_set(enum mxc_cpu_pwr_mode mode); +extern int tzic_enable_wake(int is_idle); + +/* available disableable devices in fuse */ +enum mxc_dev_type { + MXC_DEV_PXP, + MXC_DEV_OVG, + MXC_DEV_DSI_CSI2, + MXC_DEV_ENET, + MXC_DEV_MLB, + MXC_DEV_EPDC, + MXC_DEV_HDMI, + MXC_DEV_PCIE, + MXC_DEV_SATA, + MXC_DEV_DTCP, + MXC_DEV_2D, + MXC_DEV_3D, + MXC_DEV_VPU, + MXC_DEV_DIVX3, + MXC_DEV_RV, + MXC_DEV_SORENSEN, +}; +extern int fuse_dev_is_available(enum mxc_dev_type dev); + +#endif + +#if defined(CONFIG_ARCH_MX3) || defined(CONFIG_ARCH_MX2) +/* These are deprecated, use mx[23][157]_setup_weimcs instead. */ +#define CSCR_U(n) (IO_ADDRESS(WEIM_BASE_ADDR + n * 0x10)) +#define CSCR_L(n) (IO_ADDRESS(WEIM_BASE_ADDR + n * 0x10 + 0x4)) +#define CSCR_A(n) (IO_ADDRESS(WEIM_BASE_ADDR + n * 0x10 + 0x8)) +#endif + +#define cpu_is_mx5() (cpu_is_mx51() || cpu_is_mx53() || cpu_is_mx50()) +#define cpu_is_mx3() (cpu_is_mx31() || cpu_is_mx35()) +#define cpu_is_mx2() (cpu_is_mx21() || cpu_is_mx27()) +#define cpu_is_mx6() (cpu_is_mx6q() || cpu_is_mx6dl() || cpu_is_mx6sl()) + +#define MXC_PGCR_PCR 1 +#define MXC_SRPGCR_PCR 1 +#define MXC_EMPGCR_PCR 1 +#define MXC_PGSR_PSR 1 +#endif /* __ASM_ARCH_MXC_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mxc91231.h b/arch/arm/plat-mxc/include/mach/mxc91231.h new file mode 100755 index 00000000..765190fe --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/mxc91231.h @@ -0,0 +1,256 @@ +/* + * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved. + * - Platform specific register memory map + * + * Copyright 2005-2007 Motorola, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef __MACH_MXC91231_H__ +#define __MACH_MXC91231_H__ + +/* + * L2CC + */ +#define MXC91231_L2CC_BASE_ADDR 0x30000000 +#define MXC91231_L2CC_SIZE SZ_64K + +/* + * AIPS 1 + */ +#define MXC91231_AIPS1_BASE_ADDR 0x43F00000 +#define MXC91231_AIPS1_SIZE SZ_1M + +#define MXC91231_AIPS1_CTRL_BASE_ADDR MXC91231_AIPS1_BASE_ADDR +#define MXC91231_MAX_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x04000) +#define MXC91231_EVTMON_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x08000) +#define MXC91231_CLKCTL_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x0C000) +#define MXC91231_ETB_SLOT4_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x10000) +#define MXC91231_ETB_SLOT5_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x14000) +#define MXC91231_ECT_CTIO_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x18000) +#define MXC91231_I2C_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x80000) +#define MXC91231_MU_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x88000) +#define MXC91231_UART1_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x90000) +#define MXC91231_UART2_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x94000) +#define MXC91231_DSM_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x98000) +#define MXC91231_OWIRE_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x9C000) +#define MXC91231_SSI1_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0xA0000) +#define MXC91231_KPP_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0xA8000) +#define MXC91231_IOMUX_AP_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0xAC000) +#define MXC91231_CTI_AP_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0xB8000) + +/* + * AIPS 2 + */ +#define MXC91231_AIPS2_BASE_ADDR 0x53F00000 +#define MXC91231_AIPS2_SIZE SZ_1M + +#define MXC91231_GEMK_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0x8C000) +#define MXC91231_GPT1_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0x90000) +#define MXC91231_EPIT1_AP_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0x94000) +#define MXC91231_SCC_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xAC000) +#define MXC91231_RNGA_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xB0000) +#define MXC91231_IPU_CTRL_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xC0000) +#define MXC91231_AUDMUX_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xC4000) +#define MXC91231_EDIO_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xC8000) +#define MXC91231_GPIO1_AP_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xCC000) +#define MXC91231_GPIO2_AP_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xD0000) +#define MXC91231_SDMA_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xD4000) +#define MXC91231_RTC_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xD8000) +#define MXC91231_WDOG1_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xDC000) +#define MXC91231_PWM_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xE0000) +#define MXC91231_GPIO3_AP_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xE4000) +#define MXC91231_WDOG2_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xE8000) +#define MXC91231_RTIC_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xEC000) +#define MXC91231_LPMC_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xF0000) + +/* + * SPBA global module 0 + */ +#define MXC91231_SPBA0_BASE_ADDR 0x50000000 +#define MXC91231_SPBA0_SIZE SZ_1M + +#define MXC91231_MMC_SDHC1_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x04000) +#define MXC91231_MMC_SDHC2_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x08000) +#define MXC91231_UART3_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x0C000) +#define MXC91231_CSPI2_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x10000) +#define MXC91231_SSI2_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x14000) +#define MXC91231_SIM_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x18000) +#define MXC91231_IIM_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x1C000) +#define MXC91231_CTI_SDMA_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x20000) +#define MXC91231_USBOTG_CTRL_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x24000) +#define MXC91231_USBOTG_DATA_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x28000) +#define MXC91231_CSPI1_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x30000) +#define MXC91231_SPBA_CTRL_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x3C000) +#define MXC91231_IOMUX_COM_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x40000) +#define MXC91231_CRM_COM_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x44000) +#define MXC91231_CRM_AP_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x48000) +#define MXC91231_PLL0_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x4C000) +#define MXC91231_PLL1_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x50000) +#define MXC91231_PLL2_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x54000) +#define MXC91231_GPIO4_SH_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x58000) +#define MXC91231_HAC_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x5C000) +#define MXC91231_SAHARA_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x5C000) +#define MXC91231_PLL3_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x60000) + +/* + * SPBA global module 1 + */ +#define MXC91231_SPBA1_BASE_ADDR 0x52000000 +#define MXC91231_SPBA1_SIZE SZ_1M + +#define MXC91231_MQSPI_BASE_ADDR (MXC91231_SPBA1_BASE_ADDR + 0x34000) +#define MXC91231_EL1T_BASE_ADDR (MXC91231_SPBA1_BASE_ADDR + 0x38000) + +/*! + * Defines for SPBA modules + */ +#define MXC91231_SPBA_SDHC1 0x04 +#define MXC91231_SPBA_SDHC2 0x08 +#define MXC91231_SPBA_UART3 0x0C +#define MXC91231_SPBA_CSPI2 0x10 +#define MXC91231_SPBA_SSI2 0x14 +#define MXC91231_SPBA_SIM 0x18 +#define MXC91231_SPBA_IIM 0x1C +#define MXC91231_SPBA_CTI_SDMA 0x20 +#define MXC91231_SPBA_USBOTG_CTRL_REGS 0x24 +#define MXC91231_SPBA_USBOTG_DATA_REGS 0x28 +#define MXC91231_SPBA_CSPI1 0x30 +#define MXC91231_SPBA_MQSPI 0x34 +#define MXC91231_SPBA_EL1T 0x38 +#define MXC91231_SPBA_IOMUX 0x40 +#define MXC91231_SPBA_CRM_COM 0x44 +#define MXC91231_SPBA_CRM_AP 0x48 +#define MXC91231_SPBA_PLL0 0x4C +#define MXC91231_SPBA_PLL1 0x50 +#define MXC91231_SPBA_PLL2 0x54 +#define MXC91231_SPBA_GPIO4 0x58 +#define MXC91231_SPBA_SAHARA 0x5C + +/* + * ROMP and AVIC + */ +#define MXC91231_ROMP_BASE_ADDR 0x60000000 +#define MXC91231_ROMP_SIZE SZ_64K + +#define MXC91231_AVIC_BASE_ADDR 0x68000000 +#define MXC91231_AVIC_SIZE SZ_64K + +/* + * NAND, SDRAM, WEIM, M3IF, EMI controllers + */ +#define MXC91231_X_MEMC_BASE_ADDR 0xB8000000 +#define MXC91231_X_MEMC_SIZE SZ_64K + +#define MXC91231_NFC_BASE_ADDR (MXC91231_X_MEMC_BASE_ADDR + 0x0000) +#define MXC91231_ESDCTL_BASE_ADDR (MXC91231_X_MEMC_BASE_ADDR + 0x1000) +#define MXC91231_WEIM_BASE_ADDR (MXC91231_X_MEMC_BASE_ADDR + 0x2000) +#define MXC91231_M3IF_BASE_ADDR (MXC91231_X_MEMC_BASE_ADDR + 0x3000) +#define MXC91231_EMI_CTL_BASE_ADDR (MXC91231_X_MEMC_BASE_ADDR + 0x4000) + +/* + * Memory regions and CS + * CPLD is connected on CS4 + * CS5 is TP1021 or it is not connected + * */ +#define MXC91231_FB_RAM_BASE_ADDR 0x78000000 +#define MXC91231_FB_RAM_SIZE SZ_256K +#define MXC91231_CSD0_BASE_ADDR 0x80000000 +#define MXC91231_CSD1_BASE_ADDR 0x90000000 +#define MXC91231_CS0_BASE_ADDR 0xA0000000 +#define MXC91231_CS1_BASE_ADDR 0xA8000000 +#define MXC91231_CS2_BASE_ADDR 0xB0000000 +#define MXC91231_CS3_BASE_ADDR 0xB2000000 +#define MXC91231_CS4_BASE_ADDR 0xB4000000 +#define MXC91231_CS5_BASE_ADDR 0xB6000000 + +/* + * This macro defines the physical to virtual address mapping for all the + * peripheral modules. It is used by passing in the physical address as x + * and returning the virtual address. + */ +#define MXC91231_IO_P2V(x) IMX_IO_P2V(x) +#define MXC91231_IO_ADDRESS(x) IOMEM(MXC91231_IO_P2V(x)) + +/* + * Interrupt numbers + */ +#define MXC91231_INT_GPIO3 0 +#define MXC91231_INT_EL1T_CI 1 +#define MXC91231_INT_EL1T_RFCI 2 +#define MXC91231_INT_EL1T_RFI 3 +#define MXC91231_INT_EL1T_MCU 4 +#define MXC91231_INT_EL1T_IPI 5 +#define MXC91231_INT_MU_GEN 6 +#define MXC91231_INT_GPIO4 7 +#define MXC91231_INT_MMC_SDHC2 8 +#define MXC91231_INT_MMC_SDHC1 9 +#define MXC91231_INT_I2C 10 +#define MXC91231_INT_SSI2 11 +#define MXC91231_INT_SSI1 12 +#define MXC91231_INT_CSPI2 13 +#define MXC91231_INT_CSPI1 14 +#define MXC91231_INT_RTIC 15 +#define MXC91231_INT_SAHARA 15 +#define MXC91231_INT_HAC 15 +#define MXC91231_INT_UART3_RX 16 +#define MXC91231_INT_UART3_TX 17 +#define MXC91231_INT_UART3_MINT 18 +#define MXC91231_INT_ECT 19 +#define MXC91231_INT_SIM_IPB 20 +#define MXC91231_INT_SIM_DATA 21 +#define MXC91231_INT_RNGA 22 +#define MXC91231_INT_DSM_AP 23 +#define MXC91231_INT_KPP 24 +#define MXC91231_INT_RTC 25 +#define MXC91231_INT_PWM 26 +#define MXC91231_INT_GEMK_AP 27 +#define MXC91231_INT_EPIT 28 +#define MXC91231_INT_GPT 29 +#define MXC91231_INT_UART2_RX 30 +#define MXC91231_INT_UART2_TX 31 +#define MXC91231_INT_UART2_MINT 32 +#define MXC91231_INT_NANDFC 33 +#define MXC91231_INT_SDMA 34 +#define MXC91231_INT_USB_WAKEUP 35 +#define MXC91231_INT_USB_SOF 36 +#define MXC91231_INT_PMU_EVTMON 37 +#define MXC91231_INT_USB_FUNC 38 +#define MXC91231_INT_USB_DMA 39 +#define MXC91231_INT_USB_CTRL 40 +#define MXC91231_INT_IPU_ERR 41 +#define MXC91231_INT_IPU_SYN 42 +#define MXC91231_INT_UART1_RX 43 +#define MXC91231_INT_UART1_TX 44 +#define MXC91231_INT_UART1_MINT 45 +#define MXC91231_INT_IIM 46 +#define MXC91231_INT_MU_RX_OR 47 +#define MXC91231_INT_MU_TX_OR 48 +#define MXC91231_INT_SCC_SCM 49 +#define MXC91231_INT_SCC_SMN 50 +#define MXC91231_INT_GPIO2 51 +#define MXC91231_INT_GPIO1 52 +#define MXC91231_INT_MQSPI1 53 +#define MXC91231_INT_MQSPI2 54 +#define MXC91231_INT_WDOG2 55 +#define MXC91231_INT_EXT_INT7 56 +#define MXC91231_INT_EXT_INT6 57 +#define MXC91231_INT_EXT_INT5 58 +#define MXC91231_INT_EXT_INT4 59 +#define MXC91231_INT_EXT_INT3 60 +#define MXC91231_INT_EXT_INT2 61 +#define MXC91231_INT_EXT_INT1 62 +#define MXC91231_INT_EXT_INT0 63 + +#define MXC91231_MAX_INT_LINES 63 +#define MXC91231_MAX_EXT_LINES 8 + +#endif /* __MACH_MXC91231_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mxc_asrc.h b/arch/arm/plat-mxc/include/mach/mxc_asrc.h new file mode 100644 index 00000000..1b73c477 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/mxc_asrc.h @@ -0,0 +1,26 @@ +/* + * Copyright (C) 2011 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#ifndef __MACH_ASRC_H +#define __MACH_ASRC_H + +struct imx_asrc_platform_data { + struct clk *asrc_core_clk; + struct clk *asrc_audio_clk; + unsigned int channel_bits; + int clk_map_ver; +}; + +#endif /* __MACH_ASRC_H */ + diff --git a/arch/arm/plat-mxc/include/mach/mxc_dvfs.h b/arch/arm/plat-mxc/include/mach/mxc_dvfs.h new file mode 100755 index 00000000..64639ae8 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/mxc_dvfs.h @@ -0,0 +1,277 @@ +/* + * Copyright (C) 2009-2012 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @defgroup DVFS Dynamic Voltage and Frequency Scaling (DVFS) Driver + */ + +/*! + * @file arch-mxc/mxc_dvfs.h + * + * @brief This file contains the DVFS configuration structure definition. + * + * + * @ingroup DVFS + */ + +#ifndef __ASM_ARCH_MXC_DVFS_H__ +#define __ASM_ARCH_MXC_DVFS_H__ + +#ifdef __KERNEL__ + +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/workqueue.h> +#include <linux/device.h> + +extern void __iomem *gpc_base; +extern void __iomem *ccm_base; + +#define MXC_GPCCNTR_GPCIRQ2M (1 << 25) +#define MXC_GPCCNTR_GPCIRQ2 (1 << 24) +#define MXC_GPCCNTR_GPCIRQM (1 << 21) +#define MXC_GPCCNTR_GPCIRQ_ARM (1 << 20) +#define MXC_GPCCNTR_GPCIRQ_SDMA (0 << 20) +#define MXC_GPCCNTR_DVFS0CR (1 << 16) +#define MXC_GPCCNTR_DVFS1CR (1 << 17) +#define MXC_GPCCNTR_ADU_MASK 0x8000 +#define MXC_GPCCNTR_ADU (1 << 15) +#define MXC_GPCCNTR_STRT (1 << 14) +#define MXC_GPCCNTR_FUPD_MASK 0x2000 +#define MXC_GPCCNTR_FUPD (1 << 13) +#define MXC_GPCCNTR_HTRI_MASK 0x0000000F +#define MXC_GPCCNTR_HTRI_OFFSET 0 + +#define MXC_GPCVCR_VINC_MASK 0x00020000 +#define MXC_GPCVCR_VINC_OFFSET 17 +#define MXC_GPCVCR_VCNTU_MASK 0x00010000 +#define MXC_GPCVCR_VCNTU_OFFSET 16 +#define MXC_GPCVCR_VCNT_MASK 0x00007FFF +#define MXC_GPCVCR_VCNT_OFFSET 0 + +/* DVFS-PER */ +#define MXC_DVFSPER_PMCR0_UDCS (1 << 27) +#define MXC_DVFSPER_PMCR0_UDCS_MASK 0x8000000 +#define MXC_DVFSPER_PMCR0_ENABLE_MASK 0x10 +#define MXC_DVFSPER_PMCR0_ENABLE (1 << 4) + +#define MXC_DVFSLTR0_UPTHR_MASK 0x0FC00000 +#define MXC_DVFSLTR0_UPTHR_OFFSET 22 +#define MXC_DVFSLTR0_DNTHR_MASK 0x003F0000 +#define MXC_DVFSLTR0_DNTHR_OFFSET 16 + +#define MXC_DVFSLTR1_PNCTHR_MASK 0x0000003F +#define MXC_DVFSLTR1_PNCTHR_OFFSET 0 +#define MXC_DVFSLTR1_DNCNT_MASK 0x003FC000 +#define MXC_DVFSLTR1_DNCNT_OFFSET 14 +#define MXC_DVFSLTR1_UPCNT_MASK 0x00003FC0 +#define MXC_DVFSLTR1_UPCNT_OFFSET 6 +#define MXC_DVFSLTR1_LTBRSR 0x800000 +#define MXC_DVFSLTR1_LTBRSH 0x400000 + +#define MXC_DVFSLTR2_EMAC_MASK 0x000001FF +#define MXC_DVFSLTR2_EMAC_OFFSET 0 + +#define MXC_DVFSPMCR0_UDCS 0x8000000 +#define MXC_DVFSPMCR0_DVFEV 0x800000 +#define MXC_DVFSPMCR0_DVFIS 0x400000 +#define MXC_DVFSPMCR0_LBMI 0x200000 +#define MXC_DVFSPMCR0_LBFL 0x100000 +#define MXC_DVFSPMCR0_LBFC_MASK 0xC0000 +#define MXC_DVFSPMCR0_LBFC_OFFSET 18 +#define MXC_DVFSPMCR0_FSVAIM 0x00008000 +#define MXC_DVFSPMCR0_FSVAI_MASK 0x00006000 +#define MXC_DVFSPMCR0_FSVAI_OFFSET 13 +#define MXC_DVFSPMCR0_WFIM 0x00000400 +#define MXC_DVFSPMCR0_WFIM_OFFSET 10 +#define MXC_DVFSPMCR0_DVFEN 0x00000010 + +#define MXC_DVFSPMCR1_P1INM 0x00100000 +#define MXC_DVFSPMCR1_P1ISM 0x00080000 +#define MXC_DVFSPMCR1_P1IFM 0x00040000 +#define MXC_DVFSPMCR1_P4PM 0x00020000 +#define MXC_DVFSPMCR1_P2PM 0x00010000 + +/* DVFS CORE register offsets*/ +#define MXC_DVFSCORE_THRS 0x00 +#define MXC_DVFSCORE_COUN 0x04 +#define MXC_DVFSCORE_SIG1 0x08 +#define MXC_DVFSCORE_SIG0 0x0C +#define MXC_DVFSCORE_GPC0 0x10 +#define MXC_DVFSCORE_GPC1 0x14 +#define MXC_DVFSCORE_GPBT 0x18 +#define MXC_DVFSCORE_EMAC 0x1C +#define MXC_DVFSCORE_CNTR 0x20 +#define MXC_DVFSCORE_LTR0_0 0x24 +#define MXC_DVFSCORE_LTR0_1 0x28 +#define MXC_DVFSCORE_LTR1_0 0x2C +#define MXC_DVFSCORE_LTR1_1 0x30 +#define MXC_DVFSCORE_PT0 0x34 +#define MXC_DVFSCORE_PT1 0x38 +#define MXC_DVFSCORE_PT2 0x3C +#define MXC_DVFSCORE_PT3 0x40 + +/* + * DVFS structure + */ +struct dvfs_op { + int upthr; + int downthr; + int panicthr; + int upcnt; + int downcnt; + int emac; +}; + +struct mxc_dvfs_platform_data { + /** Supply voltage regulator name string */ + char *reg_id; + /*vdd_soc regulator name string*/ + char *soc_id; + /*vdd_pu regulator name string*/ + char *pu_id; + /* CPU clock name string */ + char *clk1_id; + /* DVFS clock name string */ + char *clk2_id; + /* The base address of the DVFS core */ + void __iomem *membase; + /* The interrupt number used by the DVFS core */ + int irq; + /* GPC control reg offset */ + int gpc_cntr_offset; + /* GPC voltage counter reg offset */ + int gpc_vcr_offset; + /* CCM DVFS control reg offset */ + int ccm_cdcr_offset; + /* CCM ARM clock root reg offset */ + int ccm_cacrr_offset; + /* CCM divider handshake in-progress reg offset */ + int ccm_cdhipr_offset; + /* PREDIV mask */ + u32 prediv_mask; + /* PREDIV offset */ + int prediv_offset; + /* PREDIV value */ + int prediv_val; + /* DIV3CK mask */ + u32 div3ck_mask; + /* DIV3CK offset */ + int div3ck_offset; + /* DIV3CK value */ + int div3ck_val; + /* EMAC value */ + int emac_val; + /* Frequency increase threshold. Increase frequency change request + will be sent if DVFS counter value will be more than this value */ + int upthr_val; + /* Frequency decrease threshold. Decrease frequency change request + will be sent if DVFS counter value will be less than this value */ + int dnthr_val; + /* Panic threshold. Panic frequency change request + will be sent if DVFS counter value will be more than this value */ + int pncthr_val; + /* The amount of times the up threshold should be exceeded + before DVFS will trigger frequency increase request */ + int upcnt_val; + /* The amount of times the down threshold should be exceeded + before DVFS will trigger frequency decrease request */ + int dncnt_val; + /* Delay time in us */ + int delay_time; +}; + +/*! + * This structure is used to define the dvfs controller's platform + * data. It includes the regulator name string and DVFS clock name string. + */ +struct mxc_dvfsper_data { + /** Regulator name string */ + char *reg_id; + /* DVFS clock name string */ + char *clk_id; + /* The base address of the DVFS per */ + void __iomem *membase; + /* GPC control reg address */ + void __iomem *gpc_cntr_reg_addr; + /* GPC VCR reg address */ + void __iomem *gpc_vcr_reg_addr; + /* DVFS enable bit */ + u32 dvfs_enable_bit; + /* DVFS ADU bit */ + int gpc_adu; + /* VAI mask */ + u32 vai_mask; + /* VAI offset */ + int vai_offset; + /* Mask DVFS interrupt */ + u32 irq_mask; + /* Div3 clock offset. */ + u32 div3_offset; + /*div3 clock mask. */ + u32 div3_mask; + /*div3 clock divider */ + u32 div3_div; + /* LP voltage - high setpoint*/ + u32 lp_high; + /* LP voltage - low setpoint*/ + u32 lp_low; +}; + +/*! + * This structure is used to define the platform data of bus freq + * driver. It includes the regulator name strings. + */ +struct mxc_regulator_platform_data { + /* VDDGP regulator name */ + char *cpu_reg_id; + /* VCC regulator name */ + char *vcc_reg_id; +}; + +#if defined(CONFIG_MXC_DVFS_PER) +extern int start_dvfs_per(void); +extern void stop_dvfs_per(void); +extern int dvfs_per_active(void); +extern int dvfs_per_divider_active(void); +extern int dvfs_per_pixel_clk_limit(void); +#else +static inline int start_dvfs_per(void) +{ + return 0; +} + +static inline void stop_dvfs_per(void) +{ +} + +static inline int dvfs_per_active(void) +{ + return 0; +} + +static inline int dvfs_per_divider_active(void) +{ + return 0; +} + +static inline int dvfs_per_pixel_clk_limit(void) +{ + return 0; +} + +#endif + +#endif /* __KERNEL__ */ + +#endif /* __ASM_ARCH_MXC_DVFS_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mxc_edid.h b/arch/arm/plat-mxc/include/mach/mxc_edid.h new file mode 100755 index 00000000..38bad6b7 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/mxc_edid.h @@ -0,0 +1,105 @@ +/* + * Copyright 2009-2012 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @defgroup Framebuffer Framebuffer Driver for SDC and ADC. + */ + +/*! + * @file mxc_edid.h + * + * @brief MXC EDID tools + * + * @ingroup Framebuffer + */ + +#ifndef MXC_EDID_H +#define MXC_EDID_H + +#include <linux/fb.h> + +#define FB_VMODE_ASPECT_4_3 0x10 +#define FB_VMODE_ASPECT_16_9 0x20 +#define FB_VMODE_ASPECT_MASK (FB_VMODE_ASPECT_4_3 | FB_VMODE_ASPECT_16_9) + +enum cea_audio_coding_types { + AUDIO_CODING_TYPE_REF_STREAM_HEADER = 0, + AUDIO_CODING_TYPE_LPCM = 1, + AUDIO_CODING_TYPE_AC3 = 2, + AUDIO_CODING_TYPE_MPEG1 = 3, + AUDIO_CODING_TYPE_MP3 = 4, + AUDIO_CODING_TYPE_MPEG2 = 5, + AUDIO_CODING_TYPE_AACLC = 6, + AUDIO_CODING_TYPE_DTS = 7, + AUDIO_CODING_TYPE_ATRAC = 8, + AUDIO_CODING_TYPE_SACD = 9, + AUDIO_CODING_TYPE_EAC3 = 10, + AUDIO_CODING_TYPE_DTS_HD = 11, + AUDIO_CODING_TYPE_MLP = 12, + AUDIO_CODING_TYPE_DST = 13, + AUDIO_CODING_TYPE_WMAPRO = 14, + AUDIO_CODING_TYPE_RESERVED = 15, +}; + +struct mxc_hdmi_3d_format { + unsigned char vic_order_2d; + unsigned char struct_3d; + unsigned char detail_3d; + unsigned char reserved; +}; + +struct mxc_edid_cfg { + bool cea_underscan; + bool cea_basicaudio; + bool cea_ycbcr444; + bool cea_ycbcr422; + bool hdmi_cap; + + /*VSD*/ + bool vsd_support_ai; + bool vsd_dc_48bit; + bool vsd_dc_36bit; + bool vsd_dc_30bit; + bool vsd_dc_y444; + bool vsd_dvi_dual; + + bool vsd_cnc0; + bool vsd_cnc1; + bool vsd_cnc2; + bool vsd_cnc3; + + u8 vsd_video_latency; + u8 vsd_audio_latency; + u8 vsd_I_video_latency; + u8 vsd_I_audio_latency; + + u8 physical_address[4]; + u8 hdmi_vic[64]; + struct mxc_hdmi_3d_format hdmi_3d_format[64]; + u16 hdmi_3d_mask_all; + u16 hdmi_3d_struct_all; + u32 vsd_max_tmdsclk_rate; + + u8 max_channels; + u8 sample_sizes; + u8 sample_rates; + u8 speaker_alloc; +}; + +int mxc_edid_var_to_vic(struct fb_var_screeninfo *var); +int mxc_edid_mode_to_vic(const struct fb_videomode *mode); +int mxc_edid_read(struct i2c_adapter *adp, unsigned short addr, + unsigned char *edid, struct mxc_edid_cfg *cfg, struct fb_info *fbi); +int mxc_edid_parse_ext_blk(unsigned char *edid, struct mxc_edid_cfg *cfg, + struct fb_monspecs *specs); +#endif diff --git a/arch/arm/plat-mxc/include/mach/mxc_ehci.h b/arch/arm/plat-mxc/include/mach/mxc_ehci.h new file mode 100644 index 00000000..2c159dc2 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/mxc_ehci.h @@ -0,0 +1,57 @@ +#ifndef __INCLUDE_ASM_ARCH_MXC_EHCI_H +#define __INCLUDE_ASM_ARCH_MXC_EHCI_H + +/* values for portsc field */ +#define MXC_EHCI_PHY_LOW_POWER_SUSPEND (1 << 23) +#define MXC_EHCI_FORCE_FS (1 << 24) +#define MXC_EHCI_UTMI_8BIT (0 << 28) +#define MXC_EHCI_UTMI_16BIT (1 << 28) +#define MXC_EHCI_SERIAL (1 << 29) +#define MXC_EHCI_MODE_UTMI (0 << 30) +#define MXC_EHCI_MODE_PHILIPS (1 << 30) +#define MXC_EHCI_MODE_ULPI (2 << 30) +#define MXC_EHCI_MODE_SERIAL (3 << 30) + +/* values for flags field */ +#define MXC_EHCI_INTERFACE_DIFF_UNI (0 << 0) +#define MXC_EHCI_INTERFACE_DIFF_BI (1 << 0) +#define MXC_EHCI_INTERFACE_SINGLE_UNI (2 << 0) +#define MXC_EHCI_INTERFACE_SINGLE_BI (3 << 0) +#define MXC_EHCI_INTERFACE_MASK (0xf) + +#define MXC_EHCI_POWER_PINS_ENABLED (1 << 5) +#define MXC_EHCI_TTL_ENABLED (1 << 6) + +#define MXC_EHCI_INTERNAL_PHY (1 << 7) +#define MXC_EHCI_IPPUE_DOWN (1 << 8) +#define MXC_EHCI_IPPUE_UP (1 << 9) +#define MXC_EHCI_WAKEUP_ENABLED (1 << 10) +#define MXC_EHCI_ITC_NO_THRESHOLD (1 << 11) + +#define MXC_USBCTRL_OFFSET 0 +#define MXC_USB_PHY_CTR_FUNC_OFFSET 0x8 +#define MXC_USB_PHY_CTR_FUNC2_OFFSET 0xc +#define MXC_USBH2CTRL_OFFSET 0x14 + +#define MX5_USBOTHER_REGS_OFFSET 0x800 + +/* USB_PHY_CTRL_FUNC2*/ +#define MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK 0x3 +#define MX5_USB_UTMI_PHYCTRL1_PLLDIV_SHIFT 0 + +struct mxc_usbh_platform_data { + int (*init)(struct platform_device *pdev); + int (*exit)(struct platform_device *pdev); + + unsigned int portsc; + struct otg_transceiver *otg; +}; + +int mx51_initialize_usb_hw(int port, unsigned int flags); +int mx25_initialize_usb_hw(int port, unsigned int flags); +int mx31_initialize_usb_hw(int port, unsigned int flags); +int mx35_initialize_usb_hw(int port, unsigned int flags); +int mx27_initialize_usb_hw(int port, unsigned int flags); + +#endif /* __INCLUDE_ASM_ARCH_MXC_EHCI_H */ + diff --git a/arch/arm/plat-mxc/include/mach/mxc_gpu.h b/arch/arm/plat-mxc/include/mach/mxc_gpu.h new file mode 100644 index 00000000..a43d6ec9 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/mxc_gpu.h @@ -0,0 +1,24 @@ +/* + * Copyright (C) 2011 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#ifndef __MACH_MXC_GPU_H_ +#define __MACH_MXC_GPU_H_ + +struct mxc_gpu_platform_data { + int z160_revision; + resource_size_t reserved_mem_base; + resource_size_t reserved_mem_size; +}; + +#endif /* __MACH_MXC_GPU_H_ */ diff --git a/arch/arm/plat-mxc/include/mach/mxc_hdmi.h b/arch/arm/plat-mxc/include/mach/mxc_hdmi.h new file mode 100644 index 00000000..94f76380 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/mxc_hdmi.h @@ -0,0 +1,1095 @@ +/* + * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __MXC_HDMI_H__ +#define __MXC_HDMI_H__ + +/* + * Hdmi controller registers + */ + +/* Identification Registers */ +#define HDMI_DESIGN_ID 0x0000 +#define HDMI_REVISION_ID 0x0001 +#define HDMI_PRODUCT_ID0 0x0002 +#define HDMI_PRODUCT_ID1 0x0003 +#define HDMI_CONFIG0_ID 0x0004 +#define HDMI_CONFIG1_ID 0x0005 +#define HDMI_CONFIG2_ID 0x0006 +#define HDMI_CONFIG3_ID 0x0007 + +/* Interrupt Registers */ +#define HDMI_IH_FC_STAT0 0x0100 +#define HDMI_IH_FC_STAT1 0x0101 +#define HDMI_IH_FC_STAT2 0x0102 +#define HDMI_IH_AS_STAT0 0x0103 +#define HDMI_IH_PHY_STAT0 0x0104 +#define HDMI_IH_I2CM_STAT0 0x0105 +#define HDMI_IH_CEC_STAT0 0x0106 +#define HDMI_IH_VP_STAT0 0x0107 +#define HDMI_IH_I2CMPHY_STAT0 0x0108 +#define HDMI_IH_AHBDMAAUD_STAT0 0x0109 + +#define HDMI_IH_MUTE_FC_STAT0 0x0180 +#define HDMI_IH_MUTE_FC_STAT1 0x0181 +#define HDMI_IH_MUTE_FC_STAT2 0x0182 +#define HDMI_IH_MUTE_AS_STAT0 0x0183 +#define HDMI_IH_MUTE_PHY_STAT0 0x0184 +#define HDMI_IH_MUTE_I2CM_STAT0 0x0185 +#define HDMI_IH_MUTE_CEC_STAT0 0x0186 +#define HDMI_IH_MUTE_VP_STAT0 0x0187 +#define HDMI_IH_MUTE_I2CMPHY_STAT0 0x0188 +#define HDMI_IH_MUTE_AHBDMAAUD_STAT0 0x0189 +#define HDMI_IH_MUTE 0x01FF + +/* Video Sample Registers */ +#define HDMI_TX_INVID0 0x0200 +#define HDMI_TX_INSTUFFING 0x0201 +#define HDMI_TX_GYDATA0 0x0202 +#define HDMI_TX_GYDATA1 0x0203 +#define HDMI_TX_RCRDATA0 0x0204 +#define HDMI_TX_RCRDATA1 0x0205 +#define HDMI_TX_BCBDATA0 0x0206 +#define HDMI_TX_BCBDATA1 0x0207 + +/* Video Packetizer Registers */ +#define HDMI_VP_STATUS 0x0800 +#define HDMI_VP_PR_CD 0x0801 +#define HDMI_VP_STUFF 0x0802 +#define HDMI_VP_REMAP 0x0803 +#define HDMI_VP_CONF 0x0804 +#define HDMI_VP_STAT 0x0805 +#define HDMI_VP_INT 0x0806 +#define HDMI_VP_MASK 0x0807 +#define HDMI_VP_POL 0x0808 + +/* Frame Composer Registers */ +#define HDMI_FC_INVIDCONF 0x1000 +#define HDMI_FC_INHACTV0 0x1001 +#define HDMI_FC_INHACTV1 0x1002 +#define HDMI_FC_INHBLANK0 0x1003 +#define HDMI_FC_INHBLANK1 0x1004 +#define HDMI_FC_INVACTV0 0x1005 +#define HDMI_FC_INVACTV1 0x1006 +#define HDMI_FC_INVBLANK 0x1007 +#define HDMI_FC_HSYNCINDELAY0 0x1008 +#define HDMI_FC_HSYNCINDELAY1 0x1009 +#define HDMI_FC_HSYNCINWIDTH0 0x100A +#define HDMI_FC_HSYNCINWIDTH1 0x100B +#define HDMI_FC_VSYNCINDELAY 0x100C +#define HDMI_FC_VSYNCINWIDTH 0x100D +#define HDMI_FC_INFREQ0 0x100E +#define HDMI_FC_INFREQ1 0x100F +#define HDMI_FC_INFREQ2 0x1010 +#define HDMI_FC_CTRLDUR 0x1011 +#define HDMI_FC_EXCTRLDUR 0x1012 +#define HDMI_FC_EXCTRLSPAC 0x1013 +#define HDMI_FC_CH0PREAM 0x1014 +#define HDMI_FC_CH1PREAM 0x1015 +#define HDMI_FC_CH2PREAM 0x1016 +#define HDMI_FC_AVICONF3 0x1017 +#define HDMI_FC_GCP 0x1018 +#define HDMI_FC_AVICONF0 0x1019 +#define HDMI_FC_AVICONF1 0x101A +#define HDMI_FC_AVICONF2 0x101B +#define HDMI_FC_AVIVID 0x101C +#define HDMI_FC_AVIETB0 0x101D +#define HDMI_FC_AVIETB1 0x101E +#define HDMI_FC_AVISBB0 0x101F +#define HDMI_FC_AVISBB1 0x1020 +#define HDMI_FC_AVIELB0 0x1021 +#define HDMI_FC_AVIELB1 0x1022 +#define HDMI_FC_AVISRB0 0x1023 +#define HDMI_FC_AVISRB1 0x1024 +#define HDMI_FC_AUDICONF0 0x1025 +#define HDMI_FC_AUDICONF1 0x1026 +#define HDMI_FC_AUDICONF2 0x1027 +#define HDMI_FC_AUDICONF3 0x1028 +#define HDMI_FC_VSDIEEEID0 0x1029 +#define HDMI_FC_VSDSIZE 0x102A +#define HDMI_FC_VSDIEEEID1 0x1030 +#define HDMI_FC_VSDIEEEID2 0x1031 +#define HDMI_FC_VSDPAYLOAD0 0x1032 +#define HDMI_FC_VSDPAYLOAD1 0x1033 +#define HDMI_FC_VSDPAYLOAD2 0x1034 +#define HDMI_FC_VSDPAYLOAD3 0x1035 +#define HDMI_FC_VSDPAYLOAD4 0x1036 +#define HDMI_FC_VSDPAYLOAD5 0x1037 +#define HDMI_FC_VSDPAYLOAD6 0x1038 +#define HDMI_FC_VSDPAYLOAD7 0x1039 +#define HDMI_FC_VSDPAYLOAD8 0x103A +#define HDMI_FC_VSDPAYLOAD9 0x103B +#define HDMI_FC_VSDPAYLOAD10 0x103C +#define HDMI_FC_VSDPAYLOAD11 0x103D +#define HDMI_FC_VSDPAYLOAD12 0x103E +#define HDMI_FC_VSDPAYLOAD13 0x103F +#define HDMI_FC_VSDPAYLOAD14 0x1040 +#define HDMI_FC_VSDPAYLOAD15 0x1041 +#define HDMI_FC_VSDPAYLOAD16 0x1042 +#define HDMI_FC_VSDPAYLOAD17 0x1043 +#define HDMI_FC_VSDPAYLOAD18 0x1044 +#define HDMI_FC_VSDPAYLOAD19 0x1045 +#define HDMI_FC_VSDPAYLOAD20 0x1046 +#define HDMI_FC_VSDPAYLOAD21 0x1047 +#define HDMI_FC_VSDPAYLOAD22 0x1048 +#define HDMI_FC_VSDPAYLOAD23 0x1049 +#define HDMI_FC_SPDVENDORNAME0 0x104A +#define HDMI_FC_SPDVENDORNAME1 0x104B +#define HDMI_FC_SPDVENDORNAME2 0x104C +#define HDMI_FC_SPDVENDORNAME3 0x104D +#define HDMI_FC_SPDVENDORNAME4 0x104E +#define HDMI_FC_SPDVENDORNAME5 0x104F +#define HDMI_FC_SPDVENDORNAME6 0x1050 +#define HDMI_FC_SPDVENDORNAME7 0x1051 +#define HDMI_FC_SDPPRODUCTNAME0 0x1052 +#define HDMI_FC_SDPPRODUCTNAME1 0x1053 +#define HDMI_FC_SDPPRODUCTNAME2 0x1054 +#define HDMI_FC_SDPPRODUCTNAME3 0x1055 +#define HDMI_FC_SDPPRODUCTNAME4 0x1056 +#define HDMI_FC_SDPPRODUCTNAME5 0x1057 +#define HDMI_FC_SDPPRODUCTNAME6 0x1058 +#define HDMI_FC_SDPPRODUCTNAME7 0x1059 +#define HDMI_FC_SDPPRODUCTNAME8 0x105A +#define HDMI_FC_SDPPRODUCTNAME9 0x105B +#define HDMI_FC_SDPPRODUCTNAME10 0x105C +#define HDMI_FC_SDPPRODUCTNAME11 0x105D +#define HDMI_FC_SDPPRODUCTNAME12 0x105E +#define HDMI_FC_SDPPRODUCTNAME13 0x105F +#define HDMI_FC_SDPPRODUCTNAME14 0x1060 +#define HDMI_FC_SPDPRODUCTNAME15 0x1061 +#define HDMI_FC_SPDDEVICEINF 0x1062 +#define HDMI_FC_AUDSCONF 0x1063 +#define HDMI_FC_AUDSSTAT 0x1064 +#define HDMI_FC_DATACH0FILL 0x1070 +#define HDMI_FC_DATACH1FILL 0x1071 +#define HDMI_FC_DATACH2FILL 0x1072 +#define HDMI_FC_CTRLQHIGH 0x1073 +#define HDMI_FC_CTRLQLOW 0x1074 +#define HDMI_FC_ACP0 0x1075 +#define HDMI_FC_ACP28 0x1076 +#define HDMI_FC_ACP27 0x1077 +#define HDMI_FC_ACP26 0x1078 +#define HDMI_FC_ACP25 0x1079 +#define HDMI_FC_ACP24 0x107A +#define HDMI_FC_ACP23 0x107B +#define HDMI_FC_ACP22 0x107C +#define HDMI_FC_ACP21 0x107D +#define HDMI_FC_ACP20 0x107E +#define HDMI_FC_ACP19 0x107F +#define HDMI_FC_ACP18 0x1080 +#define HDMI_FC_ACP17 0x1081 +#define HDMI_FC_ACP16 0x1082 +#define HDMI_FC_ACP15 0x1083 +#define HDMI_FC_ACP14 0x1084 +#define HDMI_FC_ACP13 0x1085 +#define HDMI_FC_ACP12 0x1086 +#define HDMI_FC_ACP11 0x1087 +#define HDMI_FC_ACP10 0x1088 +#define HDMI_FC_ACP9 0x1089 +#define HDMI_FC_ACP8 0x108A +#define HDMI_FC_ACP7 0x108B +#define HDMI_FC_ACP6 0x108C +#define HDMI_FC_ACP5 0x108D +#define HDMI_FC_ACP4 0x108E +#define HDMI_FC_ACP3 0x108F +#define HDMI_FC_ACP2 0x1090 +#define HDMI_FC_ACP1 0x1091 +#define HDMI_FC_ISCR1_0 0x1092 +#define HDMI_FC_ISCR1_16 0x1093 +#define HDMI_FC_ISCR1_15 0x1094 +#define HDMI_FC_ISCR1_14 0x1095 +#define HDMI_FC_ISCR1_13 0x1096 +#define HDMI_FC_ISCR1_12 0x1097 +#define HDMI_FC_ISCR1_11 0x1098 +#define HDMI_FC_ISCR1_10 0x1099 +#define HDMI_FC_ISCR1_9 0x109A +#define HDMI_FC_ISCR1_8 0x109B +#define HDMI_FC_ISCR1_7 0x109C +#define HDMI_FC_ISCR1_6 0x109D +#define HDMI_FC_ISCR1_5 0x109E +#define HDMI_FC_ISCR1_4 0x109F +#define HDMI_FC_ISCR1_3 0x10A0 +#define HDMI_FC_ISCR1_2 0x10A1 +#define HDMI_FC_ISCR1_1 0x10A2 +#define HDMI_FC_ISCR2_15 0x10A3 +#define HDMI_FC_ISCR2_14 0x10A4 +#define HDMI_FC_ISCR2_13 0x10A5 +#define HDMI_FC_ISCR2_12 0x10A6 +#define HDMI_FC_ISCR2_11 0x10A7 +#define HDMI_FC_ISCR2_10 0x10A8 +#define HDMI_FC_ISCR2_9 0x10A9 +#define HDMI_FC_ISCR2_8 0x10AA +#define HDMI_FC_ISCR2_7 0x10AB +#define HDMI_FC_ISCR2_6 0x10AC +#define HDMI_FC_ISCR2_5 0x10AD +#define HDMI_FC_ISCR2_4 0x10AE +#define HDMI_FC_ISCR2_3 0x10AF +#define HDMI_FC_ISCR2_2 0x10B0 +#define HDMI_FC_ISCR2_1 0x10B1 +#define HDMI_FC_ISCR2_0 0x10B2 +#define HDMI_FC_DATAUTO0 0x10B3 +#define HDMI_FC_DATAUTO1 0x10B4 +#define HDMI_FC_DATAUTO2 0x10B5 +#define HDMI_FC_DATMAN 0x10B6 +#define HDMI_FC_DATAUTO3 0x10B7 +#define HDMI_FC_RDRB0 0x10B8 +#define HDMI_FC_RDRB1 0x10B9 +#define HDMI_FC_RDRB2 0x10BA +#define HDMI_FC_RDRB3 0x10BB +#define HDMI_FC_RDRB4 0x10BC +#define HDMI_FC_RDRB5 0x10BD +#define HDMI_FC_RDRB6 0x10BE +#define HDMI_FC_RDRB7 0x10BF +#define HDMI_FC_STAT0 0x10D0 +#define HDMI_FC_INT0 0x10D1 +#define HDMI_FC_MASK0 0x10D2 +#define HDMI_FC_POL0 0x10D3 +#define HDMI_FC_STAT1 0x10D4 +#define HDMI_FC_INT1 0x10D5 +#define HDMI_FC_MASK1 0x10D6 +#define HDMI_FC_POL1 0x10D7 +#define HDMI_FC_STAT2 0x10D8 +#define HDMI_FC_INT2 0x10D9 +#define HDMI_FC_MASK2 0x10DA +#define HDMI_FC_POL2 0x10DB +#define HDMI_FC_PRCONF 0x10E0 + +#define HDMI_FC_GMD_STAT 0x1100 +#define HDMI_FC_GMD_EN 0x1101 +#define HDMI_FC_GMD_UP 0x1102 +#define HDMI_FC_GMD_CONF 0x1103 +#define HDMI_FC_GMD_HB 0x1104 +#define HDMI_FC_GMD_PB0 0x1105 +#define HDMI_FC_GMD_PB1 0x1106 +#define HDMI_FC_GMD_PB2 0x1107 +#define HDMI_FC_GMD_PB3 0x1108 +#define HDMI_FC_GMD_PB4 0x1109 +#define HDMI_FC_GMD_PB5 0x110A +#define HDMI_FC_GMD_PB6 0x110B +#define HDMI_FC_GMD_PB7 0x110C +#define HDMI_FC_GMD_PB8 0x110D +#define HDMI_FC_GMD_PB9 0x110E +#define HDMI_FC_GMD_PB10 0x110F +#define HDMI_FC_GMD_PB11 0x1110 +#define HDMI_FC_GMD_PB12 0x1111 +#define HDMI_FC_GMD_PB13 0x1112 +#define HDMI_FC_GMD_PB14 0x1113 +#define HDMI_FC_GMD_PB15 0x1114 +#define HDMI_FC_GMD_PB16 0x1115 +#define HDMI_FC_GMD_PB17 0x1116 +#define HDMI_FC_GMD_PB18 0x1117 +#define HDMI_FC_GMD_PB19 0x1118 +#define HDMI_FC_GMD_PB20 0x1119 +#define HDMI_FC_GMD_PB21 0x111A +#define HDMI_FC_GMD_PB22 0x111B +#define HDMI_FC_GMD_PB23 0x111C +#define HDMI_FC_GMD_PB24 0x111D +#define HDMI_FC_GMD_PB25 0x111E +#define HDMI_FC_GMD_PB26 0x111F +#define HDMI_FC_GMD_PB27 0x1120 + +#define HDMI_FC_DBGFORCE 0x1200 +#define HDMI_FC_DBGAUD0CH0 0x1201 +#define HDMI_FC_DBGAUD1CH0 0x1202 +#define HDMI_FC_DBGAUD2CH0 0x1203 +#define HDMI_FC_DBGAUD0CH1 0x1204 +#define HDMI_FC_DBGAUD1CH1 0x1205 +#define HDMI_FC_DBGAUD2CH1 0x1206 +#define HDMI_FC_DBGAUD0CH2 0x1207 +#define HDMI_FC_DBGAUD1CH2 0x1208 +#define HDMI_FC_DBGAUD2CH2 0x1209 +#define HDMI_FC_DBGAUD0CH3 0x120A +#define HDMI_FC_DBGAUD1CH3 0x120B +#define HDMI_FC_DBGAUD2CH3 0x120C +#define HDMI_FC_DBGAUD0CH4 0x120D +#define HDMI_FC_DBGAUD1CH4 0x120E +#define HDMI_FC_DBGAUD2CH4 0x120F +#define HDMI_FC_DBGAUD0CH5 0x1210 +#define HDMI_FC_DBGAUD1CH5 0x1211 +#define HDMI_FC_DBGAUD2CH5 0x1212 +#define HDMI_FC_DBGAUD0CH6 0x1213 +#define HDMI_FC_DBGAUD1CH6 0x1214 +#define HDMI_FC_DBGAUD2CH6 0x1215 +#define HDMI_FC_DBGAUD0CH7 0x1216 +#define HDMI_FC_DBGAUD1CH7 0x1217 +#define HDMI_FC_DBGAUD2CH7 0x1218 +#define HDMI_FC_DBGTMDS0 0x1219 +#define HDMI_FC_DBGTMDS1 0x121A +#define HDMI_FC_DBGTMDS2 0x121B + +/* HDMI Source PHY Registers */ +#define HDMI_PHY_CONF0 0x3000 +#define HDMI_PHY_TST0 0x3001 +#define HDMI_PHY_TST1 0x3002 +#define HDMI_PHY_TST2 0x3003 +#define HDMI_PHY_STAT0 0x3004 +#define HDMI_PHY_INT0 0x3005 +#define HDMI_PHY_MASK0 0x3006 +#define HDMI_PHY_POL0 0x3007 + +/* HDMI Master PHY Registers */ +#define HDMI_PHY_I2CM_SLAVE_ADDR 0x3020 +#define HDMI_PHY_I2CM_ADDRESS_ADDR 0x3021 +#define HDMI_PHY_I2CM_DATAO_1_ADDR 0x3022 +#define HDMI_PHY_I2CM_DATAO_0_ADDR 0x3023 +#define HDMI_PHY_I2CM_DATAI_1_ADDR 0x3024 +#define HDMI_PHY_I2CM_DATAI_0_ADDR 0x3025 +#define HDMI_PHY_I2CM_OPERATION_ADDR 0x3026 +#define HDMI_PHY_I2CM_INT_ADDR 0x3027 +#define HDMI_PHY_I2CM_CTLINT_ADDR 0x3028 +#define HDMI_PHY_I2CM_DIV_ADDR 0x3029 +#define HDMI_PHY_I2CM_SOFTRSTZ_ADDR 0x302a +#define HDMI_PHY_I2CM_SS_SCL_HCNT_1_ADDR 0x302b +#define HDMI_PHY_I2CM_SS_SCL_HCNT_0_ADDR 0x302c +#define HDMI_PHY_I2CM_SS_SCL_LCNT_1_ADDR 0x302d +#define HDMI_PHY_I2CM_SS_SCL_LCNT_0_ADDR 0x302e +#define HDMI_PHY_I2CM_FS_SCL_HCNT_1_ADDR 0x302f +#define HDMI_PHY_I2CM_FS_SCL_HCNT_0_ADDR 0x3030 +#define HDMI_PHY_I2CM_FS_SCL_LCNT_1_ADDR 0x3031 +#define HDMI_PHY_I2CM_FS_SCL_LCNT_0_ADDR 0x3032 + +/* Audio Sampler Registers */ +#define HDMI_AUD_CONF0 0x3100 +#define HDMI_AUD_CONF1 0x3101 +#define HDMI_AUD_INT 0x3102 +#define HDMI_AUD_CONF2 0x3103 +#define HDMI_AUD_N1 0x3200 +#define HDMI_AUD_N2 0x3201 +#define HDMI_AUD_N3 0x3202 +#define HDMI_AUD_CTS1 0x3203 +#define HDMI_AUD_CTS2 0x3204 +#define HDMI_AUD_CTS3 0x3205 +#define HDMI_AUD_INPUTCLKFS 0x3206 +#define HDMI_AUD_SPDIFINT 0x3302 +#define HDMI_AUD_CONF0_HBR 0x3400 +#define HDMI_AUD_HBR_STATUS 0x3401 +#define HDMI_AUD_HBR_INT 0x3402 +#define HDMI_AUD_HBR_POL 0x3403 +#define HDMI_AUD_HBR_MASK 0x3404 + +/* Generic Parallel Audio Interface Registers */ +/* Not used as GPAUD interface is not enabled in hw */ +#define HDMI_GP_CONF0 0x3500 +#define HDMI_GP_CONF1 0x3501 +#define HDMI_GP_CONF2 0x3502 +#define HDMI_GP_STAT 0x3503 +#define HDMI_GP_INT 0x3504 +#define HDMI_GP_MASK 0x3505 +#define HDMI_GP_POL 0x3506 + +/* Audio DMA Registers */ +#define HDMI_AHB_DMA_CONF0 0x3600 +#define HDMI_AHB_DMA_START 0x3601 +#define HDMI_AHB_DMA_STOP 0x3602 +#define HDMI_AHB_DMA_THRSLD 0x3603 +#define HDMI_AHB_DMA_STRADDR0 0x3604 +#define HDMI_AHB_DMA_STRADDR1 0x3605 +#define HDMI_AHB_DMA_STRADDR2 0x3606 +#define HDMI_AHB_DMA_STRADDR3 0x3607 +#define HDMI_AHB_DMA_STPADDR0 0x3608 +#define HDMI_AHB_DMA_STPADDR1 0x3609 +#define HDMI_AHB_DMA_STPADDR2 0x360a +#define HDMI_AHB_DMA_STPADDR3 0x360b +#define HDMI_AHB_DMA_BSTADDR0 0x360c +#define HDMI_AHB_DMA_BSTADDR1 0x360d +#define HDMI_AHB_DMA_BSTADDR2 0x360e +#define HDMI_AHB_DMA_BSTADDR3 0x360f +#define HDMI_AHB_DMA_MBLENGTH0 0x3610 +#define HDMI_AHB_DMA_MBLENGTH1 0x3611 +#define HDMI_AHB_DMA_STAT 0x3612 +#define HDMI_AHB_DMA_INT 0x3613 +#define HDMI_AHB_DMA_MASK 0x3614 +#define HDMI_AHB_DMA_POL 0x3615 +#define HDMI_AHB_DMA_CONF1 0x3616 +#define HDMI_AHB_DMA_BUFFSTAT 0x3617 +#define HDMI_AHB_DMA_BUFFINT 0x3618 +#define HDMI_AHB_DMA_BUFFMASK 0x3619 +#define HDMI_AHB_DMA_BUFFPOL 0x361a + +/* Main Controller Registers */ +#define HDMI_MC_SFRDIV 0x4000 +#define HDMI_MC_CLKDIS 0x4001 +#define HDMI_MC_SWRSTZ 0x4002 +#define HDMI_MC_OPCTRL 0x4003 +#define HDMI_MC_FLOWCTRL 0x4004 +#define HDMI_MC_PHYRSTZ 0x4005 +#define HDMI_MC_LOCKONCLOCK 0x4006 +#define HDMI_MC_HEACPHY_RST 0x4007 + +/* Color Space Converter Registers */ +#define HDMI_CSC_CFG 0x4100 +#define HDMI_CSC_SCALE 0x4101 +#define HDMI_CSC_COEF_A1_MSB 0x4102 +#define HDMI_CSC_COEF_A1_LSB 0x4103 +#define HDMI_CSC_COEF_A2_MSB 0x4104 +#define HDMI_CSC_COEF_A2_LSB 0x4105 +#define HDMI_CSC_COEF_A3_MSB 0x4106 +#define HDMI_CSC_COEF_A3_LSB 0x4107 +#define HDMI_CSC_COEF_A4_MSB 0x4108 +#define HDMI_CSC_COEF_A4_LSB 0x4109 +#define HDMI_CSC_COEF_B1_MSB 0x410A +#define HDMI_CSC_COEF_B1_LSB 0x410B +#define HDMI_CSC_COEF_B2_MSB 0x410C +#define HDMI_CSC_COEF_B2_LSB 0x410D +#define HDMI_CSC_COEF_B3_MSB 0x410E +#define HDMI_CSC_COEF_B3_LSB 0x410F +#define HDMI_CSC_COEF_B4_MSB 0x4110 +#define HDMI_CSC_COEF_B4_LSB 0x4111 +#define HDMI_CSC_COEF_C1_MSB 0x4112 +#define HDMI_CSC_COEF_C1_LSB 0x4113 +#define HDMI_CSC_COEF_C2_MSB 0x4114 +#define HDMI_CSC_COEF_C2_LSB 0x4115 +#define HDMI_CSC_COEF_C3_MSB 0x4116 +#define HDMI_CSC_COEF_C3_LSB 0x4117 +#define HDMI_CSC_COEF_C4_MSB 0x4118 +#define HDMI_CSC_COEF_C4_LSB 0x4119 + +/* HDCP Encryption Engine Registers */ +#define HDMI_A_HDCPCFG0 0x5000 +#define HDMI_A_HDCPCFG1 0x5001 +#define HDMI_A_HDCPOBS0 0x5002 +#define HDMI_A_HDCPOBS1 0x5003 +#define HDMI_A_HDCPOBS2 0x5004 +#define HDMI_A_HDCPOBS3 0x5005 +#define HDMI_A_APIINTCLR 0x5006 +#define HDMI_A_APIINTSTAT 0x5007 +#define HDMI_A_APIINTMSK 0x5008 +#define HDMI_A_VIDPOLCFG 0x5009 +#define HDMI_A_OESSWCFG 0x500A +#define HDMI_A_TIMER1SETUP0 0x500B +#define HDMI_A_TIMER1SETUP1 0x500C +#define HDMI_A_TIMER2SETUP0 0x500D +#define HDMI_A_TIMER2SETUP1 0x500E +#define HDMI_A_100MSCFG 0x500F +#define HDMI_A_2SCFG0 0x5010 +#define HDMI_A_2SCFG1 0x5011 +#define HDMI_A_5SCFG0 0x5012 +#define HDMI_A_5SCFG1 0x5013 +#define HDMI_A_SRMVERLSB 0x5014 +#define HDMI_A_SRMVERMSB 0x5015 +#define HDMI_A_SRMCTRL 0x5016 +#define HDMI_A_SFRSETUP 0x5017 +#define HDMI_A_I2CHSETUP 0x5018 +#define HDMI_A_INTSETUP 0x5019 +#define HDMI_A_PRESETUP 0x501A +#define HDMI_A_SRM_BASE 0x5020 + +/* CEC Engine Registers */ +#define HDMI_CEC_CTRL 0x7D00 +#define HDMI_CEC_STAT 0x7D01 +#define HDMI_CEC_MASK 0x7D02 +#define HDMI_CEC_POLARITY 0x7D03 +#define HDMI_CEC_INT 0x7D04 +#define HDMI_CEC_ADDR_L 0x7D05 +#define HDMI_CEC_ADDR_H 0x7D06 +#define HDMI_CEC_TX_CNT 0x7D07 +#define HDMI_CEC_RX_CNT 0x7D08 +#define HDMI_CEC_TX_DATA0 0x7D10 +#define HDMI_CEC_TX_DATA1 0x7D11 +#define HDMI_CEC_TX_DATA2 0x7D12 +#define HDMI_CEC_TX_DATA3 0x7D13 +#define HDMI_CEC_TX_DATA4 0x7D14 +#define HDMI_CEC_TX_DATA5 0x7D15 +#define HDMI_CEC_TX_DATA6 0x7D16 +#define HDMI_CEC_TX_DATA7 0x7D17 +#define HDMI_CEC_TX_DATA8 0x7D18 +#define HDMI_CEC_TX_DATA9 0x7D19 +#define HDMI_CEC_TX_DATA10 0x7D1a +#define HDMI_CEC_TX_DATA11 0x7D1b +#define HDMI_CEC_TX_DATA12 0x7D1c +#define HDMI_CEC_TX_DATA13 0x7D1d +#define HDMI_CEC_TX_DATA14 0x7D1e +#define HDMI_CEC_TX_DATA15 0x7D1f +#define HDMI_CEC_RX_DATA0 0x7D20 +#define HDMI_CEC_RX_DATA1 0x7D21 +#define HDMI_CEC_RX_DATA2 0x7D22 +#define HDMI_CEC_RX_DATA3 0x7D23 +#define HDMI_CEC_RX_DATA4 0x7D24 +#define HDMI_CEC_RX_DATA5 0x7D25 +#define HDMI_CEC_RX_DATA6 0x7D26 +#define HDMI_CEC_RX_DATA7 0x7D27 +#define HDMI_CEC_RX_DATA8 0x7D28 +#define HDMI_CEC_RX_DATA9 0x7D29 +#define HDMI_CEC_RX_DATA10 0x7D2a +#define HDMI_CEC_RX_DATA11 0x7D2b +#define HDMI_CEC_RX_DATA12 0x7D2c +#define HDMI_CEC_RX_DATA13 0x7D2d +#define HDMI_CEC_RX_DATA14 0x7D2e +#define HDMI_CEC_RX_DATA15 0x7D2f +#define HDMI_CEC_LOCK 0x7D30 +#define HDMI_CEC_WKUPCTRL 0x7D31 + +/* I2C Master Registers (E-DDC) */ +#define HDMI_I2CM_SLAVE 0x7E00 +#define HDMI_I2CM_ADDRESS 0x7E01 +#define HDMI_I2CM_DATAO 0x7E02 +#define HDMI_I2CM_DATAI 0x7E03 +#define HDMI_I2CM_OPERATION 0x7E04 +#define HDMI_I2CM_INT 0x7E05 +#define HDMI_I2CM_CTLINT 0x7E06 +#define HDMI_I2CM_DIV 0x7E07 +#define HDMI_I2CM_SEGADDR 0x7E08 +#define HDMI_I2CM_SOFTRSTZ 0x7E09 +#define HDMI_I2CM_SEGPTR 0x7E0A +#define HDMI_I2CM_SS_SCL_HCNT_1_ADDR 0x7E0B +#define HDMI_I2CM_SS_SCL_HCNT_0_ADDR 0x7E0C +#define HDMI_I2CM_SS_SCL_LCNT_1_ADDR 0x7E0D +#define HDMI_I2CM_SS_SCL_LCNT_0_ADDR 0x7E0E +#define HDMI_I2CM_FS_SCL_HCNT_1_ADDR 0x7E0F +#define HDMI_I2CM_FS_SCL_HCNT_0_ADDR 0x7E10 +#define HDMI_I2CM_FS_SCL_LCNT_1_ADDR 0x7E11 +#define HDMI_I2CM_FS_SCL_LCNT_0_ADDR 0x7E12 + +/* Random Number Generator Registers (RNG) */ +#define HDMI_RNG_BASE 0x8000 + + +/* + * Register field definitions + */ +enum { +/* IH_FC_INT2 field values */ + HDMI_IH_FC_INT2_OVERFLOW_MASK = 0x03, + HDMI_IH_FC_INT2_LOW_PRIORITY_OVERFLOW = 0x02, + HDMI_IH_FC_INT2_HIGH_PRIORITY_OVERFLOW = 0x01, + +/* IH_FC_STAT2 field values */ + HDMI_IH_FC_STAT2_OVERFLOW_MASK = 0x03, + HDMI_IH_FC_STAT2_LOW_PRIORITY_OVERFLOW = 0x02, + HDMI_IH_FC_STAT2_HIGH_PRIORITY_OVERFLOW = 0x01, + +/* IH_PHY_STAT0 field values */ + HDMI_IH_PHY_STAT0_RX_SENSE3 = 0x20, + HDMI_IH_PHY_STAT0_RX_SENSE2 = 0x10, + HDMI_IH_PHY_STAT0_RX_SENSE1 = 0x8, + HDMI_IH_PHY_STAT0_RX_SENSE0 = 0x4, + HDMI_IH_PHY_STAT0_TX_PHY_LOCK = 0x2, + HDMI_IH_PHY_STAT0_HPD = 0x1, + +/* IH_CEC_STAT0 field values */ + HDMI_IH_CEC_STAT0_WAKEUP = 0x40, + HDMI_IH_CEC_STAT0_ERROR_FOLL = 0x20, + HDMI_IH_CEC_STAT0_ERROR_INIT = 0x10, + HDMI_IH_CEC_STAT0_ARB_LOST = 0x8, + HDMI_IH_CEC_STAT0_NACK = 0x4, + HDMI_IH_CEC_STAT0_EOM = 0x2, + HDMI_IH_CEC_STAT0_DONE = 0x1, + + +/* IH_MUTE_I2CMPHY_STAT0 field values */ + HDMI_IH_MUTE_I2CMPHY_STAT0_I2CMPHYDONE = 0x2, + HDMI_IH_MUTE_I2CMPHY_STAT0_I2CMPHYERROR = 0x1, + +/* IH_PHY_STAT0 field values */ + HDMI_IH_MUTE_PHY_STAT0_RX_SENSE3 = 0x20, + HDMI_IH_MUTE_PHY_STAT0_RX_SENSE2 = 0x10, + HDMI_IH_MUTE_PHY_STAT0_RX_SENSE1 = 0x8, + HDMI_IH_MUTE_PHY_STAT0_RX_SENSE0 = 0x4, + HDMI_IH_MUTE_PHY_STAT0_TX_PHY_LOCK = 0x2, + HDMI_IH_MUTE_PHY_STAT0_HPD = 0x1, + +/* IH_AHBDMAAUD_STAT0 field values */ + HDMI_IH_AHBDMAAUD_STAT0_ERROR = 0x20, + HDMI_IH_AHBDMAAUD_STAT0_LOST = 0x10, + HDMI_IH_AHBDMAAUD_STAT0_RETRY = 0x08, + HDMI_IH_AHBDMAAUD_STAT0_DONE = 0x04, + HDMI_IH_AHBDMAAUD_STAT0_BUFFFULL = 0x02, + HDMI_IH_AHBDMAAUD_STAT0_BUFFEMPTY = 0x01, + +/* IH_MUTE_FC_STAT2 field values */ + HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK = 0x03, + HDMI_IH_MUTE_FC_STAT2_LOW_PRIORITY_OVERFLOW = 0x02, + HDMI_IH_MUTE_FC_STAT2_HIGH_PRIORITY_OVERFLOW = 0x01, + +/* IH_MUTE_AHBDMAAUD_STAT0 field values */ + HDMI_IH_MUTE_AHBDMAAUD_STAT0_ERROR = 0x20, + HDMI_IH_MUTE_AHBDMAAUD_STAT0_LOST = 0x10, + HDMI_IH_MUTE_AHBDMAAUD_STAT0_RETRY = 0x08, + HDMI_IH_MUTE_AHBDMAAUD_STAT0_DONE = 0x04, + HDMI_IH_MUTE_AHBDMAAUD_STAT0_BUFFFULL = 0x02, + HDMI_IH_MUTE_AHBDMAAUD_STAT0_BUFFEMPTY = 0x01, + +/* IH_MUTE field values */ + HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT = 0x2, + HDMI_IH_MUTE_MUTE_ALL_INTERRUPT = 0x1, + +/* TX_INVID0 field values */ + HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_MASK = 0x80, + HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_ENABLE = 0x80, + HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE = 0x00, + HDMI_TX_INVID0_VIDEO_MAPPING_MASK = 0x1F, + HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET = 0, + +/* TX_INSTUFFING field values */ + HDMI_TX_INSTUFFING_BDBDATA_STUFFING_MASK = 0x4, + HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE = 0x4, + HDMI_TX_INSTUFFING_BDBDATA_STUFFING_DISABLE = 0x0, + HDMI_TX_INSTUFFING_RCRDATA_STUFFING_MASK = 0x2, + HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE = 0x2, + HDMI_TX_INSTUFFING_RCRDATA_STUFFING_DISABLE = 0x0, + HDMI_TX_INSTUFFING_GYDATA_STUFFING_MASK = 0x1, + HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE = 0x1, + HDMI_TX_INSTUFFING_GYDATA_STUFFING_DISABLE = 0x0, + +/* VP_PR_CD field values */ + HDMI_VP_PR_CD_COLOR_DEPTH_MASK = 0xF0, + HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET = 4, + HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK = 0x0F, + HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET = 0, + +/* VP_STUFF field values */ + HDMI_VP_STUFF_IDEFAULT_PHASE_MASK = 0x20, + HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET = 5, + HDMI_VP_STUFF_IFIX_PP_TO_LAST_MASK = 0x10, + HDMI_VP_STUFF_IFIX_PP_TO_LAST_OFFSET = 4, + HDMI_VP_STUFF_ICX_GOTO_P0_ST_MASK = 0x8, + HDMI_VP_STUFF_ICX_GOTO_P0_ST_OFFSET = 3, + HDMI_VP_STUFF_YCC422_STUFFING_MASK = 0x4, + HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE = 0x4, + HDMI_VP_STUFF_YCC422_STUFFING_DIRECT_MODE = 0x0, + HDMI_VP_STUFF_PP_STUFFING_MASK = 0x2, + HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE = 0x2, + HDMI_VP_STUFF_PP_STUFFING_DIRECT_MODE = 0x0, + HDMI_VP_STUFF_PR_STUFFING_MASK = 0x1, + HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE = 0x1, + HDMI_VP_STUFF_PR_STUFFING_DIRECT_MODE = 0x0, + +/* VP_CONF field values */ + HDMI_VP_CONF_BYPASS_EN_MASK = 0x40, + HDMI_VP_CONF_BYPASS_EN_ENABLE = 0x40, + HDMI_VP_CONF_BYPASS_EN_DISABLE = 0x00, + HDMI_VP_CONF_PP_EN_ENMASK = 0x20, + HDMI_VP_CONF_PP_EN_ENABLE = 0x20, + HDMI_VP_CONF_PP_EN_DISABLE = 0x00, + HDMI_VP_CONF_PR_EN_MASK = 0x10, + HDMI_VP_CONF_PR_EN_ENABLE = 0x10, + HDMI_VP_CONF_PR_EN_DISABLE = 0x00, + HDMI_VP_CONF_YCC422_EN_MASK = 0x8, + HDMI_VP_CONF_YCC422_EN_ENABLE = 0x8, + HDMI_VP_CONF_YCC422_EN_DISABLE = 0x0, + HDMI_VP_CONF_BYPASS_SELECT_MASK = 0x4, + HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER = 0x4, + HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER = 0x0, + HDMI_VP_CONF_OUTPUT_SELECTOR_MASK = 0x3, + HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS = 0x3, + HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422 = 0x1, + HDMI_VP_CONF_OUTPUT_SELECTOR_PP = 0x0, + +/* VP_REMAP field values */ + HDMI_VP_REMAP_MASK = 0x3, + HDMI_VP_REMAP_YCC422_24bit = 0x2, + HDMI_VP_REMAP_YCC422_20bit = 0x1, + HDMI_VP_REMAP_YCC422_16bit = 0x0, + +/* FC_INVIDCONF field values */ + HDMI_FC_INVIDCONF_HDCP_KEEPOUT_MASK = 0x80, + HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE = 0x80, + HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE = 0x00, + HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_MASK = 0x40, + HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH = 0x40, + HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW = 0x00, + HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_MASK = 0x20, + HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH = 0x20, + HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW = 0x00, + HDMI_FC_INVIDCONF_DE_IN_POLARITY_MASK = 0x10, + HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH = 0x10, + HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW = 0x00, + HDMI_FC_INVIDCONF_DVI_MODEZ_MASK = 0x8, + HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE = 0x8, + HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE = 0x0, + HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_MASK = 0x2, + HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH = 0x2, + HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW = 0x0, + HDMI_FC_INVIDCONF_IN_I_P_MASK = 0x1, + HDMI_FC_INVIDCONF_IN_I_P_INTERLACED = 0x1, + HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE = 0x0, + +/* FC_AUDICONF0 field values */ + HDMI_FC_AUDICONF0_CC_OFFSET = 4, + HDMI_FC_AUDICONF0_CC_MASK = 0x70, + HDMI_FC_AUDICONF0_CT_OFFSET = 0, + HDMI_FC_AUDICONF0_CT_MASK = 0xF, + +/* FC_AUDICONF1 field values */ + HDMI_FC_AUDICONF1_SS_OFFSET = 3, + HDMI_FC_AUDICONF1_SS_MASK = 0x18, + HDMI_FC_AUDICONF1_SF_OFFSET = 0, + HDMI_FC_AUDICONF1_SF_MASK = 0x7, + +/* FC_AUDICONF3 field values */ + HDMI_FC_AUDICONF3_LFEPBL_OFFSET = 5, + HDMI_FC_AUDICONF3_LFEPBL_MASK = 0x60, + HDMI_FC_AUDICONF3_DM_INH_OFFSET = 4, + HDMI_FC_AUDICONF3_DM_INH_MASK = 0x10, + HDMI_FC_AUDICONF3_LSV_OFFSET = 0, + HDMI_FC_AUDICONF3_LSV_MASK = 0xF, + +/* FC_AUDSCHNLS0 field values */ + HDMI_FC_AUDSCHNLS0_CGMSA_OFFSET = 4, + HDMI_FC_AUDSCHNLS0_CGMSA_MASK = 0x30, + HDMI_FC_AUDSCHNLS0_COPYRIGHT_OFFSET = 0, + HDMI_FC_AUDSCHNLS0_COPYRIGHT_MASK = 0x01, + +/* FC_AUDSCHNLS3-6 field values */ + HDMI_FC_AUDSCHNLS3_OIEC_CH0_OFFSET = 0, + HDMI_FC_AUDSCHNLS3_OIEC_CH0_MASK = 0x0f, + HDMI_FC_AUDSCHNLS3_OIEC_CH1_OFFSET = 4, + HDMI_FC_AUDSCHNLS3_OIEC_CH1_MASK = 0xf0, + HDMI_FC_AUDSCHNLS4_OIEC_CH2_OFFSET = 0, + HDMI_FC_AUDSCHNLS4_OIEC_CH2_MASK = 0x0f, + HDMI_FC_AUDSCHNLS4_OIEC_CH3_OFFSET = 4, + HDMI_FC_AUDSCHNLS4_OIEC_CH3_MASK = 0xf0, + + HDMI_FC_AUDSCHNLS5_OIEC_CH0_OFFSET = 0, + HDMI_FC_AUDSCHNLS5_OIEC_CH0_MASK = 0x0f, + HDMI_FC_AUDSCHNLS5_OIEC_CH1_OFFSET = 4, + HDMI_FC_AUDSCHNLS5_OIEC_CH1_MASK = 0xf0, + HDMI_FC_AUDSCHNLS6_OIEC_CH2_OFFSET = 0, + HDMI_FC_AUDSCHNLS6_OIEC_CH2_MASK = 0x0f, + HDMI_FC_AUDSCHNLS6_OIEC_CH3_OFFSET = 4, + HDMI_FC_AUDSCHNLS6_OIEC_CH3_MASK = 0xf0, + +/* HDMI_FC_AUDSCHNLS7 field values */ + HDMI_FC_AUDSCHNLS7_ACCURACY_OFFSET = 4, + HDMI_FC_AUDSCHNLS7_ACCURACY_MASK = 0x30, + +/* HDMI_FC_AUDSCHNLS8 field values */ + HDMI_FC_AUDSCHNLS8_ORIGSAMPFREQ_MASK = 0xf0, + HDMI_FC_AUDSCHNLS8_ORIGSAMPFREQ_OFFSET = 4, + HDMI_FC_AUDSCHNLS8_WORDLEGNTH_MASK = 0x0f, + HDMI_FC_AUDSCHNLS8_WORDLEGNTH_OFFSET = 0, + +/* FC_AUDSCONF field values */ + HDMI_FC_AUDSCONF_AUD_PACKET_SAMPFIT_MASK = 0xF0, + HDMI_FC_AUDSCONF_AUD_PACKET_SAMPFIT_OFFSET = 4, + HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_MASK = 0x1, + HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_OFFSET = 0, + HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT1 = 0x1, + HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT0 = 0x0, + +/* FC_STAT2 field values */ + HDMI_FC_STAT2_OVERFLOW_MASK = 0x03, + HDMI_FC_STAT2_LOW_PRIORITY_OVERFLOW = 0x02, + HDMI_FC_STAT2_HIGH_PRIORITY_OVERFLOW = 0x01, + +/* FC_INT2 field values */ + HDMI_FC_INT2_OVERFLOW_MASK = 0x03, + HDMI_FC_INT2_LOW_PRIORITY_OVERFLOW = 0x02, + HDMI_FC_INT2_HIGH_PRIORITY_OVERFLOW = 0x01, + +/* FC_MASK2 field values */ + HDMI_FC_MASK2_OVERFLOW_MASK = 0x03, + HDMI_FC_MASK2_LOW_PRIORITY_OVERFLOW = 0x02, + HDMI_FC_MASK2_HIGH_PRIORITY_OVERFLOW = 0x01, + +/* FC_PRCONF field values */ + HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK = 0xF0, + HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET = 4, + HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK = 0x0F, + HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET = 0, + +/* FC_AVICONF0-FC_AVICONF3 field values */ + HDMI_FC_AVICONF0_PIX_FMT_MASK = 0x03, + HDMI_FC_AVICONF0_PIX_FMT_RGB = 0x00, + HDMI_FC_AVICONF0_PIX_FMT_YCBCR422 = 0x01, + HDMI_FC_AVICONF0_PIX_FMT_YCBCR444 = 0x02, + HDMI_FC_AVICONF0_ACTIVE_FMT_MASK = 0x40, + HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT = 0x40, + HDMI_FC_AVICONF0_ACTIVE_FMT_NO_INFO = 0x00, + HDMI_FC_AVICONF0_BAR_DATA_MASK = 0x0C, + HDMI_FC_AVICONF0_BAR_DATA_NO_DATA = 0x00, + HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR = 0x04, + HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR = 0x08, + HDMI_FC_AVICONF0_BAR_DATA_VERT_HORIZ_BAR = 0x0C, + HDMI_FC_AVICONF0_SCAN_INFO_MASK = 0x30, + HDMI_FC_AVICONF0_SCAN_INFO_OVERSCAN = 0x10, + HDMI_FC_AVICONF0_SCAN_INFO_UNDERSCAN = 0x20, + HDMI_FC_AVICONF0_SCAN_INFO_NODATA = 0x00, + + HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_MASK = 0x0F, + HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_USE_CODED = 0x08, + HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_4_3 = 0x09, + HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_16_9 = 0x0A, + HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_14_9 = 0x0B, + HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_MASK = 0x30, + HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_NO_DATA = 0x00, + HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_4_3 = 0x10, + HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_16_9 = 0x20, + HDMI_FC_AVICONF1_COLORIMETRY_MASK = 0xC0, + HDMI_FC_AVICONF1_COLORIMETRY_NO_DATA = 0x00, + HDMI_FC_AVICONF1_COLORIMETRY_SMPTE = 0x40, + HDMI_FC_AVICONF1_COLORIMETRY_ITUR = 0x80, + HDMI_FC_AVICONF1_COLORIMETRY_EXTENDED_INFO = 0xC0, + + HDMI_FC_AVICONF2_SCALING_MASK = 0x03, + HDMI_FC_AVICONF2_SCALING_NONE = 0x00, + HDMI_FC_AVICONF2_SCALING_HORIZ = 0x01, + HDMI_FC_AVICONF2_SCALING_VERT = 0x02, + HDMI_FC_AVICONF2_SCALING_HORIZ_VERT = 0x03, + HDMI_FC_AVICONF2_RGB_QUANT_MASK = 0x0C, + HDMI_FC_AVICONF2_RGB_QUANT_DEFAULT = 0x00, + HDMI_FC_AVICONF2_RGB_QUANT_LIMITED_RANGE = 0x04, + HDMI_FC_AVICONF2_RGB_QUANT_FULL_RANGE = 0x08, + HDMI_FC_AVICONF2_EXT_COLORIMETRY_MASK = 0x70, + HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601 = 0x00, + HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC709 = 0x10, + HDMI_FC_AVICONF2_EXT_COLORIMETRY_SYCC601 = 0x20, + HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_YCC601 = 0x30, + HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_RGB = 0x40, + HDMI_FC_AVICONF2_IT_CONTENT_MASK = 0x80, + HDMI_FC_AVICONF2_IT_CONTENT_NO_DATA = 0x00, + HDMI_FC_AVICONF2_IT_CONTENT_VALID = 0x80, + + HDMI_FC_AVICONF3_IT_CONTENT_TYPE_MASK = 0x03, + HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GRAPHICS = 0x00, + HDMI_FC_AVICONF3_IT_CONTENT_TYPE_PHOTO = 0x01, + HDMI_FC_AVICONF3_IT_CONTENT_TYPE_CINEMA = 0x02, + HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GAME = 0x03, + HDMI_FC_AVICONF3_QUANT_RANGE_MASK = 0x0C, + HDMI_FC_AVICONF3_QUANT_RANGE_LIMITED = 0x00, + HDMI_FC_AVICONF3_QUANT_RANGE_FULL = 0x04, + +/* FC_DBGFORCE field values */ + HDMI_FC_DBGFORCE_FORCEAUDIO = 0x10, + HDMI_FC_DBGFORCE_FORCEVIDEO = 0x1, + +/* PHY_CONF0 field values */ + HDMI_PHY_CONF0_PDZ_MASK = 0x80, + HDMI_PHY_CONF0_PDZ_OFFSET = 7, + HDMI_PHY_CONF0_ENTMDS_MASK = 0x40, + HDMI_PHY_CONF0_ENTMDS_OFFSET = 6, + HDMI_PHY_CONF0_SPARECTRL = 0x20, + HDMI_PHY_CONF0_GEN2_PDDQ_MASK = 0x10, + HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET = 4, + HDMI_PHY_CONF0_GEN2_TXPWRON_MASK = 0x8, + HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET = 3, + HDMI_PHY_CONF0_GEN2_ENHPDRXSENSE_MASK = 0x4, + HDMI_PHY_CONF0_GEN2_ENHPDRXSENSE_OFFSET = 2, + HDMI_PHY_CONF0_SELDATAENPOL_MASK = 0x2, + HDMI_PHY_CONF0_SELDATAENPOL_OFFSET = 1, + HDMI_PHY_CONF0_SELDIPIF_MASK = 0x1, + HDMI_PHY_CONF0_SELDIPIF_OFFSET = 0, + +/* PHY_TST0 field values */ + HDMI_PHY_TST0_TSTCLR_MASK = 0x20, + HDMI_PHY_TST0_TSTCLR_OFFSET = 5, + HDMI_PHY_TST0_TSTEN_MASK = 0x10, + HDMI_PHY_TST0_TSTEN_OFFSET = 4, + HDMI_PHY_TST0_TSTCLK_MASK = 0x1, + HDMI_PHY_TST0_TSTCLK_OFFSET = 0, + +/* PHY_STAT0 field values */ + HDMI_PHY_RX_SENSE3 = 0x80, + HDMI_PHY_RX_SENSE2 = 0x40, + HDMI_PHY_RX_SENSE1 = 0x20, + HDMI_PHY_RX_SENSE0 = 0x10, + HDMI_PHY_HPD = 0x02, + HDMI_PHY_TX_PHY_LOCK = 0x01, + +/* PHY_I2CM_SLAVE_ADDR field values */ + HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2 = 0x69, + HDMI_PHY_I2CM_SLAVE_ADDR_HEAC_PHY = 0x49, + +/* PHY_I2CM_OPERATION_ADDR field values */ + HDMI_PHY_I2CM_OPERATION_ADDR_WRITE = 0x10, + HDMI_PHY_I2CM_OPERATION_ADDR_READ = 0x1, + +/* HDMI_PHY_I2CM_INT_ADDR */ + HDMI_PHY_I2CM_INT_ADDR_DONE_POL = 0x08, + HDMI_PHY_I2CM_INT_ADDR_DONE_MASK = 0x04, + +/* HDMI_PHY_I2CM_CTLINT_ADDR */ + HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL = 0x80, + HDMI_PHY_I2CM_CTLINT_ADDR_NAC_MASK = 0x40, + HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL = 0x08, + HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_MASK = 0x04, + +/* AUD_CTS3 field values */ + HDMI_AUD_CTS3_N_SHIFT_OFFSET = 5, + HDMI_AUD_CTS3_N_SHIFT_MASK = 0xe0, + HDMI_AUD_CTS3_N_SHIFT_1 = 0, + HDMI_AUD_CTS3_N_SHIFT_16 = 0x20, + HDMI_AUD_CTS3_N_SHIFT_32 = 0x40, + HDMI_AUD_CTS3_N_SHIFT_64 = 0x60, + HDMI_AUD_CTS3_N_SHIFT_128 = 0x80, + HDMI_AUD_CTS3_N_SHIFT_256 = 0xa0, + /* note that the CTS3 MANUAL bit has been removed + from our part. Can't set it, will read as 0. */ + HDMI_AUD_CTS3_CTS_MANUAL = 0x10, + HDMI_AUD_CTS3_AUDCTS19_16_MASK = 0x0f, + +/* AHB_DMA_CONF0 field values */ + HDMI_AHB_DMA_CONF0_SW_FIFO_RST_OFFSET = 7, + HDMI_AHB_DMA_CONF0_SW_FIFO_RST_MASK = 0x80, + HDMI_AHB_DMA_CONF0_HBR = 0x10, + HDMI_AHB_DMA_CONF0_EN_HLOCK_OFFSET = 3, + HDMI_AHB_DMA_CONF0_EN_HLOCK_MASK = 0x08, + HDMI_AHB_DMA_CONF0_INCR_TYPE_OFFSET = 1, + HDMI_AHB_DMA_CONF0_INCR_TYPE_MASK = 0x06, + HDMI_AHB_DMA_CONF0_INCR4 = 0x0, + HDMI_AHB_DMA_CONF0_INCR8 = 0x2, + HDMI_AHB_DMA_CONF0_INCR16 = 0x4, + HDMI_AHB_DMA_CONF0_BURST_MODE = 0x1, + +/* HDMI_AHB_DMA_START field values */ + HDMI_AHB_DMA_START_START_OFFSET = 0, + HDMI_AHB_DMA_START_START_MASK = 0x01, + +/* HDMI_AHB_DMA_STOP field values */ + HDMI_AHB_DMA_STOP_STOP_OFFSET = 0, + HDMI_AHB_DMA_STOP_STOP_MASK = 0x01, + +/* AHB_DMA_STAT, AHB_DMA_INT, AHB_DMA_MASK, AHB_DMA_POL field values */ + HDMI_AHB_DMA_DONE = 0x80, + HDMI_AHB_DMA_RETRY_SPLIT = 0x40, + HDMI_AHB_DMA_LOSTOWNERSHIP = 0x20, + HDMI_AHB_DMA_ERROR = 0x10, + HDMI_AHB_DMA_FIFO_THREMPTY = 0x04, + HDMI_AHB_DMA_FIFO_FULL = 0x02, + HDMI_AHB_DMA_FIFO_EMPTY = 0x01, + +/* AHB_DMA_BUFFSTAT, AHB_DMA_BUFFINT, AHB_DMA_BUFFMASK, AHB_DMA_BUFFPOL field values */ + HDMI_AHB_DMA_BUFFSTAT_FULL = 0x02, + HDMI_AHB_DMA_BUFFSTAT_EMPTY = 0x01, + +/* MC_CLKDIS field values */ + HDMI_MC_CLKDIS_HDCPCLK_DISABLE = 0x40, + HDMI_MC_CLKDIS_CECCLK_DISABLE = 0x20, + HDMI_MC_CLKDIS_CSCCLK_DISABLE = 0x10, + HDMI_MC_CLKDIS_AUDCLK_DISABLE = 0x8, + HDMI_MC_CLKDIS_PREPCLK_DISABLE = 0x4, + HDMI_MC_CLKDIS_TMDSCLK_DISABLE = 0x2, + HDMI_MC_CLKDIS_PIXELCLK_DISABLE = 0x1, + +/* MC_SWRSTZ field values */ + HDMI_MC_SWRSTZ_TMDSSWRST_REQ = 0x02, + +/* MC_FLOWCTRL field values */ + HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_MASK = 0x1, + HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH = 0x1, + HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS = 0x0, + +/* MC_PHYRSTZ field values */ + HDMI_MC_PHYRSTZ_ASSERT = 0x0, + HDMI_MC_PHYRSTZ_DEASSERT = 0x1, + +/* MC_HEACPHY_RST field values */ + HDMI_MC_HEACPHY_RST_ASSERT = 0x1, + HDMI_MC_HEACPHY_RST_DEASSERT = 0x0, + +/* CSC_CFG field values */ + HDMI_CSC_CFG_INTMODE_MASK = 0x30, + HDMI_CSC_CFG_INTMODE_OFFSET = 4, + HDMI_CSC_CFG_INTMODE_DISABLE = 0x00, + HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1 = 0x10, + HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA2 = 0x20, + HDMI_CSC_CFG_DECMODE_MASK = 0x3, + HDMI_CSC_CFG_DECMODE_OFFSET = 0, + HDMI_CSC_CFG_DECMODE_DISABLE = 0x0, + HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA1 = 0x1, + HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA2 = 0x2, + HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3 = 0x3, + +/* CSC_SCALE field values */ + HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK = 0xF0, + HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP = 0x00, + HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP = 0x50, + HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP = 0x60, + HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP = 0x70, + HDMI_CSC_SCALE_CSCSCALE_MASK = 0x03, + +/* A_HDCPCFG0 field values */ + HDMI_A_HDCPCFG0_ELVENA_MASK = 0x80, + HDMI_A_HDCPCFG0_ELVENA_ENABLE = 0x80, + HDMI_A_HDCPCFG0_ELVENA_DISABLE = 0x00, + HDMI_A_HDCPCFG0_I2CFASTMODE_MASK = 0x40, + HDMI_A_HDCPCFG0_I2CFASTMODE_ENABLE = 0x40, + HDMI_A_HDCPCFG0_I2CFASTMODE_DISABLE = 0x00, + HDMI_A_HDCPCFG0_BYPENCRYPTION_MASK = 0x20, + HDMI_A_HDCPCFG0_BYPENCRYPTION_ENABLE = 0x20, + HDMI_A_HDCPCFG0_BYPENCRYPTION_DISABLE = 0x00, + HDMI_A_HDCPCFG0_SYNCRICHECK_MASK = 0x10, + HDMI_A_HDCPCFG0_SYNCRICHECK_ENABLE = 0x10, + HDMI_A_HDCPCFG0_SYNCRICHECK_DISABLE = 0x00, + HDMI_A_HDCPCFG0_AVMUTE_MASK = 0x8, + HDMI_A_HDCPCFG0_AVMUTE_ENABLE = 0x8, + HDMI_A_HDCPCFG0_AVMUTE_DISABLE = 0x0, + HDMI_A_HDCPCFG0_RXDETECT_MASK = 0x4, + HDMI_A_HDCPCFG0_RXDETECT_ENABLE = 0x4, + HDMI_A_HDCPCFG0_RXDETECT_DISABLE = 0x0, + HDMI_A_HDCPCFG0_EN11FEATURE_MASK = 0x2, + HDMI_A_HDCPCFG0_EN11FEATURE_ENABLE = 0x2, + HDMI_A_HDCPCFG0_EN11FEATURE_DISABLE = 0x0, + HDMI_A_HDCPCFG0_HDMIDVI_MASK = 0x1, + HDMI_A_HDCPCFG0_HDMIDVI_HDMI = 0x1, + HDMI_A_HDCPCFG0_HDMIDVI_DVI = 0x0, + +/* A_HDCPCFG1 field values */ + HDMI_A_HDCPCFG1_DISSHA1CHECK_MASK = 0x8, + HDMI_A_HDCPCFG1_DISSHA1CHECK_DISABLE = 0x8, + HDMI_A_HDCPCFG1_DISSHA1CHECK_ENABLE = 0x0, + HDMI_A_HDCPCFG1_PH2UPSHFTENC_MASK = 0x4, + HDMI_A_HDCPCFG1_PH2UPSHFTENC_ENABLE = 0x4, + HDMI_A_HDCPCFG1_PH2UPSHFTENC_DISABLE = 0x0, + HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK = 0x2, + HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE = 0x2, + HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_ENABLE = 0x0, + HDMI_A_HDCPCFG1_SWRESET_MASK = 0x1, + HDMI_A_HDCPCFG1_SWRESET_ASSERT = 0x0, + +/* A_VIDPOLCFG field values */ + HDMI_A_VIDPOLCFG_UNENCRYPTCONF_MASK = 0x60, + HDMI_A_VIDPOLCFG_UNENCRYPTCONF_OFFSET = 5, + HDMI_A_VIDPOLCFG_DATAENPOL_MASK = 0x10, + HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH = 0x10, + HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW = 0x0, + HDMI_A_VIDPOLCFG_VSYNCPOL_MASK = 0x8, + HDMI_A_VIDPOLCFG_VSYNCPOL_ACTIVE_HIGH = 0x8, + HDMI_A_VIDPOLCFG_VSYNCPOL_ACTIVE_LOW = 0x0, + HDMI_A_VIDPOLCFG_HSYNCPOL_MASK = 0x2, + HDMI_A_VIDPOLCFG_HSYNCPOL_ACTIVE_HIGH = 0x2, + HDMI_A_VIDPOLCFG_HSYNCPOL_ACTIVE_LOW = 0x0, + + +/* I2CM_OPERATION field values */ + HDMI_I2CM_OPERATION_WRITE = 0x10, + HDMI_I2CM_OPERATION_READ_EXT = 0x2, + HDMI_I2CM_OPERATION_READ = 0x1, + +/* HDMI_I2CM_INT */ + HDMI_I2CM_INT_DONE_POL = 0x08, + HDMI_I2CM_INT_DONE_MASK = 0x04, + +/* HDMI_I2CM_CTLINT */ + HDMI_I2CM_CTLINT_NAC_POL = 0x80, + HDMI_I2CM_CTLINT_NAC_MASK = 0x40, + HDMI_I2CM_CTLINT_ARBITRATION_POL = 0x08, + HDMI_I2CM_CTLINT_ARBITRATION_MASK = 0x04, + +}; + +/* IOCTL commands */ +#define HDMI_IOC_MAGIC 'H' + +#define HDMI_IOC_GET_RESOURCE _IO(HDMI_IOC_MAGIC, 0) +#define HDMI_IOC_GET_CPU_TYPE _IO(HDMI_IOC_MAGIC, 1) + + +#endif /* __MXC_HDMI_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mxc_nand.h b/arch/arm/plat-mxc/include/mach/mxc_nand.h new file mode 100644 index 00000000..6bb96ef1 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/mxc_nand.h @@ -0,0 +1,32 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008 Sascha Hauer, kernel@pengutronix.de + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#ifndef __ASM_ARCH_NAND_H +#define __ASM_ARCH_NAND_H + +#include <linux/mtd/partitions.h> + +struct mxc_nand_platform_data { + unsigned int width; /* data bus width in bytes */ + unsigned int hw_ecc:1; /* 0 if suppress hardware ECC */ + unsigned int flash_bbt:1; /* set to 1 to use a flash based bbt */ + struct mtd_partition *parts; /* partition table */ + int nr_parts; /* size of parts */ +}; +#endif /* __ASM_ARCH_NAND_H */ diff --git a/arch/arm/plat-mxc/include/mach/mxc_uart.h b/arch/arm/plat-mxc/include/mach/mxc_uart.h new file mode 100644 index 00000000..689aaadf --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/mxc_uart.h @@ -0,0 +1,267 @@ +/* + * Copyright 2004-2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @defgroup UART Universal Asynchronous Receiver Transmitter (UART) Driver + */ + +/*! + * @file arch-mxc/mxc_uart.h + * + * @brief This file contains the UART configuration structure definition. + * + * + * @ingroup UART + */ + +#ifndef __ASM_ARCH_MXC_UART_H__ +#define __ASM_ARCH_MXC_UART_H__ + +#ifdef __KERNEL__ + +#include <linux/serial_core.h> + +/* + * The modes of the UART ports + */ +#define MODE_DTE 0 +#define MODE_DCE 1 +/* + * Is the UART configured to be a IR port + */ +#define IRDA 0 +#define NO_IRDA 1 + +/*! + * This structure is used to store the the physical and virtual + * addresses of the UART DMA receive buffer. + */ +typedef struct { + /*! + * DMA Receive buffer virtual address + */ + char *rx_buf; + /*! + * DMA Receive buffer physical address + */ + dma_addr_t rx_handle; +} mxc_uart_rxdmamap; + +/*! + * This structure is a way for the low level driver to define their own + * \b uart_port structure. This structure includes the core \b uart_port + * structure that is provided by Linux as an element and has other + * elements that are specifically required by this low-level driver. + */ +typedef struct { + /*! + * The port structure holds all the information about the UART + * port like base address, and so on. + */ + struct uart_port port; + /*! + * Flag to determine if the interrupts are muxed. + */ + int ints_muxed; + /*! + * Array that holds the receive and master interrupt numbers + * when the interrupts are not muxed. + */ + int irqs[2]; + /*! + * Flag to determine the DTE/DCE mode. + */ + int mode; + /*! + * Flag to hold the IR mode of the port. + */ + int ir_mode; + /*! + * Flag to enable/disable the UART port. + */ + int enabled; + /*! + * Flag to indicate if we wish to use hardware-driven hardware + * flow control. + */ + int hardware_flow; + /*! + * Holds the threshold value at which the CTS line is deasserted in + * case we use hardware-driven hardware flow control. + */ + unsigned int cts_threshold; + /*! + * Flag to enable/disable DMA data transfer. + */ + int dma_enabled; + /*! + * Holds the DMA receive buffer size. + */ + int dma_rxbuf_size; + /*! + * DMA Receive buffers information + */ + mxc_uart_rxdmamap *rx_dmamap; + /*! + * DMA RX buffer id + */ + int dma_rxbuf_id; + /*! + * DMA Transmit buffer virtual address + */ + char *tx_buf; + /*! + * DMA Transmit buffer physical address + */ + dma_addr_t tx_handle; + /*! + * Holds the RxFIFO threshold value. + */ + unsigned int rx_threshold; + /*! + * Holds the TxFIFO threshold value. + */ + unsigned int tx_threshold; + /*! + * Information whether this is a shared UART + */ + unsigned int shared; + /*! + * Clock id for UART clock + */ + struct clk *clk; + /*! + * Information whether RXDMUXSEL must be set or not for IR port + */ + int rxd_mux; + int ir_tx_inv; + int ir_rx_inv; +} uart_mxc_port; + +/* Address offsets of the UART registers */ +#define MXC_UARTURXD 0x000 /* Receive reg */ +#define MXC_UARTUTXD 0x040 /* Transmitter reg */ +#define MXC_UARTUCR1 0x080 /* Control reg 1 */ +#define MXC_UARTUCR2 0x084 /* Control reg 2 */ +#define MXC_UARTUCR3 0x088 /* Control reg 3 */ +#define MXC_UARTUCR4 0x08C /* Control reg 4 */ +#define MXC_UARTUFCR 0x090 /* FIFO control reg */ +#define MXC_UARTUSR1 0x094 /* Status reg 1 */ +#define MXC_UARTUSR2 0x098 /* Status reg 2 */ +#define MXC_UARTUESC 0x09C /* Escape character reg */ +#define MXC_UARTUTIM 0x0A0 /* Escape timer reg */ +#define MXC_UARTUBIR 0x0A4 /* BRM incremental reg */ +#define MXC_UARTUBMR 0x0A8 /* BRM modulator reg */ +#define MXC_UARTUBRC 0x0AC /* Baud rate count reg */ +#define MXC_UARTONEMS 0x0B0 /* One millisecond reg */ +#define MXC_UARTUTS 0x0B4 /* Test reg */ +#define MXC_UARTUMCR 0x0B8 /* RS485 Mode control */ + +/* Bit definations of UCR1 */ +#define MXC_UARTUCR1_ADEN 0x8000 +#define MXC_UARTUCR1_ADBR 0x4000 +#define MXC_UARTUCR1_TRDYEN 0x2000 +#define MXC_UARTUCR1_IDEN 0x1000 +#define MXC_UARTUCR1_RRDYEN 0x0200 +#define MXC_UARTUCR1_RXDMAEN 0x0100 +#define MXC_UARTUCR1_IREN 0x0080 +#define MXC_UARTUCR1_TXMPTYEN 0x0040 +#define MXC_UARTUCR1_RTSDEN 0x0020 +#define MXC_UARTUCR1_SNDBRK 0x0010 +#define MXC_UARTUCR1_TXDMAEN 0x0008 +#define MXC_UARTUCR1_ATDMAEN 0x0004 +#define MXC_UARTUCR1_DOZE 0x0002 +#define MXC_UARTUCR1_UARTEN 0x0001 + +/* Bit definations of UCR2 */ +#define MXC_UARTUCR2_ESCI 0x8000 +#define MXC_UARTUCR2_IRTS 0x4000 +#define MXC_UARTUCR2_CTSC 0x2000 +#define MXC_UARTUCR2_CTS 0x1000 +#define MXC_UARTUCR2_PREN 0x0100 +#define MXC_UARTUCR2_PROE 0x0080 +#define MXC_UARTUCR2_STPB 0x0040 +#define MXC_UARTUCR2_WS 0x0020 +#define MXC_UARTUCR2_RTSEN 0x0010 +#define MXC_UARTUCR2_ATEN 0x0008 +#define MXC_UARTUCR2_TXEN 0x0004 +#define MXC_UARTUCR2_RXEN 0x0002 +#define MXC_UARTUCR2_SRST 0x0001 + +/* Bit definations of UCR3 */ +#define MXC_UARTUCR3_DTREN 0x2000 +#define MXC_UARTUCR3_PARERREN 0x1000 +#define MXC_UARTUCR3_FRAERREN 0x0800 +#define MXC_UARTUCR3_DSR 0x0400 +#define MXC_UARTUCR3_DCD 0x0200 +#define MXC_UARTUCR3_RI 0x0100 +#define MXC_UARTUCR3_RXDSEN 0x0040 +#define MXC_UARTUCR3_AWAKEN 0x0010 +#define MXC_UARTUCR3_DTRDEN 0x0008 +#define MXC_UARTUCR3_RXDMUXSEL 0x0004 +#define MXC_UARTUCR3_INVT 0x0002 + +/* Bit definations of UCR4 */ +#define MXC_UARTUCR4_CTSTL_OFFSET 10 +#define MXC_UARTUCR4_CTSTL_MASK (0x3F << 10) +#define MXC_UARTUCR4_INVR 0x0200 +#define MXC_UARTUCR4_ENIRI 0x0100 +#define MXC_UARTUCR4_REF16 0x0040 +#define MXC_UARTUCR4_IRSC 0x0020 +#define MXC_UARTUCR4_TCEN 0x0008 +#define MXC_UARTUCR4_OREN 0x0002 +#define MXC_UARTUCR4_DREN 0x0001 + +/* Bit definations of UFCR */ +#define MXC_UARTUFCR_RFDIV 0x0200 /* Ref freq div is set to 2 */ +#define MXC_UARTUFCR_RFDIV_OFFSET 7 +#define MXC_UARTUFCR_RFDIV_MASK (0x7 << 7) +#define MXC_UARTUFCR_TXTL_OFFSET 10 +#define MXC_UARTUFCR_DCEDTE 0x0040 + +/* Bit definations of URXD */ +#define MXC_UARTURXD_ERR 0x4000 +#define MXC_UARTURXD_OVRRUN 0x2000 +#define MXC_UARTURXD_FRMERR 0x1000 +#define MXC_UARTURXD_BRK 0x0800 +#define MXC_UARTURXD_PRERR 0x0400 + +/* Bit definations of USR1 */ +#define MXC_UARTUSR1_PARITYERR 0x8000 +#define MXC_UARTUSR1_RTSS 0x4000 +#define MXC_UARTUSR1_TRDY 0x2000 +#define MXC_UARTUSR1_RTSD 0x1000 +#define MXC_UARTUSR1_FRAMERR 0x0400 +#define MXC_UARTUSR1_RRDY 0x0200 +#define MXC_UARTUSR1_AGTIM 0x0100 +#define MXC_UARTUSR1_DTRD 0x0080 +#define MXC_UARTUSR1_AWAKE 0x0010 + +/* Bit definations of USR2 */ +#define MXC_UARTUSR2_TXFE 0x4000 +#define MXC_UARTUSR2_IDLE 0x1000 +#define MXC_UARTUSR2_RIDELT 0x0400 +#define MXC_UARTUSR2_RIIN 0x0200 +#define MXC_UARTUSR2_DCDDELT 0x0040 +#define MXC_UARTUSR2_DCDIN 0x0020 +#define MXC_UARTUSR2_TXDC 0x0008 +#define MXC_UARTUSR2_ORE 0x0002 +#define MXC_UARTUSR2_RDR 0x0001 +#define MXC_UARTUSR2_BRCD 0x0004 + +/* Bit definations of UTS */ +#define MXC_UARTUTS_LOOP 0x1000 + +#endif /* __KERNEL__ */ + +#endif /* __ASM_ARCH_MXC_UART_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mxc_vpu.h b/arch/arm/plat-mxc/include/mach/mxc_vpu.h new file mode 100755 index 00000000..688e3aab --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/mxc_vpu.h @@ -0,0 +1,117 @@ +/* + * Copyright 2004-2013 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU Lesser General + * Public License. You may obtain a copy of the GNU Lesser General + * Public License Version 2.1 or later at the following locations: + * + * http://www.opensource.org/licenses/lgpl-license.html + * http://www.gnu.org/copyleft/lgpl.html + */ + +/*! + * @defgroup VPU Video Processor Unit Driver + */ + +/*! + * @file plat-mxc/include/mach/mxc_vpu.h + * + * @brief VPU system initialization and file operation definition + * + * @ingroup VPU + */ + +#ifndef __ASM_ARCH_MXC_VPU_H__ +#define __ASM_ARCH_MXC_VPU_H__ + +#include <linux/fs.h> + +struct mxc_vpu_platform_data { + bool iram_enable; + int iram_size; + void (*reset) (void); + void (*pg) (int); +}; + +struct vpu_mem_desc { + u32 size; + dma_addr_t phy_addr; + u32 cpu_addr; /* cpu address to free the dma mem */ + u32 virt_uaddr; /* virtual user space address */ +}; + +#define VPU_IOC_MAGIC 'V' + +#define VPU_IOC_PHYMEM_ALLOC _IO(VPU_IOC_MAGIC, 0) +#define VPU_IOC_PHYMEM_FREE _IO(VPU_IOC_MAGIC, 1) +#define VPU_IOC_WAIT4INT _IO(VPU_IOC_MAGIC, 2) +#define VPU_IOC_PHYMEM_DUMP _IO(VPU_IOC_MAGIC, 3) +#define VPU_IOC_REG_DUMP _IO(VPU_IOC_MAGIC, 4) +#define VPU_IOC_IRAM_SETTING _IO(VPU_IOC_MAGIC, 6) +#define VPU_IOC_CLKGATE_SETTING _IO(VPU_IOC_MAGIC, 7) +#define VPU_IOC_GET_WORK_ADDR _IO(VPU_IOC_MAGIC, 8) +#define VPU_IOC_REQ_VSHARE_MEM _IO(VPU_IOC_MAGIC, 9) +#define VPU_IOC_SYS_SW_RESET _IO(VPU_IOC_MAGIC, 11) +#define VPU_IOC_GET_SHARE_MEM _IO(VPU_IOC_MAGIC, 12) +#define VPU_IOC_QUERY_BITWORK_MEM _IO(VPU_IOC_MAGIC, 13) +#define VPU_IOC_SET_BITWORK_MEM _IO(VPU_IOC_MAGIC, 14) +#define VPU_IOC_PHYMEM_CHECK _IO(VPU_IOC_MAGIC, 15) + +#define BIT_CODE_RUN 0x000 +#define BIT_CODE_DOWN 0x004 +#define BIT_INT_CLEAR 0x00C +#define BIT_INT_STATUS 0x010 +#define BIT_CUR_PC 0x018 +#define BIT_INT_REASON 0x174 + +#define MJPEG_PIC_STATUS_REG 0x3004 +#define MBC_SET_SUBBLK_EN 0x4A0 + +#define BIT_WORK_CTRL_BUF_BASE 0x100 +#define BIT_WORK_CTRL_BUF_REG(i) (BIT_WORK_CTRL_BUF_BASE + i * 4) +#define BIT_CODE_BUF_ADDR BIT_WORK_CTRL_BUF_REG(0) +#define BIT_WORK_BUF_ADDR BIT_WORK_CTRL_BUF_REG(1) +#define BIT_PARA_BUF_ADDR BIT_WORK_CTRL_BUF_REG(2) +#define BIT_BIT_STREAM_CTRL BIT_WORK_CTRL_BUF_REG(3) +#define BIT_FRAME_MEM_CTRL BIT_WORK_CTRL_BUF_REG(4) +#define BIT_BIT_STREAM_PARAM BIT_WORK_CTRL_BUF_REG(5) + +#ifndef CONFIG_ARCH_MX6 +#define BIT_RESET_CTRL 0x11C +#else +#define BIT_RESET_CTRL 0x128 +#endif + +/* i could be 0, 1, 2, 3 */ +#define BIT_RD_PTR_BASE 0x120 +#define BIT_RD_PTR_REG(i) (BIT_RD_PTR_BASE + i * 8) +#define BIT_WR_PTR_REG(i) (BIT_RD_PTR_BASE + i * 8 + 4) + +/* i could be 0, 1, 2, 3 */ +#define BIT_FRM_DIS_FLG_BASE (cpu_is_mx51() ? 0x150 : 0x140) +#define BIT_FRM_DIS_FLG_REG(i) (BIT_FRM_DIS_FLG_BASE + i * 4) + +#define BIT_BUSY_FLAG 0x160 +#define BIT_RUN_COMMAND 0x164 +#define BIT_INT_ENABLE 0x170 + +#define BITVAL_PIC_RUN 8 + +#define VPU_SLEEP_REG_VALUE 10 +#define VPU_WAKE_REG_VALUE 11 + +int vl2cc_init(u32 vl2cc_hw_base); +void vl2cc_enable(void); +void vl2cc_flush(void); +void vl2cc_disable(void); +void vl2cc_cleanup(void); + +int vl2cc_init(u32 vl2cc_hw_base); +void vl2cc_enable(void); +void vl2cc_flush(void); +void vl2cc_disable(void); +void vl2cc_cleanup(void); + +#endif diff --git a/arch/arm/plat-mxc/include/mach/mxs.h b/arch/arm/plat-mxc/include/mach/mxs.h new file mode 100644 index 00000000..3d67fed1 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/mxs.h @@ -0,0 +1,113 @@ +/* + * Copyright (C) 2009-2011 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __MACH_MXS_H__ +#define __MACH_MXS_H__ + +#ifndef __ASSEMBLER__ +#include <linux/io.h> +#endif +#include <asm/mach-types.h> +#include <mach/hardware.h> + + +/* + * MXS CPU types + */ +#define cpu_is_mx23() ( \ + machine_is_mx23evk() || \ + 0) +#define cpu_is_mx28() ( \ + machine_is_mx28evk() || \ + machine_is_tx28() || \ + 0) + +#if 0 +/* + * IO addresses common to MXS-based + */ +#define MXS_IO_BASE_ADDR 0x80000000 +#define MXS_IO_SIZE SZ_1M + +#define MXS_ICOLL_BASE_ADDR (MXS_IO_BASE_ADDR + 0x000000) +#define MXS_APBH_DMA_BASE_ADDR (MXS_IO_BASE_ADDR + 0x004000) +#define MXS_BCH_BASE_ADDR (MXS_IO_BASE_ADDR + 0x00a000) +#define MXS_GPMI_BASE_ADDR (MXS_IO_BASE_ADDR + 0x00c000) +#define MXS_PINCTRL_BASE_ADDR (MXS_IO_BASE_ADDR + 0x018000) +#define MXS_DIGCTL_BASE_ADDR (MXS_IO_BASE_ADDR + 0x01c000) +#define MXS_APBX_DMA_BASE_ADDR (MXS_IO_BASE_ADDR + 0x024000) +#define MXS_DCP_BASE_ADDR (MXS_IO_BASE_ADDR + 0x028000) +#define MXS_PXP_BASE_ADDR (MXS_IO_BASE_ADDR + 0x02a000) +#define MXS_OCOTP_BASE_ADDR (MXS_IO_BASE_ADDR + 0x02c000) +#define MXS_AXI_AHB0_BASE_ADDR (MXS_IO_BASE_ADDR + 0x02e000) +#define MXS_LCDIF_BASE_ADDR (MXS_IO_BASE_ADDR + 0x030000) +#define MXS_CLKCTRL_BASE_ADDR (MXS_IO_BASE_ADDR + 0x040000) +#define MXS_SAIF0_BASE_ADDR (MXS_IO_BASE_ADDR + 0x042000) +#define MXS_POWER_BASE_ADDR (MXS_IO_BASE_ADDR + 0x044000) +#define MXS_SAIF1_BASE_ADDR (MXS_IO_BASE_ADDR + 0x046000) +#define MXS_LRADC_BASE_ADDR (MXS_IO_BASE_ADDR + 0x050000) +#define MXS_SPDIF_BASE_ADDR (MXS_IO_BASE_ADDR + 0x054000) +#define MXS_I2C0_BASE_ADDR (MXS_IO_BASE_ADDR + 0x058000) +#define MXS_PWM_BASE_ADDR (MXS_IO_BASE_ADDR + 0x064000) +#define MXS_TIMROT_BASE_ADDR (MXS_IO_BASE_ADDR + 0x068000) +#define MXS_AUART1_BASE_ADDR (MXS_IO_BASE_ADDR + 0x06c000) +#define MXS_AUART2_BASE_ADDR (MXS_IO_BASE_ADDR + 0x06e000) +#define MXS_DRAM_BASE_ADDR (MXS_IO_BASE_ADDR + 0x0e0000) +#endif + +/* + * It maps the whole address space to [0xf4000000, 0xf50fffff]. + * + * OCRAM 0x00000000+0x020000 -> 0xf4000000+0x020000 + * IO 0x80000000+0x100000 -> 0xf5000000+0x100000 + */ +#define MXS_IO_P2V(x) (0xf4000000 + \ + (((x) & 0x80000000) >> 7) + \ + (((x) & 0x000fffff))) + +#define MXS_IO_ADDRESS(x) IOMEM(MXS_IO_P2V(x)) + +#define mxs_map_entry(soc, name, _type) { \ + .virtual = soc ## _IO_P2V(soc ## _ ## name ## _BASE_ADDR), \ + .pfn = __phys_to_pfn(soc ## _ ## name ## _BASE_ADDR), \ + .length = soc ## _ ## name ## _SIZE, \ + .type = _type, \ +} + +#define MXS_SET_ADDR 0x4 +#define MXS_CLR_ADDR 0x8 +#define MXS_TOG_ADDR 0xc + +#ifndef __ASSEMBLER__ +static inline void __mxs_setl(u32 mask, void __iomem *reg) +{ + __raw_writel(mask, reg + MXS_SET_ADDR); +} + +static inline void __mxs_clrl(u32 mask, void __iomem *reg) +{ + __raw_writel(mask, reg + MXS_CLR_ADDR); +} + +static inline void __mxs_togl(u32 mask, void __iomem *reg) +{ + __raw_writel(mask, reg + MXS_TOG_ADDR); +} +#endif + +#endif /* __MACH_MXS_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/pcie.h b/arch/arm/plat-mxc/include/mach/pcie.h new file mode 100644 index 00000000..177410d8 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/pcie.h @@ -0,0 +1,40 @@ +/* + * Copyright (C) 2012-2013 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ASM_ARCH_IMX_PCIE_H +#define __ASM_ARCH_IMX_PCIE_H + +/** + * struct imx_pcie_platform_data - optional platform data for pcie on i.MX + * + * @pcie_pwr_en: used for enable/disable pcie power (-EINVAL if unused) + * @pcie_rst: used for reset pcie ep (-EINVAL if unused) + * @pcie_wake_up: used for wake up (-EINVAL if unused) + * @pcie_dis: used for disable pcie ep (-EINVAL if unused) + */ + +struct imx_pcie_platform_data { + unsigned int pcie_pwr_en; + unsigned int pcie_rst; + unsigned int pcie_wake_up; + unsigned int pcie_dis; + unsigned int type_ep; /* 1 EP, 0 RC */ +}; +#endif /* __ASM_ARCH_IMX_PCIE_H */ diff --git a/arch/arm/plat-mxc/include/mach/regs-usbphy-mx6.h b/arch/arm/plat-mxc/include/mach/regs-usbphy-mx6.h new file mode 100644 index 00000000..473d16c4 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/regs-usbphy-mx6.h @@ -0,0 +1,480 @@ +/* + * Freescale USBPHY Register Definitions + * + * Copyright 2008-2012 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.2 + * Template revision: 1.3 + */ + +#ifndef __ARCH_ARM___USBPHY_H +#define __ARCH_ARM___USBPHY_H + + +#define HW_USBPHY_PWD (0x00000000) +#define HW_USBPHY_PWD_SET (0x00000004) +#define HW_USBPHY_PWD_CLR (0x00000008) +#define HW_USBPHY_PWD_TOG (0x0000000c) + +#define BP_USBPHY_PWD_RSVD2 21 +#define BM_USBPHY_PWD_RSVD2 0xFFE00000 +#define BF_USBPHY_PWD_RSVD2(v) \ + (((v) << 21) & BM_USBPHY_PWD_RSVD2) +#define BM_USBPHY_PWD_RXPWDRX 0x00100000 +#define BM_USBPHY_PWD_RXPWDDIFF 0x00080000 +#define BM_USBPHY_PWD_RXPWD1PT1 0x00040000 +#define BM_USBPHY_PWD_RXPWDENV 0x00020000 +#define BP_USBPHY_PWD_RSVD1 13 +#define BM_USBPHY_PWD_RSVD1 0x0001E000 +#define BF_USBPHY_PWD_RSVD1(v) \ + (((v) << 13) & BM_USBPHY_PWD_RSVD1) +#define BM_USBPHY_PWD_TXPWDV2I 0x00001000 +#define BM_USBPHY_PWD_TXPWDIBIAS 0x00000800 +#define BM_USBPHY_PWD_TXPWDFS 0x00000400 +#define BP_USBPHY_PWD_RSVD0 0 +#define BM_USBPHY_PWD_RSVD0 0x000003FF +#define BF_USBPHY_PWD_RSVD0(v) \ + (((v) << 0) & BM_USBPHY_PWD_RSVD0) + +#define HW_USBPHY_TX (0x00000010) +#define HW_USBPHY_TX_SET (0x00000014) +#define HW_USBPHY_TX_CLR (0x00000018) +#define HW_USBPHY_TX_TOG (0x0000001c) + +#define BP_USBPHY_TX_RSVD5 29 +#define BM_USBPHY_TX_RSVD5 0xE0000000 +#define BF_USBPHY_TX_RSVD5(v) \ + (((v) << 29) & BM_USBPHY_TX_RSVD5) +#define BP_USBPHY_TX_USBPHY_TX_EDGECTRL 26 +#define BM_USBPHY_TX_USBPHY_TX_EDGECTRL 0x1C000000 +#define BF_USBPHY_TX_USBPHY_TX_EDGECTRL(v) \ + (((v) << 26) & BM_USBPHY_TX_USBPHY_TX_EDGECTRL) +#define BM_USBPHY_TX_USBPHY_TX_SYNC_INVERT 0x02000000 +#define BM_USBPHY_TX_USBPHY_TX_SYNC_MUX 0x01000000 +#define BP_USBPHY_TX_RSVD4 22 +#define BM_USBPHY_TX_RSVD4 0x00C00000 +#define BF_USBPHY_TX_RSVD4(v) \ + (((v) << 22) & BM_USBPHY_TX_RSVD4) +#define BM_USBPHY_TX_TXENCAL45DP 0x00200000 +#define BM_USBPHY_TX_RSVD3 0x00100000 +#define BP_USBPHY_TX_TXCAL45DP 16 +#define BM_USBPHY_TX_TXCAL45DP 0x000F0000 +#define BF_USBPHY_TX_TXCAL45DP(v) \ + (((v) << 16) & BM_USBPHY_TX_TXCAL45DP) +#define BP_USBPHY_TX_RSVD2 14 +#define BM_USBPHY_TX_RSVD2 0x0000C000 +#define BF_USBPHY_TX_RSVD2(v) \ + (((v) << 14) & BM_USBPHY_TX_RSVD2) +#define BM_USBPHY_TX_TXENCAL45DN 0x00002000 +#define BM_USBPHY_TX_RSVD1 0x00001000 +#define BP_USBPHY_TX_TXCAL45DN 8 +#define BM_USBPHY_TX_TXCAL45DN 0x00000F00 +#define BF_USBPHY_TX_TXCAL45DN(v) \ + (((v) << 8) & BM_USBPHY_TX_TXCAL45DN) +#define BP_USBPHY_TX_RSVD0 4 +#define BM_USBPHY_TX_RSVD0 0x000000F0 +#define BF_USBPHY_TX_RSVD0(v) \ + (((v) << 4) & BM_USBPHY_TX_RSVD0) +#define BP_USBPHY_TX_D_CAL 0 +#define BM_USBPHY_TX_D_CAL 0x0000000F +#define BF_USBPHY_TX_D_CAL(v) \ + (((v) << 0) & BM_USBPHY_TX_D_CAL) + +#define HW_USBPHY_RX (0x00000020) +#define HW_USBPHY_RX_SET (0x00000024) +#define HW_USBPHY_RX_CLR (0x00000028) +#define HW_USBPHY_RX_TOG (0x0000002c) + +#define BP_USBPHY_RX_RSVD2 23 +#define BM_USBPHY_RX_RSVD2 0xFF800000 +#define BF_USBPHY_RX_RSVD2(v) \ + (((v) << 23) & BM_USBPHY_RX_RSVD2) +#define BM_USBPHY_RX_RXDBYPASS 0x00400000 +#define BP_USBPHY_RX_RSVD1 7 +#define BM_USBPHY_RX_RSVD1 0x003FFF80 +#define BF_USBPHY_RX_RSVD1(v) \ + (((v) << 7) & BM_USBPHY_RX_RSVD1) +#define BP_USBPHY_RX_DISCONADJ 4 +#define BM_USBPHY_RX_DISCONADJ 0x00000070 +#define BF_USBPHY_RX_DISCONADJ(v) \ + (((v) << 4) & BM_USBPHY_RX_DISCONADJ) +#define BM_USBPHY_RX_RSVD0 0x00000008 +#define BP_USBPHY_RX_ENVADJ 0 +#define BM_USBPHY_RX_ENVADJ 0x00000007 +#define BF_USBPHY_RX_ENVADJ(v) \ + (((v) << 0) & BM_USBPHY_RX_ENVADJ) + +#define HW_USBPHY_CTRL (0x00000030) +#define HW_USBPHY_CTRL_SET (0x00000034) +#define HW_USBPHY_CTRL_CLR (0x00000038) +#define HW_USBPHY_CTRL_TOG (0x0000003c) + +#define BM_USBPHY_CTRL_SFTRST 0x80000000 +#define BM_USBPHY_CTRL_CLKGATE 0x40000000 +#define BM_USBPHY_CTRL_UTMI_SUSPENDM 0x20000000 +#define BM_USBPHY_CTRL_HOST_FORCE_LS_SE0 0x10000000 +#define BM_USBPHY_CTRL_OTG_ID_VALUE 0x08000000 +#define BM_USBPHY_CTRL_ENAUTOSET_USBCLKS 0x04000000 +#define BM_USBPHY_CTRL_ENAUTOCLR_USBCLKGATE 0x02000000 +#define BM_USBPHY_CTRL_FSDLL_RST_EN 0x01000000 +#define BM_USBPHY_CTRL_ENVBUSCHG_WKUP 0x00800000 +#define BM_USBPHY_CTRL_ENIDCHG_WKUP 0x00400000 +#define BM_USBPHY_CTRL_ENDPDMCHG_WKUP 0x00200000 +#define BM_USBPHY_CTRL_ENAUTOCLR_PHY_PWD 0x00100000 +#define BM_USBPHY_CTRL_ENAUTOCLR_CLKGATE 0x00080000 +#define BM_USBPHY_CTRL_ENAUTO_PWRON_PLL 0x00040000 +#define BM_USBPHY_CTRL_WAKEUP_IRQ 0x00020000 +#define BM_USBPHY_CTRL_ENIRQWAKEUP 0x00010000 +#define BM_USBPHY_CTRL_ENUTMILEVEL3 0x00008000 +#define BM_USBPHY_CTRL_ENUTMILEVEL2 0x00004000 +#define BM_USBPHY_CTRL_DATA_ON_LRADC 0x00002000 +#define BM_USBPHY_CTRL_DEVPLUGIN_IRQ 0x00001000 +#define BM_USBPHY_CTRL_ENIRQDEVPLUGIN 0x00000800 +#define BM_USBPHY_CTRL_RESUME_IRQ 0x00000400 +#define BM_USBPHY_CTRL_ENIRQRESUMEDETECT 0x00000200 +#define BM_USBPHY_CTRL_RESUMEIRQSTICKY 0x00000100 +#define BM_USBPHY_CTRL_ENOTGIDDETECT 0x00000080 +#define BM_USBPHY_CTRL_OTG_ID_CHG_IRQ 0x00000040 +#define BM_USBPHY_CTRL_DEVPLUGIN_POLARITY 0x00000020 +#define BM_USBPHY_CTRL_ENDEVPLUGINDETECT 0x00000010 +#define BM_USBPHY_CTRL_HOSTDISCONDETECT_IRQ 0x00000008 +#define BM_USBPHY_CTRL_ENIRQHOSTDISCON 0x00000004 +#define BM_USBPHY_CTRL_ENHOSTDISCONDETECT 0x00000002 +#define BM_USBPHY_CTRL_ENOTG_ID_CHG_IRQ 0x00000001 + +#define HW_USBPHY_STATUS (0x00000040) + +#define BP_USBPHY_STATUS_RSVD4 11 +#define BM_USBPHY_STATUS_RSVD4 0xFFFFF800 +#define BF_USBPHY_STATUS_RSVD4(v) \ + (((v) << 11) & BM_USBPHY_STATUS_RSVD4) +#define BM_USBPHY_STATUS_RESUME_STATUS 0x00000400 +#define BM_USBPHY_STATUS_RSVD3 0x00000200 +#define BM_USBPHY_STATUS_OTGID_STATUS 0x00000100 +#define BM_USBPHY_STATUS_RSVD2 0x00000080 +#define BM_USBPHY_STATUS_DEVPLUGIN_STATUS 0x00000040 +#define BP_USBPHY_STATUS_RSVD1 4 +#define BM_USBPHY_STATUS_RSVD1 0x00000030 +#define BF_USBPHY_STATUS_RSVD1(v) \ + (((v) << 4) & BM_USBPHY_STATUS_RSVD1) +#define BM_USBPHY_STATUS_HOSTDISCONDETECT_STATUS 0x00000008 +#define BP_USBPHY_STATUS_RSVD0 0 +#define BM_USBPHY_STATUS_RSVD0 0x00000007 +#define BF_USBPHY_STATUS_RSVD0(v) \ + (((v) << 0) & BM_USBPHY_STATUS_RSVD0) + +#define HW_USBPHY_DEBUG (0x00000050) +#define HW_USBPHY_DEBUG_SET (0x00000054) +#define HW_USBPHY_DEBUG_CLR (0x00000058) +#define HW_USBPHY_DEBUG_TOG (0x0000005c) + +#define BM_USBPHY_DEBUG_RSVD3 0x80000000 +#define BM_USBPHY_DEBUG_CLKGATE 0x40000000 +#define BM_USBPHY_DEBUG_HOST_RESUME_DEBUG 0x20000000 +#define BP_USBPHY_DEBUG_SQUELCHRESETLENGTH 25 +#define BM_USBPHY_DEBUG_SQUELCHRESETLENGTH 0x1E000000 +#define BF_USBPHY_DEBUG_SQUELCHRESETLENGTH(v) \ + (((v) << 25) & BM_USBPHY_DEBUG_SQUELCHRESETLENGTH) +#define BM_USBPHY_DEBUG_ENSQUELCHRESET 0x01000000 +#define BP_USBPHY_DEBUG_RSVD2 21 +#define BM_USBPHY_DEBUG_RSVD2 0x00E00000 +#define BF_USBPHY_DEBUG_RSVD2(v) \ + (((v) << 21) & BM_USBPHY_DEBUG_RSVD2) +#define BP_USBPHY_DEBUG_SQUELCHRESETCOUNT 16 +#define BM_USBPHY_DEBUG_SQUELCHRESETCOUNT 0x001F0000 +#define BF_USBPHY_DEBUG_SQUELCHRESETCOUNT(v) \ + (((v) << 16) & BM_USBPHY_DEBUG_SQUELCHRESETCOUNT) +#define BP_USBPHY_DEBUG_RSVD1 13 +#define BM_USBPHY_DEBUG_RSVD1 0x0000E000 +#define BF_USBPHY_DEBUG_RSVD1(v) \ + (((v) << 13) & BM_USBPHY_DEBUG_RSVD1) +#define BM_USBPHY_DEBUG_ENTX2RXCOUNT 0x00001000 +#define BP_USBPHY_DEBUG_TX2RXCOUNT 8 +#define BM_USBPHY_DEBUG_TX2RXCOUNT 0x00000F00 +#define BF_USBPHY_DEBUG_TX2RXCOUNT(v) \ + (((v) << 8) & BM_USBPHY_DEBUG_TX2RXCOUNT) +#define BP_USBPHY_DEBUG_RSVD0 6 +#define BM_USBPHY_DEBUG_RSVD0 0x000000C0 +#define BF_USBPHY_DEBUG_RSVD0(v) \ + (((v) << 6) & BM_USBPHY_DEBUG_RSVD0) +#define BP_USBPHY_DEBUG_ENHSTPULLDOWN 4 +#define BM_USBPHY_DEBUG_ENHSTPULLDOWN 0x00000030 +#define BF_USBPHY_DEBUG_ENHSTPULLDOWN(v) \ + (((v) << 4) & BM_USBPHY_DEBUG_ENHSTPULLDOWN) +#define BP_USBPHY_DEBUG_HSTPULLDOWN 2 +#define BM_USBPHY_DEBUG_HSTPULLDOWN 0x0000000C +#define BF_USBPHY_DEBUG_HSTPULLDOWN(v) \ + (((v) << 2) & BM_USBPHY_DEBUG_HSTPULLDOWN) +#define BM_USBPHY_DEBUG_DEBUG_INTERFACE_HOLD 0x00000002 +#define BM_USBPHY_DEBUG_OTGIDPIOLOCK 0x00000001 + +#define HW_USBPHY_DEBUG0_STATUS (0x00000060) + +#define BP_USBPHY_DEBUG0_STATUS_SQUELCH_COUNT 26 +#define BM_USBPHY_DEBUG0_STATUS_SQUELCH_COUNT 0xFC000000 +#define BF_USBPHY_DEBUG0_STATUS_SQUELCH_COUNT(v) \ + (((v) << 26) & BM_USBPHY_DEBUG0_STATUS_SQUELCH_COUNT) +#define BP_USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT 16 +#define BM_USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT 0x03FF0000 +#define BF_USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT(v) \ + (((v) << 16) & BM_USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT) +#define BP_USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT 0 +#define BM_USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT 0x0000FFFF +#define BF_USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT(v) \ + (((v) << 0) & BM_USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT) + +#define HW_USBPHY_DEBUG1 (0x00000070) +#define HW_USBPHY_DEBUG1_SET (0x00000074) +#define HW_USBPHY_DEBUG1_CLR (0x00000078) +#define HW_USBPHY_DEBUG1_TOG (0x0000007c) + +#define BP_USBPHY_DEBUG1_RSVD1 15 +#define BM_USBPHY_DEBUG1_RSVD1 0xFFFF8000 +#define BF_USBPHY_DEBUG1_RSVD1(v) \ + (((v) << 15) & BM_USBPHY_DEBUG1_RSVD1) +#define BP_USBPHY_DEBUG1_ENTAILADJVD 13 +#define BM_USBPHY_DEBUG1_ENTAILADJVD 0x00006000 +#define BF_USBPHY_DEBUG1_ENTAILADJVD(v) \ + (((v) << 13) & BM_USBPHY_DEBUG1_ENTAILADJVD) +#define BM_USBPHY_DEBUG1_ENTX2TX 0x00001000 +#define BP_USBPHY_DEBUG1_RSVD0 4 +#define BM_USBPHY_DEBUG1_RSVD0 0x00000FF0 +#define BF_USBPHY_DEBUG1_RSVD0(v) \ + (((v) << 4) & BM_USBPHY_DEBUG1_RSVD0) +#define BP_USBPHY_DEBUG1_DBG_ADDRESS 0 +#define BM_USBPHY_DEBUG1_DBG_ADDRESS 0x0000000F +#define BF_USBPHY_DEBUG1_DBG_ADDRESS(v) \ + (((v) << 0) & BM_USBPHY_DEBUG1_DBG_ADDRESS) + +#define HW_USBPHY_VERSION (0x00000080) + +#define BP_USBPHY_VERSION_MAJOR 24 +#define BM_USBPHY_VERSION_MAJOR 0xFF000000 +#define BF_USBPHY_VERSION_MAJOR(v) \ + (((v) << 24) & BM_USBPHY_VERSION_MAJOR) +#define BP_USBPHY_VERSION_MINOR 16 +#define BM_USBPHY_VERSION_MINOR 0x00FF0000 +#define BF_USBPHY_VERSION_MINOR(v) \ + (((v) << 16) & BM_USBPHY_VERSION_MINOR) +#define BP_USBPHY_VERSION_STEP 0 +#define BM_USBPHY_VERSION_STEP 0x0000FFFF +#define BF_USBPHY_VERSION_STEP(v) \ + (((v) << 0) & BM_USBPHY_VERSION_STEP) + +#define HW_USBPHY_IP (0x00000090) +#define HW_USBPHY_IP_SET (0x00000094) +#define HW_USBPHY_IP_CLR (0x00000098) +#define HW_USBPHY_IP_TOG (0x0000009c) + +#define BP_USBPHY_IP_RSVD1 25 +#define BM_USBPHY_IP_RSVD1 0xFE000000 +#define BF_USBPHY_IP_RSVD1(v) \ + (((v) << 25) & BM_USBPHY_IP_RSVD1) +#define BP_USBPHY_IP_DIV_SEL 23 +#define BM_USBPHY_IP_DIV_SEL 0x01800000 +#define BF_USBPHY_IP_DIV_SEL(v) \ + (((v) << 23) & BM_USBPHY_IP_DIV_SEL) +#define BV_USBPHY_IP_DIV_SEL__DEFAULT 0x0 +#define BV_USBPHY_IP_DIV_SEL__LOWER 0x1 +#define BV_USBPHY_IP_DIV_SEL__LOWEST 0x2 +#define BV_USBPHY_IP_DIV_SEL__UNDEFINED 0x3 +#define BP_USBPHY_IP_LFR_SEL 21 +#define BM_USBPHY_IP_LFR_SEL 0x00600000 +#define BF_USBPHY_IP_LFR_SEL(v) \ + (((v) << 21) & BM_USBPHY_IP_LFR_SEL) +#define BV_USBPHY_IP_LFR_SEL__DEFAULT 0x0 +#define BV_USBPHY_IP_LFR_SEL__TIMES_2 0x1 +#define BV_USBPHY_IP_LFR_SEL__TIMES_05 0x2 +#define BV_USBPHY_IP_LFR_SEL__UNDEFINED 0x3 +#define BP_USBPHY_IP_CP_SEL 19 +#define BM_USBPHY_IP_CP_SEL 0x00180000 +#define BF_USBPHY_IP_CP_SEL(v) \ + (((v) << 19) & BM_USBPHY_IP_CP_SEL) +#define BV_USBPHY_IP_CP_SEL__DEFAULT 0x0 +#define BV_USBPHY_IP_CP_SEL__TIMES_2 0x1 +#define BV_USBPHY_IP_CP_SEL__TIMES_05 0x2 +#define BV_USBPHY_IP_CP_SEL__UNDEFINED 0x3 +#define BM_USBPHY_IP_TSTI_TX_DP 0x00040000 +#define BM_USBPHY_IP_TSTI_TX_DM 0x00020000 +#define BM_USBPHY_IP_ANALOG_TESTMODE 0x00010000 +#define BP_USBPHY_IP_RSVD0 3 +#define BM_USBPHY_IP_RSVD0 0x0000FFF8 +#define BF_USBPHY_IP_RSVD0(v) \ + (((v) << 3) & BM_USBPHY_IP_RSVD0) +#define BM_USBPHY_IP_EN_USB_CLKS 0x00000004 +#define BM_USBPHY_IP_PLL_LOCKED 0x00000002 +#define BM_USBPHY_IP_PLL_POWER 0x00000001 + +/* The register definition for usbphy which includes at usb core's register set + * (from USB_CORE_BASE + 0x800) + */ +#define USB_CTRL USBOTHER_REG(0x00) /* USB OTG Control register */ +#define USB_H1_CTRL USBOTHER_REG(0x04) /* USB H1 Control register */ +#define USB_H2_CTRL USBOTHER_REG(0x08) /* USB H2 Control register */ +#define USB_H3_CTRL USBOTHER_REG(0x0c) /* USB H3 Control register */ +#define USB_UH2_HSIC_CTRL USBOTHER_REG(0x10) /* USB Host2 HSIC Control Register */ +#define USB_UH3_HSIC_CTRL USBOTHER_REG(0x14) /* USB Host3 HSIC Control Register */ +#define USB_OTG_PHY_CTRL_0 USBOTHER_REG(0x18) /* OTG UTMI PHY Control 0 Register */ +#define USB_H1_PHY_CTRL_0 USBOTHER_REG(0x1c) /* OTG UTMI PHY Control 1 Register */ +#define USB_UH2_HSIC_DLL_CFG1 USBOTHER_REG(0x20) /* USB Host2 HSIC DLL Configuration Register 1 */ +#define USB_UH2_HSIC_DLL_CFG2 USBOTHER_REG(0x24) /* USB Host2 HSIC DLL Configuration Register 2 */ +#define USB_UH2_HSIC_DLL_CFG3 USBOTHER_REG(0x28) /* USB Host2 HSIC DLL Configuration Register 3 */ +#define USB_UH3_HSIC_DLL_CFG1 USBOTHER_REG(0x30) /* USB Host3 HSIC DLL Configuration Register 1 */ +#define USB_UH3_HSIC_DLL_CFG2 USBOTHER_REG(0x34) /* USB Host3 HSIC DLL Configuration Register 2 */ +#define USB_UH3_HSIC_DLL_CFG3 USBOTHER_REG(0x38) /* USB Host3 HSIC DLL Configuration Register 3 */ + +/* + * register bits + */ + +/* USBCTRL */ +#define UCTRL_OSIC_MASK (3 << 29) /* OTG Serial Interface Config: */ +#define UCTRL_OSIC_DU6 (0 << 29) /* Differential/unidirectional 6 wire */ +#define UCTRL_OSIC_DB4 (1 << 29) /* Differential/bidirectional 4 wire */ +#define UCTRL_OSIC_SU6 (2 << 29) /* single-ended/unidirectional 6 wire */ +#define UCTRL_OSIC_SB3 (3 << 29) /* single-ended/bidirectional 3 wire */ +#define UCTRL_OUIE (1 << 28) /* OTG ULPI intr enable */ +#define UCTRL_OBPVAL_RXDP (1 << 26) /* OTG RxDp status in bypass mode */ +#define UCTRL_OBPVAL_RXDM (1 << 25) /* OTG RxDm status in bypass mode */ +#define UCTRL_OPM (1 << 24) /* OTG power mask */ +#define UCTRL_O_PWR_POL (1 << 24) /* OTG power pin polarity */ +#define UCTRL_H2WIR (1 << 17) /* HOST2 wakeup intr request received */ +#define UCTRL_H2SIC_MASK (3 << 21) /* HOST2 Serial Interface Config: */ +#define UCTRL_H2SIC_DU6 (0 << 21) /* Differential/unidirectional 6 wire */ +#define UCTRL_H2SIC_DB4 (1 << 21) /* Differential/bidirectional 4 wire */ +#define UCTRL_H2SIC_SU6 (2 << 21) /* single-ended/unidirectional 6 wire */ +#define UCTRL_H2SIC_SB3 (3 << 21) /* single-ended/bidirectional 3 wire */ +#define UCTRL_H2UIE (1 << 8) /* HOST2 ULPI intr enable */ +#define UCTRL_H2WIE (1 << 7) /* HOST2 wakeup intr enable */ +#define UCTRL_H2PP 0 /* Power Polarity for uh2 */ +#define UCTRL_H2PM (1 << 4) /* HOST2 power mask */ +#define UCTRL_H2OVBWK_EN (1 << 6) /* OTG VBUS Wakeup Enable */ +#define UCTRL_H2OIDWK_EN (1 << 5) /* OTG ID Wakeup Enable */ + +#define UCTRL_H1WIR (1 << 15) /* HOST1 wakeup intr request received */ +#define UCTRL_H1SIC_MASK (3 << 13) /* HOST1 Serial Interface Config: */ +#define UCTRL_H1SIC_DU6 (0 << 13) /* Differential/unidirectional 6 wire */ +#define UCTRL_H1SIC_DB4 (1 << 13) /* Differential/bidirectional 4 wire */ +#define UCTRL_H1SIC_SU6 (2 << 13) /* single-ended/unidirectional 6 wire */ +#define UCTRL_H1SIC_SB3 (3 << 13) /* single-ended/bidirectional 3 wire */ +#define UCTRL_OLOCKD (1 << 13) /* otg lock disable */ +#define UCTRL_H2LOCKD (1 << 12) /* HOST2 lock disable */ +#define UCTRL_H1UIE (1 << 12) /* Host1 ULPI interrupt enable */ + +#define UCTRL_PP (1 << 11) /* power polarity bit */ +#define UCTRL_H1WIE (1 << 11) /* HOST1 wakeup intr enable */ +#define UCTRL_H1BPVAL_RXDP (1 << 10) /* HOST1 RxDp status in bypass mode */ +#define UCTRL_XCSO (1 << 10) /* Xcvr Clock Select for OTG port */ +#define UCTRL_H1BPVAL_RXDM (1 << 9) /* HOST1 RxDm status in bypass mode */ +#define UCTRL_XCSH2 (1 << 9) /* Xcvr Clock Select for Host port */ +#define UCTRL_H1PM (1 << 8) /* HOST1 power mask */ +#define UCTRL_IP_PULIDP (1 << 8) /* Ipp_Puimpel_Pullup_Dp */ + +#define UCTRL_IP_PUE_UP (1 << 7) /* ipp_pue_pullup_dp */ +#define UCTRL_IP_PUE_DOWN (1 << 6) /* ipp_pue_pulldwn_dpdm */ +#define UCTRL_H2DT (1 << 5) /* HOST2 TLL disabled */ +#define UCTRL_H1DT (1 << 4) /* HOST1 TLL disabled */ +#define UCTRL_USBTE (1 << 4) /* USBT Transceiver enable */ +#define UCTRL_OCPOL (1 << 3) /* OverCurrent Polarity */ +#define UCTRL_OCE (1 << 2) /* OverCurrent Enable */ +#define UCTRL_H2OCPOL (1 << 2) /* OverCurrent Polarity of Host2 */ +#define UCTRL_H2OCS (1 << 1) /* Host OverCurrent State */ +#define UCTRL_BPE (1 << 0) /* bypass mode enable */ +#define UCTRL_OTD (1 << 0) /* OTG TLL Disable */ +#define UCTRL_OOCS (1 << 0) /* OTG OverCurrent State */ + +/* OTG_MIRROR */ +#define OTGM_SESEND (1 << 4) /* B device session end */ +#define OTGM_VBUSVAL (1 << 3) /* Vbus valid */ +#define OTGM_BSESVLD (1 << 2) /* B session Valid */ +#define OTGM_ASESVLD (1 << 1) /* A session Valid */ +#define OTGM_IDIDG (1 << 0) /* OTG ID pin status */ + /* 1=high: Operate as B-device */ + /* 0=low : Operate as A-device */ + +/* USB_PHY_CTRL_FUNC */ +/* PHY control0 Register Bit Masks */ +#define USB_UTMI_PHYCTRL_CONF2 (1 << 26) + +#define USB_UTMI_PHYCTRL_UTMI_ENABLE (1 << 24) +#define USB_UTMI_PHYCTRL_CHGRDETEN (1 << 24) /* Enable Charger Detector */ +#define USB_UTMI_PHYCTRL_CHGRDETON (1 << 23) /* Charger Detector Power On Control */ +#define USB_UTMI_PHYCTRL_OC_POL (1 << 9) /* OTG Polarity of Overcurrent */ +#define USB_UTMI_PHYCTRL_OC_DIS (1 << 8) /* OTG Disable Overcurrent Event */ +#define USB_UH1_OC_DIS (1 << 5) /* UH1 Disable Overcurrent Event */ +#define USB_UH1_OC_POL (1 << 6) /* UH1 Polarity of OC,Low active */ +/* USB_PHY_CTRL_FUNC2*/ +#define USB_UTMI_PHYCTRL2_PLLDIV_MASK 0x3 +#define USB_UTMI_PHYCTRL2_PLLDIV_SHIFT 0 +#define USB_UTMI_PHYCTRL2_HSDEVSEL_MASK 0x3 +#define USB_UTMI_PHYCTRL2_HSDEVSEL_SHIFT 19 + +/* USB_CTRL_1 */ +#define USB_CTRL_UH1_EXT_CLK_EN (1 << 25) +#define USB_CTRL_UH2_EXT_CLK_EN (1 << 26) +#define USB_CTRL_UH2_CLK_FROM_ULPI_PHY (1 << 2) +/* ULPIVIEW register bits */ +#define ULPIVW_OFF (0x170) +#define ULPIVW_WU (1 << 31) /* Wakeup */ +#define ULPIVW_RUN (1 << 30) /* read/write run */ +#define ULPIVW_WRITE (1 << 29) /* 0=read 1=write */ +#define ULPIVW_SS (1 << 27) /* SyncState */ +#define ULPIVW_PORT_MASK 0x07 /* Port field */ +#define ULPIVW_PORT_SHIFT 24 +#define ULPIVW_ADDR_MASK 0xFF /* data address field */ +#define ULPIVW_ADDR_SHIFT 16 +#define ULPIVW_RDATA_MASK 0xFF /* read data field */ +#define ULPIVW_RDATA_SHIFT 8 +#define ULPIVW_WDATA_MASK 0xFF /* write data field */ +#define ULPIVW_WDATA_SHIFT 0 + +/* USB Clock on/off Control Register */ +#define OTG_AHBCLK_OFF (0x1<<17) /* 1: OFF */ +#define H1_AHBCLK_OFF (0x1<<18) /* 1: OFF */ + +/* mx6q's register bit begins*/ + +/* OTG CTRL - H3 CTRL */ +#define UCTRL_OWIR (1 << 31) /* OTG wakeup intr request received */ +/* bit 18 - bit 30 is reserved at mx6q */ +#define UCTRL_WKUP_VBUS_EN (1 << 17) /* OTG wake-up on VBUS change enable */ +#define UCTRL_WKUP_ID_EN (1 << 16) /* OTG wake-up on ID change enable */ +#define UCTRL_WKUP_SW (1 << 15) /* OTG Software Wake-up */ +#define UCTRL_WKUP_SW_EN (1 << 14) /* OTG Software Wake-up enable */ +#define UCTRL_UTMI_ON_CLOCK (1 << 13) /* Force OTG UTMI PHY clock output on even if suspend mode */ +#define UCTRL_SUSPENDM (1 << 12) /* Force OTG UTMI PHY Suspend */ +#define UCTRL_RESET (1 << 11) /* Force OTG UTMI PHY Reset */ +#define UCTRL_OWIE (1 << 10) /* OTG wakeup intr request received */ +#define UCTRL_PM (1 << 9) /* OTG Power Mask */ +#define UCTRL_OVER_CUR_POL (1 << 8) /* OTG Polarity of Overcurrent */ +#define UCTRL_OVER_CUR_DIS (1 << 7) /* Disable OTG Overcurrent Detection */ +/* bit 0 - bit 6 is reserved at mx6q */ + +/* Host2/3 HSIC Ctrl */ +#define CLK_VLD (1 << 31) /* Indicating whether HSIC clock is valid */ +#define HSIC_DEV_CONN (1 << 21) /* set after device connected */ +#define HSIC_EN (1 << 12) /* HSIC enable */ +#define HSIC_CLK_ON (1 << 11) /* Force HSIC module 480M clock on, + * even when in Host is in suspend mode + */ +/* OTG/HOST1 Phy Ctrl */ +#define PHY_UTMI_CLK_VLD (1 << 31) /* Indicating whether OTG UTMI PHY Clock Valida */ + +#define NOP_XCVR (0xffffffff) /* Indicate it is no usb phy */ +#endif /* __ARCH_ARM___USBPHY_H */ diff --git a/arch/arm/plat-mxc/include/mach/regs-usbphy-others.h b/arch/arm/plat-mxc/include/mach/regs-usbphy-others.h new file mode 100644 index 00000000..7d8d1ff6 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/regs-usbphy-others.h @@ -0,0 +1,161 @@ +/* + * Copyright (C) 2005-2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __ASM_ARCH_MXC_USB_PHY_OTHERS_H__ +#define __ASM_ARCH_MXC_USB_PHY_OTHERS_H__ + +/* + * This file describes the registers of chipidea's phy + * This file can be used for i.MX1x, i.MX21. i.MX25. i.MX3x. i.MX5x. + */ + +#define USBCTRL USBOTHER_REG(0x00) /* USB Control register */ +#define USB_OTG_MIRROR USBOTHER_REG(0x04) /* USB OTG mirror register */ +#define USB_PHY_CTR_FUNC USBOTHER_REG(0x08) /* OTG UTMI PHY Function Control register */ +#define USB_PHY_CTR_FUNC2 USBOTHER_REG(0x0c) /* OTG UTMI PHY Function Control register */ +#define USB_CTRL_1 USBOTHER_REG(0x10) /* USB Cotrol Register 1*/ +#define USBCTRL_HOST2 USBOTHER_REG(0x14) /* USB Cotrol Register 1*/ +#define USBCTRL_HOST3 USBOTHER_REG(0x18) /* USB Cotrol Register 1*/ +#define USBH1_PHY_CTRL0 USBOTHER_REG(0x1c) /* USB Cotrol Register 1*/ +#define USBH1_PHY_CTRL1 USBOTHER_REG(0x20) /* USB Cotrol Register 1*/ +#define USB_CLKONOFF_CTRL USBOTHER_REG(0x24) /* USB Clock on/off Control Register */ + +/* + * register bits + */ + +/* USBCTRL */ +#define UCTRL_OWIR (1 << 31) /* OTG wakeup intr request received */ +#define UCTRL_OSIC_MASK (3 << 29) /* OTG Serial Interface Config: */ +#define UCTRL_OSIC_DU6 (0 << 29) /* Differential/unidirectional 6 wire */ +#define UCTRL_OSIC_DB4 (1 << 29) /* Differential/bidirectional 4 wire */ +#define UCTRL_OSIC_SU6 (2 << 29) /* single-ended/unidirectional 6 wire */ +#define UCTRL_OSIC_SB3 (3 << 29) /* single-ended/bidirectional 3 wire */ +#define UCTRL_OUIE (1 << 28) /* OTG ULPI intr enable */ +#define UCTRL_OWIE (1 << 27) /* OTG wakeup intr enable */ +#define UCTRL_OBPVAL_RXDP (1 << 26) /* OTG RxDp status in bypass mode */ +#define UCTRL_OBPVAL_RXDM (1 << 25) /* OTG RxDm status in bypass mode */ +#define UCTRL_OPM (1 << 24) /* OTG power mask */ +#define UCTRL_O_PWR_POL (1 << 24) /* OTG power pin polarity */ +#ifdef CONFIG_ARCH_MX5 +#define UCTRL_H2WIR (1 << 17) /* HOST2 wakeup intr request received */ +#else +#define UCTRL_H2WIR (1 << 23) /* HOST2 wakeup intr request received */ +#endif +#define UCTRL_H2SIC_MASK (3 << 21) /* HOST2 Serial Interface Config: */ +#define UCTRL_H2SIC_DU6 (0 << 21) /* Differential/unidirectional 6 wire */ +#define UCTRL_H2SIC_DB4 (1 << 21) /* Differential/bidirectional 4 wire */ +#define UCTRL_H2SIC_SU6 (2 << 21) /* single-ended/unidirectional 6 wire */ +#define UCTRL_H2SIC_SB3 (3 << 21) /* single-ended/bidirectional 3 wire */ + +#ifdef CONFIG_ARCH_MX5 +#define UCTRL_H2UIE (1 << 8) /* HOST2 ULPI intr enable */ +#define UCTRL_H2WIE (1 << 7) /* HOST2 wakeup intr enable */ +#define UCTRL_H2PP 0 /* Power Polarity for uh2 */ +#define UCTRL_H2PM (1 << 4) /* HOST2 power mask */ +#else +#define UCTRL_H2UIE (1 << 20) /* HOST2 ULPI intr enable */ +#define UCTRL_H2WIE (1 << 19) /* HOST2 wakeup intr enable */ +#define UCTRL_H2PP (1 << 18) /* Power Polarity for uh2 */ +#define UCTRL_H2PM (1 << 16) /* HOST2 power mask */ +#endif +#define UCTRL_H2OVBWK_EN (1 << 6) /* OTG VBUS Wakeup Enable */ +#define UCTRL_H2OIDWK_EN (1 << 5) /* OTG ID Wakeup Enable */ + +#define UCTRL_H1WIR (1 << 15) /* HOST1 wakeup intr request received */ +#define UCTRL_H1SIC_MASK (3 << 13) /* HOST1 Serial Interface Config: */ +#define UCTRL_H1SIC_DU6 (0 << 13) /* Differential/unidirectional 6 wire */ +#define UCTRL_H1SIC_DB4 (1 << 13) /* Differential/bidirectional 4 wire */ +#define UCTRL_H1SIC_SU6 (2 << 13) /* single-ended/unidirectional 6 wire */ +#define UCTRL_H1SIC_SB3 (3 << 13) /* single-ended/bidirectional 3 wire */ +#define UCTRL_OLOCKD (1 << 13) /* otg lock disable */ +#define UCTRL_H2LOCKD (1 << 12) /* HOST2 lock disable */ +#define UCTRL_H1UIE (1 << 12) /* Host1 ULPI interrupt enable */ + +#if defined(CONFIG_ARCH_MX37) +/* VBUS wakeup enable, UTMI only */ +#define UCTRL_VBUS_WKUP_EN (1 << 12) +#elif defined(CONFIG_ARCH_MX25) || defined(CONFIG_ARCH_MX35) +#define UCTRL_VBUS_WKUP_EN (1 << 15) +#endif + +#define UCTRL_PP (1 << 11) /* power polarity bit */ +#define UCTRL_H1WIE (1 << 11) /* HOST1 wakeup intr enable */ +#define UCTRL_H1BPVAL_RXDP (1 << 10) /* HOST1 RxDp status in bypass mode */ +#define UCTRL_XCSO (1 << 10) /* Xcvr Clock Select for OTG port */ +#define UCTRL_H1BPVAL_RXDM (1 << 9) /* HOST1 RxDm status in bypass mode */ +#define UCTRL_XCSH2 (1 << 9) /* Xcvr Clock Select for Host port */ +#define UCTRL_H1PM (1 << 8) /* HOST1 power mask */ +#define UCTRL_IP_PULIDP (1 << 8) /* Ipp_Puimpel_Pullup_Dp */ + +#define UCTRL_IP_PUE_UP (1 << 7) /* ipp_pue_pullup_dp */ +#define UCTRL_IP_PUE_DOWN (1 << 6) /* ipp_pue_pulldwn_dpdm */ +#define UCTRL_H2DT (1 << 5) /* HOST2 TLL disabled */ +#define UCTRL_H1DT (1 << 4) /* HOST1 TLL disabled */ +#define UCTRL_USBTE (1 << 4) /* USBT Transceiver enable */ +#define UCTRL_OCPOL (1 << 3) /* OverCurrent Polarity */ +#define UCTRL_OCE (1 << 2) /* OverCurrent Enable */ +#define UCTRL_H2OCPOL (1 << 2) /* OverCurrent Polarity of Host2 */ +#define UCTRL_H2OCS (1 << 1) /* Host OverCurrent State */ +#define UCTRL_BPE (1 << 0) /* bypass mode enable */ +#define UCTRL_OTD (1 << 0) /* OTG TLL Disable */ +#define UCTRL_OOCS (1 << 0) /* OTG OverCurrent State */ + +/* OTG_MIRROR */ +#define OTGM_SESEND (1 << 4) /* B device session end */ +#define OTGM_VBUSVAL (1 << 3) /* Vbus valid */ +#define OTGM_BSESVLD (1 << 2) /* B session Valid */ +#define OTGM_ASESVLD (1 << 1) /* A session Valid */ +#define OTGM_IDIDG (1 << 0) /* OTG ID pin status */ + /* 1=high: Operate as B-device */ + /* 0=low : Operate as A-device */ + +/* USB_PHY_CTRL_FUNC */ +/* PHY control0 Register Bit Masks */ +#define USB_UTMI_PHYCTRL_CONF2 (1 << 26) + +#define USB_UTMI_PHYCTRL_UTMI_ENABLE (1 << 24) +#define USB_UTMI_PHYCTRL_CHGRDETEN (1 << 24) /* Enable Charger Detector */ +#define USB_UTMI_PHYCTRL_CHGRDETON (1 << 23) /* Charger Detector Power On Control */ +#define USB_UTMI_PHYCTRL_OC_POL (1 << 9) /* OTG Polarity of Overcurrent */ +#define USB_UTMI_PHYCTRL_OC_DIS (1 << 8) /* OTG Disable Overcurrent Event */ +#define USB_UH1_OC_DIS (1 << 5) /* UH1 Disable Overcurrent Event */ +#define USB_UH1_OC_POL (1 << 6) /* UH1 Polarity of OC,Low active */ +/* USB_PHY_CTRL_FUNC2*/ +#define USB_UTMI_PHYCTRL2_PLLDIV_MASK 0x3 +#define USB_UTMI_PHYCTRL2_PLLDIV_SHIFT 0 +#define USB_UTMI_PHYCTRL2_HSDEVSEL_MASK 0x3 +#define USB_UTMI_PHYCTRL2_HSDEVSEL_SHIFT 19 + +/* USB_CTRL_1 */ +#define USB_CTRL_UH1_EXT_CLK_EN (1 << 25) +#define USB_CTRL_UH2_EXT_CLK_EN (1 << 26) +#define USB_CTRL_UH2_CLK_FROM_ULPI_PHY (1 << 2) +/* ULPIVIEW register bits */ +#define ULPIVW_OFF (0x170) +#define ULPIVW_WU (1 << 31) /* Wakeup */ +#define ULPIVW_RUN (1 << 30) /* read/write run */ +#define ULPIVW_WRITE (1 << 29) /* 0=read 1=write */ +#define ULPIVW_SS (1 << 27) /* SyncState */ +#define ULPIVW_PORT_MASK 0x07 /* Port field */ +#define ULPIVW_PORT_SHIFT 24 +#define ULPIVW_ADDR_MASK 0xFF /* data address field */ +#define ULPIVW_ADDR_SHIFT 16 +#define ULPIVW_RDATA_MASK 0xFF /* read data field */ +#define ULPIVW_RDATA_SHIFT 8 +#define ULPIVW_WDATA_MASK 0xFF /* write data field */ +#define ULPIVW_WDATA_SHIFT 0 + +/* USB Clock on/off Control Register */ +#define OTG_AHBCLK_OFF (0x1<<17) /* 1: OFF */ +#define H1_AHBCLK_OFF (0x1<<18) /* 1: OFF */ +#endif /* __ASM_ARCH_MXC_USB_PHY_OTHERS_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/sdma.h b/arch/arm/plat-mxc/include/mach/sdma.h new file mode 100644 index 00000000..cee7fe49 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/sdma.h @@ -0,0 +1,66 @@ +#ifndef __MACH_MXC_SDMA_H__ +#define __MACH_MXC_SDMA_H__ + +/** + * struct sdma_script_start_addrs - SDMA script start pointers + * + * start addresses of the different functions in the physical + * address space of the SDMA engine. + */ +struct sdma_script_start_addrs { + s32 ap_2_ap_addr; + s32 ap_2_bp_addr; + s32 ap_2_ap_fixed_addr; + s32 bp_2_ap_addr; + s32 loopback_on_dsp_side_addr; + s32 mcu_interrupt_only_addr; + s32 firi_2_per_addr; + s32 firi_2_mcu_addr; + s32 per_2_firi_addr; + s32 mcu_2_firi_addr; + s32 uart_2_per_addr; + s32 uart_2_mcu_addr; + s32 per_2_app_addr; + s32 mcu_2_app_addr; + s32 per_2_per_addr; + s32 uartsh_2_per_addr; + s32 uartsh_2_mcu_addr; + s32 per_2_shp_addr; + s32 mcu_2_shp_addr; + s32 ata_2_mcu_addr; + s32 mcu_2_ata_addr; + s32 app_2_per_addr; + s32 app_2_mcu_addr; + s32 shp_2_per_addr; + s32 shp_2_mcu_addr; + s32 mshc_2_mcu_addr; + s32 mcu_2_mshc_addr; + s32 spdif_2_mcu_addr; + s32 mcu_2_spdif_addr; + s32 asrc_2_mcu_addr; + s32 ext_mem_2_ipu_addr; + s32 descrambler_addr; + s32 dptc_dvfs_addr; + s32 utra_addr; + s32 ram_code_start_addr; + s32 mcu_2_ssish_addr; + s32 ssish_2_mcu_addr; + s32 hdmi_dma_addr; +}; + +/** + * struct sdma_platform_data - platform specific data for SDMA engine + * + * @sdma_version The version of this SDMA engine + * @cpu_name used to generate the firmware name + * @to_version CPU Tape out version + * @script_addrs SDMA scripts addresses in SDMA ROM + */ +struct sdma_platform_data { + int sdma_version; + char *cpu_name; + int to_version; + struct sdma_script_start_addrs *script_addrs; +}; + +#endif /* __MACH_MXC_SDMA_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/sdram_autogating.h b/arch/arm/plat-mxc/include/mach/sdram_autogating.h new file mode 100755 index 00000000..e102add8 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/sdram_autogating.h @@ -0,0 +1,56 @@ +/* + * Copyright 2009-2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @defgroup DVFS Dynamic Voltage and Frequency Scaling (DVFS) Driver + */ + +/*! + * @file arch-mxc/sdram_autogating.h + * + * @brief This file contains the SDRAM autogating function prototypes + * + * + * @ingroup PM + */ + +#ifndef __ASM_ARCH_SDRAM_AUTOGATING_H__ +#define __ASM_ARCH_SDRAM_AUTOGATING_H__ + +#ifdef __KERNEL__ + +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/workqueue.h> +#include <linux/device.h> + + +#ifdef CONFIG_ARCH_MX5 +extern void start_sdram_autogating(void); +extern void stop_sdram_autogating(void); +extern int sdram_autogating_active(void); +#else +static inline void start_sdram_autogating(void) +{} + +static inline void stop_sdram_autogating(void) +{} + +static inline int sdram_autogating_active(void) +{ + return 0; +} +#endif + +#endif /*__KERNEL__ */ +#endif /* __ASM_ARCH_MXC_DVFS_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/smp.h b/arch/arm/plat-mxc/include/mach/smp.h new file mode 100644 index 00000000..fcc42535 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/smp.h @@ -0,0 +1,18 @@ +/* + * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef FSL_ARCH_SMP_H +#define FSL_ARCH_SMP_H + +#include <asm/hardware/gic.h> + +/* Needed for secondary core boot */ +extern void mx6_secondary_startup(void); + +#endif diff --git a/arch/arm/plat-mxc/include/mach/spi.h b/arch/arm/plat-mxc/include/mach/spi.h new file mode 100644 index 00000000..08be445e --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/spi.h @@ -0,0 +1,27 @@ + +#ifndef __MACH_SPI_H_ +#define __MACH_SPI_H_ + +/* + * struct spi_imx_master - device.platform_data for SPI controller devices. + * @chipselect: Array of chipselects for this master. Numbers >= 0 mean gpio + * pins, numbers < 0 mean internal CSPI chipselects according + * to MXC_SPI_CS(). Normally you want to use gpio based chip + * selects as the CSPI module tries to be intelligent about + * when to assert the chipselect: The CSPI module deasserts the + * chipselect once it runs out of input data. The other problem + * is that it is not possible to mix between high active and low + * active chipselects on one single bus using the internal + * chipselects. Unfortunately Freescale decided to put some + * chipselects on dedicated pins which are not usable as gpios, + * so we have to support the internal chipselects. + * @num_chipselect: ARRAY_SIZE(chipselect) + */ +struct spi_imx_master { + int *chipselect; + int num_chipselect; +}; + +#define MXC_SPI_CS(no) ((no) - 32) + +#endif /* __MACH_SPI_H_*/ diff --git a/arch/arm/plat-mxc/include/mach/ssi.h b/arch/arm/plat-mxc/include/mach/ssi.h new file mode 100644 index 00000000..63f3c280 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/ssi.h @@ -0,0 +1,21 @@ +#ifndef __MACH_SSI_H +#define __MACH_SSI_H + +struct snd_ac97; + +extern unsigned char imx_ssi_fiq_start, imx_ssi_fiq_end; +extern unsigned long imx_ssi_fiq_base, imx_ssi_fiq_tx_buffer, imx_ssi_fiq_rx_buffer; + +struct imx_ssi_platform_data { + unsigned int flags; +#define IMX_SSI_DMA (1 << 0) +#define IMX_SSI_USE_AC97 (1 << 1) +#define IMX_SSI_NET (1 << 2) +#define IMX_SSI_SYN (1 << 3) +#define IMX_SSI_USE_I2S_SLAVE (1 << 4) + void (*ac97_reset) (struct snd_ac97 *ac97); + void (*ac97_warm_reset)(struct snd_ac97 *ac97); +}; + +#endif /* __MACH_SSI_H */ + diff --git a/arch/arm/plat-mxc/include/mach/system.h b/arch/arm/plat-mxc/include/mach/system.h new file mode 100755 index 00000000..649a97ce --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/system.h @@ -0,0 +1,48 @@ +/* + * Copyright (C) 1999 ARM Limited + * Copyright (C) 2000 Deep Blue Solutions Ltd + * Copyright 2004-2012 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __ASM_ARCH_MXC_SYSTEM_H__ +#define __ASM_ARCH_MXC_SYSTEM_H__ + +#include <mach/hardware.h> +#include <mach/common.h> + +#define LDO_MODE_DEFAULT 0 +#define LDO_MODE_BYPASSED 1 +#define LDO_MODE_ENABLED 2 +extern void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode); + +void arch_idle(void); + +void arch_reset(char mode, const char *cmd); + +#ifdef CONFIG_MXC_REBOOT_MFGMODE +void do_switch_mfgmode(void); +void mxc_clear_mfgmode(void); +#else +#define do_switch_mfgmode() do {} while (0) +#define mxc_clear_mfgmode() do {} while (0) +#endif + +#ifdef CONFIG_MXC_REBOOT_ANDROID_CMD +void do_switch_recovery(void); +void do_switch_fastboot(void); +#else +#define do_switch_recovery() do {} while (0) +#define do_switch_fastboot() do {} while (0) +#endif + +#endif /* __ASM_ARCH_MXC_SYSTEM_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/timex.h b/arch/arm/plat-mxc/include/mach/timex.h new file mode 100644 index 00000000..695063bd --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/timex.h @@ -0,0 +1,33 @@ +/* + * Copyright (C) 1999 ARM Limited + * Copyright (C) 2004-2011 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __ASM_ARCH_MXC_TIMEX_H__ +#define __ASM_ARCH_MXC_TIMEX_H__ + +#if defined CONFIG_ARCH_MX1 +#define CLOCK_TICK_RATE 16000000 +#elif defined CONFIG_ARCH_MX2 +#define CLOCK_TICK_RATE 13300000 +#elif defined CONFIG_ARCH_MX3 +#define CLOCK_TICK_RATE 16625000 +#elif defined CONFIG_ARCH_MX25 +#define CLOCK_TICK_RATE 16000000 +#elif defined CONFIG_ARCH_MX5 +#define CLOCK_TICK_RATE 8000000 +#elif defined CONFIG_ARCH_MX6 +#define CLOCK_TICK_RATE 8000000 +#endif + +#endif /* __ASM_ARCH_MXC_TIMEX_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/ulpi.h b/arch/arm/plat-mxc/include/mach/ulpi.h new file mode 100644 index 00000000..f9161c96 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/ulpi.h @@ -0,0 +1,16 @@ +#ifndef __MACH_ULPI_H +#define __MACH_ULPI_H + +#ifdef CONFIG_USB_ULPI +struct otg_transceiver *imx_otg_ulpi_create(unsigned int flags); +#else +static inline struct otg_transceiver *imx_otg_ulpi_create(unsigned int flags) +{ + return NULL; +} +#endif + +extern struct otg_io_access_ops mxc_ulpi_access_ops; + +#endif /* __MACH_ULPI_H */ + diff --git a/arch/arm/plat-mxc/include/mach/uncompress.h b/arch/arm/plat-mxc/include/mach/uncompress.h new file mode 100644 index 00000000..92e777e1 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/uncompress.h @@ -0,0 +1,145 @@ +/* + * arch/arm/plat-mxc/include/mach/uncompress.h + * + * Copyright (C) 1999 ARM Limited + * Copyright (C) Shane Nay (shane@minirl.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef __ASM_ARCH_MXC_UNCOMPRESS_H__ +#define __ASM_ARCH_MXC_UNCOMPRESS_H__ + +#define __MXC_BOOT_UNCOMPRESS + +#include <asm/mach-types.h> + +unsigned long uart_base; + +#define UART(x) (*(volatile unsigned long *)(uart_base + (x))) + +#define USR2 0x98 +#define USR2_TXFE (1<<14) +#define TXR 0x40 +#define UCR1 0x80 +#define UCR1_UARTEN 1 + +/* + * The following code assumes the serial port has already been + * initialized by the bootloader. We search for the first enabled + * port in the most probable order. If you didn't setup a port in + * your bootloader then nothing will appear (which might be desired). + * + * This does not append a newline + */ + +static void putc(int ch) +{ + if (!uart_base) + return; + if (!(UART(UCR1) & UCR1_UARTEN)) + return; + + while (!(UART(USR2) & USR2_TXFE)) + barrier(); + + UART(TXR) = ch; +} + +static inline void flush(void) +{ +} + +#define MX1_UART1_BASE_ADDR 0x00206000 +#define MX25_UART1_BASE_ADDR 0x43f90000 +#define MX2X_UART1_BASE_ADDR 0x1000a000 +#define MX3X_UART1_BASE_ADDR 0x43F90000 +#define MX3X_UART2_BASE_ADDR 0x43F94000 +#define MX3X_UART5_BASE_ADDR 0x43FB4000 +#define MX51_UART1_BASE_ADDR 0x73fbc000 +#define MX50_UART1_BASE_ADDR 0x53fbc000 +#define MX53_UART1_BASE_ADDR 0x53fbc000 +#define MX6Q_UART4_BASE_ADDR 0x021f0000 +#define MX6Q_UART2_BASE_ADDR 0x021e8000 +#define MX6Q_UART1_BASE_ADDR 0x02020000 + +static __inline__ void __arch_decomp_setup(unsigned long arch_id) +{ + switch (arch_id) { + case MACH_TYPE_MX1ADS: + case MACH_TYPE_SCB9328: + uart_base = MX1_UART1_BASE_ADDR; + break; + case MACH_TYPE_MX25_3DS: + uart_base = MX25_UART1_BASE_ADDR; + break; + case MACH_TYPE_IMX27LITE: + case MACH_TYPE_MX27_3DS: + case MACH_TYPE_MX27ADS: + case MACH_TYPE_PCM038: + case MACH_TYPE_MX21ADS: + case MACH_TYPE_PCA100: + case MACH_TYPE_MXT_TD60: + case MACH_TYPE_IMX27IPCAM: + uart_base = MX2X_UART1_BASE_ADDR; + break; + case MACH_TYPE_MX31LITE: + case MACH_TYPE_ARMADILLO5X0: + case MACH_TYPE_MX31MOBOARD: + case MACH_TYPE_QONG: + case MACH_TYPE_MX31_3DS: + case MACH_TYPE_PCM037: + case MACH_TYPE_MX31ADS: + case MACH_TYPE_MX35_3DS: + case MACH_TYPE_PCM043: + case MACH_TYPE_LILLY1131: + case MACH_TYPE_VPR200: + uart_base = MX3X_UART1_BASE_ADDR; + break; + case MACH_TYPE_MAGX_ZN5: + uart_base = MX3X_UART2_BASE_ADDR; + break; + case MACH_TYPE_BUG: + uart_base = MX3X_UART5_BASE_ADDR; + break; + case MACH_TYPE_MX51_BABBAGE: + case MACH_TYPE_EUKREA_CPUIMX51SD: + case MACH_TYPE_MX51_3DS: + uart_base = MX51_UART1_BASE_ADDR; + break; + case MACH_TYPE_MX50_RDP: + uart_base = MX50_UART1_BASE_ADDR; + break; + case MACH_TYPE_MX53_EVK: + case MACH_TYPE_MX53_LOCO: + case MACH_TYPE_MX53_SMD: + uart_base = MX53_UART1_BASE_ADDR; + break; + case MACH_TYPE_MX6Q_ARM2: + uart_base = MX6Q_UART4_BASE_ADDR; + break; + case MACH_TYPE_MX6Q_SABRELITE: + uart_base = MX6Q_UART2_BASE_ADDR; + break; + case MACH_TYPE_MX6Q_SABRESD: + uart_base = MX6Q_UART1_BASE_ADDR; + break; + case MACH_TYPE_MX6Q_SABREAUTO: + uart_base = MX6Q_UART4_BASE_ADDR; + break; + default: + break; + } +} + +#define arch_decomp_setup() __arch_decomp_setup(arch_id) +#define arch_decomp_wdog() + +#endif /* __ASM_ARCH_MXC_UNCOMPRESS_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/usb.h b/arch/arm/plat-mxc/include/mach/usb.h new file mode 100644 index 00000000..be273371 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/usb.h @@ -0,0 +1,23 @@ +/* + * Copyright (C) 2008 Darius Augulis <augulis.darius@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __ASM_ARCH_MXC_USB +#define __ASM_ARCH_MXC_USB + +struct imxusb_platform_data { + int (*init)(struct device *); + void (*exit)(struct device *); +}; + +#endif /* __ASM_ARCH_MXC_USB */ diff --git a/arch/arm/plat-mxc/include/mach/viv_gpu.h b/arch/arm/plat-mxc/include/mach/viv_gpu.h new file mode 100644 index 00000000..f3136cec --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/viv_gpu.h @@ -0,0 +1,23 @@ +/* + * Copyright (C) 2011 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#ifndef __MACH_VIV_GPU_H_ +#define __MACH_VIV_GPU_H_ + +struct viv_gpu_platform_data { + resource_size_t reserved_mem_base; + resource_size_t reserved_mem_size; +}; + +#endif /* __MACH_VIV_GPU_H_ */ diff --git a/arch/arm/plat-mxc/include/mach/vmalloc.h b/arch/arm/plat-mxc/include/mach/vmalloc.h new file mode 100644 index 00000000..44ea15a8 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/vmalloc.h @@ -0,0 +1,22 @@ +/* + * Copyright (C) 2000 Russell King. + * Copyright 2004-2011 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __ASM_ARCH_MXC_VMALLOC_H__ +#define __ASM_ARCH_MXC_VMALLOC_H__ + +/* vmalloc ending address */ +#define VMALLOC_END 0xf2000000UL + +#endif /* __ASM_ARCH_MXC_VMALLOC_H__ */ diff --git a/arch/arm/plat-mxc/iomux-v1.c b/arch/arm/plat-mxc/iomux-v1.c new file mode 100644 index 00000000..3238c10d --- /dev/null +++ b/arch/arm/plat-mxc/iomux-v1.c @@ -0,0 +1,220 @@ +/* + * arch/arm/plat-mxc/iomux-v1.c + * + * Copyright (C) 2004 Sascha Hauer, Synertronixx GmbH + * Copyright (C) 2009 Uwe Kleine-Koenig, Pengutronix + * + * Common code for i.MX1, i.MX21 and i.MX27 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#include <linux/errno.h> +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/string.h> +#include <linux/gpio.h> + +#include <mach/hardware.h> +#include <asm/mach/map.h> +#include <mach/iomux-v1.h> + +static void __iomem *imx_iomuxv1_baseaddr; +static unsigned imx_iomuxv1_numports; + +static inline unsigned long imx_iomuxv1_readl(unsigned offset) +{ + return __raw_readl(imx_iomuxv1_baseaddr + offset); +} + +static inline void imx_iomuxv1_writel(unsigned long val, unsigned offset) +{ + __raw_writel(val, imx_iomuxv1_baseaddr + offset); +} + +static inline void imx_iomuxv1_rmwl(unsigned offset, + unsigned long mask, unsigned long value) +{ + unsigned long reg = imx_iomuxv1_readl(offset); + + reg &= ~mask; + reg |= value; + + imx_iomuxv1_writel(reg, offset); +} + +static inline void imx_iomuxv1_set_puen( + unsigned int port, unsigned int pin, int on) +{ + unsigned long mask = 1 << pin; + + imx_iomuxv1_rmwl(MXC_PUEN(port), mask, on ? mask : 0); +} + +static inline void imx_iomuxv1_set_ddir( + unsigned int port, unsigned int pin, int out) +{ + unsigned long mask = 1 << pin; + + imx_iomuxv1_rmwl(MXC_DDIR(port), mask, out ? mask : 0); +} + +static inline void imx_iomuxv1_set_gpr( + unsigned int port, unsigned int pin, int af) +{ + unsigned long mask = 1 << pin; + + imx_iomuxv1_rmwl(MXC_GPR(port), mask, af ? mask : 0); +} + +static inline void imx_iomuxv1_set_gius( + unsigned int port, unsigned int pin, int inuse) +{ + unsigned long mask = 1 << pin; + + imx_iomuxv1_rmwl(MXC_GIUS(port), mask, inuse ? mask : 0); +} + +static inline void imx_iomuxv1_set_ocr( + unsigned int port, unsigned int pin, unsigned int ocr) +{ + unsigned long shift = (pin & 0xf) << 1; + unsigned long mask = 3 << shift; + unsigned long value = ocr << shift; + unsigned long offset = pin < 16 ? MXC_OCR1(port) : MXC_OCR2(port); + + imx_iomuxv1_rmwl(offset, mask, value); +} + +static inline void imx_iomuxv1_set_iconfa( + unsigned int port, unsigned int pin, unsigned int aout) +{ + unsigned long shift = (pin & 0xf) << 1; + unsigned long mask = 3 << shift; + unsigned long value = aout << shift; + unsigned long offset = pin < 16 ? MXC_ICONFA1(port) : MXC_ICONFA2(port); + + imx_iomuxv1_rmwl(offset, mask, value); +} + +static inline void imx_iomuxv1_set_iconfb( + unsigned int port, unsigned int pin, unsigned int bout) +{ + unsigned long shift = (pin & 0xf) << 1; + unsigned long mask = 3 << shift; + unsigned long value = bout << shift; + unsigned long offset = pin < 16 ? MXC_ICONFB1(port) : MXC_ICONFB2(port); + + imx_iomuxv1_rmwl(offset, mask, value); +} + +int mxc_gpio_mode(int gpio_mode) +{ + unsigned int pin = gpio_mode & GPIO_PIN_MASK; + unsigned int port = (gpio_mode & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + unsigned int ocr = (gpio_mode & GPIO_OCR_MASK) >> GPIO_OCR_SHIFT; + unsigned int aout = (gpio_mode >> GPIO_AOUT_SHIFT) & 3; + unsigned int bout = (gpio_mode >> GPIO_BOUT_SHIFT) & 3; + + if (port >= imx_iomuxv1_numports) + return -EINVAL; + + /* Pullup enable */ + imx_iomuxv1_set_puen(port, pin, gpio_mode & GPIO_PUEN); + + /* Data direction */ + imx_iomuxv1_set_ddir(port, pin, gpio_mode & GPIO_OUT); + + /* Primary / alternate function */ + imx_iomuxv1_set_gpr(port, pin, gpio_mode & GPIO_AF); + + /* use as gpio? */ + imx_iomuxv1_set_gius(port, pin, !(gpio_mode & (GPIO_PF | GPIO_AF))); + + imx_iomuxv1_set_ocr(port, pin, ocr); + + imx_iomuxv1_set_iconfa(port, pin, aout); + + imx_iomuxv1_set_iconfb(port, pin, bout); + + return 0; +} +EXPORT_SYMBOL(mxc_gpio_mode); + +static int imx_iomuxv1_setup_multiple(const int *list, unsigned count) +{ + size_t i; + int ret; + + for (i = 0; i < count; ++i) { + ret = mxc_gpio_mode(list[i]); + + if (ret) + return ret; + } + + return ret; +} + +int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count, + const char *label) +{ + size_t i; + int ret; + + for (i = 0; i < count; ++i) { + unsigned gpio = pin_list[i] & (GPIO_PIN_MASK | GPIO_PORT_MASK); + + ret = gpio_request(gpio, label); + if (ret) + goto err_gpio_request; + } + + ret = imx_iomuxv1_setup_multiple(pin_list, count); + if (ret) + goto err_setup; + + return 0; + +err_setup: + BUG_ON(i != count); + +err_gpio_request: + mxc_gpio_release_multiple_pins(pin_list, i); + + return ret; +} +EXPORT_SYMBOL(mxc_gpio_setup_multiple_pins); + +void mxc_gpio_release_multiple_pins(const int *pin_list, int count) +{ + size_t i; + + for (i = 0; i < count; ++i) { + unsigned gpio = pin_list[i] & (GPIO_PIN_MASK | GPIO_PORT_MASK); + + gpio_free(gpio); + } +} +EXPORT_SYMBOL(mxc_gpio_release_multiple_pins); + +int __init imx_iomuxv1_init(void __iomem *base, int numports) +{ + imx_iomuxv1_baseaddr = base; + imx_iomuxv1_numports = numports; + + return 0; +} diff --git a/arch/arm/plat-mxc/iomux-v3.c b/arch/arm/plat-mxc/iomux-v3.c new file mode 100644 index 00000000..b88208c1 --- /dev/null +++ b/arch/arm/plat-mxc/iomux-v3.c @@ -0,0 +1,148 @@ +/* + * Copyright 2004-2012 Freescale Semiconductor, Inc. + * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> + * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH, + * <armlinux@phytec.de> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ +#include <linux/errno.h> +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/string.h> +#include <linux/gpio.h> + +#include <mach/hardware.h> +#include <asm/mach/map.h> +#include <mach/iomux-v3.h> + +static void __iomem *base; + +/* + * configures a single pad in the iomuxer + */ +int mxc_iomux_v3_setup_pad(iomux_v3_cfg_t pad) +{ + u32 mux_ctrl_ofs = (pad & MUX_CTRL_OFS_MASK) >> MUX_CTRL_OFS_SHIFT; + u32 mux_mode = (pad & MUX_MODE_MASK) >> MUX_MODE_SHIFT; + u32 sel_input_ofs = (pad & MUX_SEL_INPUT_OFS_MASK) >> MUX_SEL_INPUT_OFS_SHIFT; + u32 sel_input = (pad & MUX_SEL_INPUT_MASK) >> MUX_SEL_INPUT_SHIFT; + u32 pad_ctrl_ofs = (pad & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT; + u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT; + + if (mux_ctrl_ofs) + __raw_writel(mux_mode, base + mux_ctrl_ofs); + + if (sel_input_ofs) + __raw_writel(sel_input, base + sel_input_ofs); + + if (!(pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs) + __raw_writel(pad_ctrl, base + pad_ctrl_ofs); + + return 0; +} +EXPORT_SYMBOL(mxc_iomux_v3_setup_pad); + +/* + * Read a single pad in the iomuxer + */ +int mxc_iomux_v3_get_pad(iomux_v3_cfg_t *pad) +{ + u32 mux_ctrl_ofs = (*pad & MUX_CTRL_OFS_MASK) >> MUX_CTRL_OFS_SHIFT; + u32 pad_ctrl_ofs = (*pad & MUX_PAD_CTRL_OFS_MASK) + >> MUX_PAD_CTRL_OFS_SHIFT; + u32 sel_input_ofs = (*pad & MUX_SEL_INPUT_OFS_MASK) + >> MUX_SEL_INPUT_OFS_SHIFT; + u32 mux_mode = 0; + u32 sel_input = 0; + u32 pad_ctrl = 0; + iomux_v3_cfg_t pad_info = 0; + + mux_mode = __raw_readl(base + mux_ctrl_ofs) & 0xFF; + pad_ctrl = __raw_readl(base + pad_ctrl_ofs) & 0x1FFFF; + sel_input = __raw_readl(base + sel_input_ofs) & 0x7; + + pad_info = (((iomux_v3_cfg_t)mux_mode << MUX_MODE_SHIFT) | \ + ((iomux_v3_cfg_t)pad_ctrl << MUX_PAD_CTRL_SHIFT) | \ + ((iomux_v3_cfg_t)sel_input << MUX_SEL_INPUT_SHIFT)); + + *pad &= ~(MUX_MODE_MASK | MUX_PAD_CTRL_MASK | MUX_SEL_INPUT_MASK); + *pad |= pad_info; + + return 0; +} + + +int mxc_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count) +{ + iomux_v3_cfg_t *p = pad_list; + int i; + int ret; + + for (i = 0; i < count; i++) { + ret = mxc_iomux_v3_setup_pad(*p); + if (ret) + return ret; + p++; + } + return 0; +} +EXPORT_SYMBOL(mxc_iomux_v3_setup_multiple_pads); + +/* + * Read multiple pads in the iomuxer + */ +int mxc_iomux_v3_get_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count) +{ + iomux_v3_cfg_t *p = pad_list; + int i; + + for (i = 0; i < count; i++) { + mxc_iomux_v3_get_pad(p); + p++; + } + return 0; +} +EXPORT_SYMBOL(mxc_iomux_v3_get_multiple_pads); + +void mxc_iomux_set_gpr_register(int group, int start_bit, int num_bits, int value) +{ + int i = 0; + u32 reg; + reg = __raw_readl(base + group * 4); + while (num_bits) { + reg &= ~(1<<(start_bit + i)); + i++; + num_bits--; + } + reg |= (value << start_bit); + __raw_writel(reg, base + group * 4); +} +EXPORT_SYMBOL(mxc_iomux_set_gpr_register); +void mxc_iomux_set_specialbits_register(u32 pad_addr, u32 value, u32 mask) +{ + u32 reg; + reg = __raw_readl(base + pad_addr); + reg &= ~mask; + reg |= value; + __raw_writel(reg, base + pad_addr); +} +EXPORT_SYMBOL(mxc_iomux_set_specialbits_register); + +void mxc_iomux_v3_init(void __iomem *iomux_v3_base) +{ + base = iomux_v3_base; +} diff --git a/arch/arm/plat-mxc/iram_alloc.c b/arch/arm/plat-mxc/iram_alloc.c new file mode 100644 index 00000000..074c3869 --- /dev/null +++ b/arch/arm/plat-mxc/iram_alloc.c @@ -0,0 +1,73 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#include <linux/kernel.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/spinlock.h> +#include <linux/genalloc.h> +#include <mach/iram.h> + +static unsigned long iram_phys_base; +static void __iomem *iram_virt_base; +static struct gen_pool *iram_pool; + +static inline void __iomem *iram_phys_to_virt(unsigned long p) +{ + return iram_virt_base + (p - iram_phys_base); +} + +void __iomem *iram_alloc(unsigned int size, unsigned long *dma_addr) +{ + if (!iram_pool) + return NULL; + + *dma_addr = gen_pool_alloc(iram_pool, size); + pr_debug("iram alloc - %dB@0x%lX\n", size, *dma_addr); + if (!*dma_addr) + return NULL; + return iram_phys_to_virt(*dma_addr); +} +EXPORT_SYMBOL(iram_alloc); + +void iram_free(unsigned long addr, unsigned int size) +{ + if (!iram_pool) + return; + + gen_pool_free(iram_pool, addr, size); +} +EXPORT_SYMBOL(iram_free); + +int __init iram_init(unsigned long base, unsigned long size) +{ + iram_phys_base = base; + + iram_pool = gen_pool_create(PAGE_SHIFT, -1); + if (!iram_pool) + return -ENOMEM; + + gen_pool_add(iram_pool, base, size, -1); + iram_virt_base = ioremap(iram_phys_base, size); + if (!iram_virt_base) + return -EIO; + + pr_debug("i.MX IRAM pool: %ld KB@0x%p\n", size / 1024, iram_virt_base); + return 0; +} diff --git a/arch/arm/plat-mxc/irq-common.c b/arch/arm/plat-mxc/irq-common.c new file mode 100644 index 00000000..e1c6eff7 --- /dev/null +++ b/arch/arm/plat-mxc/irq-common.c @@ -0,0 +1,60 @@ +/* + * Copyright (C) BitBox Ltd 2010 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#include <linux/module.h> +#include <linux/irq.h> + +#include "irq-common.h" + +int imx_irq_set_priority(unsigned char irq, unsigned char prio) +{ + struct mxc_irq_chip *chip; + struct irq_chip *base; + int ret; + + ret = -ENOSYS; + + base = irq_get_chip(irq); + if (base) { + chip = container_of(base, struct mxc_irq_chip, base); + if (chip->set_priority) + ret = chip->set_priority(irq, prio); + } + + return ret; +} +EXPORT_SYMBOL(imx_irq_set_priority); + +int mxc_set_irq_fiq(unsigned int irq, unsigned int type) +{ + struct mxc_irq_chip *chip; + struct irq_chip *base; + int ret; + + ret = -ENOSYS; + + base = irq_get_chip(irq); + if (base) { + chip = container_of(base, struct mxc_irq_chip, base); + if (chip->set_irq_fiq) + ret = chip->set_irq_fiq(irq, type); + } + + return ret; +} +EXPORT_SYMBOL(mxc_set_irq_fiq); diff --git a/arch/arm/plat-mxc/irq-common.h b/arch/arm/plat-mxc/irq-common.h new file mode 100644 index 00000000..7203543f --- /dev/null +++ b/arch/arm/plat-mxc/irq-common.h @@ -0,0 +1,29 @@ +/* + * Copyright (C) BitBox Ltd 2010 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#ifndef __PLAT_MXC_IRQ_COMMON_H__ +#define __PLAT_MXC_IRQ_COMMON_H__ + +struct mxc_irq_chip +{ + struct irq_chip base; + int (*set_priority)(unsigned char irq, unsigned char prio); + int (*set_irq_fiq)(unsigned int irq, unsigned int type); +}; + +#endif diff --git a/arch/arm/plat-mxc/isp1504xc.c b/arch/arm/plat-mxc/isp1504xc.c new file mode 100755 index 00000000..8fd7bf2d --- /dev/null +++ b/arch/arm/plat-mxc/isp1504xc.c @@ -0,0 +1,275 @@ +/* + * Copyright (C) 2005-2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/platform_device.h> +#include <linux/fsl_devices.h> +#include <linux/delay.h> +#include <linux/usb/fsl_xcvr.h> + +#include <mach/hardware.h> +#include <mach/arc_otg.h> +#include <asm/mach-types.h> + +/* ISP 1504 register addresses */ +#define ISP1504_VID_LOW 0x00 /* Vendor ID low */ +#define ISP1504_VID_HIGH 0x01 /* Vendor ID high */ +#define ISP1504_PID_LOW 0x02 /* Product ID low */ +#define ISP1504_PID_HIGH 0x03 /* Product ID high */ +#define ISP1504_FUNC 0x04 /* Function Control */ +#define ISP1504_ITFCTL 0x07 /* Interface Control */ +#define ISP1504_OTGCTL 0x0A /* OTG Control */ + +/* add to above register address to access Set/Clear functions */ +#define ISP1504_REG_SET 0x01 +#define ISP1504_REG_CLEAR 0x02 + +/* 1504 OTG Control Register bits */ +#define USE_EXT_VBUS_IND (1 << 7) /* Use ext. Vbus indicator */ +#define DRV_VBUS_EXT (1 << 6) /* Drive Vbus external */ +#define DRV_VBUS (1 << 5) /* Drive Vbus */ +#define CHRG_VBUS (1 << 4) /* Charge Vbus */ +#define DISCHRG_VBUS (1 << 3) /* Discharge Vbus */ +#define DM_PULL_DOWN (1 << 2) /* enable DM Pull Down */ +#define DP_PULL_DOWN (1 << 1) /* enable DP Pull Down */ +#define ID_PULL_UP (1 << 0) /* enable ID Pull Up */ + +/* 1504 OTG Function Control Register bits */ +#define SUSPENDM (1 << 6) /* places the PHY into + low-power mode */ +#define DRV_RESET (1 << 5) /* Active HIGH transceiver + reset */ + +/*! + * read ULPI register 'reg' thru VIEWPORT register 'view' + * + * @param reg register to read + * @param view the ULPI VIEWPORT register address + * @return return isp1504 register value + */ +static u8 isp1504_read(int reg, volatile u32 *view) +{ + u32 data; + + /* make sure interface is running */ + if (!(__raw_readl(view) && ULPIVW_SS)) { + __raw_writel(ULPIVW_WU, view); + do { /* wait for wakeup */ + data = __raw_readl(view); + } while (data & ULPIVW_WU); + } + + /* read the register */ + __raw_writel((ULPIVW_RUN | (reg << ULPIVW_ADDR_SHIFT)), view); + + do { /* wait for completion */ + data = __raw_readl(view); + } while (data & ULPIVW_RUN); + + return (u8) (data >> ULPIVW_RDATA_SHIFT) & ULPIVW_RDATA_MASK; +} + +/*! + * set bits into OTG ISP1504 register 'reg' thru VIEWPORT register 'view' + * + * @param bits set value + * @param reg which register + * @param view the ULPI VIEWPORT register address + */ +static void isp1504_set(u8 bits, int reg, volatile u32 *view) +{ + u32 data; + + /* make sure interface is running */ + if (!(__raw_readl(view) && ULPIVW_SS)) { + __raw_writel(ULPIVW_WU, view); + do { /* wait for wakeup */ + data = __raw_readl(view); + } while (data & ULPIVW_WU); + } + + __raw_writel((ULPIVW_RUN | ULPIVW_WRITE | + ((reg + ISP1504_REG_SET) << ULPIVW_ADDR_SHIFT) | + ((bits & ULPIVW_WDATA_MASK) << ULPIVW_WDATA_SHIFT)), + view); + + while (__raw_readl(view) & ULPIVW_RUN) /* wait for completion */ + continue; +} + +/*! + * clear bits in OTG ISP1504 register 'reg' thru VIEWPORT register 'view' + * + * @param bits bits to clear + * @param reg in this register + * @param view the ULPI VIEWPORT register address + */ +static void isp1504_clear(u8 bits, int reg, volatile u32 *view) +{ + __raw_writel((ULPIVW_RUN | ULPIVW_WRITE | + ((reg + ISP1504_REG_CLEAR) << ULPIVW_ADDR_SHIFT) | + ((bits & ULPIVW_WDATA_MASK) << ULPIVW_WDATA_SHIFT)), + view); + + while (__raw_readl(view) & ULPIVW_RUN) /* wait for completion */ + continue; +} + + +static void isp1508_fix(u32 *view) +{ + /* Set bits IND_PASS_THRU and IND_COMPL */ + isp1504_set(0x60, ISP1504_ITFCTL, view); + + /* Set bit USE_EXT_VBUS_IND */ + isp1504_set(USE_EXT_VBUS_IND, ISP1504_OTGCTL, view); +} + +/*! + * set vbus power + * + * @param view viewport register + * @param on power on or off + */ +static void isp1504_set_vbus_power(struct fsl_xcvr_ops *this, + struct fsl_usb2_platform_data *pdata, int on) +{ + u32 *view = pdata->regs + ULPIVW_OFF; + + pr_debug("real %s(on=%d) view=0x%p\n", __FUNCTION__, on, view); + + pr_debug("ULPI Vendor ID 0x%x Product ID 0x%x\n", + (isp1504_read(ISP1504_VID_HIGH, view) << 8) | + isp1504_read(ISP1504_VID_LOW, view), + (isp1504_read(ISP1504_PID_HIGH, view) << 8) | + isp1504_read(ISP1504_PID_LOW, view)); + + pr_debug("OTG Control before=0x%x\n", + isp1504_read(ISP1504_OTGCTL, view)); + + if (on) { + isp1504_set(DRV_VBUS_EXT | /* enable external Vbus */ + DRV_VBUS | /* enable internal Vbus */ + USE_EXT_VBUS_IND | /* use external indicator */ + CHRG_VBUS, /* charge Vbus */ + ISP1504_OTGCTL, view); + + } else { + isp1508_fix(view); + + isp1504_clear(DRV_VBUS_EXT | /* disable external Vbus */ + DRV_VBUS, /* disable internal Vbus */ + ISP1504_OTGCTL, view); + + isp1504_set(USE_EXT_VBUS_IND | /* use external indicator */ + DISCHRG_VBUS, /* discharge Vbus */ + ISP1504_OTGCTL, view); + } + + pr_debug("OTG Control after = 0x%x\n", + isp1504_read(ISP1504_OTGCTL, view)); +} + +/*! + * set remote wakeup + * + * @param view viewport register + */ +static void isp1504_set_remote_wakeup(u32 *view) +{ + __raw_writel(~ULPIVW_WRITE & __raw_readl(view), view); + __raw_writel((1 << ULPIVW_PORT_SHIFT) | __raw_readl(view), view); + __raw_writel(ULPIVW_RUN | __raw_readl(view), view); + + while (__raw_readl(view) & ULPIVW_RUN) /* wait for completion */ + continue; +} + +static void isp1504_init(struct fsl_xcvr_ops *this) +{ + pr_debug("%s:\n", __FUNCTION__); +} + +static void isp1504_uninit(struct fsl_xcvr_ops *this) +{ + pr_debug("%s:\n", __FUNCTION__); +} + +static void isp1504_suspend(struct fsl_xcvr_ops *this) +{ + pr_debug("%s\n", __func__); + + /* send suspend command */ + isp1504_clear(SUSPENDM, ISP1504_FUNC, &UOG_ULPIVIEW); + pr_debug("%s.\n", __func__); +} + +/*! + * Set the 1504 transceiver to the proper mode for testing purposes. + * + * @param view the ULPI VIEWPORT register address + * @param test_mode Set the 1504 transceiver to disable bit stuffing and NRZI + */ + static void isp1504_set_test_mode(u32 *view, enum usb_test_mode test_mode) +{ + if (test_mode == USB_TEST_J || test_mode == USB_TEST_K) { + printk(KERN_INFO "udc: disable bit stuffing and NRZI\n"); + /* Disable bit-stuffing and NRZI encoding. */ + isp1504_set(0x10, 0x04, view); + } +} + +static struct fsl_xcvr_ops isp1504_ops = { + .name = "isp1504", + .xcvr_type = PORTSC_PTS_ULPI, + .init = isp1504_init, + .uninit = isp1504_uninit, + .suspend = isp1504_suspend, + .set_vbus_power = isp1504_set_vbus_power, + .set_remote_wakeup = isp1504_set_remote_wakeup, + .set_test_mode = isp1504_set_test_mode, +}; + +extern void fsl_usb_xcvr_register(struct fsl_xcvr_ops *xcvr_ops); +extern int fsl_usb_xcvr_suspend(struct fsl_xcvr_ops *xcvr_ops); + +static int __init isp1504xc_init(void) +{ + pr_debug("%s\n", __FUNCTION__); + + fsl_usb_xcvr_register(&isp1504_ops); + + /* suspend isp1504 */ + if (fsl_usb_xcvr_suspend(&isp1504_ops)) + pr_debug("%s: failed to suspend isp1504\n", __func__); + + return 0; +} + +extern void fsl_usb_xcvr_unregister(struct fsl_xcvr_ops *xcvr_ops); + +static void __exit isp1504xc_exit(void) +{ + fsl_usb_xcvr_unregister(&isp1504_ops); +} + +subsys_initcall(isp1504xc_init); +module_exit(isp1504xc_exit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("isp1504 xcvr driver"); +MODULE_LICENSE("GPL"); diff --git a/arch/arm/plat-mxc/pwm.c b/arch/arm/plat-mxc/pwm.c new file mode 100755 index 00000000..eb490571 --- /dev/null +++ b/arch/arm/plat-mxc/pwm.c @@ -0,0 +1,343 @@ +/* + * simple driver for PWM (Pulse Width Modulator) controller + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Derived from pxa PWM driver by eric miao <eric.miao@marvell.com> + * Copyright 2009-2013 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/platform_device.h> +#include <linux/slab.h> +#include <linux/err.h> +#include <linux/clk.h> +#include <linux/io.h> +#include <linux/pwm.h> +#include <linux/fsl_devices.h> +#include <mach/hardware.h> + + +/* i.MX1 and i.MX21 share the same PWM function block: */ + +#define MX1_PWMC 0x00 /* PWM Control Register */ +#define MX1_PWMS 0x04 /* PWM Sample Register */ +#define MX1_PWMP 0x08 /* PWM Period Register */ + + +/* i.MX27, i.MX31, i.MX35 share the same PWM function block: */ + +#define MX3_PWMCR 0x00 /* PWM Control Register */ +#define MX3_PWMSAR 0x0C /* PWM Sample Register */ +#define MX3_PWMPR 0x10 /* PWM Period Register */ +#define MX3_PWMCR_PRESCALER(x) (((x - 1) & 0xFFF) << 4) +#define MX3_PWMCR_DOZEEN (1 << 24) +#define MX3_PWMCR_WAITEN (1 << 23) +#define MX3_PWMCR_DBGEN (1 << 22) +#define MX3_PWMCR_CLKSRC_IPG_HIGH (2 << 16) +#define MX3_PWMCR_CLKSRC_IPG (1 << 16) +#define MX3_PWMCR_SWR (1 << 3) +#define MX3_PWMCR_EN (1 << 0) + +#define MX3_PWMCR_STOPEN (1 << 25) +#define MX3_PWMCR_DOZEEN (1 << 24) +#define MX3_PWMCR_WAITEN (1 << 23) +#define MX3_PWMCR_DBGEN (1 << 22) +#define MX3_PWMCR_CLKSRC_IPG (1 << 16) +#define MX3_PWMCR_CLKSRC_IPG_32k (3 << 16) + +struct pwm_device { + struct list_head node; + struct platform_device *pdev; + + const char *label; + struct clk *clk; + + int clk_enabled; + void __iomem *mmio_base; + + unsigned int use_count; + unsigned int pwm_id; + int pwmo_invert; + void (*enable_pwm_pad)(void); + void (*disable_pwm_pad)(void); +}; + +int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) +{ + if (pwm == NULL || period_ns == 0 || duty_ns > period_ns) + return -EINVAL; + + if (!(cpu_is_mx1() || cpu_is_mx21())) { + unsigned long long c; + unsigned long period_cycles, duty_cycles, prescale; + u32 cr; + + if (pwm->pwmo_invert) + duty_ns = period_ns - duty_ns; + + c = clk_get_rate(pwm->clk); + c = c * period_ns; + do_div(c, 1000000000); + period_cycles = c; + + prescale = period_cycles / 0x10000 + 1; + + period_cycles /= prescale; + c = (unsigned long long)period_cycles * duty_ns; + do_div(c, period_ns); + duty_cycles = c; + + /* + * according to imx pwm RM, the real period value should be + * PERIOD value in PWMPR plus 2. + */ + if (period_cycles > 2) + period_cycles -= 2; + else + period_cycles = 0; + + writel(duty_cycles, pwm->mmio_base + MX3_PWMSAR); + writel(period_cycles, pwm->mmio_base + MX3_PWMPR); + + cr = MX3_PWMCR_PRESCALER(prescale) | + MX3_PWMCR_STOPEN | MX3_PWMCR_DOZEEN | + MX3_PWMCR_WAITEN | MX3_PWMCR_DBGEN; + + if (cpu_is_mx25()) + cr |= MX3_PWMCR_CLKSRC_IPG; + else + cr |= MX3_PWMCR_CLKSRC_IPG_HIGH; + + writel(cr, pwm->mmio_base + MX3_PWMCR); + } else if (cpu_is_mx1() || cpu_is_mx21()) { + /* The PWM subsystem allows for exact frequencies. However, + * I cannot connect a scope on my device to the PWM line and + * thus cannot provide the program the PWM controller + * exactly. Instead, I'm relying on the fact that the + * Bootloader (u-boot or WinCE+haret) has programmed the PWM + * function group already. So I'll just modify the PWM sample + * register to follow the ratio of duty_ns vs. period_ns + * accordingly. + * + * This is good enough for programming the brightness of + * the LCD backlight. + * + * The real implementation would divide PERCLK[0] first by + * both the prescaler (/1 .. /128) and then by CLKSEL + * (/2 .. /16). + */ + u32 max = readl(pwm->mmio_base + MX1_PWMP); + u32 p; + if (pwm->pwmo_invert) + duty_ns = period_ns - duty_ns; + p = max * duty_ns / period_ns; + writel(max - p, pwm->mmio_base + MX1_PWMS); + } else { + BUG(); + } + + return 0; +} +EXPORT_SYMBOL(pwm_config); + +int pwm_enable(struct pwm_device *pwm) +{ + unsigned long reg; + int rc = 0; + + if (!pwm->clk_enabled) { + rc = clk_enable(pwm->clk); + if (!rc) + pwm->clk_enabled = 1; + } + + reg = readl(pwm->mmio_base + MX3_PWMCR); + reg |= MX3_PWMCR_EN; + writel(reg, pwm->mmio_base + MX3_PWMCR); + + if (pwm->enable_pwm_pad) + pwm->enable_pwm_pad(); + + return rc; +} +EXPORT_SYMBOL(pwm_enable); + +void pwm_disable(struct pwm_device *pwm) +{ + if (pwm->disable_pwm_pad) + pwm->disable_pwm_pad(); + + writel(MX3_PWMCR_SWR, pwm->mmio_base + MX3_PWMCR); + while (readl(pwm->mmio_base + MX3_PWMCR) & MX3_PWMCR_SWR) + ; + + if (pwm->clk_enabled) { + clk_disable(pwm->clk); + pwm->clk_enabled = 0; + } +} +EXPORT_SYMBOL(pwm_disable); + +static DEFINE_MUTEX(pwm_lock); +static LIST_HEAD(pwm_list); + +struct pwm_device *pwm_request(int pwm_id, const char *label) +{ + struct pwm_device *pwm; + int found = 0; + + mutex_lock(&pwm_lock); + + list_for_each_entry(pwm, &pwm_list, node) { + if (pwm->pwm_id == pwm_id) { + found = 1; + break; + } + } + + if (found) { + if (pwm->use_count == 0) { + pwm->use_count++; + pwm->label = label; + } else + pwm = ERR_PTR(-EBUSY); + } else + pwm = ERR_PTR(-ENOENT); + + mutex_unlock(&pwm_lock); + return pwm; +} +EXPORT_SYMBOL(pwm_request); + +void pwm_free(struct pwm_device *pwm) +{ + mutex_lock(&pwm_lock); + + if (pwm->use_count) { + pwm->use_count--; + pwm->label = NULL; + } else + pr_warning("PWM device already freed\n"); + + mutex_unlock(&pwm_lock); +} +EXPORT_SYMBOL(pwm_free); + +static int __devinit mxc_pwm_probe(struct platform_device *pdev) +{ + struct pwm_device *pwm; + struct resource *r; + struct mxc_pwm_platform_data *plat_data = pdev->dev.platform_data; + int ret = 0; + + pwm = kzalloc(sizeof(struct pwm_device), GFP_KERNEL); + if (pwm == NULL) { + dev_err(&pdev->dev, "failed to allocate memory\n"); + return -ENOMEM; + } + + pwm->clk = clk_get(&pdev->dev, "pwm"); + + if (IS_ERR(pwm->clk)) { + ret = PTR_ERR(pwm->clk); + goto err_free; + } + + pwm->clk_enabled = 0; + + pwm->use_count = 0; + pwm->pwm_id = pdev->id; + pwm->pdev = pdev; + if (plat_data != NULL) { + pwm->pwmo_invert = plat_data->pwmo_invert; + pwm->enable_pwm_pad = plat_data->enable_pwm_pad; + pwm->disable_pwm_pad = plat_data->disable_pwm_pad; + } + + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (r == NULL) { + dev_err(&pdev->dev, "no memory resource defined\n"); + ret = -ENODEV; + goto err_free_clk; + } + + r = request_mem_region(r->start, r->end - r->start + 1, pdev->name); + if (r == NULL) { + dev_err(&pdev->dev, "failed to request memory resource\n"); + ret = -EBUSY; + goto err_free_clk; + } + + pwm->mmio_base = ioremap(r->start, r->end - r->start + 1); + if (pwm->mmio_base == NULL) { + dev_err(&pdev->dev, "failed to ioremap() registers\n"); + ret = -ENODEV; + goto err_free_mem; + } + + mutex_lock(&pwm_lock); + list_add_tail(&pwm->node, &pwm_list); + mutex_unlock(&pwm_lock); + + platform_set_drvdata(pdev, pwm); + return 0; + +err_free_mem: + release_mem_region(r->start, r->end - r->start + 1); +err_free_clk: + clk_put(pwm->clk); +err_free: + kfree(pwm); + return ret; +} + +static int __devexit mxc_pwm_remove(struct platform_device *pdev) +{ + struct pwm_device *pwm; + struct resource *r; + + pwm = platform_get_drvdata(pdev); + if (pwm == NULL) + return -ENODEV; + + mutex_lock(&pwm_lock); + list_del(&pwm->node); + mutex_unlock(&pwm_lock); + + iounmap(pwm->mmio_base); + + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); + release_mem_region(r->start, r->end - r->start + 1); + + clk_put(pwm->clk); + + kfree(pwm); + return 0; +} + +static struct platform_driver mxc_pwm_driver = { + .driver = { + .name = "mxc_pwm", + }, + .probe = mxc_pwm_probe, + .remove = __devexit_p(mxc_pwm_remove), +}; + +static int __init mxc_pwm_init(void) +{ + return platform_driver_register(&mxc_pwm_driver); +} +arch_initcall(mxc_pwm_init); + +static void __exit mxc_pwm_exit(void) +{ + platform_driver_unregister(&mxc_pwm_driver); +} +module_exit(mxc_pwm_exit); + +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>"); diff --git a/arch/arm/plat-mxc/serialxc.c b/arch/arm/plat-mxc/serialxc.c new file mode 100755 index 00000000..a3eeef96 --- /dev/null +++ b/arch/arm/plat-mxc/serialxc.c @@ -0,0 +1,64 @@ +/* + * Copyright (C) 2005-2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/errno.h> +#include <linux/init.h> +#include <linux/err.h> +#include <linux/platform_device.h> +#include <linux/usb/fsl_xcvr.h> + +#include <mach/hardware.h> +#include <mach/arc_otg.h> + +static void usb_serial_init(struct fsl_xcvr_ops *this) +{ +} + +static void usb_serial_uninit(struct fsl_xcvr_ops *this) +{ +} + +static struct fsl_xcvr_ops serial_ops = { + .name = "serial", + .xcvr_type = PORTSC_PTS_SERIAL, + .init = usb_serial_init, + .uninit = usb_serial_uninit, +}; + +extern void fsl_usb_xcvr_register(struct fsl_xcvr_ops *xcvr_ops); + +static int __init serialxc_init(void) +{ + pr_debug("%s\n", __FUNCTION__); + + fsl_usb_xcvr_register(&serial_ops); + + return 0; +} + +extern void fsl_usb_xcvr_unregister(struct fsl_xcvr_ops *xcvr_ops); + +static void __exit serialxc_exit(void) +{ + fsl_usb_xcvr_unregister(&serial_ops); +} + +subsys_initcall(serialxc_init); +module_exit(serialxc_exit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("serial xcvr driver"); +MODULE_LICENSE("GPL"); diff --git a/arch/arm/plat-mxc/ssi-fiq-ksym.c b/arch/arm/plat-mxc/ssi-fiq-ksym.c new file mode 100644 index 00000000..b5fad454 --- /dev/null +++ b/arch/arm/plat-mxc/ssi-fiq-ksym.c @@ -0,0 +1,20 @@ +/* + * Exported ksyms for the SSI FIQ handler + * + * Copyright (C) 2009, Sascha Hauer <s.hauer@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/module.h> + +#include <mach/ssi.h> + +EXPORT_SYMBOL(imx_ssi_fiq_tx_buffer); +EXPORT_SYMBOL(imx_ssi_fiq_rx_buffer); +EXPORT_SYMBOL(imx_ssi_fiq_start); +EXPORT_SYMBOL(imx_ssi_fiq_end); +EXPORT_SYMBOL(imx_ssi_fiq_base); + diff --git a/arch/arm/plat-mxc/ssi-fiq.S b/arch/arm/plat-mxc/ssi-fiq.S new file mode 100644 index 00000000..8397a2dd --- /dev/null +++ b/arch/arm/plat-mxc/ssi-fiq.S @@ -0,0 +1,136 @@ +/* + * Copyright (C) 2009 Sascha Hauer <s.hauer@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/linkage.h> +#include <asm/assembler.h> + +/* + * r8 = bit 0-15: tx offset, bit 16-31: tx buffer size + * r9 = bit 0-15: rx offset, bit 16-31: rx buffer size + */ + +#define SSI_STX0 0x00 +#define SSI_SRX0 0x08 +#define SSI_SISR 0x14 +#define SSI_SIER 0x18 +#define SSI_SACNT 0x38 + +#define SSI_SACNT_AC97EN (1 << 0) + +#define SSI_SIER_TFE0_EN (1 << 0) +#define SSI_SISR_TFE0 (1 << 0) +#define SSI_SISR_RFF0 (1 << 2) +#define SSI_SIER_RFF0_EN (1 << 2) + + .text + .global imx_ssi_fiq_start + .global imx_ssi_fiq_end + .global imx_ssi_fiq_base + .global imx_ssi_fiq_rx_buffer + .global imx_ssi_fiq_tx_buffer + +imx_ssi_fiq_start: + ldr r12, imx_ssi_fiq_base + + /* TX */ + ldr r11, imx_ssi_fiq_tx_buffer + + /* shall we send? */ + ldr r13, [r12, #SSI_SIER] + tst r13, #SSI_SIER_TFE0_EN + beq 1f + + /* TX FIFO empty? */ + ldr r13, [r12, #SSI_SISR] + tst r13, #SSI_SISR_TFE0 + beq 1f + + mov r10, #0x10000 + sub r10, #1 + and r10, r10, r8 /* r10: current buffer offset */ + + add r11, r11, r10 + + ldrh r13, [r11] + strh r13, [r12, #SSI_STX0] + + ldrh r13, [r11, #2] + strh r13, [r12, #SSI_STX0] + + ldrh r13, [r11, #4] + strh r13, [r12, #SSI_STX0] + + ldrh r13, [r11, #6] + strh r13, [r12, #SSI_STX0] + + add r10, #8 + lsr r13, r8, #16 /* r13: buffer size */ + cmp r10, r13 + lslgt r8, r13, #16 + addle r8, #8 +1: + /* RX */ + + /* shall we receive? */ + ldr r13, [r12, #SSI_SIER] + tst r13, #SSI_SIER_RFF0_EN + beq 1f + + /* RX FIFO full? */ + ldr r13, [r12, #SSI_SISR] + tst r13, #SSI_SISR_RFF0 + beq 1f + + ldr r11, imx_ssi_fiq_rx_buffer + + mov r10, #0x10000 + sub r10, #1 + and r10, r10, r9 /* r10: current buffer offset */ + + add r11, r11, r10 + + ldr r13, [r12, #SSI_SACNT] + tst r13, #SSI_SACNT_AC97EN + + ldr r13, [r12, #SSI_SRX0] + strh r13, [r11] + + ldr r13, [r12, #SSI_SRX0] + strh r13, [r11, #2] + + /* dummy read to skip slot 12 */ + ldrne r13, [r12, #SSI_SRX0] + + ldr r13, [r12, #SSI_SRX0] + strh r13, [r11, #4] + + ldr r13, [r12, #SSI_SRX0] + strh r13, [r11, #6] + + /* dummy read to skip slot 12 */ + ldrne r13, [r12, #SSI_SRX0] + + add r10, #8 + lsr r13, r9, #16 /* r13: buffer size */ + cmp r10, r13 + lslgt r9, r13, #16 + addle r9, #8 + +1: + @ return from FIQ + subs pc, lr, #4 + + .align +imx_ssi_fiq_base: + .word 0x0 +imx_ssi_fiq_rx_buffer: + .word 0x0 +imx_ssi_fiq_tx_buffer: + .word 0x0 +imx_ssi_fiq_end: + diff --git a/arch/arm/plat-mxc/system.c b/arch/arm/plat-mxc/system.c new file mode 100644 index 00000000..e216f687 --- /dev/null +++ b/arch/arm/plat-mxc/system.c @@ -0,0 +1,118 @@ +/* + * Copyright (C) 1999 ARM Limited + * Copyright (C) 2000 Deep Blue Solutions Ltd + * Copyright 2006-2012 Freescale Semiconductor, Inc. + * Copyright 2008 Juergen Beisert, kernel@pengutronix.de + * Copyright 2009 Ilya Yanok, Emcraft Systems Ltd, yanok@emcraft.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/kernel.h> +#include <linux/clk.h> +#include <linux/io.h> +#include <linux/err.h> +#include <linux/delay.h> +#include <linux/string.h> +#include <mach/hardware.h> +#include <mach/common.h> +#include <mach/system.h> +#include <asm/proc-fns.h> +#include <asm/system.h> +#ifdef CONFIG_SMP +#include <linux/smp.h> +#endif +#include <asm/mach-types.h> + +static void __iomem *wdog_base; +extern u32 enable_ldo_mode; + + +static void arch_reset_special_mode(char mode, const char *cmd) +{ + if (strcmp(cmd, "download") == 0) + do_switch_mfgmode(); + else if (strcmp(cmd, "recovery") == 0) + do_switch_recovery(); + else if (strcmp(cmd, "fastboot") == 0) + do_switch_fastboot(); +} + +/* + * Reset the system. It is called by machine_restart(). + */ +void arch_reset(char mode, const char *cmd) +{ + unsigned int wcr_enable; + + arch_reset_special_mode(mode, cmd); + +#ifdef CONFIG_ARCH_MX6 + /* wait for reset to assert... */ + if (enable_ldo_mode == LDO_MODE_BYPASSED) { + /*On Sabresd board use WDOG2 to reset external PMIC, so here do + * more WDOG2 reset.*/ + wcr_enable = 0x14; + __raw_writew(wcr_enable, IO_ADDRESS(MX6Q_WDOG2_BASE_ADDR)); + __raw_writew(wcr_enable, IO_ADDRESS(MX6Q_WDOG2_BASE_ADDR)); + } else + wcr_enable = (1 << 2); + __raw_writew(wcr_enable, wdog_base); + /* errata TKT039676, SRS bit may be missed when + SRC sample it, need to write the wdog controller + twice to avoid it */ + __raw_writew(wcr_enable, wdog_base); + + /* wait for reset to assert... */ + mdelay(500); + + printk(KERN_ERR "Watchdog reset failed to assert reset\n"); + + return; +#endif + +#ifdef CONFIG_MACH_MX51_EFIKAMX + if (machine_is_mx51_efikamx()) { + mx51_efikamx_reset(); + return; + } +#endif + + if (cpu_is_mx1()) { + wcr_enable = (1 << 0); + } else { + struct clk *clk; + + clk = clk_get_sys("imx2-wdt.0", NULL); + if (!IS_ERR(clk)) + clk_enable(clk); + wcr_enable = (1 << 2); + } + + /* Assert SRS signal */ + __raw_writew(wcr_enable, wdog_base); + + /* wait for reset to assert... */ + mdelay(500); + + printk(KERN_ERR "Watchdog reset failed to assert reset\n"); + + /* delay to allow the serial port to show the message */ + mdelay(50); + + /* we'll take a jump through zero as a poor second */ + cpu_reset(0); +} + +void mxc_arch_reset_init(void __iomem *base) +{ + wdog_base = base; +} diff --git a/arch/arm/plat-mxc/time.c b/arch/arm/plat-mxc/time.c new file mode 100644 index 00000000..08504b3e --- /dev/null +++ b/arch/arm/plat-mxc/time.c @@ -0,0 +1,343 @@ +/* + * linux/arch/arm/plat-mxc/time.c + * + * Copyright (C) 2000-2001 Deep Blue Solutions + * Copyright (C) 2002 Shane Nay (shane@minirl.com) + * Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com) + * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/clockchips.h> +#include <linux/clk.h> + +#include <mach/hardware.h> +#include <asm/sched_clock.h> +#include <asm/mach/time.h> +#include <mach/common.h> + +/* + * There are 2 versions of the timer hardware on Freescale MXC hardware. + * Version 1: MX1/MXL, MX21, MX27. + * Version 2: MX25, MX31, MX35, MX37, MX51 + */ + +/* defines common for all i.MX */ +#define MXC_TCTL 0x00 +#define MXC_TCTL_TEN (1 << 0) /* Enable module */ +#define MXC_TPRER 0x04 + +/* MX1, MX21, MX27 */ +#define MX1_2_TCTL_CLK_PCLK1 (1 << 1) +#define MX1_2_TCTL_IRQEN (1 << 4) +#define MX1_2_TCTL_FRR (1 << 8) +#define MX1_2_TCMP 0x08 +#define MX1_2_TCN 0x10 +#define MX1_2_TSTAT 0x14 + +/* MX21, MX27 */ +#define MX2_TSTAT_CAPT (1 << 1) +#define MX2_TSTAT_COMP (1 << 0) + +/* MX31, MX35, MX25, MX5 */ +#define V2_TCTL_WAITEN (1 << 3) /* Wait enable mode */ +#define V2_TCTL_CLK_IPG (1 << 6) +#define V2_TCTL_CLK_PER (2 << 6) +#define V2_TCTL_CLK_OSC_DIV8 (5 << 6) +#define V2_TCTL_CLK_OSC (7 << 6) +#define V2_TCTL_FRR (1 << 9) +#define V2_TCTL_ENABLE24M (1 << 10) +#define V2_TPRER_PRE24M_DIV8 7 +#define V2_TPRER_PRE24M_MASK 0xF +#define V2_TPRER_PRE24M_OFFSET 12 +#define V2_IR 0x0c +#define V2_TSTAT 0x08 +#define V2_TSTAT_OF1 (1 << 0) +#define V2_TCN 0x24 +#define V2_TCMP 0x10 + +#define timer_is_v1() (cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27()) +#define timer_is_v2() (!timer_is_v1()) + +static struct clock_event_device clockevent_mxc; +static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED; + +static void __iomem *timer_base; + +static inline void gpt_irq_disable(void) +{ + unsigned int tmp; + + if (timer_is_v2()) + __raw_writel(0, timer_base + V2_IR); + else { + tmp = __raw_readl(timer_base + MXC_TCTL); + __raw_writel(tmp & ~MX1_2_TCTL_IRQEN, timer_base + MXC_TCTL); + } +} + +static inline void gpt_irq_enable(void) +{ + if (timer_is_v2()) + __raw_writel(1<<0, timer_base + V2_IR); + else { + __raw_writel(__raw_readl(timer_base + MXC_TCTL) | MX1_2_TCTL_IRQEN, + timer_base + MXC_TCTL); + } +} + +static void gpt_irq_acknowledge(void) +{ + if (timer_is_v1()) { + if (cpu_is_mx1()) + __raw_writel(0, timer_base + MX1_2_TSTAT); + else + __raw_writel(MX2_TSTAT_CAPT | MX2_TSTAT_COMP, + timer_base + MX1_2_TSTAT); + } else if (timer_is_v2()) + __raw_writel(V2_TSTAT_OF1, timer_base + V2_TSTAT); +} + +static void __iomem *sched_clock_reg; + +static DEFINE_CLOCK_DATA(cd); +unsigned long long notrace sched_clock(void) +{ + cycle_t cyc = sched_clock_reg ? __raw_readl(sched_clock_reg) : 0; + + return cyc_to_sched_clock(&cd, cyc, (u32)~0); +} + +static void notrace mxc_update_sched_clock(void) +{ + cycle_t cyc = sched_clock_reg ? __raw_readl(sched_clock_reg) : 0; + update_sched_clock(&cd, cyc, (u32)~0); +} + +static int __init mxc_clocksource_init(struct clk *timer_clk) +{ + unsigned int c = clk_get_rate(timer_clk); + void __iomem *reg = timer_base + (timer_is_v2() ? V2_TCN : MX1_2_TCN); + + sched_clock_reg = reg; + + init_sched_clock(&cd, mxc_update_sched_clock, 32, c); + return clocksource_mmio_init(reg, "mxc_timer1", c, 200, 32, + clocksource_mmio_readl_up); +} + +/* clock event */ + +static int mx1_2_set_next_event(unsigned long evt, + struct clock_event_device *unused) +{ + unsigned long tcmp; + + tcmp = __raw_readl(timer_base + MX1_2_TCN) + evt; + + __raw_writel(tcmp, timer_base + MX1_2_TCMP); + + return (int)(tcmp - __raw_readl(timer_base + MX1_2_TCN)) < 0 ? + -ETIME : 0; +} + +static int v2_set_next_event(unsigned long evt, + struct clock_event_device *unused) +{ + unsigned long tcmp; + + tcmp = __raw_readl(timer_base + V2_TCN) + evt; + + __raw_writel(tcmp, timer_base + V2_TCMP); + + return evt < 0x7fffffff && + (int)(tcmp - __raw_readl(timer_base + V2_TCN)) < 0 ? + -ETIME : 0; +} + +#ifdef DEBUG +static const char *clock_event_mode_label[] = { + [CLOCK_EVT_MODE_PERIODIC] = "CLOCK_EVT_MODE_PERIODIC", + [CLOCK_EVT_MODE_ONESHOT] = "CLOCK_EVT_MODE_ONESHOT", + [CLOCK_EVT_MODE_SHUTDOWN] = "CLOCK_EVT_MODE_SHUTDOWN", + [CLOCK_EVT_MODE_UNUSED] = "CLOCK_EVT_MODE_UNUSED" +}; +#endif /* DEBUG */ + +static void mxc_set_mode(enum clock_event_mode mode, + struct clock_event_device *evt) +{ + unsigned long flags; + + /* + * The timer interrupt generation is disabled at least + * for enough time to call mxc_set_next_event() + */ + local_irq_save(flags); + + /* Disable interrupt in GPT module */ + gpt_irq_disable(); + + if (mode != clockevent_mode) { + /* Set event time into far-far future */ + if (timer_is_v2()) + __raw_writel(__raw_readl(timer_base + V2_TCN) - 3, + timer_base + V2_TCMP); + else + __raw_writel(__raw_readl(timer_base + MX1_2_TCN) - 3, + timer_base + MX1_2_TCMP); + + /* Clear pending interrupt */ + gpt_irq_acknowledge(); + } + +#ifdef DEBUG + printk(KERN_INFO "mxc_set_mode: changing mode from %s to %s\n", + clock_event_mode_label[clockevent_mode], + clock_event_mode_label[mode]); +#endif /* DEBUG */ + + /* Remember timer mode */ + clockevent_mode = mode; + local_irq_restore(flags); + + switch (mode) { + case CLOCK_EVT_MODE_PERIODIC: + printk(KERN_ERR"mxc_set_mode: Periodic mode is not " + "supported for i.MX\n"); + break; + case CLOCK_EVT_MODE_ONESHOT: + /* + * Do not put overhead of interrupt enable/disable into + * mxc_set_next_event(), the core has about 4 minutes + * to call mxc_set_next_event() or shutdown clock after + * mode switching + */ + local_irq_save(flags); + gpt_irq_enable(); + local_irq_restore(flags); + break; + case CLOCK_EVT_MODE_SHUTDOWN: + case CLOCK_EVT_MODE_UNUSED: + case CLOCK_EVT_MODE_RESUME: + /* Left event sources disabled, no more interrupts appear */ + break; + } +} + +/* + * IRQ handler for the timer + */ +static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id) +{ + struct clock_event_device *evt = &clockevent_mxc; + uint32_t tstat; + + if (timer_is_v2()) + tstat = __raw_readl(timer_base + V2_TSTAT); + else + tstat = __raw_readl(timer_base + MX1_2_TSTAT); + + gpt_irq_acknowledge(); + + evt->event_handler(evt); + + return IRQ_HANDLED; +} + +static struct irqaction mxc_timer_irq = { + .name = "i.MX Timer Tick", + .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, + .handler = mxc_timer_interrupt, +}; + +static struct clock_event_device clockevent_mxc = { + .name = "mxc_timer1", + .features = CLOCK_EVT_FEAT_ONESHOT, + .shift = 32, + .set_mode = mxc_set_mode, + .set_next_event = mx1_2_set_next_event, + .rating = 200, +}; + +static int __init mxc_clockevent_init(struct clk *timer_clk) +{ + unsigned int c = clk_get_rate(timer_clk); + + if (timer_is_v2()) + clockevent_mxc.set_next_event = v2_set_next_event; + + clockevent_mxc.mult = div_sc(c, NSEC_PER_SEC, + clockevent_mxc.shift); + clockevent_mxc.max_delta_ns = + clockevent_delta2ns(0xfffffffe, &clockevent_mxc); + clockevent_mxc.min_delta_ns = + clockevent_delta2ns(0xff, &clockevent_mxc); + + clockevent_mxc.cpumask = cpumask_of(0); + + clockevents_register_device(&clockevent_mxc); + + return 0; +} + +void __init mxc_timer_init(struct clk *timer_clk, void __iomem *base, int irq) +{ + uint32_t tctl_val; + u32 reg; + + clk_enable(timer_clk); + + timer_base = base; + + /* + * Initialise to a known state (all timers off, and timing reset) + */ + + __raw_writel(0, timer_base + MXC_TCTL); + __raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */ + + if (timer_is_v2()) { + if (cpu_is_mx5() || cpu_is_mx6sl() || + mx6q_revision() == IMX_CHIP_REVISION_1_0) + tctl_val = V2_TCTL_CLK_PER | V2_TCTL_FRR | + V2_TCTL_WAITEN | MXC_TCTL_TEN; + else { + tctl_val = V2_TCTL_CLK_OSC_DIV8 | V2_TCTL_FRR | + V2_TCTL_WAITEN | MXC_TCTL_TEN; + if (!cpu_is_mx6q()) { + reg = __raw_readl(timer_base + MXC_TPRER); + reg |= (V2_TPRER_PRE24M_DIV8 << + V2_TPRER_PRE24M_OFFSET); + __raw_writel(reg, timer_base + MXC_TPRER); + /* Enable the 24MHz input clock. */ + tctl_val |= V2_TCTL_ENABLE24M; + } + } + } else + tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN; + + __raw_writel(tctl_val, timer_base + MXC_TCTL); + + /* init and register the timer to the framework */ + mxc_clocksource_init(timer_clk); + mxc_clockevent_init(timer_clk); + + /* Make irqs happen */ + setup_irq(irq, &mxc_timer_irq); +} diff --git a/arch/arm/plat-mxc/tzic.c b/arch/arm/plat-mxc/tzic.c new file mode 100644 index 00000000..57f9395f --- /dev/null +++ b/arch/arm/plat-mxc/tzic.c @@ -0,0 +1,205 @@ +/* + * Copyright (C)2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include <linux/module.h> +#include <linux/moduleparam.h> +#include <linux/init.h> +#include <linux/device.h> +#include <linux/errno.h> +#include <linux/io.h> + +#include <asm/mach/irq.h> + +#include <mach/hardware.h> +#include <mach/common.h> + +#include "irq-common.h" + +/* + ***************************************** + * TZIC Registers * + ***************************************** + */ + +#define TZIC_INTCNTL 0x0000 /* Control register */ +#define TZIC_INTTYPE 0x0004 /* Controller Type register */ +#define TZIC_IMPID 0x0008 /* Distributor Implementer Identification */ +#define TZIC_PRIOMASK 0x000C /* Priority Mask Reg */ +#define TZIC_SYNCCTRL 0x0010 /* Synchronizer Control register */ +#define TZIC_DSMINT 0x0014 /* DSM interrupt Holdoffregister */ +#define TZIC_INTSEC0(i) (0x0080 + ((i) << 2)) /* Interrupt Security Reg 0 */ +#define TZIC_ENSET0(i) (0x0100 + ((i) << 2)) /* Enable Set Reg 0 */ +#define TZIC_ENCLEAR0(i) (0x0180 + ((i) << 2)) /* Enable Clear Reg 0 */ +#define TZIC_SRCSET0 0x0200 /* Source Set Register 0 */ +#define TZIC_SRCCLAR0 0x0280 /* Source Clear Register 0 */ +#define TZIC_PRIORITY0 0x0400 /* Priority Register 0 */ +#define TZIC_PND0 0x0D00 /* Pending Register 0 */ +#define TZIC_HIPND0 0x0D80 /* High Priority Pending Register */ +#define TZIC_WAKEUP0(i) (0x0E00 + ((i) << 2)) /* Wakeup Config Register */ +#define TZIC_SWINT 0x0F00 /* Software Interrupt Rigger Register */ +#define TZIC_ID0 0x0FD0 /* Indentification Register 0 */ + +void __iomem *tzic_base; /* Used as irq controller base in entry-macro.S */ + +#ifdef CONFIG_FIQ +static int tzic_set_irq_fiq(unsigned int irq, unsigned int type) +{ + unsigned int index, mask, value; + + index = irq >> 5; + if (unlikely(index >= 4)) + return -EINVAL; + mask = 1U << (irq & 0x1F); + + value = __raw_readl(tzic_base + TZIC_INTSEC0(index)) | mask; + if (type) + value &= ~mask; + __raw_writel(value, tzic_base + TZIC_INTSEC0(index)); + + return 0; +} +#endif + +/** + * tzic_mask_irq() - Disable interrupt source "d" in the TZIC + * + * @param d interrupt source + */ +static void tzic_mask_irq(struct irq_data *d) +{ + int index, off; + + index = d->irq >> 5; + off = d->irq & 0x1F; + __raw_writel(1 << off, tzic_base + TZIC_ENCLEAR0(index)); +} + +/** + * tzic_unmask_irq() - Enable interrupt source "d" in the TZIC + * + * @param d interrupt source + */ +static void tzic_unmask_irq(struct irq_data *d) +{ + int index, off; + + index = d->irq >> 5; + off = d->irq & 0x1F; + __raw_writel(1 << off, tzic_base + TZIC_ENSET0(index)); +} + +static unsigned int wakeup_intr[4]; + +/** + * tzic_set_wake_irq() - Set interrupt source "d" in the TZIC as a wake-up source. + * + * @param d interrupt source + * @param enable enable as wake-up if equal to non-zero + * disble as wake-up if equal to zero + * + * @return This function returns 0 on success. + */ +static int tzic_set_wake_irq(struct irq_data *d, unsigned int enable) +{ + unsigned int index, off; + + index = d->irq >> 5; + off = d->irq & 0x1F; + + if (index > 3) + return -EINVAL; + + if (enable) + wakeup_intr[index] |= (1 << off); + else + wakeup_intr[index] &= ~(1 << off); + + return 0; +} + +static struct mxc_irq_chip mxc_tzic_chip = { + .base = { + .name = "MXC_TZIC", + .irq_ack = tzic_mask_irq, + .irq_mask = tzic_mask_irq, + .irq_unmask = tzic_unmask_irq, + .irq_set_wake = tzic_set_wake_irq, + }, +#ifdef CONFIG_FIQ + .set_irq_fiq = tzic_set_irq_fiq, +#endif +}; + +/* + * This function initializes the TZIC hardware and disables all the + * interrupts. It registers the interrupt enable and disable functions + * to the kernel for each interrupt source. + */ +void __init tzic_init_irq(void __iomem *irqbase) +{ + int i; + + tzic_base = irqbase; + /* put the TZIC into the reset value with + * all interrupts disabled + */ + i = __raw_readl(tzic_base + TZIC_INTCNTL); + + __raw_writel(0x80010001, tzic_base + TZIC_INTCNTL); + __raw_writel(0x1f, tzic_base + TZIC_PRIOMASK); + __raw_writel(0x02, tzic_base + TZIC_SYNCCTRL); + + for (i = 0; i < 4; i++) + __raw_writel(0xFFFFFFFF, tzic_base + TZIC_INTSEC0(i)); + + /* disable all interrupts */ + for (i = 0; i < 4; i++) + __raw_writel(0xFFFFFFFF, tzic_base + TZIC_ENCLEAR0(i)); + + /* all IRQ no FIQ Warning :: No selection */ + + for (i = 0; i < MXC_INTERNAL_IRQS; i++) { + irq_set_chip_and_handler(i, &mxc_tzic_chip.base, + handle_level_irq); + set_irq_flags(i, IRQF_VALID); + } + +#ifdef CONFIG_FIQ + /* Initialize FIQ */ + init_FIQ(); +#endif + + pr_info("TrustZone Interrupt Controller (TZIC) initialized\n"); +} + +/** + * tzic_enable_wake() - enable wakeup interrupt + * + * @param is_idle 1 if called in idle loop (ENSET0 register); + * 0 to be used when called from low power entry + * @return 0 if successful; non-zero otherwise + */ +int tzic_enable_wake(int is_idle) +{ + unsigned int i, v; + + __raw_writel(1, tzic_base + TZIC_DSMINT); + if (unlikely(__raw_readl(tzic_base + TZIC_DSMINT) == 0)) + return -EAGAIN; + + for (i = 0; i < 4; i++) { + v = is_idle ? __raw_readl(tzic_base + TZIC_ENSET0(i)) : + wakeup_intr[i]; + __raw_writel(v, tzic_base + TZIC_WAKEUP0(i)); + } + + return 0; +} diff --git a/arch/arm/plat-mxc/ulpi.c b/arch/arm/plat-mxc/ulpi.c new file mode 100644 index 00000000..477e45be --- /dev/null +++ b/arch/arm/plat-mxc/ulpi.c @@ -0,0 +1,118 @@ +/* + * Copyright 2008 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> + * Copyright 2009 Daniel Mack <daniel@caiaq.de> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/io.h> +#include <linux/delay.h> +#include <linux/usb/otg.h> +#include <linux/usb/ulpi.h> + +#include <mach/ulpi.h> + +/* ULPIVIEW register bits */ +#define ULPIVW_WU (1 << 31) /* Wakeup */ +#define ULPIVW_RUN (1 << 30) /* read/write run */ +#define ULPIVW_WRITE (1 << 29) /* 0 = read 1 = write */ +#define ULPIVW_SS (1 << 27) /* SyncState */ +#define ULPIVW_PORT_MASK 0x07 /* Port field */ +#define ULPIVW_PORT_SHIFT 24 +#define ULPIVW_ADDR_MASK 0xff /* data address field */ +#define ULPIVW_ADDR_SHIFT 16 +#define ULPIVW_RDATA_MASK 0xff /* read data field */ +#define ULPIVW_RDATA_SHIFT 8 +#define ULPIVW_WDATA_MASK 0xff /* write data field */ +#define ULPIVW_WDATA_SHIFT 0 + +static int ulpi_poll(void __iomem *view, u32 bit) +{ + int timeout = 10000; + + while (timeout--) { + u32 data = __raw_readl(view); + + if (!(data & bit)) + return 0; + + cpu_relax(); + }; + + printk(KERN_WARNING "timeout polling for ULPI device\n"); + + return -ETIMEDOUT; +} + +static int ulpi_read(struct otg_transceiver *otg, u32 reg) +{ + int ret; + void __iomem *view = otg->io_priv; + + /* make sure interface is running */ + if (!(__raw_readl(view) & ULPIVW_SS)) { + __raw_writel(ULPIVW_WU, view); + + /* wait for wakeup */ + ret = ulpi_poll(view, ULPIVW_WU); + if (ret) + return ret; + } + + /* read the register */ + __raw_writel((ULPIVW_RUN | (reg << ULPIVW_ADDR_SHIFT)), view); + + /* wait for completion */ + ret = ulpi_poll(view, ULPIVW_RUN); + if (ret) + return ret; + + return (__raw_readl(view) >> ULPIVW_RDATA_SHIFT) & ULPIVW_RDATA_MASK; +} + +static int ulpi_write(struct otg_transceiver *otg, u32 val, u32 reg) +{ + int ret; + void __iomem *view = otg->io_priv; + + /* make sure the interface is running */ + if (!(__raw_readl(view) & ULPIVW_SS)) { + __raw_writel(ULPIVW_WU, view); + /* wait for wakeup */ + ret = ulpi_poll(view, ULPIVW_WU); + if (ret) + return ret; + } + + __raw_writel((ULPIVW_RUN | ULPIVW_WRITE | + (reg << ULPIVW_ADDR_SHIFT) | + ((val & ULPIVW_WDATA_MASK) << ULPIVW_WDATA_SHIFT)), view); + + /* wait for completion */ + return ulpi_poll(view, ULPIVW_RUN); +} + +struct otg_io_access_ops mxc_ulpi_access_ops = { + .read = ulpi_read, + .write = ulpi_write, +}; +EXPORT_SYMBOL_GPL(mxc_ulpi_access_ops); + +struct otg_transceiver *imx_otg_ulpi_create(unsigned int flags) +{ + return otg_ulpi_create(&mxc_ulpi_access_ops, flags); +} diff --git a/arch/arm/plat-mxc/usb_common.c b/arch/arm/plat-mxc/usb_common.c new file mode 100755 index 00000000..855e6722 --- /dev/null +++ b/arch/arm/plat-mxc/usb_common.c @@ -0,0 +1,972 @@ +/* + * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +/*! + *@defgroup USB ARC OTG USB Driver + */ + +/*! + * @file usb_common.c + * + * @brief platform related part of usb driver. + * @ingroup USB + */ + +/*! + *Include files + */ +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/errno.h> +#include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/clk.h> +#include <linux/err.h> +#include <linux/delay.h> +#include <linux/platform_device.h> +#include <linux/fsl_devices.h> +#include <linux/usb/otg.h> +#include <linux/usb/fsl_xcvr.h> +#include <linux/regulator/consumer.h> +#include <linux/io.h> +#include <asm/mach-types.h> +#include <mach/arc_otg.h> +#include <mach/hardware.h> +#include <mach/mxc.h> +typedef void (*driver_vbus_func)(bool); + +void __iomem *imx_otg_base; +static driver_vbus_func s_h1_driver_vbus; +static driver_vbus_func s_otg_driver_vbus; + +EXPORT_SYMBOL(imx_otg_base); + +#define MXC_NUMBER_USB_TRANSCEIVER 6 +struct fsl_xcvr_ops *g_xc_ops[MXC_NUMBER_USB_TRANSCEIVER] = { NULL }; + +bool usb_icbug_swfix_need(void) +{ + if (cpu_is_mx6sl()) + return false; + else if ((mx6q_revision() > IMX_CHIP_REVISION_1_1)) + return false; + else if ((mx6dl_revision() > IMX_CHIP_REVISION_1_0)) + return false; + return true; +} +EXPORT_SYMBOL(usb_icbug_swfix_need); + +void mx6_set_host1_vbus_func(driver_vbus_func driver_vbus) +{ + s_h1_driver_vbus = driver_vbus; +} + +void mx6_get_host1_vbus_func(driver_vbus_func *driver_vbus) +{ + *driver_vbus = s_h1_driver_vbus; +} +EXPORT_SYMBOL(mx6_get_host1_vbus_func); + +void mx6_set_otghost_vbus_func(driver_vbus_func driver_vbus) +{ + s_otg_driver_vbus = driver_vbus; +} + +void mx6_get_otghost_vbus_func(driver_vbus_func *driver_vbus) +{ + *driver_vbus = s_otg_driver_vbus; +} +EXPORT_SYMBOL(mx6_get_otghost_vbus_func); + + +enum fsl_usb2_modes get_usb_mode(struct fsl_usb2_platform_data *pdata) +{ + enum fsl_usb2_modes mode; + mode = FSL_USB_UNKNOWN; + + if (!strcmp("DR", pdata->name)) { + if ((UOG_USBMODE & 0x3) == 0x2) + mode = FSL_USB_DR_DEVICE; + else if ((UOG_USBMODE & 0x3) == 0x3) + mode = FSL_USB_DR_HOST; + } else if (!strcmp("Host 1", pdata->name)) + mode = FSL_USB_MPH_HOST1; + else if (!strcmp("Host 2", pdata->name)) + mode = FSL_USB_MPH_HOST2; + + if (mode == FSL_USB_UNKNOWN) + printk(KERN_ERR "unknow usb mode,name is %s\n", pdata->name); + return mode; +} + +static struct clk *usb_clk; +static struct clk *usb_ahb_clk; + + +/* + * make sure USB_CLK is running at 60 MHz +/- 1000 Hz + */ +static int fsl_check_usbclk(void) +{ + unsigned long freq; + + usb_ahb_clk = clk_get(NULL, "usb_ahb_clk"); + if (clk_enable(usb_ahb_clk)) { + if (cpu_is_mx6()) + return 0; /* there is no ahb clock at mx6 */ + printk(KERN_ERR "clk_enable(usb_ahb_clk) failed\n"); + return -EINVAL; + } + clk_put(usb_ahb_clk); + + usb_clk = clk_get(NULL, "usb_clk"); + if (clk_enable(usb_clk)) { + if (cpu_is_mx6()) + return 0; /* there is usb_clk at mx6 */ + printk(KERN_ERR "clk_enable(usb_clk) failed\n"); + return -EINVAL; + } + freq = clk_get_rate(usb_clk); + clk_put(usb_clk); + if ((freq < 59999000) || (freq > 60001000)) { + printk(KERN_ERR "USB_CLK=%lu, should be 60MHz\n", freq); + return -1; + } + + return 0; +} + +void fsl_usb_xcvr_register(struct fsl_xcvr_ops *xcvr_ops) +{ + int i; + + pr_debug("%s\n", __func__); + for (i = 0; i < MXC_NUMBER_USB_TRANSCEIVER; i++) { + if (g_xc_ops[i] == NULL) { + g_xc_ops[i] = xcvr_ops; + return; + } + } + + pr_debug("Failed %s\n", __func__); +} +EXPORT_SYMBOL(fsl_usb_xcvr_register); + +void fsl_platform_set_test_mode (struct fsl_usb2_platform_data *pdata, enum usb_test_mode mode) +{ + if (pdata->xcvr_ops && pdata->xcvr_ops->set_test_mode) + pdata->xcvr_ops->set_test_mode((u32 *)(pdata->regs + ULPIVW_OFF), mode); +} +EXPORT_SYMBOL(fsl_platform_set_test_mode); + +void fsl_usb_xcvr_unregister(struct fsl_xcvr_ops *xcvr_ops) +{ + int i; + + pr_debug("%s\n", __func__); + for (i = 0; i < MXC_NUMBER_USB_TRANSCEIVER; i++) { + if (g_xc_ops[i] && (g_xc_ops[i] == xcvr_ops)) { + g_xc_ops[i] = NULL; + return; + } + } + + pr_debug("Failed %s\n", __func__); +} +EXPORT_SYMBOL(fsl_usb_xcvr_unregister); + +static struct fsl_xcvr_ops *fsl_usb_get_xcvr(char *name) +{ + int i; + + pr_debug("%s\n", __func__); + if (name == NULL) { + printk(KERN_ERR "get_xcvr(): No tranceiver name\n"); + return NULL; + } + + for (i = 0; i < MXC_NUMBER_USB_TRANSCEIVER; i++) { + if (g_xc_ops[i] && (strcmp(g_xc_ops[i]->name, name) == 0)) { + return g_xc_ops[i]; + } + } + pr_debug("Failed %s\n", __func__); + return NULL; +} + +/* The dmamask must be set for EHCI to work */ +static u64 ehci_dmamask = ~(u32) 0; + +/*! + * Register an instance of a USB host platform device. + * + * @param res: resource pointer + * @param n_res: number of resources + * @param config: config pointer + * + * @return newly-registered platform_device + * + * The USB controller supports 3 host interfaces, and the + * kernel can be configured to support some number of them. + * Each supported host interface is registered as an instance + * of the "fsl-ehci" device. Call this function multiple times + * to register each host interface. + */ +static int usb_mxc_instance_id; +__init struct platform_device *host_pdev_register(struct resource *res, int n_res, + struct fsl_usb2_platform_data *config) +{ + struct platform_device *pdev; + int rc; + + pr_debug("register host res=0x%p, size=%d\n", res, n_res); + + pdev = platform_device_register_simple("fsl-ehci", + usb_mxc_instance_id, res, n_res); + if (IS_ERR(pdev)) { + pr_debug("can't register %s Host, %ld\n", + config->name, PTR_ERR(pdev)); + return NULL; + } + + pdev->dev.coherent_dma_mask = 0xffffffff; + pdev->dev.dma_mask = &ehci_dmamask; + + /* + * platform_device_add_data() makes a copy of + * the platform_data passed in. That makes it + * impossible to share the same config struct for + * all OTG devices (host,gadget,otg). So, just + * set the platorm_data pointer ourselves. + */ + rc = platform_device_add_data(pdev, config, + sizeof(struct fsl_usb2_platform_data)); + if (rc) { + platform_device_unregister(pdev); + return NULL; + } + + printk(KERN_INFO "usb: %s host (%s) registered\n", config->name, + config->transceiver); + pr_debug("pdev=0x%p dev=0x%p resources=0x%p pdata=0x%p\n", + pdev, &pdev->dev, pdev->resource, pdev->dev.platform_data); + + usb_mxc_instance_id++; + + return pdev; +} + +static void usbh1_set_serial_xcvr(void) +{ + pr_debug("%s: \n", __func__); + USBCTRL &= ~(UCTRL_H1SIC_MASK | UCTRL_BPE); /* disable bypass mode */ + USBCTRL |= UCTRL_H1SIC_SU6 | /* single-ended / unidir. */ + UCTRL_H1WIE | UCTRL_H1DT | /* disable H1 TLL */ + UCTRL_H1PM; /* power mask */ +} + +static void usbh1_set_ulpi_xcvr(void) +{ + pr_debug("%s: \n", __func__); + + /* Stop then Reset */ + UH1_USBCMD &= ~UCMD_RUN_STOP; + while (UH1_USBCMD & UCMD_RUN_STOP) + ; + + UH1_USBCMD |= UCMD_RESET; + while (UH1_USBCMD & UCMD_RESET) + ; + + /* Select the clock from external PHY */ + USB_CTRL_1 |= USB_CTRL_UH1_EXT_CLK_EN; + + /* select ULPI PHY PTS=2 */ + UH1_PORTSC1 = (UH1_PORTSC1 & ~PORTSC_PTS_MASK) | PORTSC_PTS_ULPI; + + USBCTRL &= ~UCTRL_H1WIE; /* HOST1 wakeup intr disable */ + USBCTRL &= ~UCTRL_H1UIE; /* Host1 ULPI interrupt disable */ + USBCTRL |= UCTRL_H1PM; /* HOST1 power mask */ + USB_PHY_CTR_FUNC |= USB_UH1_OC_DIS; /* OC is not used */ + + /* Interrupt Threshold Control:Immediate (no threshold) */ + UH1_USBCMD &= UCMD_ITC_NO_THRESHOLD; + + UH1_USBCMD |= UCMD_RESET; /* reset the controller */ + + /* allow controller to reset, and leave time for + * the ULPI transceiver to reset too. + */ + msleep(100); + + /* Turn off the usbpll for ulpi tranceivers */ + clk_disable(usb_clk); +} + +static void usbh1_set_utmi_xcvr(void) +{ + u32 tmp; + + /* Stop then Reset */ + UH1_USBCMD &= ~UCMD_RUN_STOP; + while (UH1_USBCMD & UCMD_RUN_STOP) + ; + + UH1_USBCMD |= UCMD_RESET; + while ((UH1_USBCMD) & (UCMD_RESET)) + ; + + /* For OC and PWR, it is board level setting + * The default setting is for mx53 evk + */ + USBCTRL &= ~UCTRL_H1PM; /* Host1 Power Mask */ + USBCTRL &= ~UCTRL_H1WIE; /* Host1 Wakeup Intr Disable */ + USB_PHY_CTR_FUNC |= USB_UH1_OC_DIS; /* Over current disable */ + + if (cpu_is_mx50()) { + USBCTRL |= UCTRL_H1PM; /* Host1 Power Mask */ + USB_PHY_CTR_FUNC &= ~USB_UH1_OC_DIS; /* Over current enable */ + /* Over current polarity low active */ + USB_PHY_CTR_FUNC |= USB_UH1_OC_POL; + } + /* set UTMI xcvr */ + tmp = UH1_PORTSC1 & ~PORTSC_PTS_MASK; + tmp |= PORTSC_PTS_UTMI; + UH1_PORTSC1 = tmp; + + /* Set the PHY clock to 24MHz */ + USBH1_PHY_CTRL1 &= ~USB_UTMI_PHYCTRL2_PLLDIV_MASK; + USBH1_PHY_CTRL1 |= 0x01; + + /* Workaround an IC issue for ehci driver: + * when turn off root hub port power, EHCI set + * PORTSC reserved bits to be 0, but PTW with 0 + * means 8 bits tranceiver width, here change + * it back to be 16 bits and do PHY diable and + * then enable. + */ + UH1_PORTSC1 |= PORTSC_PTW; + + /* need to reset the controller here so that the ID pin + * is correctly detected. + */ + /* Stop then Reset */ + UH1_USBCMD &= ~UCMD_RUN_STOP; + while (UH1_USBCMD & UCMD_RUN_STOP) + ; + + UH1_USBCMD |= UCMD_RESET; + while ((UH1_USBCMD) & (UCMD_RESET)) + ; + + /* allow controller to reset, and leave time for + * the ULPI transceiver to reset too. + */ + msleep(100); + + /* Turn off the usbpll for UTMI tranceivers */ + clk_disable(usb_clk); +} + +static void usbh2_set_ulpi_xcvr(void) +{ + u32 tmp; + + pr_debug("%s\n", __func__); + + UH2_USBCMD &= ~UCMD_RUN_STOP; + while (UH2_USBCMD & UCMD_RUN_STOP) + ; + + UH2_USBCMD |= UCMD_RESET; + while (UH2_USBCMD & UCMD_RESET) + + USBCTRL_HOST2 &= ~(UCTRL_H2SIC_MASK | UCTRL_BPE); + USBCTRL_HOST2 &= ~UCTRL_H2WIE; /* wakeup intr enable */ + USBCTRL_HOST2 &= ~UCTRL_H2UIE; /* ULPI intr enable */ + USB_CTRL_1 |= USB_CTRL_UH2_EXT_CLK_EN; + if (cpu_is_mx53()) + USB_CTRL_1 |= USB_CTRL_UH2_CLK_FROM_ULPI_PHY; + if (cpu_is_mx51())/* not tested */ + USBCTRL_HOST2 |= (1 << 12); + /* must set ULPI phy before turning off clock */ + tmp = UH2_PORTSC1 & ~PORTSC_PTS_MASK; + tmp |= PORTSC_PTS_ULPI; + UH2_PORTSC1 = tmp; + if (cpu_is_mx53()) { + /* turn off the internal 60MHZ clk */ + USB_CLKONOFF_CTRL |= (1 << 21); + } + UH2_USBCMD |= UCMD_RESET; /* reset the controller */ + + /* allow controller to reset, and leave time for + * the ULPI transceiver to reset too. + */ + msleep(100); + + /* Turn off the usbpll for ulpi tranceivers */ + clk_disable(usb_clk); +} + +static void usbh2_set_serial_xcvr(void) +{ + pr_debug("%s: \n", __func__); + + /* Stop then Reset */ + UH2_USBCMD &= ~UCMD_RUN_STOP; + while (UH2_USBCMD & UCMD_RUN_STOP) + ; + + UH2_USBCMD |= UCMD_RESET; + while (UH2_USBCMD & UCMD_RESET) + ; + + USBCTRL &= ~(UCTRL_H2SIC_MASK); /* Disable bypass mode */ + USBCTRL &= ~(UCTRL_H2PM); /* Power Mask */ + USBCTRL &= ~UCTRL_H2OCPOL; /* OverCurrent Polarity is Low Active */ + USBCTRL &= ~UCTRL_H2WIE; /* Wakeup intr disable */ + USBCTRL |= UCTRL_IP_PUE_DOWN | /* ipp_pue_pulldwn_dpdm */ + UCTRL_USBTE | /* USBT is enabled */ + UCTRL_H2DT; /* Disable H2 TLL */ + + if (cpu_is_mx25()) { + /* + * USBH2_PWR and USBH2_OC are active high. + * Must force xcvr clock to "internal" so that + * we can write to PTS field after it's been + * cleared by ehci_turn_off_all_ports(). + */ + USBCTRL |= UCTRL_H2PP | UCTRL_H2OCPOL | UCTRL_XCSH2; + /* Disable Host2 bus Lock */ + USBCTRL |= UCTRL_H2LOCKD; + } + + USBCTRL &= ~(UCTRL_PP); + UH2_PORTSC1 = (UH2_PORTSC1 & (~PORTSC_PTS_MASK)) | PORTSC_PTS_SERIAL; + + if (UH2_HCSPARAMS & HCSPARAMS_PPC) + UH2_PORTSC1 |= PORTSC_PORT_POWER; + + /* Reset controller before set host mode */ + UH2_USBCMD |= UCMD_RESET; + while (UH2_USBCMD & UCMD_RESET) + ; + + msleep(100); +} + +/*! + * Register remote wakeup by this usb controller + * + * @param pdev: platform_device for this usb controller + * + * @return 0 or negative error code in case not supportted. + */ +static int usb_register_remote_wakeup(struct platform_device *pdev) +{ + struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data; + struct resource *res; + int irq; + + pr_debug("%s: pdev=0x%p \n", __func__, pdev); + if (!(pdata->wake_up_enable)) + return -ECANCELED; + + res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + if (!res) { + dev_err(&pdev->dev, + "Found HC with no IRQ. Check %s setup!\n", + dev_name(&pdev->dev)); + return -ENODEV; + } + irq = res->start; + device_set_wakeup_capable(&pdev->dev, true); + enable_irq_wake(irq); + + return 0; +} + +int fsl_usb_host_init(struct platform_device *pdev) +{ + struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data; + struct fsl_xcvr_ops *xops; + + pr_debug("%s: pdev=0x%p pdata=0x%p\n", __func__, pdev, pdata); + + xops = fsl_usb_get_xcvr(pdata->transceiver); + if (!xops) { + printk(KERN_ERR "%s transceiver ops missing\n", pdata->name); + return -EINVAL; + } + pdata->xcvr_ops = xops; + pdata->xcvr_type = xops->xcvr_type; + pdata->pdev = pdev; + + if (fsl_check_usbclk() != 0) + return -EINVAL; + + pr_debug("%s: grab pins\n", __func__); + if (pdata->gpio_usb_active && pdata->gpio_usb_active()) + return -EINVAL; + + if (cpu_is_mx50()) + /* Turn on AHB CLK for H1*/ + USB_CLKONOFF_CTRL &= ~H1_AHBCLK_OFF; + + /* enable board power supply for xcvr */ + if (pdata->xcvr_pwr) { + if (pdata->xcvr_pwr->regu1) + regulator_enable(pdata->xcvr_pwr->regu1); + if (pdata->xcvr_pwr->regu2) + regulator_enable(pdata->xcvr_pwr->regu2); + } + + if (xops->init) + xops->init(xops); + + if (usb_register_remote_wakeup(pdev)) + pr_debug("%s port is not a wakeup source.\n", pdata->name); + if (!(cpu_is_mx6())) { + if (xops->xcvr_type == PORTSC_PTS_SERIAL) { + if (cpu_is_mx35()) { + usbh2_set_serial_xcvr(); + /* Close the internal 60Mhz */ + USBCTRL &= ~UCTRL_XCSH2; + } else if (cpu_is_mx25()) + usbh2_set_serial_xcvr(); + else + usbh1_set_serial_xcvr(); + } else if (xops->xcvr_type == PORTSC_PTS_ULPI) { + if (!strcmp("Host 1", pdata->name)) + usbh1_set_ulpi_xcvr(); + if (!strcmp("Host 2", pdata->name)) + usbh2_set_ulpi_xcvr(); + } else if (xops->xcvr_type == PORTSC_PTS_UTMI) { + usbh1_set_utmi_xcvr(); + } + } else { +#ifdef CONFIG_ARCH_MX6 + if (!strcmp("Host 1", pdata->name)) { + if (machine_is_mx6q_arm2()) + USB_H1_CTRL &= ~UCTRL_OVER_CUR_POL; + else if (machine_is_mx6q_sabrelite()) + USB_H1_CTRL |= UCTRL_OVER_CUR_POL; + USB_H1_CTRL |= UCTRL_OVER_CUR_DIS; + } +#endif + } + + pr_debug("%s: %s success\n", __func__, pdata->name); + return 0; +} +EXPORT_SYMBOL(fsl_usb_host_init); + +void fsl_usb_host_uninit(struct fsl_usb2_platform_data *pdata) +{ + pr_debug("%s\n", __func__); + + if (pdata->xcvr_ops && pdata->xcvr_ops->uninit) + pdata->xcvr_ops->uninit(pdata->xcvr_ops); + + pdata->regs = NULL; + + if (pdata->gpio_usb_inactive) + pdata->gpio_usb_inactive(); + if (pdata->xcvr_type == PORTSC_PTS_SERIAL) { + /* Workaround an IC issue for ehci driver. + * when turn off root hub port power, EHCI set + * PORTSC reserved bits to be 0, but PTS with 0 + * means UTMI interface, so here force the Host2 + * port use the internal 60Mhz. + */ + if (cpu_is_mx35()) + USBCTRL |= UCTRL_XCSH2; + clk_disable(usb_clk); + } + + /* disable board power supply for xcvr */ + if (pdata->xcvr_pwr) { + if (pdata->xcvr_pwr->regu1) + regulator_disable(pdata->xcvr_pwr->regu1); + if (pdata->xcvr_pwr->regu2) + regulator_disable(pdata->xcvr_pwr->regu2); + } + + clk_disable(usb_ahb_clk); +} +EXPORT_SYMBOL(fsl_usb_host_uninit); + +static void otg_set_serial_xcvr(void) +{ + pr_debug("%s\n", __func__); +} + +void otg_set_serial_host(void) +{ + pr_debug("%s\n", __func__); + /* set USBCTRL for host operation + * disable: bypass mode, + * set: single-ended/unidir/6 wire, OTG wakeup intr enable, + * power mask + */ + USBCTRL &= ~UCTRL_OSIC_MASK; +#if defined(CONFIG_ARCH_MX27) || defined(CONFIG_ARCH_MX3) + USBCTRL &= ~UCTRL_BPE; +#endif + +#if defined(CONFIG_MXC_USB_SB3) + USBCTRL |= UCTRL_OSIC_SB3 | UCTRL_OWIE | UCTRL_OPM; +#elif defined(CONFIG_MXC_USB_SU6) + USBCTRL |= UCTRL_OSIC_SU6 | UCTRL_OWIE | UCTRL_OPM; +#elif defined(CONFIG_MXC_USB_DB4) + USBCTRL |= UCTRL_OSIC_DB4 | UCTRL_OWIE | UCTRL_OPM; +#else + USBCTRL |= UCTRL_OSIC_DU6 | UCTRL_OWIE | UCTRL_OPM; +#endif + + USB_OTG_MIRROR = OTGM_VBUSVAL | OTGM_ASESVLD; /* 0xa */ +} +EXPORT_SYMBOL(otg_set_serial_host); + +void otg_set_serial_peripheral(void) +{ + /* set USBCTRL for device operation + * disable: bypass mode + * set: differential/unidir/6 wire, OTG wakeup intr enable, + * power mask + */ + USBCTRL &= ~UCTRL_OSIC_MASK; +#if defined(CONFIG_ARCH_MX27) || defined(CONFIG_ARCH_MX3) + USBCTRL &= ~UCTRL_BPE; +#endif + +#if defined(CONFIG_MXC_USB_SB3) + USBCTRL |= UCTRL_OSIC_SB3 | UCTRL_OWIE | UCTRL_OPM; +#elif defined(CONFIG_MXC_USB_SU6) + USBCTRL |= UCTRL_OSIC_SU6 | UCTRL_OWIE | UCTRL_OPM; +#elif defined(CONFIG_MXC_USB_DB4) + USBCTRL |= UCTRL_OSIC_DB4 | UCTRL_OWIE | UCTRL_OPM; +#else + USBCTRL |= UCTRL_OSIC_DU6 | UCTRL_OWIE | UCTRL_OPM; +#endif + + USB_OTG_MIRROR = OTGM_VBUSVAL | OTGM_BSESVLD | OTGM_IDIDG; /* oxd */ +} +EXPORT_SYMBOL(otg_set_serial_peripheral); + +static void otg_set_ulpi_xcvr(void) +{ + u32 tmp; + + pr_debug("%s\n", __func__); + USBCTRL &= ~UCTRL_OSIC_MASK; +#if defined(CONFIG_ARCH_MX27) || defined(CONFIG_ARCH_MX3) + USBCTRL &= ~UCTRL_BPE; +#endif + USBCTRL |= UCTRL_OUIE | /* ULPI intr enable */ + UCTRL_OWIE | /* OTG wakeup intr enable */ + UCTRL_OPM; /* power mask */ + + /* must set ULPI phy before turning off clock */ + tmp = UOG_PORTSC1 & ~PORTSC_PTS_MASK; + tmp |= PORTSC_PTS_ULPI; + UOG_PORTSC1 = tmp; + + /* need to reset the controller here so that the ID pin + * is correctly detected. + */ + UOG_USBCMD |= UCMD_RESET; + + /* allow controller to reset, and leave time for + * the ULPI transceiver to reset too. + */ + msleep(100); + + /* Turn off the usbpll for ulpi tranceivers */ + clk_disable(usb_clk); +} + +int fsl_usb_xcvr_suspend(struct fsl_xcvr_ops *xcvr_ops) +{ + if (!machine_is_mx31_3ds()) + return -ECANCELED; + + if (xcvr_ops->xcvr_type == PORTSC_PTS_ULPI) { + if (fsl_check_usbclk() != 0) + return -EINVAL; + clk_enable(usb_clk); + + otg_set_ulpi_xcvr(); + + if (xcvr_ops->suspend) + /* suspend transceiver */ + xcvr_ops->suspend(xcvr_ops); + + clk_disable(usb_clk); + } + return 0; +} +EXPORT_SYMBOL(fsl_usb_xcvr_suspend); + +static void otg_set_utmi_xcvr(void) +{ + u32 tmp; + + /* Stop then Reset */ + UOG_USBCMD &= ~UCMD_RUN_STOP; + while (UOG_USBCMD & UCMD_RUN_STOP) + ; + + UOG_USBCMD |= UCMD_RESET; + while ((UOG_USBCMD) & (UCMD_RESET)) + ; + + if (cpu_is_mx53()) + USB_PHY_CTR_FUNC |= USB_UTMI_PHYCTRL_OC_DIS; + + if (cpu_is_mx51()) { + if (machine_is_mx51_3ds()) { + /* OTG Polarity of Overcurrent is Low active */ + USB_PHY_CTR_FUNC |= USB_UTMI_PHYCTRL_OC_POL; + /* Enable OTG Overcurrent Event */ + USB_PHY_CTR_FUNC &= ~USB_UTMI_PHYCTRL_OC_DIS; + } else { + /* BBG is not using OC */ + USB_PHY_CTR_FUNC |= USB_UTMI_PHYCTRL_OC_DIS; + } + } else if (cpu_is_mx25()) { + USBCTRL |= UCTRL_OCPOL; + USBCTRL &= ~UCTRL_PP; + } else if (cpu_is_mx50()) { + USB_PHY_CTR_FUNC |= USB_UTMI_PHYCTRL_OC_DIS; + } else { + /* USBOTG_PWR low active */ + USBCTRL &= ~UCTRL_PP; + /* OverCurrent Polarity is Low Active */ + USBCTRL &= ~UCTRL_OCPOL; + + if (cpu_is_mx35() && (imx_cpu_ver() < IMX_CHIP_REVISION_2_0)) + /* OTG Lock Disable */ + USBCTRL |= UCTRL_OLOCKD; + } + + if (cpu_is_mx51()) + USBCTRL &= ~UCTRL_OPM; /* OTG Power Mask */ + + USBCTRL &= ~UCTRL_OWIE; /* OTG Wakeup Intr Disable */ + + /* set UTMI xcvr */ + tmp = UOG_PORTSC1 & ~PORTSC_PTS_MASK; + tmp |= PORTSC_PTS_UTMI; + UOG_PORTSC1 = tmp; + + if (cpu_is_mx51()) { + /* Set the PHY clock to 19.2MHz */ + USB_PHY_CTR_FUNC2 &= ~USB_UTMI_PHYCTRL2_PLLDIV_MASK; + USB_PHY_CTR_FUNC2 |= 0x01; + } + + /* Workaround an IC issue for ehci driver: + * when turn off root hub port power, EHCI set + * PORTSC reserved bits to be 0, but PTW with 0 + * means 8 bits tranceiver width, here change + * it back to be 16 bits and do PHY diable and + * then enable. + */ + UOG_PORTSC1 |= PORTSC_PTW; + + if (cpu_is_mx35() || cpu_is_mx25()) { + /* Enable UTMI interface in PHY control Reg */ + USB_PHY_CTR_FUNC &= ~USB_UTMI_PHYCTRL_UTMI_ENABLE; + USB_PHY_CTR_FUNC |= USB_UTMI_PHYCTRL_UTMI_ENABLE; + } + + /* need to reset the controller here so that the ID pin + * is correctly detected. + */ + /* Stop then Reset */ + UOG_USBCMD &= ~UCMD_RUN_STOP; + while (UOG_USBCMD & UCMD_RUN_STOP) + ; + + UOG_USBCMD |= UCMD_RESET; + while ((UOG_USBCMD) & (UCMD_RESET)) + ; + + /* allow controller to reset, and leave time for + * the ULPI transceiver to reset too. + */ + msleep(100); + + if (cpu_is_mx37()) { + /* fix USB PHY Power Gating leakage issue for i.MX37 */ + USB_PHY_CTR_FUNC &= ~USB_UTMI_PHYCTRL_CHGRDETON; + USB_PHY_CTR_FUNC &= ~USB_UTMI_PHYCTRL_CHGRDETEN; + } + + /* Turn off the usbpll for UTMI tranceivers */ + clk_disable(usb_clk); +} + +static int mxc_otg_used; + +int usbotg_init(struct platform_device *pdev) +{ + struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data; + struct fsl_xcvr_ops *xops; + + pr_debug("%s: pdev=0x%p pdata=0x%p\n", __func__, pdev, pdata); + + xops = fsl_usb_get_xcvr(pdata->transceiver); + if (!xops) { + printk(KERN_ERR "DR transceiver ops missing\n"); + return -EINVAL; + } + pdata->xcvr_ops = xops; + pdata->xcvr_type = xops->xcvr_type; + pdata->pdev = pdev; + + if (fsl_check_usbclk() != 0) + return -EINVAL; + if (!mxc_otg_used) { + if (cpu_is_mx50()) + /* Turn on AHB CLK for OTG*/ + USB_CLKONOFF_CTRL &= ~OTG_AHBCLK_OFF; + + pr_debug("%s: grab pins\n", __func__); + if (pdata->gpio_usb_active && pdata->gpio_usb_active()) + return -EINVAL; + if (xops->init) + xops->init(xops); + if (!(cpu_is_mx6())) { + UOG_PORTSC1 = UOG_PORTSC1 & ~PORTSC_PHCD; + + + if (xops->xcvr_type == PORTSC_PTS_SERIAL) { + if (pdata->operating_mode == FSL_USB2_DR_HOST) { + otg_set_serial_host(); + /* need reset */ + UOG_USBCMD |= UCMD_RESET; + msleep(100); + } else if (pdata->operating_mode == FSL_USB2_DR_DEVICE) + otg_set_serial_peripheral(); + otg_set_serial_xcvr(); + } else if (xops->xcvr_type == PORTSC_PTS_ULPI) { + otg_set_ulpi_xcvr(); + } else if (xops->xcvr_type == PORTSC_PTS_UTMI) { + otg_set_utmi_xcvr(); + } + } else { +#ifdef CONFIG_ARCH_MX6 + if (machine_is_mx6q_arm2()) + USB_OTG_CTRL &= ~UCTRL_OVER_CUR_POL; + else if (machine_is_mx6q_sabrelite()) + USB_OTG_CTRL |= UCTRL_OVER_CUR_POL; + USB_OTG_CTRL |= UCTRL_OVER_CUR_DIS; +#endif + } + } + + if (usb_register_remote_wakeup(pdev)) + pr_debug("DR is not a wakeup source.\n"); + + mxc_otg_used++; + pr_debug("%s: success\n", __func__); + return 0; +} +EXPORT_SYMBOL(usbotg_init); + +void usbotg_uninit(struct fsl_usb2_platform_data *pdata) +{ + pr_debug("%s\n", __func__); + + mxc_otg_used--; + if (!mxc_otg_used) { + if (pdata->xcvr_ops && pdata->xcvr_ops->uninit) + pdata->xcvr_ops->uninit(pdata->xcvr_ops); + + pdata->regs = NULL; + + if (machine_is_mx31_3ds()) { + if (pdata->xcvr_ops && pdata->xcvr_ops->suspend) + pdata->xcvr_ops->suspend(pdata->xcvr_ops); + clk_disable(usb_clk); + } + msleep(1); + UOG_PORTSC1 = UOG_PORTSC1 | PORTSC_PHCD; + if (pdata->gpio_usb_inactive) + pdata->gpio_usb_inactive(); + if (pdata->xcvr_type == PORTSC_PTS_SERIAL) + clk_disable(usb_clk); + clk_disable(usb_ahb_clk); + } +} +EXPORT_SYMBOL(usbotg_uninit); + +/* + * This function is used to debounce the reading value for id/vbus at + * the register of otgsc + */ +void usb_debounce_id_vbus(void) +{ + msleep(3); +} +EXPORT_SYMBOL(usb_debounce_id_vbus); + +int usb_event_is_otg_wakeup(struct fsl_usb2_platform_data *pdata) +{ + return (USBCTRL & UCTRL_OWIR) ? true : false; +} +EXPORT_SYMBOL(usb_event_is_otg_wakeup); + +#ifdef CONFIG_ARCH_MX6 +/* enable/disable high-speed disconnect detector of phy ctrl */ +void fsl_platform_set_usb_phy_dis(struct fsl_usb2_platform_data *pdata, + bool enable) +{ + u32 usb_phy_ctrl_dcdt = 0; + /* for HSIC, we do not need to enable disconnect detection */ + if (pdata->phy_mode == FSL_USB2_PHY_HSIC) + return; + usb_phy_ctrl_dcdt = __raw_readl( + MX6_IO_ADDRESS(pdata->phy_regs) + HW_USBPHY_CTRL) & + BM_USBPHY_CTRL_ENHOSTDISCONDETECT; + if (enable) { + if (usb_phy_ctrl_dcdt == 0) + __raw_writel(BM_USBPHY_CTRL_ENHOSTDISCONDETECT, + MX6_IO_ADDRESS(pdata->phy_regs) + + HW_USBPHY_CTRL_SET); + } else { + if (usb_phy_ctrl_dcdt + == BM_USBPHY_CTRL_ENHOSTDISCONDETECT) + __raw_writel(BM_USBPHY_CTRL_ENHOSTDISCONDETECT, + MX6_IO_ADDRESS(pdata->phy_regs) + + HW_USBPHY_CTRL_CLR); + } +} +EXPORT_SYMBOL(fsl_platform_set_usb_phy_dis); +#endif + +void usb_host_set_wakeup(struct device *wkup_dev, bool para) +{ + struct fsl_usb2_platform_data *pdata = wkup_dev->platform_data; + if (pdata->wake_up_enable) + pdata->wake_up_enable(pdata, para); +} +EXPORT_SYMBOL(usb_host_set_wakeup); diff --git a/arch/arm/plat-mxc/usb_hsic_xcvr.c b/arch/arm/plat-mxc/usb_hsic_xcvr.c new file mode 100644 index 00000000..9dbbdc46 --- /dev/null +++ b/arch/arm/plat-mxc/usb_hsic_xcvr.c @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2005-2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + * For HSIC, there is no usb phy, so the operation at this file is noop + */ + +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/device.h> +#include <linux/errno.h> +#include <linux/init.h> +#include <linux/err.h> +#include <linux/platform_device.h> +#include <linux/fsl_devices.h> +#include <linux/pmic_external.h> +#include <linux/usb/fsl_xcvr.h> + +#include <mach/hardware.h> +#include <mach/arc_otg.h> +#include <asm/mach-types.h> + +static struct fsl_xcvr_ops hsic_xcvr_ops = { + .name = "hsic_xcvr", + .xcvr_type = PORTSC_HSIC_MODE, +}; + +extern void fsl_usb_xcvr_register(struct fsl_xcvr_ops *xcvr_ops); + +static int __init hsic_xcvr_init(void) +{ + fsl_usb_xcvr_register(&hsic_xcvr_ops); + return 0; +} + +extern void fsl_usb_xcvr_unregister(struct fsl_xcvr_ops *xcvr_ops); + +static void __exit hsic_xcvr_exit(void) +{ + fsl_usb_xcvr_unregister(&hsic_xcvr_ops); +} + +subsys_initcall(hsic_xcvr_init); +module_exit(hsic_xcvr_exit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("nop xcvr driver"); +MODULE_LICENSE("GPL"); diff --git a/arch/arm/plat-mxc/usb_wakeup.c b/arch/arm/plat-mxc/usb_wakeup.c new file mode 100755 index 00000000..c0fc70ec --- /dev/null +++ b/arch/arm/plat-mxc/usb_wakeup.c @@ -0,0 +1,275 @@ +/* + * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <linux/sched.h> +#include <linux/delay.h> +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/slab.h> +#include <linux/kthread.h> +#include <linux/platform_device.h> +#include <linux/mutex.h> +#include <linux/fsl_devices.h> +#include <linux/suspend.h> +#include <linux/io.h> +#include <mach/arc_otg.h> + +struct wakeup_ctrl { + int wakeup_irq; + int usb_irq; + bool thread_close; + struct fsl_usb2_wakeup_platform_data *pdata; + struct task_struct *thread; + struct completion event; +}; + +extern int usb_event_is_otg_wakeup(struct fsl_usb2_platform_data *pdata); +extern void usb_debounce_id_vbus(void); + +static void wakeup_clk_gate(struct fsl_usb2_wakeup_platform_data *pdata, bool on) +{ + if (pdata->usb_clock_for_pm) + pdata->usb_clock_for_pm(on); +} +static bool phy_in_lowpower_mode(struct fsl_usb2_platform_data *pdata) +{ + unsigned long flags; + bool ret = true; + + spin_lock_irqsave(&pdata->lock, flags); + + if (!pdata->lowpower) + ret = false; + + spin_unlock_irqrestore(&pdata->lock, flags); + + return ret; +} + +static bool usb2_is_in_lowpower(struct wakeup_ctrl *ctrl) +{ + int i; + struct fsl_usb2_wakeup_platform_data *pdata = ctrl->pdata; + /* all the usb module related the wakeup is in lowpower mode */ + for (i = 0; i < 3; i++) { + if (pdata->usb_pdata[i] && pdata->usb_pdata[i]->phy_lowpower_suspend) { + if (!phy_in_lowpower_mode(pdata->usb_pdata[i])) + return false; + } + } + + return true; +} + +static void delay_process_wakeup(struct wakeup_ctrl *ctrl) +{ + int i; + struct fsl_usb2_wakeup_platform_data *pdata = ctrl->pdata; + disable_irq_nosync(ctrl->wakeup_irq); + if ((ctrl->usb_irq > 0) && (ctrl->wakeup_irq != ctrl->usb_irq)) + disable_irq_nosync(ctrl->usb_irq); + + for (i = 0; i < 3; i++) { + if (pdata->usb_pdata[i]) { + pdata->usb_pdata[i]->irq_delay = 1; + } + } + + pdata->usb_wakeup_is_pending = true; + complete(&ctrl->event); +} + +static irqreturn_t usb_wakeup_handler(int irq, void *_dev) +{ + struct wakeup_ctrl *ctrl = (struct wakeup_ctrl *)_dev; + irqreturn_t ret = IRQ_NONE; + if (usb2_is_in_lowpower(ctrl)) { + pr_debug("usb wakeup is here\n"); + delay_process_wakeup(ctrl); + ret = IRQ_HANDLED; + } + return ret; +} + +static enum usb_wakeup_event is_wakeup(struct fsl_usb2_platform_data *pdata) +{ + if (pdata->is_wakeup_event) + return pdata->is_wakeup_event(pdata); + else + return WAKEUP_EVENT_INVALID; +} + +static void wakeup_event_handler(struct wakeup_ctrl *ctrl) +{ + struct fsl_usb2_wakeup_platform_data *pdata = ctrl->pdata; + int already_waked = 0; + enum usb_wakeup_event wakeup_evt; + int i; + + wakeup_clk_gate(ctrl->pdata, true); + + for (i = 0; i < 3; i++) { + struct fsl_usb2_platform_data *usb_pdata = pdata->usb_pdata[i]; + if (usb_pdata) { + /* In order to get the real id/vbus value */ + if (usb_event_is_otg_wakeup(usb_pdata)) + usb_debounce_id_vbus(); + + usb_pdata->irq_delay = 0; + wakeup_evt = is_wakeup(usb_pdata); + usb_pdata->wakeup_event = wakeup_evt; + if (wakeup_evt != WAKEUP_EVENT_INVALID) { + if (usb2_is_in_lowpower(ctrl)) + if (usb_pdata->usb_clock_for_pm) + usb_pdata->usb_clock_for_pm(true); + usb_pdata->lowpower = 0; + already_waked = 1; + if (usb_pdata->wakeup_handler) { + usb_pdata->wakeup_handler(usb_pdata); + } + } + } + } + + /* If nothing to wakeup, clear wakeup event */ + if ((already_waked == 0) && pdata->usb_wakeup_exhandle) { +#if 1 + struct fsl_usb2_wakeup_platform_data *pdata = ctrl->pdata; + /* all the usb module related the wakeup is in lowpower mode */ + for (i = 0; i < 3; i++) { + if (pdata->usb_pdata[i] && pdata->usb_pdata[i]->phy_lowpower_suspend) { + printk(KERN_EMERG "usb_phy[%d] lowpower_mode = %d\n", + i, phy_in_lowpower_mode(pdata->usb_pdata[i])); + } + } +#endif + pdata->usb_wakeup_exhandle(); + } + + wakeup_clk_gate(ctrl->pdata, false); + pdata->usb_wakeup_is_pending = false; + wake_up(&pdata->wq); +} + +static int wakeup_event_thread(void *param) +{ + struct wakeup_ctrl *ctrl = (struct wakeup_ctrl *)param; + struct sched_param sch_param = {.sched_priority = 1}; + u32 timeout = 0; + + sched_setscheduler(current, SCHED_RR, &sch_param); + while (1) { + wait_for_completion_interruptible(&ctrl->event); + if (ctrl->thread_close) { + while (!kthread_should_stop() && (timeout < 1000)) { + timeout++; + msleep(1); + } + break; + } + wakeup_event_handler(ctrl); + enable_irq(ctrl->wakeup_irq); + if ((ctrl->usb_irq > 0) && (ctrl->wakeup_irq != ctrl->usb_irq)) + enable_irq(ctrl->usb_irq); + } + return 0; +} + +static int wakeup_dev_probe(struct platform_device *pdev) +{ + struct fsl_usb2_wakeup_platform_data *pdata; + struct wakeup_ctrl *ctrl = NULL; + int status; + unsigned long interrupt_flag; + + printk(KERN_INFO "IMX usb wakeup probe\n"); + + if (!pdev || !pdev->dev.platform_data) + return -ENODEV; + ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL); + if (!ctrl) + return -ENOMEM; + pdata = pdev->dev.platform_data; + ctrl->pdata = pdata; + init_waitqueue_head(&pdata->wq); + pdata->usb_wakeup_is_pending = false; + + init_completion(&ctrl->event); + /* Currently, both mx5x and mx6q uses usb controller's irq + * as wakeup irq. + */ + ctrl->wakeup_irq = platform_get_irq(pdev, 1); + ctrl->usb_irq = platform_get_irq(pdev, 1); + pdata->wakeup_irq = ctrl->wakeup_irq; + pdata->usb_irq = ctrl->usb_irq; + ctrl->thread_close = false; + if (ctrl->wakeup_irq != ctrl->usb_irq) + interrupt_flag = IRQF_DISABLED; + else + interrupt_flag = IRQF_SHARED; + status = request_irq(ctrl->wakeup_irq, usb_wakeup_handler, interrupt_flag, "usb_wakeup", (void *)ctrl); + if (status) + goto error1; + + ctrl->thread = kthread_run(wakeup_event_thread, (void *)ctrl, "usb_wakeup thread"); + status = IS_ERR(ctrl->thread) ? -1 : 0; + if (status) + goto error2; + platform_set_drvdata(pdev, ctrl); + + printk(KERN_DEBUG "the wakeup pdata is 0x%p\n", pdata); + return 0; +error2: + free_irq(ctrl->wakeup_irq, (void *)ctrl); +error1: + kfree(ctrl); + return status; +} + +static int wakeup_dev_exit(struct platform_device *pdev) +{ + struct wakeup_ctrl *wctrl = platform_get_drvdata(pdev); + + wctrl->thread_close = true; + complete(&wctrl->event); + kthread_stop(wctrl->thread); + free_irq(wctrl->wakeup_irq, (void *)wctrl); + kfree(wctrl); + + return 0; +} +static struct platform_driver wakeup_d = { + .probe = wakeup_dev_probe, + .remove = wakeup_dev_exit, + .driver = { + .name = "usb-wakeup", + }, +}; + +static int __init wakeup_dev_init(void) +{ + return platform_driver_register(&wakeup_d); +} +static void __exit wakeup_dev_uninit(void) +{ + platform_driver_unregister(&wakeup_d); +} + +subsys_initcall(wakeup_dev_init); +module_exit(wakeup_dev_uninit); + diff --git a/arch/arm/plat-mxc/utmixc.c b/arch/arm/plat-mxc/utmixc.c new file mode 100755 index 00000000..227943ba --- /dev/null +++ b/arch/arm/plat-mxc/utmixc.c @@ -0,0 +1,91 @@ +/* + * Copyright (C) 2005-2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/device.h> +#include <linux/errno.h> +#include <linux/init.h> +#include <linux/err.h> +#include <linux/platform_device.h> +#include <linux/fsl_devices.h> +#include <linux/pmic_external.h> +#include <linux/usb/fsl_xcvr.h> + +#include <mach/hardware.h> +#include <mach/arc_otg.h> +#include <asm/mach-types.h> + +static void usb_utmi_init(struct fsl_xcvr_ops *this) +{ +#if defined(CONFIG_MXC_PMIC_MC13892_MODULE) || defined(CONFIG_MXC_PMIC_MC13892) + if (machine_is_mx51_3ds()) { + unsigned int value; + + /* VUSBIN */ + pmic_read_reg(REG_USB1, &value, 0xffffff); + value |= 0x1; + value |= (0x1 << 3); + pmic_write_reg(REG_USB1, value, 0xffffff); + } +#endif +} + +static void usb_utmi_uninit(struct fsl_xcvr_ops *this) +{ +} + +/*! + * set vbus power + * + * @param view viewport register + * @param on power on or off + */ +static void set_power(struct fsl_xcvr_ops *this, + struct fsl_usb2_platform_data *pdata, int on) +{ + pr_debug("real %s(on=%d) pdata=0x%p\n", __func__, on, pdata); + if (pdata && pdata->platform_driver_vbus) + pdata->platform_driver_vbus(on); +} + +static struct fsl_xcvr_ops utmi_ops = { + .name = "utmi", + .xcvr_type = PORTSC_PTS_UTMI, + .init = usb_utmi_init, + .uninit = usb_utmi_uninit, + .set_vbus_power = set_power, +}; + +extern void fsl_usb_xcvr_register(struct fsl_xcvr_ops *xcvr_ops); + +static int __init utmixc_init(void) +{ + fsl_usb_xcvr_register(&utmi_ops); + return 0; +} + +extern void fsl_usb_xcvr_unregister(struct fsl_xcvr_ops *xcvr_ops); + +static void __exit utmixc_exit(void) +{ + fsl_usb_xcvr_unregister(&utmi_ops); +} + +subsys_initcall(utmixc_init); +module_exit(utmixc_exit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("utmi xcvr driver"); +MODULE_LICENSE("GPL"); |