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authorGabor Juhos <juhosg@openwrt.org>2016-03-21 13:15:16 +0000
committerGabor Juhos <juhosg@openwrt.org>2016-03-21 13:15:16 +0000
commit8cee8ec41aec732dc1a89ca835ab8f180f91cff9 (patch)
treeee8e71805501f5bdba72aa6669a776a613748129
parent8c4d4881623ba525dd8b1406eaac5a9977f1a40a (diff)
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adm5120: lzma-loader: fix cache invalidation
The current code only partially invalidates both caches because the cache size and cache-line size values are incorrectly passed to the C code. Fix the assembly code to pass the arguments in the correct order. Compile tested only. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> git-svn-id: svn://svn.openwrt.org/openwrt/trunk@49058 3c298f89-4303-0410-b956-a3cf2f4a3e73
-rw-r--r--target/linux/adm5120/image/lzma-loader/src/head.S8
1 files changed, 4 insertions, 4 deletions
diff --git a/target/linux/adm5120/image/lzma-loader/src/head.S b/target/linux/adm5120/image/lzma-loader/src/head.S
index 329f437382..9f82fabdc2 100644
--- a/target/linux/adm5120/image/lzma-loader/src/head.S
+++ b/target/linux/adm5120/image/lzma-loader/src/head.S
@@ -195,10 +195,10 @@ noic:
sw a2, 8(sp)
sw a3, 12(sp)
#endif
- sw s3, 16(sp) /* icache line size */
- sw s4, 20(sp) /* icache size */
- sw s1, 24(sp) /* dcache line size */
- sw s2, 28(sp) /* dcache size */
+ sw s4, 16(sp) /* icache size */
+ sw s3, 20(sp) /* icache line size */
+ sw s2, 24(sp) /* dcache size */
+ sw s1, 28(sp) /* dcache line size */
/* jump to the decompressor routine */
la t0, decompress_entry