[package] mac80211: add preliminary support for the AR913x SoCs

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@13835 3c298f89-4303-0410-b956-a3cf2f4a3e73

1 files changed, 74 insertions, 0 deletions

diff --git a/package/mac80211/patches/403-ath9k-introduce-bus-specific-cache-size-routine.patch b/package/mac80211/patches/403-ath9k-introduce-bus-specific-cache-size-routine.patch
new file mode 100644
index 0000000000..30bdcd5e17
--- /dev/null
+++ b/package/mac80211/patches/403-ath9k-introduce-bus-specific-cache-size-routine.patch
@@ -0,0 +1,74 @@
+From a81f936d72caabbcf5698a6636185a8f6630d692 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Fri, 2 Jan 2009 16:08:22 +0100
+Subject: [RFC 03/12] ath9k: introduce bus specific cache size routine
+
+The PCI specific bus_read_cachesize routine won't work on the AHB bus,
+we have to replace it with a suitable one later.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
+---
+ drivers/net/wireless/ath9k/core.h |    7 +++++++
+ drivers/net/wireless/ath9k/main.c |    8 +++++---
+ 2 files changed, 12 insertions(+), 3 deletions(-)
+
+--- a/drivers/net/wireless/ath9k/core.h
++++ b/drivers/net/wireless/ath9k/core.h
+@@ -721,6 +721,8 @@ struct ath_bus_ops {
+ 
+ 	u32		(*reg_read)(struct ath_hal *ah, unsigned reg);
+ 	void		(*reg_write)(struct ath_hal *ah, unsigned reg, u32 val);
++
++	void		(*read_cachesize)(struct ath_softc *sc, int *csz);
+ };
+ 
+ struct ath_softc {
+@@ -843,4 +845,9 @@ static inline void ath_reg_write(struct 
+ 	sc->bus_ops->reg_write(ah, reg, val);
+ }
+ 
++static inline void ath_read_cachesize(struct ath_softc *sc, int *csz)
++{
++	sc->bus_ops->read_cachesize(sc, csz);
++}
++
+ #endif /* CORE_H */
+--- a/drivers/net/wireless/ath9k/main.c
++++ b/drivers/net/wireless/ath9k/main.c
+@@ -41,8 +41,7 @@ static struct pci_device_id ath_pci_id_t
+ static void ath_detach(struct ath_softc *sc);
+ 
+ /* return bus cachesize in 4B word units */
+-
+-static void bus_read_cachesize(struct ath_softc *sc, int *csz)
++static void ath_pci_read_cachesize(struct ath_softc *sc, int *csz)
+ {
+ 	u8 u8tmp;
+ 
+@@ -59,6 +58,7 @@ static void bus_read_cachesize(struct at
+ 		*csz = DEFAULT_CACHELINE >> 2;   /* Use the default size */
+ }
+ 
++
+ static void ath_setcurmode(struct ath_softc *sc, enum wireless_mode mode)
+ {
+ 	sc->cur_rate_table = sc->hw_rate_table[mode];
+@@ -1347,7 +1347,7 @@ static int ath_init(u16 devid, struct at
+ 	 * Cache line size is used to size and align various
+ 	 * structures used to communicate with the hardware.
+ 	 */
+-	bus_read_cachesize(sc, &csz);
++	ath_read_cachesize(sc, &csz);
+ 	/* XXX assert csz is non-zero */
+ 	sc->sc_cachelsz = csz << 2;	/* convert to bytes */
+ 
+@@ -2618,6 +2618,8 @@ static struct ath_bus_ops ath_pci_bus_op
+ 
+ 	.reg_read = ath_pci_reg_read,
+ 	.reg_write = ath_pci_reg_write,
++
++	.read_cachesize = ath_pci_read_cachesize,
+ };
+ 
+ static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)