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authorJohn Crispin <blogic@openwrt.org>2014-07-20 17:30:32 +0000
committerJohn Crispin <blogic@openwrt.org>2014-07-20 17:30:32 +0000
commit64b0959222839e9459d279be4de3f630cb9ebbb8 (patch)
treedef1dda8f74fc045cd1fd5459336030a67db86f2 /target/linux/ar71xx/files/arch/mips
parent1522d47c2158b419242a8355142f99df85cc84d9 (diff)
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ar71xx: add kernel support for the OpenMesh OM5P board
Signed-off-by: Marek Lindner <marek@open-mesh.com> [sven@open-mesh.com: Rebased] Signed-off-by: Sven Eckelmann <sven@open-mesh.com> git-svn-id: svn://svn.openwrt.org/openwrt/trunk@41769 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/ar71xx/files/arch/mips')
-rw-r--r--target/linux/ar71xx/files/arch/mips/ath79/mach-om5p.c122
1 files changed, 122 insertions, 0 deletions
diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-om5p.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-om5p.c
new file mode 100644
index 0000000000..c1cfa18098
--- /dev/null
+++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-om5p.c
@@ -0,0 +1,122 @@
+/*
+ * OpenMesh OM5P support
+ *
+ * Copyright (C) 2013 Marek Lindner <marek@open-mesh.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <linux/gpio.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/platform_device.h>
+
+#include <asm/mach-ath79/ar71xx_regs.h>
+#include <asm/mach-ath79/ath79.h>
+
+#include "common.h"
+#include "dev-ap9x-pci.h"
+#include "dev-eth.h"
+#include "dev-gpio-buttons.h"
+#include "dev-leds-gpio.h"
+#include "dev-m25p80.h"
+#include "dev-wmac.h"
+#include "machtypes.h"
+
+#define OM5P_GPIO_LED_POWER 13
+#define OM5P_GPIO_LED_GREEN 16
+#define OM5P_GPIO_LED_RED 19
+#define OM5P_GPIO_LED_YELLOW 17
+#define OM5P_GPIO_LED_LAN 14
+#define OM5P_GPIO_LED_WAN 15
+#define OM5P_GPIO_BTN_RESET 4
+
+#define OM5P_KEYS_POLL_INTERVAL 20 /* msecs */
+#define OM5P_KEYS_DEBOUNCE_INTERVAL (3 * OM5P_KEYS_POLL_INTERVAL)
+
+#define OM5P_WMAC_CALDATA_OFFSET 0x1000
+
+static struct gpio_led om5p_leds_gpio[] __initdata = {
+ {
+ .name = "om5p:blue:power",
+ .gpio = OM5P_GPIO_LED_POWER,
+ .active_low = 1,
+ }, {
+ .name = "om5p:red:wifi",
+ .gpio = OM5P_GPIO_LED_RED,
+ .active_low = 1,
+ }, {
+ .name = "om5p:yellow:wifi",
+ .gpio = OM5P_GPIO_LED_YELLOW,
+ .active_low = 1,
+ }, {
+ .name = "om5p:green:wifi",
+ .gpio = OM5P_GPIO_LED_GREEN,
+ .active_low = 1,
+ }, {
+ .name = "om5p:blue:lan",
+ .gpio = OM5P_GPIO_LED_LAN,
+ .active_low = 1,
+ }, {
+ .name = "om5p:blue:wan",
+ .gpio = OM5P_GPIO_LED_WAN,
+ .active_low = 1,
+ }
+};
+
+static struct gpio_keys_button om5p_gpio_keys[] __initdata = {
+ {
+ .desc = "reset",
+ .type = EV_KEY,
+ .code = KEY_RESTART,
+ .debounce_interval = OM5P_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = OM5P_GPIO_BTN_RESET,
+ .active_low = 1,
+ }
+};
+
+static struct flash_platform_data om5p_flash_data = {
+ .type = "mx25l12805d",
+};
+
+static void __init om5p_setup(void)
+{
+ u8 *art = (u8 *)KSEG1ADDR(0x1fff0000);
+ u8 mac[6];
+
+ /* make lan / wan leds software controllable */
+ ath79_gpio_output_select(OM5P_GPIO_LED_LAN, AR934X_GPIO_OUT_GPIO);
+ ath79_gpio_output_select(OM5P_GPIO_LED_WAN, AR934X_GPIO_OUT_GPIO);
+
+ ath79_register_m25p80(&om5p_flash_data);
+ ath79_register_leds_gpio(-1, ARRAY_SIZE(om5p_leds_gpio),
+ om5p_leds_gpio);
+ ath79_register_gpio_keys_polled(-1, OM5P_KEYS_POLL_INTERVAL,
+ ARRAY_SIZE(om5p_gpio_keys),
+ om5p_gpio_keys);
+
+ ath79_init_mac(mac, art, 2);
+ ath79_register_wmac(art + OM5P_WMAC_CALDATA_OFFSET, mac);
+
+ ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_PHY_SWAP);
+ ath79_register_mdio(1, 0x0);
+
+ ath79_init_mac(ath79_eth0_data.mac_addr, art, 0);
+ ath79_init_mac(ath79_eth1_data.mac_addr, art, 1);
+
+ /* GMAC0 is connected to the PHY0 of the internal switch */
+ ath79_switch_data.phy4_mii_en = 1;
+ ath79_switch_data.phy_poll_mask = BIT(0);
+ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
+ ath79_eth0_data.phy_mask = BIT(0);
+ ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev;
+ ath79_register_eth(0);
+
+ /* GMAC1 is connected to the internal switch */
+ ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
+ ath79_register_eth(1);
+}
+
+MIPS_MACHINE(ATH79_MACH_OM5P, "OM5P", "OpenMesh OM5P", om5p_setup);