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| author | Jonas Gorski <jogo@openwrt.org> | 2014-08-01 21:56:35 +0000 |
|---|---|---|
| committer | Jonas Gorski <jogo@openwrt.org> | 2014-08-01 21:56:35 +0000 |
| commit | 6354265168e5c7b593c6579c3a211cd94e914f94 (patch) | |
| tree | 88a9fb14dbdecfde63ca70c49860b2269f0f3886 /target/linux/brcm63xx/patches-3.10/331-MIPS-BCM63XX-define-variant-id-field.patch | |
| parent | 9762c605fe5fe106010f441c9daf42b08c1fcad8 (diff) | |
| download | master-187ad058-6354265168e5c7b593c6579c3a211cd94e914f94.tar.gz master-187ad058-6354265168e5c7b593c6579c3a211cd94e914f94.tar.bz2 master-187ad058-6354265168e5c7b593c6579c3a211cd94e914f94.zip | |
brcm63xx: switch to 3.14
Now that BB is branched off, we can now switch to 3.14 and start
breaking stuff again.
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@41941 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/brcm63xx/patches-3.10/331-MIPS-BCM63XX-define-variant-id-field.patch')
| -rw-r--r-- | target/linux/brcm63xx/patches-3.10/331-MIPS-BCM63XX-define-variant-id-field.patch | 23 |
1 files changed, 0 insertions, 23 deletions
diff --git a/target/linux/brcm63xx/patches-3.10/331-MIPS-BCM63XX-define-variant-id-field.patch b/target/linux/brcm63xx/patches-3.10/331-MIPS-BCM63XX-define-variant-id-field.patch deleted file mode 100644 index 2e21c65009..0000000000 --- a/target/linux/brcm63xx/patches-3.10/331-MIPS-BCM63XX-define-variant-id-field.patch +++ /dev/null @@ -1,23 +0,0 @@ -From 3bd8e2535265f06f79ed9c0ad788405441e091dc Mon Sep 17 00:00:00 2001 -From: Jonas Gorski <jogo@openwrt.org> -Date: Sat, 7 Dec 2013 14:22:41 +0100 -Subject: [PATCH 21/45] MIPS: BCM63XX: define variant id field - -Some SoC have a variant id field in the chip id register. - -Signed-off-by: Jonas Gorski <jogo@openwrt.org> ---- - arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h -+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h -@@ -9,6 +9,8 @@ - #define PERF_REV_REG 0x0 - #define REV_CHIPID_SHIFT 16 - #define REV_CHIPID_MASK (0xffff << REV_CHIPID_SHIFT) -+#define REV_VARID_SHIFT 12 -+#define REV_VARID_MASK (0xf << REV_VARID_SHIFT) - #define REV_REVID_SHIFT 0 - #define REV_REVID_MASK (0xff << REV_REVID_SHIFT) - |