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author | Imre Kaloz <kaloz@openwrt.org> | 2011-07-08 09:33:13 +0000 |
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committer | Imre Kaloz <kaloz@openwrt.org> | 2011-07-08 09:33:13 +0000 |
commit | 7844e358ab833c58a338175046188656179d451d (patch) | |
tree | 431b8960a1afd696ac9a51a18c735bcc610e9bb7 /target/linux/generic/patches-3.0/994-mpcore_wdt_fix_timer_mode_setup.patch | |
parent | f5c37ab96a57d5e0d7867aecc64c5a4d70922495 (diff) | |
download | master-187ad058-7844e358ab833c58a338175046188656179d451d.tar.gz master-187ad058-7844e358ab833c58a338175046188656179d451d.tar.bz2 master-187ad058-7844e358ab833c58a338175046188656179d451d.zip |
[generic/3.0]: add mpcore_wdt fixes
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@27557 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/generic/patches-3.0/994-mpcore_wdt_fix_timer_mode_setup.patch')
-rw-r--r-- | target/linux/generic/patches-3.0/994-mpcore_wdt_fix_timer_mode_setup.patch | 57 |
1 files changed, 57 insertions, 0 deletions
diff --git a/target/linux/generic/patches-3.0/994-mpcore_wdt_fix_timer_mode_setup.patch b/target/linux/generic/patches-3.0/994-mpcore_wdt_fix_timer_mode_setup.patch new file mode 100644 index 0000000000..009092376f --- /dev/null +++ b/target/linux/generic/patches-3.0/994-mpcore_wdt_fix_timer_mode_setup.patch @@ -0,0 +1,57 @@ +Allow watchdog to set its iterrupt as pending when it is configured +for timer mode (in other words, allow emitting interrupt). +Also add macros for all Watchdog Control Register flags. + +Signed-off-by: Vitaly Kuzmichev <vkuzmichev@mvista.com> +--- + arch/arm/include/asm/smp_twd.h | 6 ++++++ + drivers/watchdog/mpcore_wdt.c | 15 +++++++++++---- + 2 files changed, 17 insertions(+), 4 deletions(-) + +--- a/arch/arm/include/asm/smp_twd.h ++++ b/arch/arm/include/asm/smp_twd.h +@@ -18,6 +18,12 @@ + #define TWD_TIMER_CONTROL_PERIODIC (1 << 1) + #define TWD_TIMER_CONTROL_IT_ENABLE (1 << 2) + ++#define TWD_WDOG_CONTROL_ENABLE (1 << 0) ++#define TWD_WDOG_CONTROL_PERIODIC (1 << 1) ++#define TWD_WDOG_CONTROL_IT_ENABLE (1 << 2) ++#define TWD_WDOG_CONTROL_TIMER_MODE (0 << 3) ++#define TWD_WDOG_CONTROL_WATCHDOG_MODE (1 << 3) ++ + struct clock_event_device; + + extern void __iomem *twd_base; +--- a/drivers/watchdog/mpcore_wdt.c ++++ b/drivers/watchdog/mpcore_wdt.c +@@ -118,18 +118,25 @@ static void mpcore_wdt_stop(struct mpcor + + static void mpcore_wdt_start(struct mpcore_wdt *wdt) + { ++ u32 mode; ++ + dev_printk(KERN_INFO, wdt->dev, "enabling watchdog.\n"); + + /* This loads the count register but does NOT start the count yet */ + mpcore_wdt_keepalive(wdt); + ++ /* Setup watchdog - prescale=256, enable=1 */ ++ mode = (255 << 8) | TWD_WDOG_CONTROL_ENABLE; ++ + if (mpcore_noboot) { +- /* Enable watchdog - prescale=256, watchdog mode=0, enable=1 */ +- writel(0x0000FF01, wdt->base + TWD_WDOG_CONTROL); ++ /* timer mode, send interrupt */ ++ mode |= TWD_WDOG_CONTROL_TIMER_MODE | ++ TWD_WDOG_CONTROL_IT_ENABLE; + } else { +- /* Enable watchdog - prescale=256, watchdog mode=1, enable=1 */ +- writel(0x0000FF09, wdt->base + TWD_WDOG_CONTROL); ++ /* watchdog mode */ ++ mode |= TWD_WDOG_CONTROL_WATCHDOG_MODE; + } ++ writel(mode, wdt->base + TWD_WDOG_CONTROL); + } + + static int mpcore_wdt_set_heartbeat(int t) |