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author | Felix Fietkau <nbd@openwrt.org> | 2008-06-28 19:53:41 +0000 |
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committer | Felix Fietkau <nbd@openwrt.org> | 2008-06-28 19:53:41 +0000 |
commit | f5345b1aabed2f76933ba40b9be672f639a62b5c (patch) | |
tree | a2b20d7ed8890acb2de9a5436db408b52a2f1aac /target/linux/ifxmips/image/u-boot/files/board/danube/ddr_settings_r111.h | |
parent | 68f8bcd23666dd5ad3e58e2fe9a79ff1d57e0746 (diff) | |
download | master-187ad058-f5345b1aabed2f76933ba40b9be672f639a62b5c.tar.gz master-187ad058-f5345b1aabed2f76933ba40b9be672f639a62b5c.tar.bz2 master-187ad058-f5345b1aabed2f76933ba40b9be672f639a62b5c.zip |
move ifxmips uboot to package/
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@11601 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/ifxmips/image/u-boot/files/board/danube/ddr_settings_r111.h')
-rw-r--r-- | target/linux/ifxmips/image/u-boot/files/board/danube/ddr_settings_r111.h | 50 |
1 files changed, 0 insertions, 50 deletions
diff --git a/target/linux/ifxmips/image/u-boot/files/board/danube/ddr_settings_r111.h b/target/linux/ifxmips/image/u-boot/files/board/danube/ddr_settings_r111.h deleted file mode 100644 index 385f7e4e58..0000000000 --- a/target/linux/ifxmips/image/u-boot/files/board/danube/ddr_settings_r111.h +++ /dev/null @@ -1,50 +0,0 @@ -/* Settings for Denali DDR SDRAM controller */
-/* Optimise for Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 29th April */
-#define MC_DC0_VALUE 0x1B1B
-#define MC_DC1_VALUE 0x0
-#define MC_DC2_VALUE 0x0
-#define MC_DC3_VALUE 0x0
-#define MC_DC4_VALUE 0x0
-#define MC_DC5_VALUE 0x200
-#define MC_DC6_VALUE 0x605
-#define MC_DC7_VALUE 0x303
-#define MC_DC8_VALUE 0x102
-#define MC_DC9_VALUE 0x70a
-#define MC_DC10_VALUE 0x203
-#define MC_DC11_VALUE 0xc02
-#define MC_DC12_VALUE 0x1C8
-#define MC_DC13_VALUE 0x1
-#define MC_DC14_VALUE 0x0
-#define MC_DC15_VALUE 0xf3c /* WDQS tuning for clk_wr*/
-#define MC_DC16_VALUE 0xC800
-#define MC_DC17_VALUE 0xd
-#define MC_DC18_VALUE 0x300
-#define MC_DC19_VALUE 0x200
-#define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */
-#define MC_DC21_VALUE 0x1200
-#define MC_DC22_VALUE 0x1212
-#define MC_DC23_VALUE 0x0
-#define MC_DC24_VALUE 0x5e /* WDQS Tuning for DQS */
-#define MC_DC25_VALUE 0x0
-#define MC_DC26_VALUE 0x0
-#define MC_DC27_VALUE 0x0
-#define MC_DC28_VALUE 0x510
-#define MC_DC29_VALUE 0x2d89
-#define MC_DC30_VALUE 0x8300
-#define MC_DC31_VALUE 0x0
-#define MC_DC32_VALUE 0x0
-#define MC_DC33_VALUE 0x0
-#define MC_DC34_VALUE 0x0
-#define MC_DC35_VALUE 0x0
-#define MC_DC36_VALUE 0x0
-#define MC_DC37_VALUE 0x0
-#define MC_DC38_VALUE 0x0
-#define MC_DC39_VALUE 0x0
-#define MC_DC40_VALUE 0x0
-#define MC_DC41_VALUE 0x0
-#define MC_DC42_VALUE 0x0
-#define MC_DC43_VALUE 0x0
-#define MC_DC44_VALUE 0x0
-#define MC_DC45_VALUE 0x500
-//#define MC_DC45_VALUE 0x400
-#define MC_DC46_VALUE 0x0
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