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author | Luka Perkov <luka@openwrt.org> | 2013-12-19 02:03:16 +0000 |
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committer | Luka Perkov <luka@openwrt.org> | 2013-12-19 02:03:16 +0000 |
commit | 145ab2e7ea4fa7881377919210455f079769cbd4 (patch) | |
tree | 0b48e9c1f4924d556c76b0916d58e1bfd6d94a84 /target/linux/imx6/patches-3.10/0030-PCI-imx6-remove-outbound-io-mem-ATU-region-mapping.patch | |
parent | d2908ef8883da1c4bcb9f7e682d689c9dd18fae6 (diff) | |
download | master-187ad058-145ab2e7ea4fa7881377919210455f079769cbd4.tar.gz master-187ad058-145ab2e7ea4fa7881377919210455f079769cbd4.tar.bz2 master-187ad058-145ab2e7ea4fa7881377919210455f079769cbd4.zip |
imx6: proper fix for io-remap
The previous patch was not the proper fix for PCI devices that require io
resources. The new patch is the proper fix backported from mainline.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@39133 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/imx6/patches-3.10/0030-PCI-imx6-remove-outbound-io-mem-ATU-region-mapping.patch')
-rw-r--r-- | target/linux/imx6/patches-3.10/0030-PCI-imx6-remove-outbound-io-mem-ATU-region-mapping.patch | 106 |
1 files changed, 0 insertions, 106 deletions
diff --git a/target/linux/imx6/patches-3.10/0030-PCI-imx6-remove-outbound-io-mem-ATU-region-mapping.patch b/target/linux/imx6/patches-3.10/0030-PCI-imx6-remove-outbound-io-mem-ATU-region-mapping.patch deleted file mode 100644 index bc9ad3c7a7..0000000000 --- a/target/linux/imx6/patches-3.10/0030-PCI-imx6-remove-outbound-io-mem-ATU-region-mapping.patch +++ /dev/null @@ -1,106 +0,0 @@ -From 93d2b52fe73294d59bbce3a6d4da031647b1f3b2 Mon Sep 17 00:00:00 2001 -From: Tim Harvey <tharvey@gateworks.com> -Date: Tue, 22 Oct 2013 15:56:40 -0700 -Subject: [PATCH] PCI: imx6: remove outbound io/mem ATU region mapping - -The IMX6 iATU is used for address translation between the AXI bus -address space and PCI address space. This is used for type0 and type1 -config cycles but is not necessary for outbound io/mem regions. - -This patch removes the calls that inappropriately re-configures the ATU -viewport for outbound memory and IO after config cycles and removes them -altogether as they are not necessary. - -This resolves issues with PCI devices behind switches and has been tested with -a Gige device behind a PLX PEX860x switch. - -Signed-off-by: Tim Harvey <tharvey@gateworks.com> ---- - drivers/pci/host/pcie-designware.c | 41 +++--------------------------------- - 1 file changed, 3 insertions(+), 38 deletions(-) - ---- a/drivers/pci/host/pcie-designware.c -+++ b/drivers/pci/host/pcie-designware.c -@@ -43,7 +43,6 @@ - #define PCIE_ATU_VIEWPORT 0x900 - #define PCIE_ATU_REGION_INBOUND (0x1 << 31) - #define PCIE_ATU_REGION_OUTBOUND (0x0 << 31) --#define PCIE_ATU_REGION_INDEX1 (0x1 << 0) - #define PCIE_ATU_REGION_INDEX0 (0x0 << 0) - #define PCIE_ATU_CR1 0x904 - #define PCIE_ATU_TYPE_MEM (0x0 << 0) -@@ -264,8 +263,8 @@ static void dw_pcie_prog_viewport_cfg0(s - - static void dw_pcie_prog_viewport_cfg1(struct pcie_port *pp, u32 busdev) - { -- /* Program viewport 1 : OUTBOUND : CFG1 */ -- dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1, -+ /* Program viewport 0 : OUTBOUND : CFG1 */ -+ dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0, - PCIE_ATU_VIEWPORT); - dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG1, PCIE_ATU_CR1); - dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2); -@@ -275,38 +274,8 @@ static void dw_pcie_prog_viewport_cfg1(s - PCIE_ATU_LIMIT); - dw_pcie_writel_rc(pp, busdev, PCIE_ATU_LOWER_TARGET); - dw_pcie_writel_rc(pp, 0, PCIE_ATU_UPPER_TARGET); --} -- --static void dw_pcie_prog_viewport_mem_outbound(struct pcie_port *pp) --{ -- /* Program viewport 0 : OUTBOUND : MEM */ -- dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0, -- PCIE_ATU_VIEWPORT); -- dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_MEM, PCIE_ATU_CR1); -- dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2); -- dw_pcie_writel_rc(pp, pp->mem_base, PCIE_ATU_LOWER_BASE); -- dw_pcie_writel_rc(pp, (pp->mem_base >> 32), PCIE_ATU_UPPER_BASE); -- dw_pcie_writel_rc(pp, pp->mem_base + pp->config.mem_size - 1, -- PCIE_ATU_LIMIT); -- dw_pcie_writel_rc(pp, pp->config.mem_bus_addr, PCIE_ATU_LOWER_TARGET); -- dw_pcie_writel_rc(pp, upper_32_bits(pp->config.mem_bus_addr), -- PCIE_ATU_UPPER_TARGET); --} -- --static void dw_pcie_prog_viewport_io_outbound(struct pcie_port *pp) --{ -- /* Program viewport 1 : OUTBOUND : IO */ -- dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1, -- PCIE_ATU_VIEWPORT); -- dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_IO, PCIE_ATU_CR1); -+ dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG1, PCIE_ATU_CR1); - dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2); -- dw_pcie_writel_rc(pp, pp->io_base, PCIE_ATU_LOWER_BASE); -- dw_pcie_writel_rc(pp, (pp->io_base >> 32), PCIE_ATU_UPPER_BASE); -- dw_pcie_writel_rc(pp, pp->io_base + pp->config.io_size - 1, -- PCIE_ATU_LIMIT); -- dw_pcie_writel_rc(pp, pp->config.io_bus_addr, PCIE_ATU_LOWER_TARGET); -- dw_pcie_writel_rc(pp, upper_32_bits(pp->config.io_bus_addr), -- PCIE_ATU_UPPER_TARGET); - } - - static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus, -@@ -322,11 +291,9 @@ static int dw_pcie_rd_other_conf(struct - if (bus->parent->number == pp->root_bus_nr) { - dw_pcie_prog_viewport_cfg0(pp, busdev); - ret = cfg_read(pp->va_cfg0_base + address, where, size, val); -- dw_pcie_prog_viewport_mem_outbound(pp); - } else { - dw_pcie_prog_viewport_cfg1(pp, busdev); - ret = cfg_read(pp->va_cfg1_base + address, where, size, val); -- dw_pcie_prog_viewport_io_outbound(pp); - } - - return ret; -@@ -345,11 +312,9 @@ static int dw_pcie_wr_other_conf(struct - if (bus->parent->number == pp->root_bus_nr) { - dw_pcie_prog_viewport_cfg0(pp, busdev); - ret = cfg_write(pp->va_cfg0_base + address, where, size, val); -- dw_pcie_prog_viewport_mem_outbound(pp); - } else { - dw_pcie_prog_viewport_cfg1(pp, busdev); - ret = cfg_write(pp->va_cfg1_base + address, where, size, val); -- dw_pcie_prog_viewport_io_outbound(pp); - } - - return ret; |