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| author | Jonas Gorski <jogo@openwrt.org> | 2015-02-27 17:40:17 +0000 |
|---|---|---|
| committer | Jonas Gorski <jogo@openwrt.org> | 2015-02-27 17:40:17 +0000 |
| commit | aa4d5abef003bad1eea90560ab8a5d507a349de0 (patch) | |
| tree | a5593f9bedc20d4b71279f3e1babbba599f83e16 /target/linux/lantiq | |
| parent | c5696515d1ae7d88c59291367198ed3a73d5de59 (diff) | |
| download | master-187ad058-aa4d5abef003bad1eea90560ab8a5d507a349de0.tar.gz master-187ad058-aa4d5abef003bad1eea90560ab8a5d507a349de0.tar.bz2 master-187ad058-aa4d5abef003bad1eea90560ab8a5d507a349de0.zip | |
b53: fix mmap register read/writes > 32 bit
For bcm63xx integrated switches, broadcom changed the data endianess
to match the system endianess. But this only applies to within one word,
which causes 48/64 bit values to be still split into their "litte endian"
groups.
E.g. 48 bit values (with 5 being the most significant byte) aligned
0x00 ..01 or 0123
0x04 2345 45..
will become
0x00 ..10 resp. 3210
0x04 5432 54..
Likewise for 64 bit values.
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@44568 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/lantiq')
0 files changed, 0 insertions, 0 deletions