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author | Florian Fainelli <florian@openwrt.org> | 2013-01-17 22:29:13 +0000 |
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committer | Florian Fainelli <florian@openwrt.org> | 2013-01-17 22:29:13 +0000 |
commit | 005e0ee7c98fa04776cffb044b6c5d2bea2cb491 (patch) | |
tree | 28aaf81b887b4bcd8212e99aee3297f411265556 /target/linux/mvebu/patches-3.8/042-arm_mvebu_add_pcie_dt_a370_db.patch | |
parent | 4d55ef2877053cbcf69feee2009628d31a7c65f6 (diff) | |
download | master-187ad058-005e0ee7c98fa04776cffb044b6c5d2bea2cb491.tar.gz master-187ad058-005e0ee7c98fa04776cffb044b6c5d2bea2cb491.tar.bz2 master-187ad058-005e0ee7c98fa04776cffb044b6c5d2bea2cb491.zip |
mvebu: add preliminary support for PCI express
Signed-off-by: Florian Fainelli <florian@openwrt.org>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@35211 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/mvebu/patches-3.8/042-arm_mvebu_add_pcie_dt_a370_db.patch')
-rw-r--r-- | target/linux/mvebu/patches-3.8/042-arm_mvebu_add_pcie_dt_a370_db.patch | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/target/linux/mvebu/patches-3.8/042-arm_mvebu_add_pcie_dt_a370_db.patch b/target/linux/mvebu/patches-3.8/042-arm_mvebu_add_pcie_dt_a370_db.patch new file mode 100644 index 0000000000..1a853f35c7 --- /dev/null +++ b/target/linux/mvebu/patches-3.8/042-arm_mvebu_add_pcie_dt_a370_db.patch @@ -0,0 +1,32 @@ +The Marvell evaluation board (DB) for the Armada 370 SoC has 2 +physical full-size PCIe slots, so we enable the corresponding PCIe +interfaces in the Device Tree. + +Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> +--- + arch/arm/boot/dts/armada-370-db.dts | 15 +++++++++++++++ + 1 file changed, 15 insertions(+) + +--- a/arch/arm/boot/dts/armada-370-db.dts ++++ b/arch/arm/boot/dts/armada-370-db.dts +@@ -82,5 +82,20 @@ + usb@d0051000 { + status = "okay"; + }; ++ ++ pcie-controller { ++ status = "okay"; ++ /* ++ * The two PCIe units are accessible through ++ * both standard PCIe slots and mini-PCIe ++ * slots on the board. ++ */ ++ pcie0@0xd0040000 { ++ status = "okay"; ++ }; ++ pcie1@0xd0080000 { ++ status = "okay"; ++ }; ++ }; + }; + }; |