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authorJohn Crispin <blogic@openwrt.org>2015-03-16 07:41:24 +0000
committerJohn Crispin <blogic@openwrt.org>2015-03-16 07:41:24 +0000
commitb34d1f6b435b05479c3ddee74be1ef428ae7455a (patch)
tree5517152c2f56e9778150440c47def9ed06b3eea2 /target/linux/sunxi/patches-3.14/115-dt-sun6i-fix-mod0-compat.patch
parentad966e5eaad945f22ffdfd404b58e0c3ef6cd9dc (diff)
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sunxi: drop 3.14 support
Signed-off-by: John Crispin <blogic@openwrt.org> git-svn-id: svn://svn.openwrt.org/openwrt/trunk@44824 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/sunxi/patches-3.14/115-dt-sun6i-fix-mod0-compat.patch')
-rw-r--r--target/linux/sunxi/patches-3.14/115-dt-sun6i-fix-mod0-compat.patch51
1 files changed, 0 insertions, 51 deletions
diff --git a/target/linux/sunxi/patches-3.14/115-dt-sun6i-fix-mod0-compat.patch b/target/linux/sunxi/patches-3.14/115-dt-sun6i-fix-mod0-compat.patch
deleted file mode 100644
index f2644a1df7..0000000000
--- a/target/linux/sunxi/patches-3.14/115-dt-sun6i-fix-mod0-compat.patch
+++ /dev/null
@@ -1,51 +0,0 @@
-From 95c1fe603fbea0fd01d98262bd5ff7d5442a86db Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Mon, 24 Feb 2014 17:29:06 +0100
-Subject: [PATCH] ARM: sun6i: dt: Fix mod0 compatible
-
-The module 0 clock compatibles were changed between the time the patch was sent
-and it was merged. Update the compatibles.
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- arch/arm/boot/dts/sun6i-a31.dtsi | 8 ++++----
- 1 file changed, 4 insertions(+), 4 deletions(-)
-
---- a/arch/arm/boot/dts/sun6i-a31.dtsi
-+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
-@@ -200,7 +200,7 @@
-
- spi0_clk: clk@01c200a0 {
- #clock-cells = <0>;
-- compatible = "allwinner,sun4i-mod0-clk";
-+ compatible = "allwinner,sun4i-a10-mod0-clk";
- reg = <0x01c200a0 0x4>;
- clocks = <&osc24M>, <&pll6>;
- clock-output-names = "spi0";
-@@ -208,7 +208,7 @@
-
- spi1_clk: clk@01c200a4 {
- #clock-cells = <0>;
-- compatible = "allwinner,sun4i-mod0-clk";
-+ compatible = "allwinner,sun4i-a10-mod0-clk";
- reg = <0x01c200a4 0x4>;
- clocks = <&osc24M>, <&pll6>;
- clock-output-names = "spi1";
-@@ -216,7 +216,7 @@
-
- spi2_clk: clk@01c200a8 {
- #clock-cells = <0>;
-- compatible = "allwinner,sun4i-mod0-clk";
-+ compatible = "allwinner,sun4i-a10-mod0-clk";
- reg = <0x01c200a8 0x4>;
- clocks = <&osc24M>, <&pll6>;
- clock-output-names = "spi2";
-@@ -224,7 +224,7 @@
-
- spi3_clk: clk@01c200ac {
- #clock-cells = <0>;
-- compatible = "allwinner,sun4i-mod0-clk";
-+ compatible = "allwinner,sun4i-a10-mod0-clk";
- reg = <0x01c200ac 0x4>;
- clocks = <&osc24M>, <&pll6>;
- clock-output-names = "spi3";