1 files changed, 0 insertions, 39 deletions
diff --git a/package/boot/uboot-sunxi/patches/002-sun5i-give-pll6-a-sane-value.patch b/package/boot/uboot-sunxi/patches/002-sun5i-give-pll6-a-sane-value.patch
deleted file mode 100644
index b4e0ee1847..0000000000
--- a/package/boot/uboot-sunxi/patches/002-sun5i-give-pll6-a-sane-value.patch
+++ /dev/null
@@ -1,39 +0,0 @@
-From 75ec90fda763b491e5169dcb6dce8abe3856d946 Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Sat, 14 Dec 2013 20:58:57 +0100
-Subject: [PATCH] sun5i: Give PLL6 a sane initial value
-
-The upstream kernel does not override PLL values as set by power-on-reset
-and/or the bootloader if it can avoid doing so.
-
-The power-on-reset value for PLL6 is 2400MHz, which does not actually work,
-the kernel does not know this and 2400 / 48 is 50 MHz, so the kernel happily
-tries to use it as is for mmc.
-
-Set PLL6 to a working frequency so that the kernel can use it. This fixes
-mmc in the upstream kernel not working on sun5i.
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- arch/arm/cpu/armv7/sunxi/clock.c | 5 +++++
- 1 file changed, 5 insertions(+)
-
-diff --git a/arch/arm/cpu/armv7/sunxi/clock.c b/arch/arm/cpu/armv7/sunxi/clock.c
-index 57b136d..b9dd608 100644
---- a/arch/arm/cpu/armv7/sunxi/clock.c
-+++ b/arch/arm/cpu/armv7/sunxi/clock.c
-@@ -43,6 +43,11 @@ static void clock_init_safe(void)
- 	sdelay(200);
- 	writel(AXI_DIV_1 << 0 | AHB_DIV_2 << 4 | APB0_DIV_1 << 8 |
- 	       CPU_CLK_SRC_PLL1 << 16, &ccm->cpu_ahb_apb0_cfg);
-+#ifdef CONFIG_SUN5I
-+	/* Power on reset default for PLL6 is 2400 MHz, which is faster then
-+	 * it can reliable do :|  Set it to a 600 MHz instead. */
-+	writel(0x21009900, &ccm->pll6_cfg);
-+#endif
- #ifdef CONFIG_SUN7I
- 	writel(0x1 << 6 | readl(&ccm->ahb_gate0), &ccm->ahb_gate0);
- 	writel(0x1 << 31 | readl(&ccm->pll6_cfg), &ccm->pll6_cfg);
--- 
-1.8.5.1
-