aboutsummaryrefslogtreecommitdiffstats
path: root/target/linux/brcm47xx/patches-2.6.34
diff options
context:
space:
mode:
Diffstat (limited to 'target/linux/brcm47xx/patches-2.6.34')
-rw-r--r--target/linux/brcm47xx/patches-2.6.34/220-bcm5354.patch6
-rw-r--r--target/linux/brcm47xx/patches-2.6.34/951-brcm4716-defines.patch2
2 files changed, 4 insertions, 4 deletions
diff --git a/target/linux/brcm47xx/patches-2.6.34/220-bcm5354.patch b/target/linux/brcm47xx/patches-2.6.34/220-bcm5354.patch
index a2691b008d..1d75e171d3 100644
--- a/target/linux/brcm47xx/patches-2.6.34/220-bcm5354.patch
+++ b/target/linux/brcm47xx/patches-2.6.34/220-bcm5354.patch
@@ -1,6 +1,6 @@
--- a/drivers/ssb/driver_chipcommon.c
+++ b/drivers/ssb/driver_chipcommon.c
-@@ -258,6 +258,8 @@ void ssb_chipco_resume(struct ssb_chipco
+@@ -260,6 +260,8 @@ void ssb_chipco_resume(struct ssb_chipco
void ssb_chipco_get_clockcpu(struct ssb_chipcommon *cc,
u32 *plltype, u32 *n, u32 *m)
{
@@ -9,7 +9,7 @@
*n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N);
*plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
switch (*plltype) {
-@@ -281,6 +283,8 @@ void ssb_chipco_get_clockcpu(struct ssb_
+@@ -283,6 +285,8 @@ void ssb_chipco_get_clockcpu(struct ssb_
void ssb_chipco_get_clockcontrol(struct ssb_chipcommon *cc,
u32 *plltype, u32 *n, u32 *m)
{
@@ -31,7 +31,7 @@
}
--- a/drivers/ssb/main.c
+++ b/drivers/ssb/main.c
-@@ -1070,6 +1070,8 @@ u32 ssb_clockspeed(struct ssb_bus *bus)
+@@ -1073,6 +1073,8 @@ u32 ssb_clockspeed(struct ssb_bus *bus)
if (bus->chip_id == 0x5365) {
rate = 100000000;
diff --git a/target/linux/brcm47xx/patches-2.6.34/951-brcm4716-defines.patch b/target/linux/brcm47xx/patches-2.6.34/951-brcm4716-defines.patch
index 5cc51100f8..482dbad02e 100644
--- a/target/linux/brcm47xx/patches-2.6.34/951-brcm4716-defines.patch
+++ b/target/linux/brcm47xx/patches-2.6.34/951-brcm4716-defines.patch
@@ -60,7 +60,7 @@
/* Enumeration space constants */
#define SSB_CORE_SIZE 0x1000 /* Size of a core MMIO area */
-@@ -452,5 +454,41 @@ enum {
+@@ -453,5 +455,41 @@ enum {
#define SSB_ADM_BASE2 0xFFFF0000 /* Type2 base address for the core */
#define SSB_ADM_BASE2_SHIFT 16