diff options
Diffstat (limited to 'target/linux/imx6/patches-3.12/0004-ARM-imx6q-use-common-soc-revision-helpers.patch')
| -rw-r--r-- | target/linux/imx6/patches-3.12/0004-ARM-imx6q-use-common-soc-revision-helpers.patch | 93 |
1 files changed, 93 insertions, 0 deletions
diff --git a/target/linux/imx6/patches-3.12/0004-ARM-imx6q-use-common-soc-revision-helpers.patch b/target/linux/imx6/patches-3.12/0004-ARM-imx6q-use-common-soc-revision-helpers.patch new file mode 100644 index 0000000000..1e12531546 --- /dev/null +++ b/target/linux/imx6/patches-3.12/0004-ARM-imx6q-use-common-soc-revision-helpers.patch @@ -0,0 +1,93 @@ +From 3f75978b3742157853618c5c6dd4a5f49aa950b1 Mon Sep 17 00:00:00 2001 +From: Shawn Guo <shawn.guo@linaro.org> +Date: Tue, 13 Aug 2013 14:10:29 +0800 +Subject: [PATCH] ARM: imx6q: use common soc revision helpers + +It calls imx_set_soc_revision() to set up soc revision in +imx6q_init_revision(), and replaces all the occurrences of +imx6q_revision() with common helper imx_get_soc_revision(). + +Signed-off-by: Shawn Guo <shawn.guo@linaro.org> +--- + arch/arm/mach-imx/clk-imx6q.c | 5 +++-- + arch/arm/mach-imx/common.h | 1 - + arch/arm/mach-imx/mach-imx6q.c | 13 ++++--------- + 3 files changed, 7 insertions(+), 12 deletions(-) + +--- a/arch/arm/mach-imx/clk-imx6q.c ++++ b/arch/arm/mach-imx/clk-imx6q.c +@@ -300,7 +300,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) + WARN_ON(!base); + + /* Audio/video PLL post dividers do not work on i.MX6q revision 1.0 */ +- if (cpu_is_imx6q() && imx6q_revision() == IMX_CHIP_REVISION_1_0) { ++ if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_1_0) { + post_div_table[1].div = 1; + post_div_table[2].div = 1; + video_div_table[1].div = 1; +@@ -574,7 +574,8 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) + clk_register_clkdev(clk[pll4_post_div], "pll4_post_div", NULL); + clk_register_clkdev(clk[pll4_audio], "pll4_audio", NULL); + +- if ((imx6q_revision() != IMX_CHIP_REVISION_1_0) || cpu_is_imx6dl()) { ++ if ((imx_get_soc_revision() != IMX_CHIP_REVISION_1_0) || ++ cpu_is_imx6dl()) { + clk_set_parent(clk[ldb_di0_sel], clk[pll5_video_div]); + clk_set_parent(clk[ldb_di1_sel], clk[pll5_video_div]); + } +--- a/arch/arm/mach-imx/common.h ++++ b/arch/arm/mach-imx/common.h +@@ -73,7 +73,6 @@ extern void mxc_restart(enum reboot_mode, const char *); + extern void mxc_arch_reset_init(void __iomem *); + extern void mxc_arch_reset_init_dt(void); + extern int mx53_revision(void); +-extern int imx6q_revision(void); + extern int mx53_display_revision(void); + extern void imx_set_aips(void __iomem *); + extern int mxc_device_init(void); +--- a/arch/arm/mach-imx/mach-imx6q.c ++++ b/arch/arm/mach-imx/mach-imx6q.c +@@ -38,16 +38,10 @@ + #include "cpuidle.h" + #include "hardware.h" + +-static u32 chip_revision; +- +-int imx6q_revision(void) +-{ +- return chip_revision; +-} +- + static void __init imx6q_init_revision(void) + { + u32 rev = imx_anatop_get_digprog(); ++ u32 chip_revision; + + switch (rev & 0xff) { + case 0: +@@ -64,6 +58,7 @@ static void __init imx6q_init_revision(void) + } + + mxc_set_cpu_type(rev >> 16 & 0xff); ++ imx_set_soc_revision(chip_revision); + } + + static void imx6q_restart(enum reboot_mode mode, const char *cmd) +@@ -269,7 +264,7 @@ + * WAIT mode is broken on TO 1.0 and 1.1, so there is no point + * to run cpuidle on them. + */ +- if (imx6q_revision() > IMX_CHIP_REVISION_1_1) ++ if (imx_get_soc_revision() > IMX_CHIP_REVISION_1_1) + imx6q_cpuidle_init(); + + if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ)) { +@@ -298,7 +293,7 @@ + of_clk_init(NULL); + clocksource_of_init(); + imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q", +- imx6q_revision()); ++ imx_get_soc_revision()); + } + + static const char *imx6q_dt_compat[] __initdata = { |