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-rw-r--r--target/linux/mvebu/patches-3.10/0025-arm-mvebu-avoid-hardcoded-virtual-address-in-coheren.patch81
1 files changed, 81 insertions, 0 deletions
diff --git a/target/linux/mvebu/patches-3.10/0025-arm-mvebu-avoid-hardcoded-virtual-address-in-coheren.patch b/target/linux/mvebu/patches-3.10/0025-arm-mvebu-avoid-hardcoded-virtual-address-in-coheren.patch
new file mode 100644
index 0000000000..b6c3722e34
--- /dev/null
+++ b/target/linux/mvebu/patches-3.10/0025-arm-mvebu-avoid-hardcoded-virtual-address-in-coheren.patch
@@ -0,0 +1,81 @@
+From a4dd628f515f361cecfae08e568891442042e4e2 Mon Sep 17 00:00:00 2001
+From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+Date: Wed, 5 Jun 2013 09:04:55 +0200
+Subject: [PATCH 025/203] arm: mvebu: avoid hardcoded virtual address in
+ coherency code
+
+Now that the coherency_get_cpu_count() function no longer requires a
+very early mapping of the coherency unit registers, we can avoid the
+hardcoded virtual address in coherency.c. However, the coherency
+features are still used quite early, so we need to do the of_iomap()
+early enough, at the ->init_timer() level, so we have the call of
+coherency_init() at this point.
+
+Unfortunately, at ->init_timer() time, it is not possible to register
+a bus notifier, so we add a separate coherency_late_init() function
+that gets called as as postcore_initcall(), when bus notifiers are
+available.
+
+Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+Acked-by: Arnd Bergmann <arnd@arndb.de>
+Signed-off-by: Jason Cooper <jason@lakedaemon.net>
+---
+ arch/arm/mach-mvebu/armada-370-xp.c | 2 +-
+ arch/arm/mach-mvebu/coherency.c | 20 ++++++++++----------
+ 2 files changed, 11 insertions(+), 11 deletions(-)
+
+--- a/arch/arm/mach-mvebu/armada-370-xp.c
++++ b/arch/arm/mach-mvebu/armada-370-xp.c
+@@ -47,6 +47,7 @@ static void __init armada_370_xp_timer_a
+ {
+ mvebu_clocks_init();
+ armada_370_xp_timer_init();
++ coherency_init();
+ }
+
+ static void __init armada_370_xp_init_early(void)
+@@ -76,7 +77,6 @@ static void __init armada_370_xp_init_ea
+ static void __init armada_370_xp_dt_init(void)
+ {
+ of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+- coherency_init();
+ }
+
+ static const char * const armada_370_xp_dt_compat[] = {
+--- a/arch/arm/mach-mvebu/coherency.c
++++ b/arch/arm/mach-mvebu/coherency.c
+@@ -27,14 +27,7 @@
+ #include <asm/smp_plat.h>
+ #include "armada-370-xp.h"
+
+-/*
+- * Some functions in this file are called very early during SMP
+- * initialization. At that time the device tree framework is not yet
+- * ready, and it is not possible to get the register address to
+- * ioremap it. That's why the pointer below is given with an initial
+- * value matching its virtual mapping
+- */
+-static void __iomem *coherency_base = ARMADA_370_XP_REGS_VIRT_BASE + 0x20200;
++static void __iomem *coherency_base;
+ static void __iomem *coherency_cpu_base;
+
+ /* Coherency fabric registers */
+@@ -135,9 +128,16 @@ int __init coherency_init(void)
+ coherency_base = of_iomap(np, 0);
+ coherency_cpu_base = of_iomap(np, 1);
+ set_cpu_coherent(cpu_logical_map(smp_processor_id()), 0);
+- bus_register_notifier(&platform_bus_type,
+- &mvebu_hwcc_platform_nb);
+ }
+
+ return 0;
+ }
++
++static int __init coherency_late_init(void)
++{
++ bus_register_notifier(&platform_bus_type,
++ &mvebu_hwcc_platform_nb);
++ return 0;
++}
++
++postcore_initcall(coherency_late_init);