aboutsummaryrefslogtreecommitdiffstats
path: root/target/linux/mvebu/patches-3.8/042-arm_mvebu_add_pcie_dt_a370_db.patch
diff options
context:
space:
mode:
Diffstat (limited to 'target/linux/mvebu/patches-3.8/042-arm_mvebu_add_pcie_dt_a370_db.patch')
-rw-r--r--target/linux/mvebu/patches-3.8/042-arm_mvebu_add_pcie_dt_a370_db.patch32
1 files changed, 0 insertions, 32 deletions
diff --git a/target/linux/mvebu/patches-3.8/042-arm_mvebu_add_pcie_dt_a370_db.patch b/target/linux/mvebu/patches-3.8/042-arm_mvebu_add_pcie_dt_a370_db.patch
deleted file mode 100644
index 1a853f35c7..0000000000
--- a/target/linux/mvebu/patches-3.8/042-arm_mvebu_add_pcie_dt_a370_db.patch
+++ /dev/null
@@ -1,32 +0,0 @@
-The Marvell evaluation board (DB) for the Armada 370 SoC has 2
-physical full-size PCIe slots, so we enable the corresponding PCIe
-interfaces in the Device Tree.
-
-Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
----
- arch/arm/boot/dts/armada-370-db.dts | 15 +++++++++++++++
- 1 file changed, 15 insertions(+)
-
---- a/arch/arm/boot/dts/armada-370-db.dts
-+++ b/arch/arm/boot/dts/armada-370-db.dts
-@@ -82,5 +82,20 @@
- usb@d0051000 {
- status = "okay";
- };
-+
-+ pcie-controller {
-+ status = "okay";
-+ /*
-+ * The two PCIe units are accessible through
-+ * both standard PCIe slots and mini-PCIe
-+ * slots on the board.
-+ */
-+ pcie0@0xd0040000 {
-+ status = "okay";
-+ };
-+ pcie1@0xd0080000 {
-+ status = "okay";
-+ };
-+ };
- };
- };