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authorDENG Qingfang <dengqf6@mail2.sysu.edu.cn>2020-04-01 23:14:33 +0800
committerChuanhong Guo <gch981213@gmail.com>2020-04-04 14:14:43 +0800
commit9ebb85c372e525b08debe286d976a6376ca0dbbe (patch)
treeb86fe47fd2b5dd8caa4041a4fa70716c95c6af31
parentd21d6ea4547412632e01de505b7a2c8a83817a02 (diff)
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ramips: mt7621: update PCIe node in dtsi
Update PCIe node in dtsi to match the new driver Signed-off-by: DENG Qingfang <dengqf6@mail2.sysu.edu.cn>
-rw-r--r--target/linux/ramips/dts/mt7621.dtsi43
1 files changed, 29 insertions, 14 deletions
diff --git a/target/linux/ramips/dts/mt7621.dtsi b/target/linux/ramips/dts/mt7621.dtsi
index 2db238f57f..cc387519e4 100644
--- a/target/linux/ramips/dts/mt7621.dtsi
+++ b/target/linux/ramips/dts/mt7621.dtsi
@@ -315,7 +315,7 @@
pcie_pins: pcie {
pcie {
groups = "pcie";
- function = "pcie rst";
+ function = "gpio";
};
};
@@ -540,9 +540,10 @@
pcie: pcie@1e140000 {
compatible = "mediatek,mt7621-pci";
- reg = <0x1e140000 0x100
- 0x1e142000 0x100>;
-
+ reg = <0x1e140000 0x100 /* host-pci bridge registers */
+ 0x1e142000 0x100 /* pcie port 0 RC control registers */
+ 0x1e143000 0x100 /* pcie port 1 RC control registers */
+ 0x1e144000 0x100>; /* pcie port 2 RC control registers */
#address-cells = <3>;
#size-cells = <2>;
@@ -557,10 +558,11 @@
0x01000000 0 0x00000000 0x1e160000 0 0x00010000 /* io space */
>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH
- GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH
- GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0xF0000 0 0 1>;
+ interrupt-map = <0x10000 0 0 1 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>,
+ <0x20000 0 0 1 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>,
+ <0x30000 0 0 1 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
@@ -568,32 +570,45 @@
reset-names = "pcie0", "pcie1", "pcie2";
clocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>;
clock-names = "pcie0", "pcie1", "pcie2";
+ phys = <&pcie0_phy 1>, <&pcie2_phy 0>;
+ phy-names = "pcie-phy0", "pcie-phy2";
+
+ reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
pcie0: pcie@0,0 {
reg = <0x0000 0 0 0 0>;
-
#address-cells = <3>;
#size-cells = <2>;
-
ranges;
+ bus-range = <0x00 0xff>;
};
pcie1: pcie@1,0 {
reg = <0x0800 0 0 0 0>;
-
#address-cells = <3>;
#size-cells = <2>;
-
ranges;
+ bus-range = <0x00 0xff>;
};
pcie2: pcie@2,0 {
reg = <0x1000 0 0 0 0>;
-
#address-cells = <3>;
#size-cells = <2>;
-
ranges;
+ bus-range = <0x00 0xff>;
};
};
+
+ pcie0_phy: pcie-phy@1e149000 {
+ compatible = "mediatek,mt7621-pci-phy";
+ reg = <0x1e149000 0x0700>;
+ #phy-cells = <1>;
+ };
+
+ pcie2_phy: pcie-phy@1e14a000 {
+ compatible = "mediatek,mt7621-pci-phy";
+ reg = <0x1e14a000 0x0700>;
+ #phy-cells = <1>;
+ };
};