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authorGabor Juhos <juhosg@openwrt.org>2011-05-08 16:32:53 +0000
committerGabor Juhos <juhosg@openwrt.org>2011-05-08 16:32:53 +0000
commit5d77f370d695c9a70f25ffb8367db64efadaaedd (patch)
tree447565cb138433c4789c5f2010512d9a0db57361 /package/6to4
parent37116582811963a277f3219059371998645e0b13 (diff)
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ar71xx: ag71xx: make switch register access atomic
Reading of the PHY registers occasionally returns with bogus values under heavy load. This misleads the PHY driver and thus causes false link/speed change notifications which leads to performance loss. This is easily noticable during an iperf session: ... [ 3] 52.0-53.0 sec 11.3 MBytes 94.4 Mbits/sec [ 3] 53.0-54.0 sec 11.4 MBytes 95.4 Mbits/sec eth1: link down br-lan: port 2(eth1) entering forwarding state eth1: link up (100Mbps/Full duplex) br-lan: port 2(eth1) entering forwarding state br-lan: port 2(eth1) entering forwarding state [ 3] 54.0-55.0 sec 6.75 MBytes 56.6 Mbits/sec [ 3] 55.0-56.0 sec 0.00 Bytes 0.00 bits/sec [ 3] 56.0-57.0 sec 10.5 MBytes 88.1 Mbits/sec ... [ 3] 169.0-170.0 sec 11.4 MBytes 95.4 Mbits/sec [ 3] 170.0-171.0 sec 11.4 MBytes 95.4 Mbits/sec eth1: link up (10Mbps/Half duplex) [ 3] 171.0-172.0 sec 7.63 MBytes 64.0 Mbits/sec [ 3] 172.0-173.0 sec 9.38 MBytes 78.6 Mbits/sec eth1: link up (100Mbps/Full duplex) [ 3] 173.0-174.0 sec 11.3 MBytes 94.4 Mbits/sec [ 3] 174.0-175.0 sec 11.4 MBytes 95.4 Mbits/sec SVN-Revision: 26856
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