diff options
| author | Pawel Dembicki <paweldembicki@gmail.com> | 2020-01-24 07:13:24 +0100 |
|---|---|---|
| committer | Petr Štetiar <ynezz@true.cz> | 2020-07-11 13:33:28 +0200 |
| commit | c881d7ab039022aac91a3524227df9cc5f60dd16 (patch) | |
| tree | c038b52a1dc8bb58e70105d05a035372bbd15ff1 /package/boot/uboot-kirkwood/patches/701-phy-mv88e61xx-add-support-for-RGMII-TX-RX-delay.patch | |
| parent | 9c99187e616ac54aed572a0eb310aadd06ac8e4b (diff) | |
| download | upstream-c881d7ab039022aac91a3524227df9cc5f60dd16.tar.gz upstream-c881d7ab039022aac91a3524227df9cc5f60dd16.tar.bz2 upstream-c881d7ab039022aac91a3524227df9cc5f60dd16.zip | |
uboot-kirkwood: add uboot for CheckPoint L-50
This patch add u-boot for CheckPoint L-50 routers.
Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
Diffstat (limited to 'package/boot/uboot-kirkwood/patches/701-phy-mv88e61xx-add-support-for-RGMII-TX-RX-delay.patch')
| -rw-r--r-- | package/boot/uboot-kirkwood/patches/701-phy-mv88e61xx-add-support-for-RGMII-TX-RX-delay.patch | 53 |
1 files changed, 53 insertions, 0 deletions
diff --git a/package/boot/uboot-kirkwood/patches/701-phy-mv88e61xx-add-support-for-RGMII-TX-RX-delay.patch b/package/boot/uboot-kirkwood/patches/701-phy-mv88e61xx-add-support-for-RGMII-TX-RX-delay.patch new file mode 100644 index 0000000000..6e358857b7 --- /dev/null +++ b/package/boot/uboot-kirkwood/patches/701-phy-mv88e61xx-add-support-for-RGMII-TX-RX-delay.patch @@ -0,0 +1,53 @@ +From 940e9a5828480e4185c9a276ad7f35a4069a2393 Mon Sep 17 00:00:00 2001 +From: Pawel Dembicki <paweldembicki@gmail.com> +Date: Thu, 23 Jan 2020 22:04:15 +0100 +Subject: [PATCH 1/2] phy: mv88e61xx: add support for RGMII TX/RX delay + +Clock delay in RGMII is required for some boards. +This patch introduce CONFIG_MV88E61XX_CPU_PORT_TX_DELAY and +CONFIG_MV88E61XX_CPU_PORT_RX_DELAY defines, which are setting +proper bits in PORT_REG_PHYS_CTRL register. + +Cc: Chris Packham <judge.packham@gmail.com> +Cc: Joe Hershberger <joe.hershberger@ni.com> +Cc: Anatolij Gustschin <agust@denx.de> +Cc: Tim Harvey <tharvey@gateworks.com> +Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com> +--- + drivers/net/phy/mv88e61xx.c | 11 ++++++++++- + 1 file changed, 10 insertions(+), 1 deletion(-) + +diff --git a/drivers/net/phy/mv88e61xx.c b/drivers/net/phy/mv88e61xx.c +index 5aff7ed397..889327639d 100644 +--- a/drivers/net/phy/mv88e61xx.c ++++ b/drivers/net/phy/mv88e61xx.c +@@ -94,6 +94,8 @@ + #define PORT_REG_STATUS_CMODE_1000BASE_X 0x9 + #define PORT_REG_STATUS_CMODE_SGMII 0xa + ++#define PORT_REG_PHYS_CTRL_RGMII_RX_DELAY BIT(15) ++#define PORT_REG_PHYS_CTRL_RGMII_TX_DELAY BIT(14) + #define PORT_REG_PHYS_CTRL_PCS_AN_EN BIT(10) + #define PORT_REG_PHYS_CTRL_PCS_AN_RST BIT(9) + #define PORT_REG_PHYS_CTRL_FC_VALUE BIT(7) +@@ -747,9 +749,16 @@ static int mv88e61xx_fixed_port_setup(struct phy_device *phydev, u8 port) + PORT_REG_PHYS_CTRL_SPD1000; + } + +- if (port == CONFIG_MV88E61XX_CPU_PORT) ++ if (port == CONFIG_MV88E61XX_CPU_PORT) { + val |= PORT_REG_PHYS_CTRL_LINK_VALUE | + PORT_REG_PHYS_CTRL_LINK_FORCE; ++#if defined(CONFIG_MV88E61XX_CPU_PORT_RX_DELAY) ++ val |= PORT_REG_PHYS_CTRL_RGMII_RX_DELAY; ++#endif ++#if defined(CONFIG_MV88E61XX_CPU_PORT_TX_DELAY) ++ val |= PORT_REG_PHYS_CTRL_RGMII_TX_DELAY; ++#endif ++ } + + return mv88e61xx_port_write(phydev, port, PORT_REG_PHYS_CTRL, + val); +-- +2.20.1 + |