layerscape: add 64b/32b target for ls1012ardb device

The QorIQ LS1012A processor, optimized for battery-backed or
USB-powered, integrates a single ARM Cortex-A53 core with a hardware
packet forwarding engine and high-speed interfaces to deliver
line-rate networking performance.
QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance
development platform, with a complete debugging environment.
The LS1012ARDB board supports the QorIQ LS1012A processor and is
optimized to support the high-bandwidth DDR3L memory and
a full complement of high-speed SerDes ports.

LEDE/OPENWRT will auto strip executable program file while make. So we
need select CONFIG_NO_STRIP=y while make menuconfig to avoid the ppfe network
fiemware be destroyed, then run make to build ls1012ardb firmware.

The fsl-quadspi flash with jffs2 fs is unstable and arise some failed message.
This issue have noticed the IP owner for investigate, hope he can solve it
earlier. So the ls1012ardb now also provide a xx-firmware.ext4.bin as default
firmware, and the uboot bootcmd will run wrtboot_ext4rfs for "rootfstype=ext4"
bootargs.

Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>

1 files changed, 124 insertions, 0 deletions

diff --git a/package/boot/uboot-layerscape/patches/0022-include-usb-Rename-USB-controller-base-address-mappi.patch b/package/boot/uboot-layerscape/patches/0022-include-usb-Rename-USB-controller-base-address-mappi.patch
new file mode 100644
index 0000000000..b4d1634587
--- /dev/null
+++ b/package/boot/uboot-layerscape/patches/0022-include-usb-Rename-USB-controller-base-address-mappi.patch
@@ -0,0 +1,124 @@
+From 46c9963880e5cba6390864477f19b25369c6c944 Mon Sep 17 00:00:00 2001
+From: Rajesh Bhagat <rajesh.bhagat@nxp.com>
+Date: Thu, 5 May 2016 15:01:02 +0530
+Subject: [PATCH 22/93] include: usb: Rename USB controller base address
+ mapping
+
+[context adjustment]
+
+Remove Soc specific defines and use generic chasis specific defines
+for USB controller base address mapping.
+
+Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
+Integrated-by: Jiang Yutang <yutang.jiang@nxp.com>
+---
+ .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |    6 +++---
+ .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |    4 ++--
+ arch/arm/include/asm/arch-ls102xa/config.h         |    6 ++----
+ include/linux/usb/xhci-fsl.h                       |   20 ++++++++------------
+ include/usb/ehci-fsl.h                             |    2 +-
+ 5 files changed, 16 insertions(+), 22 deletions(-)
+
+diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+index 414a222..3e37f00 100644
+--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
++++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+@@ -33,9 +33,9 @@
+ #define CONFIG_SYS_NS16550_COM2			(CONFIG_SYS_IMMR + 0x011c0600)
+ #define CONFIG_SYS_NS16550_COM3			(CONFIG_SYS_IMMR + 0x011d0500)
+ #define CONFIG_SYS_NS16550_COM4			(CONFIG_SYS_IMMR + 0x011d0600)
+-#define CONFIG_SYS_LS1043A_XHCI_USB1_ADDR	(CONFIG_SYS_IMMR + 0x01f00000)
+-#define CONFIG_SYS_LS1043A_XHCI_USB2_ADDR	(CONFIG_SYS_IMMR + 0x02000000)
+-#define CONFIG_SYS_LS1043A_XHCI_USB3_ADDR	(CONFIG_SYS_IMMR + 0x02100000)
++#define CONFIG_SYS_XHCI_USB1_ADDR		(CONFIG_SYS_IMMR + 0x01f00000)
++#define CONFIG_SYS_XHCI_USB2_ADDR		(CONFIG_SYS_IMMR + 0x02000000)
++#define CONFIG_SYS_XHCI_USB3_ADDR		(CONFIG_SYS_IMMR + 0x02100000)
+ #define CONFIG_SYS_PCIE1_ADDR			(CONFIG_SYS_IMMR + 0x2400000)
+ #define CONFIG_SYS_PCIE2_ADDR			(CONFIG_SYS_IMMR + 0x2500000)
+ #define CONFIG_SYS_PCIE3_ADDR			(CONFIG_SYS_IMMR + 0x2600000)
+diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+index 0ab709c..cf1f37a 100644
+--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
++++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+@@ -51,8 +51,8 @@
+ #define I2C3_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01020000)
+ #define I2C4_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01030000)
+ 
+-#define CONFIG_SYS_LS2080A_XHCI_USB1_ADDR	(CONFIG_SYS_IMMR + 0x02100000)
+-#define CONFIG_SYS_LS2080A_XHCI_USB2_ADDR	(CONFIG_SYS_IMMR + 0x02110000)
++#define CONFIG_SYS_XHCI_USB1_ADDR		(CONFIG_SYS_IMMR + 0x02100000)
++#define CONFIG_SYS_XHCI_USB2_ADDR		(CONFIG_SYS_IMMR + 0x02110000)
+ 
+ /* TZ Address Space Controller Definitions */
+ #define TZASC1_BASE			0x01100000	/* as per CCSR map. */
+diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h
+index 926ac58..05fff80 100644
+--- a/arch/arm/include/asm/arch-ls102xa/config.h
++++ b/arch/arm/include/asm/arch-ls102xa/config.h
+@@ -36,13 +36,11 @@
+ #define CONFIG_SYS_NS16550_COM1			(CONFIG_SYS_IMMR + 0x011c0500)
+ #define CONFIG_SYS_NS16550_COM2			(CONFIG_SYS_IMMR + 0x011d0500)
+ #define CONFIG_SYS_DCU_ADDR			(CONFIG_SYS_IMMR + 0x01ce0000)
+-#define CONFIG_SYS_LS102XA_XHCI_USB1_ADDR	(CONFIG_SYS_IMMR + 0x02100000)
+-#define CONFIG_SYS_LS102XA_USB1_ADDR \
+-	(CONFIG_SYS_IMMR + CONFIG_SYS_LS102XA_USB1_OFFSET)
++#define CONFIG_SYS_XHCI_USB1_ADDR		(CONFIG_SYS_IMMR + 0x02100000)
++#define CONFIG_SYS_EHCI_USB1_ADDR		(CONFIG_SYS_IMMR + 0x07600000)
+ 
+ #define CONFIG_SYS_FSL_SEC_OFFSET		0x00700000
+ #define CONFIG_SYS_FSL_JR0_OFFSET		0x00710000
+-#define CONFIG_SYS_LS102XA_USB1_OFFSET		0x07600000
+ #define CONFIG_SYS_TSEC1_OFFSET			0x01d10000
+ #define CONFIG_SYS_TSEC2_OFFSET			0x01d50000
+ #define CONFIG_SYS_TSEC3_OFFSET			0x01d90000
+diff --git a/include/linux/usb/xhci-fsl.h b/include/linux/usb/xhci-fsl.h
+index 7ab88c3..b2b3264 100644
+--- a/include/linux/usb/xhci-fsl.h
++++ b/include/linux/usb/xhci-fsl.h
+@@ -54,22 +54,18 @@ struct fsl_xhci {
+ 	struct dwc3 *dwc3_reg;
+ };
+ 
+-#if defined(CONFIG_LS102XA)
+-#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS102XA_XHCI_USB1_ADDR
++#if defined(CONFIG_LS102XA) || defined(CONFIG_LS1012A)
++#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_XHCI_USB1_ADDR
+ #define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0
+ #define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0
+ #elif defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+-#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS2080A_XHCI_USB1_ADDR
+-#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS2080A_XHCI_USB2_ADDR
+-#define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0
+-#elif defined(CONFIG_LS1043A) || defined(CONFIG_LS1012A)
+-#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS1043A_XHCI_USB1_ADDR
+-#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS1043A_XHCI_USB2_ADDR
+-#define CONFIG_SYS_FSL_XHCI_USB3_ADDR CONFIG_SYS_LS1043A_XHCI_USB3_ADDR
+-#elif defined(CONFIG_LS1012A)
+-#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS1043A_XHCI_USB1_ADDR
+-#define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0
++#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_XHCI_USB1_ADDR
++#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_XHCI_USB2_ADDR
+ #define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0
++#elif defined(CONFIG_LS1043A)
++#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_XHCI_USB1_ADDR
++#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_XHCI_USB2_ADDR
++#define CONFIG_SYS_FSL_XHCI_USB3_ADDR CONFIG_SYS_XHCI_USB3_ADDR
+ #endif
+ 
+ #define FSL_USB_XHCI_ADDR	{CONFIG_SYS_FSL_XHCI_USB1_ADDR, \
+diff --git a/include/usb/ehci-fsl.h b/include/usb/ehci-fsl.h
+index e9349b5..b8d78d0 100644
+--- a/include/usb/ehci-fsl.h
++++ b/include/usb/ehci-fsl.h
+@@ -164,7 +164,7 @@
+ #define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC512x_USB1_ADDR
+ #define CONFIG_SYS_FSL_USB2_ADDR	0
+ #elif defined(CONFIG_LS102XA)
+-#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_LS102XA_USB1_ADDR
++#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_EHCI_USB1_ADDR
+ #define CONFIG_SYS_FSL_USB2_ADDR        0
+ #endif
+ 
+-- 
+1.7.9.5
+