layerscape: add 64b/32b target for ls1012ardb device

The QorIQ LS1012A processor, optimized for battery-backed or
USB-powered, integrates a single ARM Cortex-A53 core with a hardware
packet forwarding engine and high-speed interfaces to deliver
line-rate networking performance.
QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance
development platform, with a complete debugging environment.
The LS1012ARDB board supports the QorIQ LS1012A processor and is
optimized to support the high-bandwidth DDR3L memory and
a full complement of high-speed SerDes ports.

LEDE/OPENWRT will auto strip executable program file while make. So we
need select CONFIG_NO_STRIP=y while make menuconfig to avoid the ppfe network
fiemware be destroyed, then run make to build ls1012ardb firmware.

The fsl-quadspi flash with jffs2 fs is unstable and arise some failed message.
This issue have noticed the IP owner for investigate, hope he can solve it
earlier. So the ls1012ardb now also provide a xx-firmware.ext4.bin as default
firmware, and the uboot bootcmd will run wrtboot_ext4rfs for "rootfstype=ext4"
bootargs.

Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>

1 files changed, 61 insertions, 0 deletions

diff --git a/package/boot/uboot-layerscape/patches/0047-Enable-second-SGMII-1G-interface.patch b/package/boot/uboot-layerscape/patches/0047-Enable-second-SGMII-1G-interface.patch
new file mode 100644
index 0000000000..79e3f40c14
--- /dev/null
+++ b/package/boot/uboot-layerscape/patches/0047-Enable-second-SGMII-1G-interface.patch
@@ -0,0 +1,61 @@
+From 61bb1dceefdb4c08ff69e7e40a766a404421206f Mon Sep 17 00:00:00 2001
+From: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
+Date: Fri, 27 May 2016 13:16:43 +0530
+Subject: [PATCH 47/93] Enable second SGMII 1G interface
+
+Enable second SGMII 1G interface on LS1012A Freedom Board
+
+Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
+---
+ board/freescale/ls1012afrdm/eth.c |   14 ++++++++++++++
+ drivers/net/pfe_eth/pfe_eth.c     |    2 +-
+ 2 files changed, 15 insertions(+), 1 deletion(-)
+
+diff --git a/board/freescale/ls1012afrdm/eth.c b/board/freescale/ls1012afrdm/eth.c
+index 8ae3f45..90ed66b 100644
+--- a/board/freescale/ls1012afrdm/eth.c
++++ b/board/freescale/ls1012afrdm/eth.c
+@@ -19,6 +19,7 @@
+ #include <asm/arch-fsl-layerscape/immap_lsch2.h>
+ 
+ #define DEFAULT_PFE_MDIO_NAME "PFE_MDIO"
++#define DEFAULT_PFE_MDIO1_NAME "PFE_MDIO1"
+ 
+ #define MASK_ETH_PHY_RST	0x00000100
+ 
+@@ -71,6 +72,19 @@ int board_eth_init(bd_t *bis)
+ 		return -1;
+ 	}
+ 
++	/*We don't really need this MDIO bus,
++	* this is called just to initialize EMAC2 MDIO interface*/
++	mac1_mdio_info.reg_base = (void *)0x04220000; /*EMAC2_BASE_ADDR*/
++	mac1_mdio_info.name = DEFAULT_PFE_MDIO1_NAME;
++
++	bus = ls1012a_mdio_init(&mac1_mdio_info);
++	if(!bus)
++	{
++		printf("Failed to register mdio \n");
++		return -1;
++	}
++
++
+ 	/*MAC1 */
+ 	ls1012a_set_mdio(0, miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME));
+ 	ls1012a_set_phy_address_mode(0,  EMAC1_PHY_ADDR, PHY_INTERFACE_MODE_SGMII);
+diff --git a/drivers/net/pfe_eth/pfe_eth.c b/drivers/net/pfe_eth/pfe_eth.c
+index 40f2c39..4aa318d 100644
+--- a/drivers/net/pfe_eth/pfe_eth.c
++++ b/drivers/net/pfe_eth/pfe_eth.c
+@@ -348,7 +348,7 @@ static void ls1012a_configure_serdes(struct ls1012a_eth_dev *priv)
+ 
+ 	printf("%s %d\n", __func__, priv->gemac_port);
+ 	/* PCS configuration done with corresponding GEMAC */
+-	bus.priv = priv->gem->gemac_base;
++	bus.priv = gem_info[priv->gemac_port].gemac_base;
+ 
+ 	ls1012a_phy_read(&bus, 0, MDIO_DEVAD_NONE, 0x0);
+ 	ls1012a_phy_read(&bus, 0, MDIO_DEVAD_NONE, 0x1);
+-- 
+1.7.9.5
+