diff options
author | John Crispin <john@openwrt.org> | 2011-02-01 14:26:47 +0000 |
---|---|---|
committer | John Crispin <john@openwrt.org> | 2011-02-01 14:26:47 +0000 |
commit | c7bb106433427d5284a853d9586298a323ad744d (patch) | |
tree | 65f8b98f2f052c814249bb42565a072e7e40cf66 /package/uboot-lantiq/files/board/arcadyan/ddr_settings.h | |
parent | 7ab8489f828715cda6fb184bf2ca1a3d5f1c8b60 (diff) | |
download | upstream-c7bb106433427d5284a853d9586298a323ad744d.tar.gz upstream-c7bb106433427d5284a853d9586298a323ad744d.tar.bz2 upstream-c7bb106433427d5284a853d9586298a323ad744d.zip |
* rework the arcadyan sku support * adds a few new boards and switches
SVN-Revision: 25273
Diffstat (limited to 'package/uboot-lantiq/files/board/arcadyan/ddr_settings.h')
-rw-r--r-- | package/uboot-lantiq/files/board/arcadyan/ddr_settings.h | 50 |
1 files changed, 50 insertions, 0 deletions
diff --git a/package/uboot-lantiq/files/board/arcadyan/ddr_settings.h b/package/uboot-lantiq/files/board/arcadyan/ddr_settings.h new file mode 100644 index 0000000000..4df6f1170c --- /dev/null +++ b/package/uboot-lantiq/files/board/arcadyan/ddr_settings.h @@ -0,0 +1,50 @@ +/* Settings for Denali DDR SDRAM controller */ +/* Optimise for DDR PSC A3S12D40ETP for arv4518pw Danube Board DDR 166 Mhz - by Ngp 14th Sept. 2010 */ + +#define MC_DC0_VALUE 0x1B1B +#define MC_DC1_VALUE 0x0 +#define MC_DC2_VALUE 0x0 +#define MC_DC3_VALUE 0x0 +#define MC_DC4_VALUE 0x0 +#define MC_DC5_VALUE 0x200 +#define MC_DC6_VALUE 0x605 +#define MC_DC7_VALUE 0x303 +#define MC_DC8_VALUE 0x102 +#define MC_DC9_VALUE 0x70a +#define MC_DC10_VALUE 0x203 +#define MC_DC11_VALUE 0xc02 +#define MC_DC12_VALUE 0x1C8 +#define MC_DC13_VALUE 0x1 +#define MC_DC14_VALUE 0x0 +#define MC_DC15_VALUE 0x130 /* WDQS tuning for clk_wr*/ +#define MC_DC16_VALUE 0xC800 +#define MC_DC17_VALUE 0xd +#define MC_DC18_VALUE 0x301 +#define MC_DC19_VALUE 0x200 +#define MC_DC20_VALUE 0xA03 /* A04 for reference board, A03 for Eval board */ +#define MC_DC21_VALUE 0x1b00 +#define MC_DC22_VALUE 0x1b1b +#define MC_DC23_VALUE 0x0 +#define MC_DC24_VALUE 0x59 /* WDQS Tuning for DQS */ +#define MC_DC25_VALUE 0x0 +#define MC_DC26_VALUE 0x0 +#define MC_DC27_VALUE 0x0 +#define MC_DC28_VALUE 0x510 +#define MC_DC29_VALUE 0x4e20 +#define MC_DC30_VALUE 0x8235 +#define MC_DC31_VALUE 0x0 +#define MC_DC32_VALUE 0x0 +#define MC_DC33_VALUE 0x0 +#define MC_DC34_VALUE 0x0 +#define MC_DC35_VALUE 0x0 +#define MC_DC36_VALUE 0x0 +#define MC_DC37_VALUE 0x0 +#define MC_DC38_VALUE 0x0 +#define MC_DC39_VALUE 0x0 +#define MC_DC40_VALUE 0x0 +#define MC_DC41_VALUE 0x0 +#define MC_DC42_VALUE 0x0 +#define MC_DC43_VALUE 0x0 +#define MC_DC44_VALUE 0x0 +#define MC_DC45_VALUE 0x500 +#define MC_DC46_VALUE 0x0 |