openwrt/upstream - upstream openwrt

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author	Jo-Philipp Wich <jo@mein.io>	2018-06-22 12:30:02 +0200
committer	Jo-Philipp Wich <jo@mein.io>	2018-06-22 12:30:02 +0200
commit	13f64a1e597e00e7bc9cf73866533f668482c4fa (patch)
tree	fcdd5eb7e1db40c34cd5fc63570a742b9b71a383 /package/utils/e2fsprogs/files/e2fsck.conf
parent	d2aa3a1b6274d29c80a33dc865035bb0d4b22dd7 (diff)
download	upstream-18.06.0-rc1.tar.gz upstream-18.06.0-rc1.tar.bz2 upstream-18.06.0-rc1.zip

OpenWrt v18.06.0-rc1: adjust config defaultsv18.06.0-rc1

Signed-off-by: Jo-Philipp Wich <jo@mein.io>

Diffstat (limited to 'package/utils/e2fsprogs/files/e2fsck.conf')

0 files changed, 0 insertions, 0 deletions

/* * This file is part of the flashrom project. * * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de> * Copyright (C) 2010, 2011 Carl-Daniel Hailfinger * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ #include <stdlib.h> #include <string.h> #include "flash.h" #include "programmer.h" #include "platform/pci.h" struct pci_access *pacc; enum pci_bartype { TYPE_MEMBAR, TYPE_IOBAR, TYPE_ROMBAR, TYPE_UNKNOWN }; uintptr_t pcidev_readbar(struct pci_dev *dev, int bar) { uint64_t addr; uint32_t upperaddr; uint8_t headertype; uint16_t supported_cycles; enum pci_bartype bartype = TYPE_UNKNOWN; headertype = pci_read_byte(dev, PCI_HEADER_TYPE) & 0x7f; msg_pspew("PCI header type 0x%02x\n", headertype); /* Don't use dev->base_addr[x] (as value for 'bar'), won't work on older libpci. */ addr = pci_read_long(dev, bar); /* Sanity checks. */ switch (headertype) { case PCI_HEADER_TYPE_NORMAL: switch (bar) { case PCI_BASE_ADDRESS_0: case PCI_BASE_ADDRESS_1: case PCI_BASE_ADDRESS_2: case PCI_BASE_ADDRESS_3: case PCI_BASE_ADDRESS_4: case PCI_BASE_ADDRESS_5: if ((addr & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) bartype = TYPE_IOBAR; else bartype = TYPE_MEMBAR; break; case PCI_ROM_ADDRESS: bartype = TYPE_ROMBAR; break; } break; case PCI_HEADER_TYPE_BRIDGE: switch (bar) { case PCI_BASE_ADDRESS_0: case PCI_BASE_ADDRESS_1: if ((addr & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) bartype = TYPE_IOBAR; else bartype = TYPE_MEMBAR; break; case PCI_ROM_ADDRESS1: bartype = TYPE_ROMBAR; break; } break; case PCI_HEADER_TYPE_CARDBUS: break; default: msg_perr("Unknown PCI header type 0x%02x, BAR type cannot be determined reliably.\n", headertype); break; } supported_cycles = pci_read_word(dev, PCI_COMMAND); msg_pdbg("Requested BAR is of type "); switch (bartype) { case TYPE_MEMBAR: msg_pdbg("MEM"); if (!(supported_cycles & PCI_COMMAND_MEMORY)) { msg_perr("MEM BAR access requested, but device has MEM space accesses disabled.\n"); /* TODO: Abort here? */ } msg_pdbg(", %sbit, %sprefetchable\n", ((addr & 0x6) == 0x0) ? "32" : (((addr & 0x6) == 0x4) ? "64" : "reserved"), (addr & 0x8) ? "" : "not "); if ((addr & 0x6) == 0x4) { /* The spec says that a 64-bit register consumes * two subsequent dword locations. */ upperaddr = pci_read_long(dev, bar + 4); if (upperaddr != 0x00000000) { /* Fun! A real 64-bit resource. */ if (sizeof(uintptr_t) != sizeof(uint64_t)) { msg_perr("BAR unreachable!"); /* TODO: Really abort here? If multiple PCI devices match, * we might never tell the user about the other devices. */ return 0; } addr |= (uint64_t)upperaddr << 32; } } addr &= PCI_BASE_ADDRESS_MEM_MASK; break; case TYPE_IOBAR: msg_pdbg("I/O\n"); #if __FLASHROM_HAVE_OUTB__ if (!(supported_cycles & PCI_COMMAND_IO)) { msg_perr("I/O BAR access requested, but device has I/O space accesses disabled.\n"); /* TODO: Abort here? */ } #else msg_perr("I/O BAR access requested, but flashrom does not support I/O BAR access on this " "platform (yet).\n"); #endif addr &= PCI_BASE_ADDRESS_IO_MASK; break; case TYPE_ROMBAR: msg_pdbg("ROM\n"); /* Not sure if this check is needed. */ if (!(supported_cycles & PCI_COMMAND_MEMORY)) { msg_perr("MEM BAR access requested, but device has MEM space accesses disabled.\n"); /* TODO: Abort here? */ } addr &= PCI_ROM_ADDRESS_MASK; break; case TYPE_UNKNOWN: msg_perr("BAR type unknown, please report a bug at flashrom@flashrom.org\n"); } return (uintptr_t)addr; } static int pcidev_shutdown(void *data) { if (pacc == NULL) { msg_perr("%s: Tried to cleanup an invalid PCI context!\n" "Please report a bug at flashrom@flashrom.org\n", __func__); return 1; } pci_cleanup(pacc); pacc = NULL; return 0; } int pci_init_common(void) { if (pacc != NULL) { msg_perr("%s: Tried to allocate a new PCI context, but there is still an old one!\n" "Please report a bug at flashrom@flashrom.org\n", __func__); return 1; } pacc = pci_alloc(); /* Get the pci_access structure */ pci_init(pacc); /* Initialize the PCI library */ if (register_shutdown(pcidev_shutdown, NULL)) return 1; pci_scan_bus(pacc); /* We want to get the list of devices */ return 0; } /* pcidev_init gets an array of allowed PCI device IDs and returns a pointer to struct pci_dev iff exactly one * match was found. If the "pci=bb:dd.f" programmer parameter was specified, a match is only considered if it * also matches the specified bus:device.function. * For convenience, this function also registers its own undo handlers. */ struct pci_dev *pcidev_init(const struct dev_entry *devs, int bar) { struct pci_dev *dev; struct pci_dev *found_dev = NULL;


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