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authorZoltan HERPAI <wigyori@uid0.hu>2019-03-13 21:14:47 +0100
committerZoltan HERPAI <wigyori@uid0.hu>2019-03-13 22:43:13 +0100
commit5e247f3ac118c0675d9e9f29a0b1fb8a959b5155 (patch)
tree578760352665d7594d34652474fa604c57c70ab7 /package
parente991fb44e08d643d719d3ca303e4025fb5a8d268 (diff)
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uboot-sunxi: add fix for A20-OLinuXino-Lime2-eMMC rev. K boards
The OLinuXino Lime2 rev. K boards use new PHYs (Micrel KSZ9031), so enable that. Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
Diffstat (limited to 'package')
-rw-r--r--package/boot/uboot-sunxi/patches/063-fix-lime2-revK-add-micrel-PHY.patch44
1 files changed, 44 insertions, 0 deletions
diff --git a/package/boot/uboot-sunxi/patches/063-fix-lime2-revK-add-micrel-PHY.patch b/package/boot/uboot-sunxi/patches/063-fix-lime2-revK-add-micrel-PHY.patch
new file mode 100644
index 0000000000..9ea0642537
--- /dev/null
+++ b/package/boot/uboot-sunxi/patches/063-fix-lime2-revK-add-micrel-PHY.patch
@@ -0,0 +1,44 @@
+--- a/configs/A20-OLinuXino-Lime2-eMMC_defconfig
++++ b/configs/A20-OLinuXino-Lime2-eMMC_defconfig
+@@ -8,6 +8,8 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+ CONFIG_USB0_VBUS_PIN="PC17"
+ CONFIG_USB0_VBUS_DET="PH5"
+ CONFIG_I2C1_ENABLE=y
++CONFIG_PHY_MICREL=y
++CONFIG_PHY_MICREL_KSZ90X1=y
+ CONFIG_SATAPWR="PC3"
+ CONFIG_AHCI=y
+ CONFIG_NR_DRAM_BANKS=1
+--- a/configs/A20-OLinuXino-Lime2_defconfig
++++ b/configs/A20-OLinuXino-Lime2_defconfig
+@@ -7,6 +7,8 @@ CONFIG_MMC0_CD_PIN="PH1"
+ CONFIG_USB0_VBUS_PIN="PC17"
+ CONFIG_USB0_VBUS_DET="PH5"
+ CONFIG_I2C1_ENABLE=y
++CONFIG_PHY_MICREL=y
++CONFIG_PHY_MICREL_KSZ90X1=y
+ CONFIG_SATAPWR="PC3"
+ CONFIG_AHCI=y
+ CONFIG_NR_DRAM_BANKS=1
+--- a/drivers/net/phy/micrel_ksz90x1.c
++++ b/drivers/net/phy/micrel_ksz90x1.c
+@@ -13,6 +13,8 @@
+ #include <errno.h>
+ #include <micrel.h>
+ #include <phy.h>
++#include <asm/io.h>
++#include <asm/arch/clock.h>
+
+ /*
+ * KSZ9021 - KSZ9031 common
+@@ -329,6 +331,10 @@ static int ksz9031_phy_extwrite(struct p
+ static int ksz9031_config(struct phy_device *phydev)
+ {
+ int ret;
++ struct sunxi_ccm_reg *const ccm =
++ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
++
++ setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_DELAY(4));
+
+ ret = ksz9031_of_config(phydev);
+ if (ret)