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| author | Felix Fietkau <nbd@openwrt.org> | 2007-06-04 09:46:30 +0000 |
|---|---|---|
| committer | Felix Fietkau <nbd@openwrt.org> | 2007-06-04 09:46:30 +0000 |
| commit | 4bc7e0ca8a72fd0e2ffc8397393a5792a03cc2d6 (patch) | |
| tree | 2ecb5d5eb92a510f0ce4cee497014a7487b558ba /target/linux/ar7-2.6/files/arch/mips/ar7/clock.c | |
| parent | 43a7635fcf7aebf499bca3e6edb05565d611c20d (diff) | |
| download | upstream-4bc7e0ca8a72fd0e2ffc8397393a5792a03cc2d6.tar.gz upstream-4bc7e0ca8a72fd0e2ffc8397393a5792a03cc2d6.tar.bz2 upstream-4bc7e0ca8a72fd0e2ffc8397393a5792a03cc2d6.zip | |
add ar7-2.6 fixes by Stefan Weil
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@7487 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/ar7-2.6/files/arch/mips/ar7/clock.c')
| -rw-r--r-- | target/linux/ar7-2.6/files/arch/mips/ar7/clock.c | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/target/linux/ar7-2.6/files/arch/mips/ar7/clock.c b/target/linux/ar7-2.6/files/arch/mips/ar7/clock.c index 04b49cc106..43e36ec902 100644 --- a/target/linux/ar7-2.6/files/arch/mips/ar7/clock.c +++ b/target/linux/ar7-2.6/files/arch/mips/ar7/clock.c @@ -174,10 +174,12 @@ static int tnetd7300_get_clock(u32 shift, struct tnetd7300_clock *clock, { int product; int base_clock = ar7_ref_clock; - int prediv = ((clock->ctrl & PREDIV_MASK) >> PREDIV_SHIFT) + 1; - int postdiv = (clock->ctrl & POSTDIV_MASK) + 1; + u32 ctrl = clock->ctrl; + u32 pll = clock->pll; + int prediv = ((ctrl & PREDIV_MASK) >> PREDIV_SHIFT) + 1; + int postdiv = (ctrl & POSTDIV_MASK) + 1; int divisor = prediv * postdiv; - int mul = ((clock->pll & MUL_MASK) >> MUL_SHIFT) + 1; + int mul = ((pll & MUL_MASK) >> MUL_SHIFT) + 1; switch ((*bootcr & (BOOT_PLL_SOURCE_MASK << shift)) >> shift) { case BOOT_PLL_SOURCE_BUS: @@ -197,10 +199,10 @@ static int tnetd7300_get_clock(u32 shift, struct tnetd7300_clock *clock, if (*bootcr & BOOT_PLL_BYPASS) return base_clock / divisor; - if ((clock->pll & PLL_MODE_MASK) == 0) + if ((pll & PLL_MODE_MASK) == 0) return (base_clock >> (mul / 16 + 1)) / divisor; - if ((clock->pll & (PLL_NDIV | PLL_DIV)) == (PLL_NDIV | PLL_DIV)) { + if ((pll & (PLL_NDIV | PLL_DIV)) == (PLL_NDIV | PLL_DIV)) { product = (mul & 1) ? (base_clock * mul) >> 1 : (base_clock * (mul - 1)) >> 2; |