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| author | Gabor Juhos <juhosg@openwrt.org> | 2008-11-26 17:34:08 +0000 |
|---|---|---|
| committer | Gabor Juhos <juhosg@openwrt.org> | 2008-11-26 17:34:08 +0000 |
| commit | b5715049675afdb617a537f322443795ae41b2ca (patch) | |
| tree | 9978364a693e208c7626bc2b6a9efef06bf0a0f6 /target/linux/ar71xx/files/include/asm-mips/mach-ar71xx | |
| parent | 9f93bd51cfb695111000605877602089622e42f0 (diff) | |
| download | upstream-b5715049675afdb617a537f322443795ae41b2ca.tar.gz upstream-b5715049675afdb617a537f322443795ae41b2ca.tar.bz2 upstream-b5715049675afdb617a537f322443795ae41b2ca.zip | |
add definitions for AR91xx specific DDR registers
SVN-Revision: 13364
Diffstat (limited to 'target/linux/ar71xx/files/include/asm-mips/mach-ar71xx')
| -rw-r--r-- | target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/ar71xx.h | 21 |
1 files changed, 13 insertions, 8 deletions
diff --git a/target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/ar71xx.h b/target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/ar71xx.h index 322f3c2ec7..f68bfff199 100644 --- a/target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/ar71xx.h +++ b/target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/ar71xx.h @@ -207,19 +207,24 @@ extern void ar71xx_gpio_function_disable(u32 mask); /* * DDR_CTRL block */ -#define AR71XX_DDR_REG_PCI_WIN0 0x7c -#define AR71XX_DDR_REG_PCI_WIN1 0x80 -#define AR71XX_DDR_REG_PCI_WIN2 0x84 -#define AR71XX_DDR_REG_PCI_WIN3 0x88 -#define AR71XX_DDR_REG_PCI_WIN4 0x8c -#define AR71XX_DDR_REG_PCI_WIN5 0x90 -#define AR71XX_DDR_REG_PCI_WIN6 0x94 -#define AR71XX_DDR_REG_PCI_WIN7 0x98 +#define AR71XX_DDR_REG_PCI_WIN0 0x7c +#define AR71XX_DDR_REG_PCI_WIN1 0x80 +#define AR71XX_DDR_REG_PCI_WIN2 0x84 +#define AR71XX_DDR_REG_PCI_WIN3 0x88 +#define AR71XX_DDR_REG_PCI_WIN4 0x8c +#define AR71XX_DDR_REG_PCI_WIN5 0x90 +#define AR71XX_DDR_REG_PCI_WIN6 0x94 +#define AR71XX_DDR_REG_PCI_WIN7 0x98 #define AR71XX_DDR_REG_FLUSH_GE0 0x9c #define AR71XX_DDR_REG_FLUSH_GE1 0xa0 #define AR71XX_DDR_REG_FLUSH_USB 0xa4 #define AR71XX_DDR_REG_FLUSH_PCI 0xa8 +#define AR91XX_DDR_REG_FLUSH_GE0 0x7c +#define AR91XX_DDR_REG_FLUSH_GE1 0x80 +#define AR91XX_DDR_REG_FLUSH_USB 0x84 +#define AR91XX_DDR_REG_FLUSH_WMAC 0x88 + #define PCI_WIN0_OFFS 0x10000000 #define PCI_WIN1_OFFS 0x11000000 #define PCI_WIN2_OFFS 0x12000000 |