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| author | Gabor Juhos <juhosg@openwrt.org> | 2008-12-04 16:55:43 +0000 |
|---|---|---|
| committer | Gabor Juhos <juhosg@openwrt.org> | 2008-12-04 16:55:43 +0000 |
| commit | d5bbef37feacac6346390f8ad51aec1cab97e2aa (patch) | |
| tree | 5ebe1e02985feb2ca0470c4200f48d3a448049d3 /target/linux/ar71xx/files/include/asm-mips/mach-ar71xx | |
| parent | 5615ec84df1bcf51aee11ffbb438bc116b1f0977 (diff) | |
| download | upstream-d5bbef37feacac6346390f8ad51aec1cab97e2aa.tar.gz upstream-d5bbef37feacac6346390f8ad51aec1cab97e2aa.tar.bz2 upstream-d5bbef37feacac6346390f8ad51aec1cab97e2aa.zip | |
rename reset register definitions
SVN-Revision: 13516
Diffstat (limited to 'target/linux/ar71xx/files/include/asm-mips/mach-ar71xx')
| -rw-r--r-- | target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/ar71xx.h | 28 |
1 files changed, 14 insertions, 14 deletions
diff --git a/target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/ar71xx.h b/target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/ar71xx.h index 5e551a14fd..33614ea354 100644 --- a/target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/ar71xx.h +++ b/target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/ar71xx.h @@ -296,20 +296,20 @@ extern void ar71xx_ddr_flush(u32 reg); /* * RESET block */ -#define RESET_REG_TIMER 0x00 -#define RESET_REG_TIMER_RELOAD 0x04 -#define RESET_REG_WDOG_CTRL 0x08 -#define RESET_REG_WDOG 0x0c -#define RESET_REG_MISC_INT_STATUS 0x10 -#define RESET_REG_MISC_INT_ENABLE 0x14 -#define RESET_REG_PCI_INT_STATUS 0x18 -#define RESET_REG_PCI_INT_ENABLE 0x1c -#define RESET_REG_GLOBAL_INT_STATUS 0x20 -#define RESET_REG_RESET_MODULE 0x24 -#define RESET_REG_PERFC_CTRL 0x2c -#define RESET_REG_PERFC0 0x30 -#define RESET_REG_PERFC1 0x34 -#define RESET_REG_REV_ID 0x90 +#define AR71XX_RESET_REG_TIMER 0x00 +#define AR71XX_RESET_REG_TIMER_RELOAD 0x04 +#define AR71XX_RESET_REG_WDOG_CTRL 0x08 +#define AR71XX_RESET_REG_WDOG 0x0c +#define AR71XX_RESET_REG_MISC_INT_STATUS 0x10 +#define AR71XX_RESET_REG_MISC_INT_ENABLE 0x14 +#define AR71XX_RESET_REG_PCI_INT_STATUS 0x18 +#define AR71XX_RESET_REG_PCI_INT_ENABLE 0x1c +#define AR71XX_RESET_REG_GLOBAL_INT_STATUS 0x20 +#define AR71XX_RESET_REG_RESET_MODULE 0x24 +#define AR71XX_RESET_REG_PERFC_CTRL 0x2c +#define AR71XX_RESET_REG_PERFC0 0x30 +#define AR71XX_RESET_REG_PERFC1 0x34 +#define AR71XX_RESET_REG_REV_ID 0x90 #define WDOG_CTRL_LAST_RESET BIT(31) #define WDOG_CTRL_ACTION_MASK 3 |