aboutsummaryrefslogtreecommitdiffstats
path: root/target/linux/ar71xx/patches-3.3/170-MIPS-ath79-add-PCI-controller-registration-code-for-.patch
diff options
context:
space:
mode:
authorGabor Juhos <juhosg@openwrt.org>2012-07-05 08:26:47 +0000
committerGabor Juhos <juhosg@openwrt.org>2012-07-05 08:26:47 +0000
commitd1b237b335776be151889d5339c672d784475c3c (patch)
treebe879011f76a6bdf58b86fdac7f05b69c39e5fcb /target/linux/ar71xx/patches-3.3/170-MIPS-ath79-add-PCI-controller-registration-code-for-.patch
parent7284cf73d69ffad645078ac5c7910913bf9757a5 (diff)
downloadupstream-d1b237b335776be151889d5339c672d784475c3c.tar.gz
upstream-d1b237b335776be151889d5339c672d784475c3c.tar.bz2
upstream-d1b237b335776be151889d5339c672d784475c3c.zip
ar71xx: add initial support for the QCA955X SoCs
SVN-Revision: 32606
Diffstat (limited to 'target/linux/ar71xx/patches-3.3/170-MIPS-ath79-add-PCI-controller-registration-code-for-.patch')
-rw-r--r--target/linux/ar71xx/patches-3.3/170-MIPS-ath79-add-PCI-controller-registration-code-for-.patch103
1 files changed, 103 insertions, 0 deletions
diff --git a/target/linux/ar71xx/patches-3.3/170-MIPS-ath79-add-PCI-controller-registration-code-for-.patch b/target/linux/ar71xx/patches-3.3/170-MIPS-ath79-add-PCI-controller-registration-code-for-.patch
new file mode 100644
index 0000000000..ccf25ed454
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.3/170-MIPS-ath79-add-PCI-controller-registration-code-for-.patch
@@ -0,0 +1,103 @@
+From 8bb54348722216a1dd6905d9d031ebdaa3a544a4 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Sun, 24 Jun 2012 23:05:20 +0200
+Subject: [PATCH 26/34] MIPS: ath79: add PCI controller registration code for the QCA9558 SoC
+
+---
+ arch/mips/ath79/Kconfig | 2 +
+ arch/mips/ath79/pci.c | 36 ++++++++++++++++++++++++
+ arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 13 ++++++++
+ 3 files changed, 51 insertions(+), 0 deletions(-)
+
+--- a/arch/mips/ath79/Kconfig
++++ b/arch/mips/ath79/Kconfig
+@@ -90,6 +90,8 @@ config SOC_AR934X
+
+ config SOC_QCA955X
+ select USB_ARCH_HAS_EHCI
++ select HW_HAS_PCI
++ select PCI_AR724X if PCI
+ def_bool n
+
+ config PCI_AR724X
+--- a/arch/mips/ath79/pci.c
++++ b/arch/mips/ath79/pci.c
+@@ -49,6 +49,21 @@ static const struct ath79_pci_irq ar724x
+ }
+ };
+
++static const struct ath79_pci_irq qca955x_pci_irq_map[] __initconst = {
++ {
++ .bus = 0,
++ .slot = 0,
++ .pin = 1,
++ .irq = ATH79_PCI_IRQ(0),
++ },
++ {
++ .bus = 1,
++ .slot = 0,
++ .pin = 1,
++ .irq = ATH79_PCI_IRQ(1),
++ },
++};
++
+ int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin)
+ {
+ int irq = -1;
+@@ -64,6 +79,9 @@ int __init pcibios_map_irq(const struct
+ soc_is_ar9344()) {
+ ath79_pci_irq_map = ar724x_pci_irq_map;
+ ath79_pci_nr_irqs = ARRAY_SIZE(ar724x_pci_irq_map);
++ } else if (soc_is_qca955x()) {
++ ath79_pci_irq_map = qca955x_pci_irq_map;
++ ath79_pci_nr_irqs = ARRAY_SIZE(qca955x_pci_irq_map);
+ } else {
+ pr_crit("pci %s: invalid irq map\n",
+ pci_name((struct pci_dev *) dev));
+@@ -215,6 +233,24 @@ int __init ath79_register_pci(void)
+ AR724X_PCI_MEM_SIZE,
+ 0,
+ ATH79_IP2_IRQ(0));
++ } else if (soc_is_qca9558()) {
++ pdev = ath79_register_pci_ar724x(0,
++ QCA955X_PCI_CFG_BASE0,
++ QCA955X_PCI_CTRL_BASE0,
++ QCA955X_PCI_CRP_BASE0,
++ QCA955X_PCI_MEM_BASE0,
++ QCA955X_PCI_MEM_SIZE,
++ 0,
++ ATH79_IP2_IRQ(0));
++
++ pdev = ath79_register_pci_ar724x(1,
++ QCA955X_PCI_CFG_BASE1,
++ QCA955X_PCI_CTRL_BASE1,
++ QCA955X_PCI_CRP_BASE1,
++ QCA955X_PCI_MEM_BASE1,
++ QCA955X_PCI_MEM_SIZE,
++ 1,
++ ATH79_IP3_IRQ(2));
+ } else {
+ /* No PCI support */
+ return -ENODEV;
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -92,6 +92,19 @@
+ #define AR934X_EHCI_BASE 0x1b000000
+ #define AR934X_EHCI_SIZE 0x1000
+
++#define QCA955X_PCI_MEM_BASE0 0x10000000
++#define QCA955X_PCI_MEM_BASE1 0x12000000
++#define QCA955X_PCI_MEM_SIZE 0x02000000
++#define QCA955X_PCI_CFG_BASE0 0x14000000
++#define QCA955X_PCI_CFG_BASE1 0x16000000
++#define QCA955X_PCI_CFG_SIZE 0x1000
++#define QCA955X_PCI_CRP_BASE0 (AR71XX_APB_BASE + 0x000c0000)
++#define QCA955X_PCI_CRP_BASE1 (AR71XX_APB_BASE + 0x00250000)
++#define QCA955X_PCI_CRP_SIZE 0x1000
++#define QCA955X_PCI_CTRL_BASE0 (AR71XX_APB_BASE + 0x000f0000)
++#define QCA955X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000)
++#define QCA955X_PCI_CTRL_SIZE 0x100
++
+ #define QCA955X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
+ #define QCA955X_WMAC_SIZE 0x20000
+ #define QCA955X_EHCI0_BASE 0x1b000000