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authorFelix Fietkau <nbd@nbd.name>2016-05-14 20:24:37 +0200
committerFelix Fietkau <nbd@nbd.name>2016-05-15 20:55:39 +0200
commit5b34dffcbd6175d92f871b69098e027341b6c82e (patch)
tree4435dd82308ac86ab73aaaf8de0b83d223ab8b2b /target/linux/ar71xx/patches-4.4/601-MIPS-ath79-add-more-register-defines.patch
parente30608b736f44e70da6bd29fbcfdc9dd5ec42f02 (diff)
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ar71xx: fix DDR write buffer flushing issues with 4.4
Signed-off-by: Felix Fietkau <nbd@nbd.name>
Diffstat (limited to 'target/linux/ar71xx/patches-4.4/601-MIPS-ath79-add-more-register-defines.patch')
-rw-r--r--target/linux/ar71xx/patches-4.4/601-MIPS-ath79-add-more-register-defines.patch4
1 files changed, 2 insertions, 2 deletions
diff --git a/target/linux/ar71xx/patches-4.4/601-MIPS-ath79-add-more-register-defines.patch b/target/linux/ar71xx/patches-4.4/601-MIPS-ath79-add-more-register-defines.patch
index 0126f6a3b9..c5035778a2 100644
--- a/target/linux/ar71xx/patches-4.4/601-MIPS-ath79-add-more-register-defines.patch
+++ b/target/linux/ar71xx/patches-4.4/601-MIPS-ath79-add-more-register-defines.patch
@@ -155,7 +155,7 @@
+#define AR934X_RESET_LUT BIT(2)
+#define AR934X_RESET_MBOX BIT(1)
+#define AR934X_RESET_I2S BIT(0)
-+
+
+#define QCA955X_RESET_HOST BIT(31)
+#define QCA955X_RESET_SLIC BIT(30)
+#define QCA955X_RESET_HDMA BIT(29)
@@ -188,7 +188,7 @@
+#define QCA955X_RESET_LUT BIT(2)
+#define QCA955X_RESET_MBOX BIT(1)
+#define QCA955X_RESET_I2S BIT(0)
-
++
+#define AR933X_BOOTSTRAP_MDIO_GPIO_EN BIT(18)
+#define AR933X_BOOTSTRAP_EEPBUSY BIT(4)
#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)