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authorHenryk Heisig <hyniu@o2.pl>2017-01-06 21:21:11 +0100
committerJo-Philipp Wich <jo@mein.io>2017-01-26 11:38:20 +0100
commiteec0c413759d360775df7419dec1bf46f6b63483 (patch)
tree74db76aba1f400f7cde3bc936fcac6d2a269cce9 /target/linux/ar71xx/patches-4.4
parentb822f29f25e145b2870949d7678cdf1b6b15c106 (diff)
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ar71xx: QCA956X: add missing register
Signed-off-by: Henryk Heisig <hyniu@o2.pl>
Diffstat (limited to 'target/linux/ar71xx/patches-4.4')
-rw-r--r--target/linux/ar71xx/patches-4.4/622-MIPS-ath79-add-more-register-defines-for-QCA956x-SoC.patch38
-rw-r--r--target/linux/ar71xx/patches-4.4/640-MIPS-ath79-add-QCA955x-wmac-reset.patch2
-rw-r--r--target/linux/ar71xx/patches-4.4/820-MIPS-ath79-add_gpio_function2_setup.patch4
3 files changed, 41 insertions, 3 deletions
diff --git a/target/linux/ar71xx/patches-4.4/622-MIPS-ath79-add-more-register-defines-for-QCA956x-SoC.patch b/target/linux/ar71xx/patches-4.4/622-MIPS-ath79-add-more-register-defines-for-QCA956x-SoC.patch
new file mode 100644
index 0000000000..dff354398c
--- /dev/null
+++ b/target/linux/ar71xx/patches-4.4/622-MIPS-ath79-add-more-register-defines-for-QCA956x-SoC.patch
@@ -0,0 +1,38 @@
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -157,6 +157,10 @@
+ #define QCA956X_EHCI0_BASE 0x1b000000
+ #define QCA956X_EHCI1_BASE 0x1b400000
+ #define QCA956X_EHCI_SIZE 0x200
++#define QCA956X_GMAC_SGMII_BASE (AR71XX_APB_BASE + 0x00070000)
++#define QCA956X_GMAC_SGMII_SIZE 0x64
++#define QCA956X_PLL_BASE (AR71XX_APB_BASE + 0x00050000)
++#define QCA956X_PLL_SIZE 0x50
+ #define QCA956X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
+ #define QCA956X_GMAC_SIZE 0x64
+
+@@ -404,6 +408,7 @@
+ #define QCA956X_PLL_DDR_CONFIG_REG 0x08
+ #define QCA956X_PLL_DDR_CONFIG1_REG 0x0c
+ #define QCA956X_PLL_CLK_CTRL_REG 0x10
++#define QCA956X_PLL_ETH_XMII_CONTROL_REG 0x30
+
+ #define QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT 12
+ #define QCA956X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
+@@ -1186,4 +1191,16 @@
+ #define QCA955X_ETH_CFG_TXE_DELAY_MASK 0x3
+ #define QCA955X_ETH_CFG_TXE_DELAY_SHIFT 20
+
++/*
++ * QCA956X GMAC Interface
++ */
++
++#define QCA956X_GMAC_REG_ETH_CFG 0x00
++
++#define QCA956X_ETH_CFG_SW_ONLY_MODE BIT(7)
++#define QCA956X_ETH_CFG_SW_PHY_SWAP BIT(8)
++#define QCA956X_ETH_CFG_SW_PHY_ADDR_SWAP BIT(9)
++#define QCA956X_ETH_CFG_SW_APB_ACCESS BIT(10)
++#define QCA956X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13)
++
+ #endif /* __ASM_MACH_AR71XX_REGS_H */
diff --git a/target/linux/ar71xx/patches-4.4/640-MIPS-ath79-add-QCA955x-wmac-reset.patch b/target/linux/ar71xx/patches-4.4/640-MIPS-ath79-add-QCA955x-wmac-reset.patch
index add2992186..8aa5957a71 100644
--- a/target/linux/ar71xx/patches-4.4/640-MIPS-ath79-add-QCA955x-wmac-reset.patch
+++ b/target/linux/ar71xx/patches-4.4/640-MIPS-ath79-add-QCA955x-wmac-reset.patch
@@ -20,7 +20,7 @@
#define AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000)
#define AR71XX_UART_SIZE 0x100
#define AR71XX_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000)
-@@ -218,6 +218,9 @@
+@@ -222,6 +222,9 @@
#define QCA953X_DDR_REG_FLUSH_PCIE 0xa8
#define QCA953X_DDR_REG_FLUSH_WMAC 0xac
diff --git a/target/linux/ar71xx/patches-4.4/820-MIPS-ath79-add_gpio_function2_setup.patch b/target/linux/ar71xx/patches-4.4/820-MIPS-ath79-add_gpio_function2_setup.patch
index 7db6ad361f..6b331587d1 100644
--- a/target/linux/ar71xx/patches-4.4/820-MIPS-ath79-add_gpio_function2_setup.patch
+++ b/target/linux/ar71xx/patches-4.4/820-MIPS-ath79-add_gpio_function2_setup.patch
@@ -48,7 +48,7 @@ functions on the Arduino Yun.
void __iomem *reg = ath79_gpio_get_function_reg();
--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
-@@ -850,6 +850,7 @@
+@@ -855,6 +855,7 @@
#define AR71XX_GPIO_REG_INT_PENDING 0x20
#define AR71XX_GPIO_REG_INT_ENABLE 0x24
#define AR71XX_GPIO_REG_FUNC 0x28
@@ -56,7 +56,7 @@ functions on the Arduino Yun.
#define AR934X_GPIO_REG_OUT_FUNC0 0x2c
#define AR934X_GPIO_REG_OUT_FUNC1 0x30
-@@ -974,6 +975,8 @@
+@@ -979,6 +980,8 @@
#define AR724X_GPIO_FUNC_UART_EN BIT(1)
#define AR724X_GPIO_FUNC_JTAG_DISABLE BIT(0)