diff options
| author | Koen Vandeputte <koen.vandeputte@ncentric.com> | 2018-10-10 11:42:42 +0200 |
|---|---|---|
| committer | Koen Vandeputte <koen.vandeputte@ncentric.com> | 2018-10-10 15:12:01 +0200 |
| commit | 13f283198ef49dedd49c106176f80dfffa16c3a8 (patch) | |
| tree | 33f816b19644afca9c3798a1120007ff45441dde /target/linux/ar71xx/patches-4.9/940-qca955x-add-more-registers.patch | |
| parent | 77d004de6d09edc6d8a5cf77471d52d4865ae577 (diff) | |
| download | upstream-13f283198ef49dedd49c106176f80dfffa16c3a8.tar.gz upstream-13f283198ef49dedd49c106176f80dfffa16c3a8.tar.bz2 upstream-13f283198ef49dedd49c106176f80dfffa16c3a8.zip | |
ar71xx: remove linux 4.9 support
Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
Diffstat (limited to 'target/linux/ar71xx/patches-4.9/940-qca955x-add-more-registers.patch')
| -rw-r--r-- | target/linux/ar71xx/patches-4.9/940-qca955x-add-more-registers.patch | 42 |
1 files changed, 0 insertions, 42 deletions
diff --git a/target/linux/ar71xx/patches-4.9/940-qca955x-add-more-registers.patch b/target/linux/ar71xx/patches-4.9/940-qca955x-add-more-registers.patch deleted file mode 100644 index ff72308465..0000000000 --- a/target/linux/ar71xx/patches-4.9/940-qca955x-add-more-registers.patch +++ /dev/null @@ -1,42 +0,0 @@ ---- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -@@ -134,7 +134,7 @@ - #define QCA955X_PCI_CTRL_SIZE 0x100 - - #define QCA955X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) --#define QCA955X_GMAC_SIZE 0x40 -+#define QCA955X_GMAC_SIZE 0x64 - #define QCA955X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) - #define QCA955X_WMAC_SIZE 0x20000 - #define QCA955X_EHCI0_BASE 0x1b000000 -@@ -1269,7 +1269,11 @@ - */ - - #define QCA955X_GMAC_REG_ETH_CFG 0x00 -+#define QCA955X_GMAC_REG_SGMII_RESET 0x14 - #define QCA955X_GMAC_REG_SGMII_SERDES 0x18 -+#define QCA955X_GMAC_REG_MR_AN_CONTROL 0x1c -+#define QCA955X_GMAC_REG_MR_AN_STATUS 0x20 -+#define QCA955X_GMAC_REG_SGMII_DEBUG 0x58 - - #define QCA955X_ETH_CFG_RGMII_EN BIT(0) - #define QCA955X_ETH_CFG_MII_GE0 BIT(1) -@@ -1291,6 +1295,18 @@ - #define QCA955X_ETH_CFG_TXE_DELAY_MASK 0x3 - #define QCA955X_ETH_CFG_TXE_DELAY_SHIFT 20 - -+#define QCA955X_SGMII_RESET_RX_CLK_N_RESET 0x0 -+#define QCA955X_SGMII_RESET_RX_CLK_N BIT(0) -+#define QCA955X_SGMII_RESET_TX_CLK_N BIT(1) -+#define QCA955X_SGMII_RESET_RX_125M_N BIT(2) -+#define QCA955X_SGMII_RESET_TX_125M_N BIT(3) -+#define QCA955X_SGMII_RESET_HW_RX_125M_N BIT(4) -+ -+#define QCA955X_MR_AN_CONTROL_PHY_RESET BIT(15) -+#define QCA955X_MR_AN_CONTROL_AN_ENABLE BIT(12) -+ -+#define QCA955X_MR_AN_STATUS_AN_ABILITY BIT(3) -+ - #define QCA955X_SGMII_SERDES_LOCK_DETECT_STATUS BIT(15) - #define QCA955X_SGMII_SERDES_RES_CALIBRATION_SHIFT 23 - #define QCA955X_SGMII_SERDES_RES_CALIBRATION_MASK 0xf |