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authorDavid Bauer <mail@david-bauer.net>2018-08-06 16:15:04 +0200
committerJohn Crispin <john@phrozen.org>2018-08-08 15:48:57 +0200
commitf4f99ec9737c653815268f2efad0210caaa32e2d (patch)
treeb0aa4b6488ecfbd36f6f11b1cd7da75cc3fb9d0f /target/linux/ar71xx/patches-4.9
parentfbe17867daddf76ec26be7dbf6b9af3cfad4a54f (diff)
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ar71xx: fix QCA955X SGMII link loss
The QCA955X is affected by a hardware bug which causes link-loss of the SGMII link between SoC and PHY. This happens on change of link-state or speed. It is not really known what causes this bug. It definitely occurs when using a AR8033 Gigabit Ethernet PHY. Qualcomm solves this Bug in a similar fashion. We need to apply the fix on a per-device base via platform-data as performing the fixup work will break connectivity in case the SGMII interface is connected to a Switch. This bug was first proposed to be fixed by Sven Eckelmann in 2016. https://patchwork.ozlabs.org/patch/604782/ Based-on-patch-by: Sven Eckelmann <sven.eckelmann@open-mesh.com> Signed-off-by: David Bauer <mail@david-bauer.net>
Diffstat (limited to 'target/linux/ar71xx/patches-4.9')
-rw-r--r--target/linux/ar71xx/patches-4.9/940-qca955x-add-more-registers.patch44
1 files changed, 44 insertions, 0 deletions
diff --git a/target/linux/ar71xx/patches-4.9/940-qca955x-add-more-registers.patch b/target/linux/ar71xx/patches-4.9/940-qca955x-add-more-registers.patch
new file mode 100644
index 0000000000..97400e3ec8
--- /dev/null
+++ b/target/linux/ar71xx/patches-4.9/940-qca955x-add-more-registers.patch
@@ -0,0 +1,44 @@
+Index: linux-4.9.111/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+===================================================================
+--- linux-4.9.111.orig/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ linux-4.9.111/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -134,7 +134,7 @@
+ #define QCA955X_PCI_CTRL_SIZE 0x100
+
+ #define QCA955X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
+-#define QCA955X_GMAC_SIZE 0x40
++#define QCA955X_GMAC_SIZE 0x64
+ #define QCA955X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
+ #define QCA955X_WMAC_SIZE 0x20000
+ #define QCA955X_EHCI0_BASE 0x1b000000
+@@ -1269,7 +1269,11 @@
+ */
+
+ #define QCA955X_GMAC_REG_ETH_CFG 0x00
++#define QCA955X_GMAC_REG_SGMII_RESET 0x14
+ #define QCA955X_GMAC_REG_SGMII_SERDES 0x18
++#define QCA955X_GMAC_REG_MR_AN_CONTROL 0x1c
++#define QCA955X_GMAC_REG_MR_AN_STATUS 0x20
++#define QCA955X_GMAC_REG_SGMII_DEBUG 0x58
+
+ #define QCA955X_ETH_CFG_RGMII_EN BIT(0)
+ #define QCA955X_ETH_CFG_MII_GE0 BIT(1)
+@@ -1291,6 +1295,18 @@
+ #define QCA955X_ETH_CFG_TXE_DELAY_MASK 0x3
+ #define QCA955X_ETH_CFG_TXE_DELAY_SHIFT 20
+
++#define QCA955X_SGMII_RESET_RX_CLK_N_RESET 0x0
++#define QCA955X_SGMII_RESET_RX_CLK_N BIT(0)
++#define QCA955X_SGMII_RESET_TX_CLK_N BIT(1)
++#define QCA955X_SGMII_RESET_RX_125M_N BIT(2)
++#define QCA955X_SGMII_RESET_TX_125M_N BIT(3)
++#define QCA955X_SGMII_RESET_HW_RX_125M_N BIT(4)
++
++#define QCA955X_MR_AN_CONTROL_PHY_RESET BIT(15)
++#define QCA955X_MR_AN_CONTROL_AN_ENABLE BIT(12)
++
++#define QCA955X_MR_AN_STATUS_AN_ABILITY BIT(3)
++
+ #define QCA955X_SGMII_SERDES_LOCK_DETECT_STATUS BIT(15)
+ #define QCA955X_SGMII_SERDES_RES_CALIBRATION_SHIFT 23
+ #define QCA955X_SGMII_SERDES_RES_CALIBRATION_MASK 0xf