aboutsummaryrefslogtreecommitdiffstats
path: root/target/linux/ar71xx
diff options
context:
space:
mode:
authorFelix Fietkau <nbd@openwrt.org>2015-11-02 18:20:51 +0000
committerFelix Fietkau <nbd@openwrt.org>2015-11-02 18:20:51 +0000
commit0b296d380807050cee0a682caf388d6d71aef435 (patch)
treefad0c9bc9a79b8609ef7f0bcf9078f8bec87e2ef /target/linux/ar71xx
parenta94636737197c82245ca1a346e1908ca60a89d45 (diff)
downloadupstream-0b296d380807050cee0a682caf388d6d71aef435.tar.gz
upstream-0b296d380807050cee0a682caf388d6d71aef435.tar.bz2
upstream-0b296d380807050cee0a682caf388d6d71aef435.zip
ar71xx: use correct PLL configuration register bitmask for QCA956x SoC.
Incorrect value causes clock inaccuracy as huge as 1/60. Signed-off-by: Dmitry Ivanov <dima@ubnt.com> Signed-off-by: Felix Fietkau <nbd@openwrt.org> SVN-Revision: 47363
Diffstat (limited to 'target/linux/ar71xx')
-rw-r--r--target/linux/ar71xx/patches-4.1/621-MIPS-ath79-add-support-for-QCA956x-SoC.patch4
1 files changed, 2 insertions, 2 deletions
diff --git a/target/linux/ar71xx/patches-4.1/621-MIPS-ath79-add-support-for-QCA956x-SoC.patch b/target/linux/ar71xx/patches-4.1/621-MIPS-ath79-add-support-for-QCA956x-SoC.patch
index 761eda4df5..ca92d0ec87 100644
--- a/target/linux/ar71xx/patches-4.1/621-MIPS-ath79-add-support-for-QCA956x-SoC.patch
+++ b/target/linux/ar71xx/patches-4.1/621-MIPS-ath79-add-support-for-QCA956x-SoC.patch
@@ -529,7 +529,7 @@
+#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT 0
+#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK 0x1f
+#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT 5
-+#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK 0x3fff
++#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK 0x1fff
+#define QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT 18
+#define QCA956X_PLL_CPU_CONFIG1_NINT_MASK 0x1ff
+
@@ -541,7 +541,7 @@
+#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT 0
+#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK 0x1f
+#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT 5
-+#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK 0x3fff
++#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK 0x1fff
+#define QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT 18
+#define QCA956X_PLL_DDR_CONFIG1_NINT_MASK 0x1ff
+