ath79: add support for Siemens WS-AP3610

Hardware
--------
SoC:  Atheros AR7161
RAM:  Samsung K4H511638D-UCCC
      2x 64M DDR1
SPI:  Micron M25P128 (16M)
WiFi: Atheros AR9160 bgn
      Atheros AR9160 an
ETH:  Broadcom BCM5481
LED:  Power (Green/Red)
      ETH (Green / Blue / Yellow)
          (PHY-controlled)
      WiFi 5 (Green / Blue)
      WiFi 2 (Green / Blue)
BTN:  Reset

Serial: Cisco-Style RJ45 - 115200 8N1

Installation
------------

1. Download the OpenWrt initramfs-image. Place it into a TFTP server
   root directory and rename it to 1401A8C0.img. Configure the TFTP
   server to listen at 192.168.1.66/24.

2. Connect the TFTP server to the access point.

3. Connect to the serial console of the access point. Attach power and
   interrupt the boot procedure when prompted (bootdelay is 1 second).

4. Configure the U-Boot environment for booting OpenWrt from Ram and
   flash:

   $ setenv boot_openwrt 'setenv bootargs; bootm 0xbf080000'
   $ setenv ramboot_openwrt 'setenv serverip 192.168.1.66;
     tftpboot; bootm'
   $ saveenv

5. Load OpenWrt into memory:

   $ run ramboot_openwrt

   Wait for the image to boot.

6. Transfer the OpenWrt sysupgrade image to the device. Write the image
   to flash using sysupgrade:

   $ sysupgrade -n /path/to/openwrt-sysuograde.bin

Signed-off-by: David Bauer <mail@david-bauer.net>

1 files changed, 186 insertions, 0 deletions

diff --git a/target/linux/ath79/dts/ar7161_siemens_ws-ap3610.dts b/target/linux/ath79/dts/ar7161_siemens_ws-ap3610.dts
new file mode 100644
index 0000000000..8e0a80cb32
--- /dev/null
+++ b/target/linux/ath79/dts/ar7161_siemens_ws-ap3610.dts
@@ -0,0 +1,186 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+#include "ar7100.dtsi"
+
+/ {
+	compatible = "siemens,ws-ap3610", "qca,ar7161";
+	model = "Siemens WS-AP3610";
+
+	chosen {
+		bootargs = "console=ttyS0,115200";
+	};
+
+	aliases {
+		led-boot = &led_power_green;
+		led-failsafe = &led_power_red;
+		led-running = &led_power_green;
+		led-upgrade = &led_power_red;
+		label-mac-device = &eth0;
+	};
+
+	extosc: ref {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-output-names = "ref";
+		clock-frequency = <40000000>;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led_power_green: led_power_green {
+			label = "ws-ap3610:green:power";
+			gpios = <&gpio 7 GPIO_ACTIVE_LOW>;
+		};
+
+		led_power_red: led_power_red {
+			label = "ws-ap3610:red:power";
+			gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
+		};
+
+		led_wlan5_blue {
+			label = "ws-ap3610:blue:wlan5";
+			gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
+			linux,default-trigger = "phy0tpt";
+		};
+
+		led_wlan5_green {
+			label = "ws-ap3610:green:wlan5";
+			gpios = <&gpio 3 GPIO_ACTIVE_LOW>;
+		};
+
+		led_wlan2_blue {
+			label = "ws-ap3610:blue:wlan2";
+			gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
+			linux,default-trigger = "phy1tpt";
+		};
+
+		led_wlan2_green {
+			label = "ws-ap3610:green:wlan2";
+			gpios = <&gpio 5 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	keys {
+		compatible = "gpio-keys";
+
+		reset {
+			label = "reset";
+			linux,code = <KEY_RESTART>;
+			gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
+		};
+	};
+};
+
+&pcie0 {
+	status = "okay";
+};
+
+&uart {
+	status = "okay";
+};
+
+&mdio0 {
+	status = "okay";
+
+	phy0: ethernet-phy@0 {
+		/*
+		 * When the compatible-is missing, PHY autodetection
+		 * is performed, but the PHY-ID reads all 0xff.
+		 *
+		 * Linux does not create the device in this case,
+		 * and the reset is never even de-asserted.
+		 */
+		compatible = "ethernet-phy-id0143.bca2",
+				"ethernet-phy-ieee802.3-c22";
+		reg = <0>;
+
+		resets = <&rst 8>;
+		reset-names = "phy";
+		reset-assert-us = <10000>;
+		reset-deassert-us = <10000>;
+	};
+};
+
+&eth0 {
+	status = "okay";
+
+	phy-mode = "rgmii-id";
+	phy-handle = <&phy0>;
+};
+
+&spi {
+	status = "okay";
+
+	num-cs = <1>;
+
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <25000000>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "u-boot";
+				reg = <0x0 0x40000>;
+				read-only;
+			};
+
+			partition@40000 {
+				label = "u-boot-bak";
+				reg = <0x40000 0x40000>;
+				read-only;
+			};
+
+			partition@80000 {
+				compatible = "denx,uimage";
+				label = "firmware";
+				reg = <0x80000 0xe00000>;
+			};
+
+			partition@e80000 {
+				label = "cfg1";
+				reg = <0xe80000 0x40000>;
+				read-only;
+			};
+
+			partition@ec0000 {
+				label = "cfg2";
+				reg = <0xec0000 0x40000>;
+				read-only;
+			};
+
+			partition@f00000 {
+				label = "nvram1";
+				reg = <0xf00000 0x40000>;
+				read-only;
+			};
+
+			partition@f40000 {
+				label = "nvram2";
+				reg = <0xf40000 0x40000>;
+				read-only;
+			};
+
+			partition@f80000 {
+				label = "rsvd1";
+				reg = <0xf80000 0x40000>;
+				read-only;
+			};
+
+			partition@fc0000 {
+				label = "rsvd2";
+				reg = <0xfc0000 0x40000>;
+				read-only;
+			};
+		};
+	};
+};