ath79: add new OF only target for QCA MIPS silicon

This target aims to replace ar71xx mid-term. The big part that is still
missing is making the MMIO/AHB wifi work using OF. NAND and mikrotik
subtargets will follow.

Signed-off-by: John Crispin <john@phrozen.org>

1 files changed, 81 insertions, 0 deletions

diff --git a/target/linux/ath79/dts/ath79.dtsi b/target/linux/ath79/dts/ath79.dtsi
new file mode 100644
index 0000000000..c49f4652fe
--- /dev/null
+++ b/target/linux/ath79/dts/ath79.dtsi
@@ -0,0 +1,81 @@
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	cpuintc: interrupt-controller {
+		compatible = "qca,ar7100-cpu-intc";
+
+		interrupt-controller;
+		#interrupt-cells = <1>;
+	};
+
+	ahb {
+		compatible = "simple-bus";
+		ranges;
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		interrupt-parent = <&cpuintc>;
+
+		apb {
+			compatible = "simple-bus";
+			ranges;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			interrupt-parent = <&miscintc>;
+
+			miscintc: interrupt-controller@18060010 {
+				compatible = "qca,ar7240-misc-intc";
+				reg = <0x18060010 0x4>;
+
+				interrupt-parent = <&cpuintc>;
+				interrupts = <6>;
+
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		eth0: eth@19000000 {
+			status = "disabled";
+
+			compatible = "qca,ath79-eth", "syscon";
+			reg = <0x19000000 0x200>;
+
+			interrupts = <4>;
+			phy-mode = "mii";
+
+			mdio0: mdio-bus {
+				status = "disabled";
+
+				regmap = <&eth0>;
+
+				clocks = <&pll ATH79_CLK_MDIO>;
+				clock-names = "ref";
+			};
+		};
+
+		eth1: eth@1a000000 {
+			status = "disabled";
+
+			compatible = "qca,ath79-eth", "syscon";
+			reg = <0x1a000000 0x200>;
+
+			interrupts = <5>;
+			phy-mode = "mii";
+
+			mdio1: mdio-bus {
+				status = "disabled";
+
+				regmap = <&eth1>;
+
+				clocks = <&pll ATH79_CLK_MDIO>;
+				clock-names = "ref";
+			};
+		};
+	};
+};