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author | Felix Fietkau <nbd@openwrt.org> | 2009-09-16 12:24:22 +0000 |
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committer | Felix Fietkau <nbd@openwrt.org> | 2009-09-16 12:24:22 +0000 |
commit | 8bf5ee0324976c1665c626e75d419bd300d7b42e (patch) | |
tree | 310cfc158c5d63f9f2eb3f9c7292ff2f21ae6109 /target/linux/atheros/patches-2.6.28/002-mips_clocksource_init_war.patch | |
parent | 9e1fd17d108dd845fa0d60670537de373d29b1e9 (diff) | |
download | upstream-8bf5ee0324976c1665c626e75d419bd300d7b42e.tar.gz upstream-8bf5ee0324976c1665c626e75d419bd300d7b42e.tar.bz2 upstream-8bf5ee0324976c1665c626e75d419bd300d7b42e.zip |
atheros: remove 2.6.28 support
SVN-Revision: 17593
Diffstat (limited to 'target/linux/atheros/patches-2.6.28/002-mips_clocksource_init_war.patch')
-rw-r--r-- | target/linux/atheros/patches-2.6.28/002-mips_clocksource_init_war.patch | 56 |
1 files changed, 0 insertions, 56 deletions
diff --git a/target/linux/atheros/patches-2.6.28/002-mips_clocksource_init_war.patch b/target/linux/atheros/patches-2.6.28/002-mips_clocksource_init_war.patch deleted file mode 100644 index 03a66ff133..0000000000 --- a/target/linux/atheros/patches-2.6.28/002-mips_clocksource_init_war.patch +++ /dev/null @@ -1,56 +0,0 @@ ---- a/arch/mips/kernel/cevt-r4k.c -+++ b/arch/mips/kernel/cevt-r4k.c -@@ -15,6 +15,22 @@ - #include <asm/cevt-r4k.h> - - /* -+ * Compare interrupt can be routed and latched outside the core, -+ * so a single execution hazard barrier may not be enough to give -+ * it time to clear as seen in the Cause register. 4 time the -+ * pipeline depth seems reasonably conservative, and empirically -+ * works better in configurations with high CPU/bus clock ratios. -+ */ -+ -+#define compare_change_hazard() \ -+ do { \ -+ irq_disable_hazard(); \ -+ irq_disable_hazard(); \ -+ irq_disable_hazard(); \ -+ irq_disable_hazard(); \ -+ } while (0) -+ -+/* - * The SMTC Kernel for the 34K, 1004K, et. al. replaces several - * of these routines with SMTC-specific variants. - */ -@@ -30,6 +46,7 @@ static int mips_next_event(unsigned long - cnt = read_c0_count(); - cnt += delta; - write_c0_compare(cnt); -+ compare_change_hazard(); - res = ((int)(read_c0_count() - cnt) > 0) ? -ETIME : 0; - return res; - } -@@ -99,22 +116,6 @@ static int c0_compare_int_pending(void) - return (read_c0_cause() >> cp0_compare_irq) & 0x100; - } - --/* -- * Compare interrupt can be routed and latched outside the core, -- * so a single execution hazard barrier may not be enough to give -- * it time to clear as seen in the Cause register. 4 time the -- * pipeline depth seems reasonably conservative, and empirically -- * works better in configurations with high CPU/bus clock ratios. -- */ -- --#define compare_change_hazard() \ -- do { \ -- irq_disable_hazard(); \ -- irq_disable_hazard(); \ -- irq_disable_hazard(); \ -- irq_disable_hazard(); \ -- } while (0) -- - int c0_compare_int_usable(void) - { - unsigned int delta; |