Remove files now present upstream in files-2.6.25 (This is mostly just drivers/ssb and include/linux/ssb) [brcm47xx] Regenerate patches against 2.6.25.1 kernel+files set Default is still to build against 2.6.23.16

SVN-Revision: 11155

1 files changed, 68 insertions, 54 deletions

diff --git a/target/linux/brcm47xx/patches-2.6.25/150-cpu_fixes.patch b/target/linux/brcm47xx/patches-2.6.25/150-cpu_fixes.patch
index d19ba81fad..a5f9a88ced 100644
--- a/target/linux/brcm47xx/patches-2.6.25/150-cpu_fixes.patch
+++ b/target/linux/brcm47xx/patches-2.6.25/150-cpu_fixes.patch
@@ -1,23 +1,23 @@
-Index: linux-2.6.23/arch/mips/kernel/genex.S
+Index: linux-2.6.25/arch/mips/kernel/genex.S
 ===================================================================
---- linux-2.6.23.orig/arch/mips/kernel/genex.S	2007-10-13 11:29:46.219648163 +0200
-+++ linux-2.6.23/arch/mips/kernel/genex.S	2007-10-13 11:29:49.619841933 +0200
-@@ -51,6 +51,10 @@
+--- linux-2.6.25.orig/arch/mips/kernel/genex.S	2008-04-26 21:56:21.000000000 +0100
++++ linux-2.6.25/arch/mips/kernel/genex.S	2008-04-26 21:57:14.000000000 +0100
+@@ -51,6 +51,10 @@ NESTED(except_vec1_generic, 0, sp)
  NESTED(except_vec3_generic, 0, sp)
  	.set	push
  	.set	noat
-+#ifdef CONFIG_BCM947XX
++#ifdef CONFIG_BCM47XX
 +	nop
 +	nop
 +#endif
  #if R5432_CP0_INTERRUPT_WAR
  	mfc0	k0, CP0_INDEX
  #endif
-Index: linux-2.6.23/arch/mips/mm/c-r4k.c
+Index: linux-2.6.25/arch/mips/mm/c-r4k.c
 ===================================================================
---- linux-2.6.23.orig/arch/mips/mm/c-r4k.c	2007-10-13 11:29:46.227648623 +0200
-+++ linux-2.6.23/arch/mips/mm/c-r4k.c	2007-10-13 11:29:49.619841933 +0200
-@@ -30,6 +30,9 @@
+--- linux-2.6.25.orig/arch/mips/mm/c-r4k.c	2008-04-26 21:57:13.000000000 +0100
++++ linux-2.6.25/arch/mips/mm/c-r4k.c	2008-04-26 21:57:14.000000000 +0100
+@@ -33,6 +33,9 @@
  #include <asm/cacheflush.h> /* for run_uncached() */
  
  
@@ -27,7 +27,7 @@ Index: linux-2.6.23/arch/mips/mm/c-r4k.c
  /*
   * Special Variant of smp_call_function for use by cache functions:
   *
-@@ -94,6 +97,9 @@
+@@ -97,6 +100,9 @@ static void __cpuinit r4k_blast_dcache_p
  {
  	unsigned long  dc_lsize = cpu_dcache_line_size();
  
@@ -37,7 +37,7 @@ Index: linux-2.6.23/arch/mips/mm/c-r4k.c
  	if (dc_lsize == 0)
  		r4k_blast_dcache_page = (void *)cache_noop;
  	else if (dc_lsize == 16)
-@@ -108,6 +114,9 @@
+@@ -111,6 +117,9 @@ static void __cpuinit r4k_blast_dcache_p
  {
  	unsigned long dc_lsize = cpu_dcache_line_size();
  
@@ -47,7 +47,7 @@ Index: linux-2.6.23/arch/mips/mm/c-r4k.c
  	if (dc_lsize == 0)
  		r4k_blast_dcache_page_indexed = (void *)cache_noop;
  	else if (dc_lsize == 16)
-@@ -122,6 +131,9 @@
+@@ -125,6 +134,9 @@ static void __cpuinit r4k_blast_dcache_s
  {
  	unsigned long dc_lsize = cpu_dcache_line_size();
  
@@ -57,7 +57,7 @@ Index: linux-2.6.23/arch/mips/mm/c-r4k.c
  	if (dc_lsize == 0)
  		r4k_blast_dcache = (void *)cache_noop;
  	else if (dc_lsize == 16)
-@@ -623,6 +635,8 @@
+@@ -630,6 +642,8 @@ static void local_r4k_flush_cache_sigtra
  	unsigned long addr = (unsigned long) arg;
  
  	R4600_HIT_CACHEOP_WAR_IMPL;
@@ -66,10 +66,10 @@ Index: linux-2.6.23/arch/mips/mm/c-r4k.c
  	if (dc_lsize)
  		protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
  	if (!cpu_icache_snoops_remote_store && scache_size)
-@@ -1198,6 +1212,17 @@
+@@ -1215,6 +1229,17 @@ static void __cpuinit coherency_setup(vo
  	 * silly idea of putting something else there ...
  	 */
- 	switch (current_cpu_data.cputype) {
+ 	switch (current_cpu_type()) {
 +	case CPU_BCM3302:
 +		{
 +			u32 cm;
@@ -84,12 +84,12 @@ Index: linux-2.6.23/arch/mips/mm/c-r4k.c
  	case CPU_R4000PC:
  	case CPU_R4000SC:
  	case CPU_R4000MC:
-@@ -1228,6 +1253,15 @@
- 	/* Default cache error handler for R4000 and R5000 family */
- 	set_uncached_handler (0x100, &except_vec2_generic, 0x80);
+@@ -1254,6 +1279,15 @@ void __cpuinit r4k_cache_init(void)
+ 		break;
+ 	}
  
 +	/* Check if special workarounds are required */
-+#ifdef CONFIG_BCM947XX
++#ifdef CONFIG_BCM47XX
 +	if (current_cpu_data.cputype == CPU_BCM4710 && (current_cpu_data.processor_id & 0xff) == 0) {
 +		printk("Enabling BCM4710A0 cache workarounds.\n");
 +		bcm4710 = 1;
@@ -100,11 +100,11 @@ Index: linux-2.6.23/arch/mips/mm/c-r4k.c
  	probe_pcache();
  	setup_scache();
  
-@@ -1273,5 +1307,13 @@
+@@ -1303,5 +1337,13 @@ void __cpuinit r4k_cache_init(void)
  	build_clear_page();
  	build_copy_page();
  	local_r4k___flush_cache_all(NULL);
-+#ifdef CONFIG_BCM947XX
++#ifdef CONFIG_BCM47XX
 +	{
 +		static void (*_coherency_setup)(void);
 +		_coherency_setup = (void (*)(void)) KSEG1ADDR(coherency_setup);
@@ -114,39 +114,39 @@ Index: linux-2.6.23/arch/mips/mm/c-r4k.c
  	coherency_setup();
 +#endif
  }
-Index: linux-2.6.23/arch/mips/mm/tlbex.c
+Index: linux-2.6.25/arch/mips/mm/tlbex.c
 ===================================================================
---- linux-2.6.23.orig/arch/mips/mm/tlbex.c	2007-10-13 11:29:46.235649074 +0200
-+++ linux-2.6.23/arch/mips/mm/tlbex.c	2007-10-13 11:35:46.076155216 +0200
-@@ -1273,6 +1273,9 @@
- 		/* No need for i_nop */
+--- linux-2.6.25.orig/arch/mips/mm/tlbex.c	2008-04-26 21:56:21.000000000 +0100
++++ linux-2.6.25/arch/mips/mm/tlbex.c	2008-04-26 21:57:14.000000000 +0100
+@@ -677,6 +677,9 @@ static void __cpuinit build_r4000_tlb_re
+ 		/* No need for uasm_i_nop */
  	}
  
-+#ifdef CONFIG_BCM947XX
-+	i_nop(&p);
++#ifdef CONFIG_BCM47XX
++	uasm_i_nop(&p);
 +#endif
  #ifdef CONFIG_64BIT
  	build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */
  #else
-@@ -1708,6 +1711,9 @@
- 				   struct reloc **r, unsigned int pte,
+@@ -1084,6 +1087,9 @@ build_r4000_tlbchange_handler_head(u32 *
+ 				   struct uasm_reloc **r, unsigned int pte,
  				   unsigned int ptr)
  {
-+#ifdef CONFIG_BCM947XX
-+	i_nop(p);
++#ifdef CONFIG_BCM47XX
++	uasm_i_nop(p);
 +#endif
  #ifdef CONFIG_64BIT
  	build_get_pmde64(p, l, r, pte, ptr); /* get pmd in ptr */
  #else
-Index: linux-2.6.23/include/asm-mips/r4kcache.h
+Index: linux-2.6.25/include/asm-mips/r4kcache.h
 ===================================================================
---- linux-2.6.23.orig/include/asm-mips/r4kcache.h	2007-10-13 11:29:46.255650214 +0200
-+++ linux-2.6.23/include/asm-mips/r4kcache.h	2007-10-13 11:29:49.631842613 +0200
+--- linux-2.6.25.orig/include/asm-mips/r4kcache.h	2008-04-26 21:56:21.000000000 +0100
++++ linux-2.6.25/include/asm-mips/r4kcache.h	2008-04-26 21:57:14.000000000 +0100
 @@ -17,6 +17,20 @@
  #include <asm/cpu-features.h>
  #include <asm/mipsmtregs.h>
  
-+#ifdef CONFIG_BCM947XX
++#ifdef CONFIG_BCM47XX
 +#include <asm/paccess.h>
 +#include <linux/ssb/ssb.h>
 +#define BCM4710_DUMMY_RREG() ((void) *((u8 *) KSEG1ADDR(SSB_ENUM_BASE + SSB_IMSTATE)))
@@ -163,7 +163,7 @@ Index: linux-2.6.23/include/asm-mips/r4kcache.h
  /*
   * This macro return a properly sign-extended address suitable as base address
   * for indexed cache operations.  Two issues here:
-@@ -150,6 +164,7 @@
+@@ -150,6 +164,7 @@ static inline void flush_icache_line_ind
  static inline void flush_dcache_line_indexed(unsigned long addr)
  {
  	__dflush_prologue
@@ -171,7 +171,7 @@ Index: linux-2.6.23/include/asm-mips/r4kcache.h
  	cache_op(Index_Writeback_Inv_D, addr);
  	__dflush_epilogue
  }
-@@ -169,6 +184,7 @@
+@@ -169,6 +184,7 @@ static inline void flush_icache_line(uns
  static inline void flush_dcache_line(unsigned long addr)
  {
  	__dflush_prologue
@@ -179,7 +179,7 @@ Index: linux-2.6.23/include/asm-mips/r4kcache.h
  	cache_op(Hit_Writeback_Inv_D, addr);
  	__dflush_epilogue
  }
-@@ -176,6 +192,7 @@
+@@ -176,6 +192,7 @@ static inline void flush_dcache_line(uns
  static inline void invalidate_dcache_line(unsigned long addr)
  {
  	__dflush_prologue
@@ -187,7 +187,7 @@ Index: linux-2.6.23/include/asm-mips/r4kcache.h
  	cache_op(Hit_Invalidate_D, addr);
  	__dflush_epilogue
  }
-@@ -208,6 +225,7 @@
+@@ -208,6 +225,7 @@ static inline void flush_scache_line(uns
   */
  static inline void protected_flush_icache_line(unsigned long addr)
  {
@@ -195,7 +195,7 @@ Index: linux-2.6.23/include/asm-mips/r4kcache.h
  	protected_cache_op(Hit_Invalidate_I, addr);
  }
  
-@@ -219,6 +237,7 @@
+@@ -219,6 +237,7 @@ static inline void protected_flush_icach
   */
  static inline void protected_writeback_dcache_line(unsigned long addr)
  {
@@ -203,7 +203,7 @@ Index: linux-2.6.23/include/asm-mips/r4kcache.h
  	protected_cache_op(Hit_Writeback_Inv_D, addr);
  }
  
-@@ -339,8 +358,52 @@
+@@ -339,8 +358,52 @@ static inline void invalidate_tcache_pag
  		: "r" (base),						\
  		  "i" (op));
  
@@ -257,23 +257,23 @@ Index: linux-2.6.23/include/asm-mips/r4kcache.h
  static inline void blast_##pfx##cache##lsize(void)			\
  {									\
  	unsigned long start = INDEX_BASE;				\
-@@ -352,6 +415,7 @@
+@@ -352,6 +415,7 @@ static inline void blast_##pfx##cache##l
  									\
  	__##pfx##flush_prologue						\
  									\
 +	war								\
  	for (ws = 0; ws < ws_end; ws += ws_inc)				\
  		for (addr = start; addr < end; addr += lsize * 32)	\
- 			cache##lsize##_unroll32(addr|ws,indexop);	\
-@@ -366,6 +430,7 @@
+ 			cache##lsize##_unroll32(addr|ws, indexop);	\
+@@ -366,6 +430,7 @@ static inline void blast_##pfx##cache##l
  									\
  	__##pfx##flush_prologue						\
  									\
 +	war								\
  	do {								\
- 		cache##lsize##_unroll32(start,hitop);			\
+ 		cache##lsize##_unroll32(start, hitop);			\
  		start += lsize * 32;					\
-@@ -384,6 +449,8 @@
+@@ -384,6 +449,8 @@ static inline void blast_##pfx##cache##l
  	                       current_cpu_data.desc.waybit;		\
  	unsigned long ws, addr;						\
  									\
@@ -282,7 +282,7 @@ Index: linux-2.6.23/include/asm-mips/r4kcache.h
  	__##pfx##flush_prologue						\
  									\
  	for (ws = 0; ws < ws_end; ws += ws_inc)				\
-@@ -393,28 +460,30 @@
+@@ -393,35 +460,37 @@ static inline void blast_##pfx##cache##l
  	__##pfx##flush_epilogue						\
  }
  
@@ -295,6 +295,13 @@ Index: linux-2.6.23/include/asm-mips/r4kcache.h
 -__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64)
 -__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64)
 -__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128)
+-
+-__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16)
+-__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32)
+-__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16)
+-__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32)
+-__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64)
+-__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128)
 +__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16, )
 +__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16, BCM4710_FILL_TLB(start);)
 +__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16, )
@@ -304,6 +311,13 @@ Index: linux-2.6.23/include/asm-mips/r4kcache.h
 +__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64, BCM4710_FILL_TLB(start);)
 +__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64, )
 +__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128, )
++
++__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16, )
++__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32, )
++__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16, )
++__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32, )
++__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64, )
++__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128, )
  
  /* build blast_xxx_range, protected_blast_xxx_range */
 -#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot) \
@@ -323,7 +337,7 @@ Index: linux-2.6.23/include/asm-mips/r4kcache.h
  		prot##cache_op(hitop, addr);				\
  		if (addr == aend)					\
  			break;						\
-@@ -424,13 +493,13 @@
+@@ -431,13 +500,13 @@ static inline void prot##blast_##pfx##ca
  	__##pfx##flush_epilogue						\
  }
  
@@ -344,15 +358,15 @@ Index: linux-2.6.23/include/asm-mips/r4kcache.h
 +__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD,,, )
  
  #endif /* _ASM_R4KCACHE_H */
-Index: linux-2.6.23/include/asm-mips/stackframe.h
+Index: linux-2.6.25/include/asm-mips/stackframe.h
 ===================================================================
---- linux-2.6.23.orig/include/asm-mips/stackframe.h	2007-10-13 11:29:46.263650671 +0200
-+++ linux-2.6.23/include/asm-mips/stackframe.h	2007-10-13 11:33:38.504885346 +0200
-@@ -350,6 +350,10 @@
+--- linux-2.6.25.orig/include/asm-mips/stackframe.h	2008-04-26 21:56:21.000000000 +0100
++++ linux-2.6.25/include/asm-mips/stackframe.h	2008-04-26 21:57:14.000000000 +0100
+@@ -359,6 +359,10 @@
  		.macro	RESTORE_SP_AND_RET
  		LONG_L	sp, PT_R29(sp)
  		.set	mips3
-+#ifdef CONFIG_BCM947XX
++#ifdef CONFIG_BCM47XX
 +		nop
 +		nop
 +#endif