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| author | Jonas Gorski <jogo@openwrt.org> | 2013-02-04 10:19:50 +0000 |
|---|---|---|
| committer | Jonas Gorski <jogo@openwrt.org> | 2013-02-04 10:19:50 +0000 |
| commit | 3b4fced67dad0b733d77f78205cfecfc0d654695 (patch) | |
| tree | a672ce6b4f937cdff5c23c4d96583c95c6357b9e /target/linux/brcm63xx/patches-3.7/001-MIPS-BCM63XX-add-softreset-register-description-for-.patch | |
| parent | 0e9365b3462d456baba85cad7269c85b0d0f7d8a (diff) | |
| download | upstream-3b4fced67dad0b733d77f78205cfecfc0d654695.tar.gz upstream-3b4fced67dad0b733d77f78205cfecfc0d654695.tar.bz2 upstream-3b4fced67dad0b733d77f78205cfecfc0d654695.zip | |
bcm63xx: add support for linux 3.7
Based on 3.7.6.
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
SVN-Revision: 35481
Diffstat (limited to 'target/linux/brcm63xx/patches-3.7/001-MIPS-BCM63XX-add-softreset-register-description-for-.patch')
| -rw-r--r-- | target/linux/brcm63xx/patches-3.7/001-MIPS-BCM63XX-add-softreset-register-description-for-.patch | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/target/linux/brcm63xx/patches-3.7/001-MIPS-BCM63XX-add-softreset-register-description-for-.patch b/target/linux/brcm63xx/patches-3.7/001-MIPS-BCM63XX-add-softreset-register-description-for-.patch new file mode 100644 index 0000000000..8c82284e50 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.7/001-MIPS-BCM63XX-add-softreset-register-description-for-.patch @@ -0,0 +1,38 @@ +From 761420215cd4c8b31500aaf5e8f5116abb962d1d Mon Sep 17 00:00:00 2001 +From: Jonas Gorski <jonas.gorski@gmail.com> +Date: Sun, 28 Oct 2012 12:48:56 +0100 +Subject: [PATCH 1/3] MIPS: BCM63XX: add softreset register description for BCM6358 + +The softreset register description for BCM6358 was missing, so add it. + +Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> +--- + arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 10 ++++++++++ + 1 files changed, 10 insertions(+), 0 deletions(-) + +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +@@ -191,6 +191,7 @@ + /* Soft Reset register */ + #define PERF_SOFTRESET_REG 0x28 + #define PERF_SOFTRESET_6328_REG 0x10 ++#define PERF_SOFTRESET_6358_REG 0x34 + #define PERF_SOFTRESET_6368_REG 0x10 + + #define SOFTRESET_6328_SPI_MASK (1 << 0) +@@ -244,6 +245,15 @@ + SOFTRESET_6348_ACLC_MASK | \ + SOFTRESET_6348_ADSLMIPSPLL_MASK) + ++#define SOFTRESET_6358_SPI_MASK (1 << 0) ++#define SOFTRESET_6358_ENET_MASK (1 << 2) ++#define SOFTRESET_6358_MPI_MASK (1 << 3) ++#define SOFTRESET_6358_EPHY_MASK (1 << 6) ++#define SOFTRESET_6358_SAR_MASK (1 << 7) ++#define SOFTRESET_6358_USBH_MASK (1 << 12) ++#define SOFTRESET_6358_PCM_MASK (1 << 13) ++#define SOFTRESET_6358_ADSL_MASK (1 << 14) ++ + #define SOFTRESET_6368_SPI_MASK (1 << 0) + #define SOFTRESET_6368_MPI_MASK (1 << 3) + #define SOFTRESET_6368_EPHY_MASK (1 << 6) |