cns3xxx: drop target

This target has not been updated to 5.4 yet, and the only person
trying it (Koen) decided to retreat based on the following reasons:

- The target is not DT-aware at all

- The huge amount of effort required

- The SoC itself reached EoL at Cavium for some time now

- Upstream removed some important parts as it's also slowly getting EoL
  over there

- The commercial product that used this will fade out shortly

- The amount of download for this binary suggest that the target is not
  that popular

Since nobody has picked up the work since then, and this is the last
remaining 4.19-only target, finally drop it now.

Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>

8 files changed, 0 insertions, 2025 deletions

diff --git a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/cns3xxx_fiq.S b/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/cns3xxx_fiq.S
deleted file mode 100644
index b1155ef570..0000000000
--- a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/cns3xxx_fiq.S
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- *  Copyright (C) 2012 Gateworks Corporation
- *      Chris Lang <clang@gateworks.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/linkage.h>
-#include <asm/assembler.h>
-#include <asm/asm-offsets.h>
-
-#define D_CACHE_LINE_SIZE 32
-
-	.text
-
-/*
- * R8  - DMA Start Address
- * R9  - DMA Length
- * R10 - DMA Direction
- * R11 - DMA type
- * R12 - fiq_buffer Address
-*/
-
-	.global	cns3xxx_fiq_end
-ENTRY(cns3xxx_fiq_start)
-	str	r8, [r13]
-
-	ldmia	r12, {r8, r9, r10}
-	and	r11, r10, #0x3000000
-	and	r10, r10, #0xff
-
-	teq	r11, #0x1000000
-	beq	cns3xxx_dma_map_area
-	teq	r11, #0x2000000
-	beq	cns3xxx_dma_unmap_area
-	/* fall through */
-cns3xxx_dma_flush_range:
-	bic	r8, r8, #D_CACHE_LINE_SIZE - 1
-1:
-	mcr	p15, 0, r8, c7, c14, 1		@ clean & invalidate D line
-	add	r8, r8, #D_CACHE_LINE_SIZE
-	cmp	r8, r9
-	blo	1b
-	/* fall through */
-cns3xxx_fiq_exit:
-	mov	r8, #0
-	str	r8, [r12, #8]
-	mcr	p15, 0, r8, c7, c10, 4		@ drain write buffer
-	subs	pc, lr, #4
-
-cns3xxx_dma_map_area:
-	add	r9, r9, r8
-	teq	r10, #DMA_FROM_DEVICE
-	beq	cns3xxx_dma_inv_range
-	teq	r10, #DMA_TO_DEVICE
-	bne	cns3xxx_dma_flush_range
-	/* fall through */
-cns3xxx_dma_clean_range:
-	bic	r8, r8, #D_CACHE_LINE_SIZE - 1
-1:
-	mcr	p15, 0, r8, c7, c10, 1		@ clean D line
-	add	r8, r8, #D_CACHE_LINE_SIZE
-	cmp	r8, r9
-	blo	1b
-	b	cns3xxx_fiq_exit
-
-cns3xxx_dma_unmap_area:
-	add	r9, r9, r8
-	teq	r10, #DMA_TO_DEVICE
-	beq	cns3xxx_fiq_exit
-	/* fall through */
-cns3xxx_dma_inv_range:
-	tst	r8, #D_CACHE_LINE_SIZE - 1
-	bic	r8, r8, #D_CACHE_LINE_SIZE - 1
-	mcrne	p15, 0, r8, c7, c10, 1		@ clean D line
-	tst	r9, #D_CACHE_LINE_SIZE - 1
-	bic	r9, r9, #D_CACHE_LINE_SIZE - 1
-	mcrne	p15, 0, r9, c7, c14, 1		@ clean & invalidate D line
-1:
-	mcr	p15, 0, r8, c7, c6, 1		@ invalidate D line
-	add	r8, r8, #D_CACHE_LINE_SIZE
-	cmp	r8, r9
-	blo	1b
-	b	cns3xxx_fiq_exit
-
-cns3xxx_fiq_end:
diff --git a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/gpio.c b/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/gpio.c
deleted file mode 100644
index bdf930a79e..0000000000
--- a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/gpio.c
+++ /dev/null
@@ -1,292 +0,0 @@
-/*
- * Copyright 2012 Gateworks Corporation
- *     Chris Lang <clang@gateworks.com>
- *     Tim Harvey <tharvey@gateworks.com>
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as
- * published by the Free Software Foundation.
- */
-
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/irqchip/chained_irq.h>
-#include <linux/io.h>
-#include <linux/gpio.h>
-#include <linux/irq.h>
-#include <linux/irqdomain.h>
-
-#include <asm/mach/irq.h>
-
-/*
- * Registers
- */
-#define GPIO_INPUT                          0x04
-#define GPIO_DIR                            0x08
-#define GPIO_SET                            0x10
-#define GPIO_CLEAR                          0x14
-#define GPIO_INTERRUPT_ENABLE               0x20
-#define GPIO_INTERRUPT_RAW_STATUS           0x24
-#define GPIO_INTERRUPT_MASKED_STATUS        0x28
-#define GPIO_INTERRUPT_MASK                 0x2C
-#define GPIO_INTERRUPT_CLEAR                0x30
-#define GPIO_INTERRUPT_TRIGGER_METHOD       0x34
-#define GPIO_INTERRUPT_TRIGGER_BOTH_EDGES   0x38
-#define GPIO_INTERRUPT_TRIGGER_TYPE         0x3C
-
-#define GPIO_INTERRUPT_TRIGGER_METHOD_EDGE  0
-#define GPIO_INTERRUPT_TRIGGER_METHOD_LEVEL 1
-#define GPIO_INTERRUPT_TRIGGER_EDGE_SINGLE  0
-#define GPIO_INTERRUPT_TRIGGER_EDGE_BOTH    1
-#define GPIO_INTERRUPT_TRIGGER_TYPE_RISING  0
-#define GPIO_INTERRUPT_TRIGGER_TYPE_FALLING 1
-#define GPIO_INTERRUPT_TRIGGER_TYPE_HIGH    0
-#define GPIO_INTERRUPT_TRIGGER_TYPE_LOW     1
-
-struct cns3xxx_gpio_chip {
-	struct gpio_chip    chip;
-	struct irq_domain   *domain;
-	spinlock_t          lock;
-	void __iomem        *base;
-};
-
-static struct cns3xxx_gpio_chip cns3xxx_gpio_chips[2];
-static int cns3xxx_gpio_chip_count;
-
-static inline void
-__set_direction(struct cns3xxx_gpio_chip *cchip, unsigned pin, int input)
-{
-	u32 reg;
-
-	reg = __raw_readl(cchip->base + GPIO_DIR);
-	if (input)
-		reg &= ~(1 << pin);
-	else
-		reg |= (1 << pin);
-	__raw_writel(reg, cchip->base + GPIO_DIR);
-}
-
-/*
- * GENERIC_GPIO primatives
- */
-static int cns3xxx_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
-{
-	struct cns3xxx_gpio_chip *cchip =
-		container_of(chip, struct cns3xxx_gpio_chip, chip);
-	unsigned long flags;
-
-	spin_lock_irqsave(&cchip->lock, flags);
-	__set_direction(cchip, pin, 1);
-	spin_unlock_irqrestore(&cchip->lock, flags);
-
-	return 0;
-}
-
-static int cns3xxx_gpio_get(struct gpio_chip *chip, unsigned pin)
-{
-	struct cns3xxx_gpio_chip *cchip =
-		container_of(chip, struct cns3xxx_gpio_chip, chip);
-	int val;
-
-	val = ((__raw_readl(cchip->base + GPIO_INPUT) >> pin) & 0x1);
-
-	return val;
-}
-
-static int cns3xxx_gpio_direction_output(struct gpio_chip *chip, unsigned pin, int level)
-{
-	struct cns3xxx_gpio_chip *cchip =
-		container_of(chip, struct cns3xxx_gpio_chip, chip);
-	unsigned long flags;
-
-	spin_lock_irqsave(&cchip->lock, flags);
-	if (level)
-		__raw_writel(1 << pin, cchip->base + GPIO_SET);
-	else
-		__raw_writel(1 << pin, cchip->base + GPIO_CLEAR);
-	__set_direction(cchip, pin, 0);
-	spin_unlock_irqrestore(&cchip->lock, flags);
-
-	return 0;
-}
-
-static void cns3xxx_gpio_set(struct gpio_chip *chip, unsigned pin,
-	int level)
-{
-	struct cns3xxx_gpio_chip *cchip =
-		container_of(chip, struct cns3xxx_gpio_chip, chip);
-
-	if (level)
-		__raw_writel(1 << pin, cchip->base + GPIO_SET);
-	else
-		__raw_writel(1 << pin, cchip->base + GPIO_CLEAR);
-}
-
-static int cns3xxx_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
-{
-	struct cns3xxx_gpio_chip *cchip =
-		container_of(chip, struct cns3xxx_gpio_chip, chip);
-
-	return irq_find_mapping(cchip->domain, pin);
-}
-
-
-/*
- * IRQ support
- */
-
-/* one interrupt per GPIO controller (GPIOA/GPIOB)
- * this is called in task context, with IRQs enabled
- */
-static void cns3xxx_gpio_irq_handler(struct irq_desc *desc)
-{
-	struct cns3xxx_gpio_chip *cchip = irq_desc_get_handler_data(desc);
-	struct irq_chip *chip = irq_desc_get_chip(desc);
-	u16 i;
-	u32 reg;
-
-	chained_irq_enter(chip, desc); /* mask and ack the base interrupt */
-
-	/* see which pin(s) triggered the interrupt */
-	reg = __raw_readl(cchip->base + GPIO_INTERRUPT_RAW_STATUS);
-	for (i = 0; i < 32; i++) {
-		if (reg & (1 << i)) {
-			/* let the generic IRQ layer handle an interrupt */
-			generic_handle_irq(irq_find_mapping(cchip->domain, i));
-		}
-	}
-
-	chained_irq_exit(chip, desc); /* unmask the base interrupt */
-}
-
-static int cns3xxx_gpio_irq_set_type(struct irq_data *d, u32 irqtype)
-{
-	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
-	struct cns3xxx_gpio_chip *cchip = gc->private;
-	u32 gpio = d->hwirq;
-	unsigned long flags;
-	u32 method, edges, type;
-
-	spin_lock_irqsave(&cchip->lock, flags);
-	method = __raw_readl(cchip->base + GPIO_INTERRUPT_TRIGGER_METHOD);
-	edges  = __raw_readl(cchip->base + GPIO_INTERRUPT_TRIGGER_BOTH_EDGES);
-	type   = __raw_readl(cchip->base + GPIO_INTERRUPT_TRIGGER_TYPE);
-	method &= ~(1 << gpio);
-	edges  &= ~(1 << gpio);
-	type   &= ~(1 << gpio);
-
-	switch(irqtype) {
-	case IRQ_TYPE_EDGE_RISING:
-		method |= (GPIO_INTERRUPT_TRIGGER_METHOD_EDGE << gpio);
-		edges  |= (GPIO_INTERRUPT_TRIGGER_EDGE_SINGLE << gpio);
-		type   |= (GPIO_INTERRUPT_TRIGGER_TYPE_RISING << gpio);
-		break;
-	case IRQ_TYPE_EDGE_FALLING:
-		method |= (GPIO_INTERRUPT_TRIGGER_METHOD_EDGE << gpio);
-		edges  |= (GPIO_INTERRUPT_TRIGGER_EDGE_SINGLE << gpio);
-		type   |= (GPIO_INTERRUPT_TRIGGER_TYPE_FALLING << gpio);
-		break;
-	case IRQ_TYPE_EDGE_BOTH:
-		method |= (GPIO_INTERRUPT_TRIGGER_METHOD_EDGE << gpio);
-		edges  |= (GPIO_INTERRUPT_TRIGGER_EDGE_BOTH << gpio);
-		break;
-	case IRQ_TYPE_LEVEL_LOW:
-		method |= (GPIO_INTERRUPT_TRIGGER_METHOD_LEVEL << gpio);
-		type   |= (GPIO_INTERRUPT_TRIGGER_TYPE_LOW << gpio);
-		break;
-	case IRQ_TYPE_LEVEL_HIGH:
-		method |= (GPIO_INTERRUPT_TRIGGER_METHOD_LEVEL << gpio);
-		type   |= (GPIO_INTERRUPT_TRIGGER_TYPE_HIGH << gpio);
-		break;
-	default:
-		printk(KERN_WARNING "No irq type\n");
-		spin_unlock_irqrestore(&cchip->lock, flags);
-		return -EINVAL;
-	}
-
-	__raw_writel(method, cchip->base + GPIO_INTERRUPT_TRIGGER_METHOD);
-	__raw_writel(edges,  cchip->base + GPIO_INTERRUPT_TRIGGER_BOTH_EDGES);
-	__raw_writel(type,   cchip->base + GPIO_INTERRUPT_TRIGGER_TYPE);
-	spin_unlock_irqrestore(&cchip->lock, flags);
-
-	if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
-		irq_set_handler_locked(d, handle_level_irq);
-	else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
-		irq_set_handler_locked(d, handle_edge_irq);
-
-	return 0;
-}
-
-void __init cns3xxx_gpio_init(int gpio_base, int ngpio,
-	u32 base, int irq, int secondary_irq_base)
-{
-	struct cns3xxx_gpio_chip *cchip;
-	struct irq_chip_generic *gc;
-	struct irq_chip_type *ct;
-	char gc_label[16];
-	int irq_base;
-
-	if (cns3xxx_gpio_chip_count == ARRAY_SIZE(cns3xxx_gpio_chips))
-		return;
-
-	snprintf(gc_label, sizeof(gc_label), "cns3xxx_gpio%d",
-		cns3xxx_gpio_chip_count);
-
-	cchip = cns3xxx_gpio_chips + cns3xxx_gpio_chip_count;
-	cchip->chip.label = kstrdup(gc_label, GFP_KERNEL);
-	cchip->chip.direction_input = cns3xxx_gpio_direction_input;
-	cchip->chip.get = cns3xxx_gpio_get;
-	cchip->chip.direction_output = cns3xxx_gpio_direction_output;
-	cchip->chip.set = cns3xxx_gpio_set;
-	cchip->chip.to_irq = cns3xxx_gpio_to_irq;
-	cchip->chip.base = gpio_base;
-	cchip->chip.ngpio = ngpio;
-	cchip->chip.can_sleep = 0;
-	spin_lock_init(&cchip->lock);
-	cchip->base = (void __iomem *)base;
-
-	BUG_ON(gpiochip_add(&cchip->chip) < 0);
-	cns3xxx_gpio_chip_count++;
-
-	/* clear GPIO interrupts */
-	__raw_writel(0xffff, cchip->base + GPIO_INTERRUPT_CLEAR);
-
-	irq_base = irq_alloc_descs(-1, secondary_irq_base, ngpio,
-		numa_node_id());
-	if (irq_base < 0)
-		goto out_irqdesc_free;
-
-	cchip->domain = irq_domain_add_legacy(NULL, ngpio, irq_base, 0,
-		&irq_domain_simple_ops, NULL);
-	if (!cchip->domain)
-		goto out_irqdesc_free;
-
-	/*
-	 * IRQ chip init
-	 */
-	gc = irq_alloc_generic_chip("cns3xxx_gpio_irq", 1, irq_base,
-		cchip->base, handle_edge_irq);
-
-	gc->private = cchip;
-
-	ct = gc->chip_types;
-	ct->type = IRQ_TYPE_EDGE_FALLING;
-	ct->regs.ack = GPIO_INTERRUPT_CLEAR;
-	ct->chip.irq_ack = irq_gc_ack_set_bit;
-	ct->regs.mask = GPIO_INTERRUPT_ENABLE;
-	ct->chip.irq_enable = irq_gc_mask_set_bit;
-	ct->chip.irq_disable = irq_gc_mask_clr_bit;
-	ct->chip.irq_set_type = cns3xxx_gpio_irq_set_type;
-	ct->handler = handle_edge_irq;
-
-	irq_setup_generic_chip(gc, IRQ_MSK(ngpio), IRQ_GC_INIT_MASK_CACHE,
-		IRQ_NOREQUEST, 0);
-	irq_set_chained_handler(irq, cns3xxx_gpio_irq_handler);
-	irq_set_handler_data(irq, cchip);
-
-	return;
-
-out_irqdesc_free:
-	irq_free_descs(irq_base, ngpio);
-}
diff --git a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/headsmp.S b/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/headsmp.S
deleted file mode 100644
index f0da8ec0a5..0000000000
--- a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/headsmp.S
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- *  linux/arch/arm/mach-cns3xxx/headsmp.S
- *
- *  Cloned from linux/arch/arm/plat-versatile/headsmp.S
- *
- *  Copyright (c) 2003 ARM Limited
- *  All Rights Reserved
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/linkage.h>
-#include <linux/init.h>
-
-/*
- * CNS3XXX specific entry point for secondary CPUs.  This provides
- * a "holding pen" into which all secondary cores are held until we're
- * ready for them to initialise.
- */
-ENTRY(cns3xxx_secondary_startup)
-	mrc	p15, 0, r0, c0, c0, 5
-	and	r0, r0, #15
-	adr	r4, 1f
-	ldmia	r4, {r5, r6}
-	sub	r4, r4, r5
-	add	r6, r6, r4
-pen:	ldr	r7, [r6]
-	cmp	r7, r0
-	bne	pen
-
-	/*
-	 * we've been released from the holding pen: secondary_stack
-	 * should now contain the SVC stack for this core
-	 */
-	b	secondary_startup
-ENDPROC(cns3xxx_secondary_startup)
-
-	.align 2
-1:	.long	.
-	.long	pen_release
diff --git a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/hotplug.c b/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/hotplug.c
deleted file mode 100644
index be0d499a38..0000000000
--- a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/hotplug.c
+++ /dev/null
@@ -1,130 +0,0 @@
-/* linux arch/arm/mach-cns3xxx/hotplug.c
- *
- *  Cloned from linux/arch/arm/mach-realview/hotplug.c
- *
- *  Copyright (C) 2002 ARM Ltd.
- *  All Rights Reserved
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/smp.h>
-
-#include <asm/cacheflush.h>
-
-extern volatile int pen_release;
-
-static inline void cpu_enter_lowpower(void)
-{
-	unsigned int v;
-
-	flush_cache_all();
-	asm volatile(
-	"	mcr	p15, 0, %1, c7, c5, 0\n"
-	"	mcr	p15, 0, %1, c7, c10, 4\n"
-	/*
-	 * Turn off coherency
-	 */
-	"	mrc	p15, 0, %0, c1, c0, 1\n"
-	"	bic	%0, %0, %3\n"
-	"	mcr	p15, 0, %0, c1, c0, 1\n"
-	"	mrc	p15, 0, %0, c1, c0, 0\n"
-	"	bic	%0, %0, %2\n"
-	"	mcr	p15, 0, %0, c1, c0, 0\n"
-	  : "=&r" (v)
-	  : "r" (0), "Ir" (CR_C), "Ir" (0x40)
-	  : "cc");
-}
-
-static inline void cpu_leave_lowpower(void)
-{
-	unsigned int v;
-
-	asm volatile(
-	"mrc	p15, 0, %0, c1, c0, 0\n"
-	"	orr	%0, %0, %1\n"
-	"	mcr	p15, 0, %0, c1, c0, 0\n"
-	"	mrc	p15, 0, %0, c1, c0, 1\n"
-	"	orr	%0, %0, %2\n"
-	"	mcr	p15, 0, %0, c1, c0, 1\n"
-	  : "=&r" (v)
-	  : "Ir" (CR_C), "Ir" (0x40)
-	  : "cc");
-}
-
-static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
-{
-	/*
-	 * there is no power-control hardware on this platform, so all
-	 * we can do is put the core into WFI; this is safe as the calling
-	 * code will have already disabled interrupts
-	 */
-	for (;;) {
-		/*
-		 * here's the WFI
-		 */
-		asm(".word	0xe320f003\n"
-		    :
-		    :
-		    : "memory", "cc");
-
-		if (pen_release == cpu) {
-			/*
-			 * OK, proper wakeup, we're done
-			 */
-			break;
-		}
-
-		/*
-		 * Getting here, means that we have come out of WFI without
-		 * having been woken up - this shouldn't happen
-		 *
-		 * Just note it happening - when we're woken, we can report
-		 * its occurrence.
-		 */
-		(*spurious)++;
-	}
-}
-
-int platform_cpu_kill(unsigned int cpu)
-{
-	return 1;
-}
-
-/*
- * platform-specific code to shutdown a CPU
- *
- * Called with IRQs disabled
- */
-void platform_cpu_die(unsigned int cpu)
-{
-	int spurious = 0;
-
-	/*
-	 * we're ready for shutdown now, so do it
-	 */
-	cpu_enter_lowpower();
-	platform_do_lowpower(cpu, &spurious);
-
-	/*
-	 * bring this CPU back into the world of cache
-	 * coherency, and then restore interrupts
-	 */
-	cpu_leave_lowpower();
-
-	if (spurious)
-		pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious);
-}
-
-int platform_cpu_disable(unsigned int cpu)
-{
-	/*
-	 * we don't allow CPU 0 to be shutdown (it is still too special
-	 * e.g. clock tick interrupts)
-	 */
-	return cpu == 0 ? -EPERM : 0;
-}
diff --git a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/include/mach/gpio.h b/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/include/mach/gpio.h
deleted file mode 100644
index 8c66748ac9..0000000000
--- a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/include/mach/gpio.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * arch/arm/mach-cns3xxx/include/mach/gpio.h
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- *
- */
-#ifndef __ASM_ARCH_CNS3XXX_GPIO_H
-#define __ASM_ARCH_CNS3XXX_GPIO_H
-
-#include <linux/kernel.h>
-
-extern void __init cns3xxx_gpio_init(int gpio_base, int ngpio,
-	u32 base, int irq, int secondary_irq_base);
-
-#endif
diff --git a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/include/mach/smp.h b/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/include/mach/smp.h
deleted file mode 100644
index e5bc56823e..0000000000
--- a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/include/mach/smp.h
+++ /dev/null
@@ -1,8 +0,0 @@
-#ifndef __MACH_SMP_H
-#define __MACH_SMP_H
-
-extern void smp_dma_map_area(const void *, size_t, int);
-extern void smp_dma_unmap_area(const void *, size_t, int);
-extern void smp_dma_flush_range(const void *, const void *);
-
-#endif
diff --git a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/laguna.c b/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/laguna.c
deleted file mode 100644
index bee7348266..0000000000
--- a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/laguna.c
+++ /dev/null
@@ -1,1123 +0,0 @@
-/*
- * Gateworks Corporation Laguna Platform
- *
- * Copyright 2000 Deep Blue Solutions Ltd
- * Copyright 2008 ARM Limited
- * Copyright 2008 Cavium Networks
- *		  Scott Shu
- * Copyright 2010 MontaVista Software, LLC.
- *		  Anton Vorontsov <avorontsov@mvista.com>
- * Copyright 2011 Gateworks Corporation
- *		  Chris Lang <clang@gateworks.com>
- * Copyright 2012-2013 Gateworks Corporation
- *		  Tim Harvey <tharvey@gateworks.com>
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as
- * published by the Free Software Foundation.
- */
-
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/compiler.h>
-#include <linux/io.h>
-#include <linux/irq.h>
-#include <linux/gpio.h>
-#include <linux/dma-mapping.h>
-#include <linux/serial_core.h>
-#include <linux/serial_8250.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/physmap.h>
-#include <linux/mtd/partitions.h>
-#include <linux/leds.h>
-#include <linux/i2c.h>
-#include <linux/platform_data/at24.h>
-#include <linux/platform_data/pca953x.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#include <linux/if_ether.h>
-#include <linux/pps-gpio.h>
-#include <linux/usb/ehci_pdriver.h>
-#include <linux/usb/ohci_pdriver.h>
-#include <linux/clk-provider.h>
-#include <linux/clkdev.h>
-#include <linux/platform_data/cns3xxx.h>
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/time.h>
-#include <mach/gpio.h>
-#include "core.h"
-#include "devices.h"
-#include "cns3xxx.h"
-#include "pm.h"
-
-#define ARRAY_AND_SIZE(x)       (x), ARRAY_SIZE(x)
-
-// Config 1 Bitmap
-#define ETH0_LOAD           BIT(0)
-#define ETH1_LOAD           BIT(1)
-#define ETH2_LOAD           BIT(2)
-#define SATA0_LOAD          BIT(3)
-#define SATA1_LOAD          BIT(4)
-#define PCM_LOAD            BIT(5)
-#define I2S_LOAD            BIT(6)
-#define SPI0_LOAD           BIT(7)
-#define SPI1_LOAD           BIT(8)
-#define PCIE0_LOAD          BIT(9)
-#define PCIE1_LOAD          BIT(10)
-#define USB0_LOAD           BIT(11)
-#define USB1_LOAD           BIT(12)
-#define USB1_ROUTE          BIT(13)
-#define SD_LOAD             BIT(14)
-#define UART0_LOAD          BIT(15)
-#define UART1_LOAD          BIT(16)
-#define UART2_LOAD          BIT(17)
-#define MPCI0_LOAD          BIT(18)
-#define MPCI1_LOAD          BIT(19)
-#define MPCI2_LOAD          BIT(20)
-#define MPCI3_LOAD          BIT(21)
-#define FP_BUT_LOAD         BIT(22)
-#define FP_BUT_HEADER_LOAD  BIT(23)
-#define FP_LED_LOAD         BIT(24)
-#define FP_LED_HEADER_LOAD  BIT(25)
-#define FP_TAMPER_LOAD      BIT(26)
-#define HEADER_33V_LOAD     BIT(27)
-#define SATA_POWER_LOAD     BIT(28)
-#define FP_POWER_LOAD       BIT(29)
-#define GPIO_HEADER_LOAD    BIT(30)
-#define GSP_BAT_LOAD        BIT(31)
-
-// Config 2 Bitmap
-#define FAN_LOAD            BIT(0)
-#define SPI_FLASH_LOAD      BIT(1)
-#define NOR_FLASH_LOAD      BIT(2)
-#define GPS_LOAD            BIT(3)
-#define SUPPLY_5V_LOAD      BIT(6)
-#define SUPPLY_33V_LOAD     BIT(7)
-
-struct laguna_board_info {
-	char model[16];
-	u32 config_bitmap;
-	u32 config2_bitmap;
-	u8 nor_flash_size;
-	u8 spi_flash_size;
-};
-
-static struct laguna_board_info laguna_info __initdata;
-
-/*
- * NOR Flash
- */
-static struct mtd_partition laguna_nor_partitions[] = {
-	{
-		.name		= "uboot",
-		.offset		= 0,
-		.size		= SZ_256K,
-		.mask_flags	= MTD_WRITEABLE,
-	}, {
-		.name		= "params",
-		.offset		= MTDPART_OFS_APPEND,
-		.size		= SZ_128K,
-	}, {
-		.name		= "firmware",
-		.offset		= MTDPART_OFS_APPEND,
-		.size		= MTDPART_SIZ_FULL,
-	},
-};
-
-static struct physmap_flash_data laguna_nor_pdata = {
-	.width = 2,
-	.parts = laguna_nor_partitions,
-	.nr_parts = ARRAY_SIZE(laguna_nor_partitions),
-};
-
-static struct resource laguna_nor_res = {
-	.start = CNS3XXX_FLASH_BASE,
-	.end = CNS3XXX_FLASH_BASE + SZ_128M - 1,
-	.flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
-};
-
-static struct platform_device laguna_nor_pdev = {
-	.name = "physmap-flash",
-	.id = 0,
-	.resource = &laguna_nor_res,
-	.num_resources = 1,
-	.dev = {
-		.platform_data = &laguna_nor_pdata,
-	},
-};
-
-/*
- * SPI
- */
-static struct mtd_partition laguna_spi_partitions[] = {
-	{
-		.name		= "uboot",
-		.offset		= 0,
-		.size		= SZ_256K,
-		.mask_flags	= MTD_WRITEABLE,
-	}, {
-		.name		= "params",
-		.offset		= MTDPART_OFS_APPEND,
-		.size		= SZ_256K,
-	}, {
-		.name		= "firmware",
-		.offset		= MTDPART_OFS_APPEND,
-		.size		= MTDPART_SIZ_FULL,
-	},
-};
-
-static struct flash_platform_data laguna_spi_pdata = {
-	.parts = laguna_spi_partitions,
-	.nr_parts = ARRAY_SIZE(laguna_spi_partitions),
-};
-
-static struct spi_board_info __initdata laguna_spi_devices[] = {
-	{
-		.modalias = "m25p80",
-		.platform_data = &laguna_spi_pdata,
-		.max_speed_hz = 50000000,
-		.bus_num = 1,
-		.chip_select = 0,
-	},
-};
-
-static struct resource laguna_spi_resource = {
-	.start    = CNS3XXX_SSP_BASE + 0x40,
-	.end      = CNS3XXX_SSP_BASE + 0x6f,
-	.flags    = IORESOURCE_MEM,
-};
-
-static struct platform_device laguna_spi_controller = {
-	.name = "cns3xxx_spi",
-	.resource = &laguna_spi_resource,
-	.num_resources = 1,
-};
-
-/*
- * LED's
- */
-static struct gpio_led laguna_gpio_leds[] = {
-	{
-		.name = "user1", /* Green Led */
-		.gpio = 115,
-		.active_low = 1,
-	},{
-		.name = "user2", /* Red Led */
-		.gpio = 114,
-		.active_low = 1,
-	},{
-		.name = "pwr1", /* Green Led */
-		.gpio = 116,
-		.active_low = 1,
-	},{
-		.name = "pwr2", /* Yellow Led */
-		.gpio = 117,
-		.active_low = 1,
-	},{
-		.name = "txd1", /* Green Led */
-		.gpio = 118,
-		.active_low = 1,
-	},{
-		.name = "txd2", /* Yellow Led */
-		.gpio = 119,
-		.active_low = 1,
-	},{
-		.name = "rxd1", /* Green Led */
-		.gpio = 120,
-		.active_low = 1,
-	},{
-		.name = "rxd2", /* Yellow Led */
-		.gpio = 121,
-		.active_low = 1,
-	},{
-		.name = "ser1", /* Green Led */
-		.gpio = 122,
-		.active_low = 1,
-	},{
-		.name = "ser2", /* Yellow Led */
-		.gpio = 123,
-		.active_low = 1,
-	},{
-		.name = "enet1", /* Green Led */
-		.gpio = 124,
-		.active_low = 1,
-	},{
-		.name = "enet2", /* Yellow Led */
-		.gpio = 125,
-		.active_low = 1,
-	},{
-		.name = "sig1_1", /* Green Led */
-		.gpio = 126,
-		.active_low = 1,
-	},{
-		.name = "sig1_2", /* Yellow Led */
-		.gpio = 127,
-		.active_low = 1,
-	},{
-		.name = "sig2_1", /* Green Led */
-		.gpio = 128,
-		.active_low = 1,
-	},{
-		.name = "sig2_2", /* Yellow Led */
-		.gpio = 129,
-		.active_low = 1,
-	},{
-		.name = "sig3_1", /* Green Led */
-		.gpio = 130,
-		.active_low = 1,
-	},{
-		.name = "sig3_2", /* Yellow Led */
-		.gpio = 131,
-		.active_low = 1,
-	},{
-		.name = "net1", /*Green Led */
-		.gpio = 109,
-		.active_low = 1,
-	},{
-		.name = "net2", /* Red Led */
-		.gpio = 110,
-		.active_low = 1,
-	},{
-		.name = "mod1", /* Green Led */
-		.gpio = 111,
-		.active_low = 1,
-	},{
-		.name = "mod2", /* Red Led */
-		.gpio = 112,
-		.active_low = 1,
-	},
-};
-
-static struct gpio_led_platform_data laguna_gpio_leds_data = {
-	.num_leds = 22,
-	.leds = laguna_gpio_leds,
-};
-
-static struct platform_device laguna_gpio_leds_device = {
-	.name = "leds-gpio",
-	.id = PLATFORM_DEVID_NONE,
-	.dev.platform_data = &laguna_gpio_leds_data,
-};
-
-/*
- * Ethernet
- */
-static struct cns3xxx_plat_info laguna_net_data = {
-	.ports = 0,
-	.phy = {
-		0,
-		1,
-		2,
-	},
-};
-
-static struct resource laguna_net_resource[] = {
-	{
-		.name = "eth0_mem",
-		.start = CNS3XXX_SWITCH_BASE,
-		.end = CNS3XXX_SWITCH_BASE + SZ_4K - 1,
-		.flags = IORESOURCE_MEM
-	}, {
-		.name = "eth_rx",
-		.start = IRQ_CNS3XXX_SW_R0RXC,
-		.end = IRQ_CNS3XXX_SW_R0RXC,
-		.flags = IORESOURCE_IRQ
-	}, {
-		.name = "eth_stat",
-		.start = IRQ_CNS3XXX_SW_STATUS,
-		.end = IRQ_CNS3XXX_SW_STATUS,
-		.flags = IORESOURCE_IRQ
-	}
-};
-
-static u64 laguna_net_dmamask = DMA_BIT_MASK(32);
-static struct platform_device laguna_net_device = {
-	.name = "cns3xxx_eth",
-	.id = 0,
-	.resource = laguna_net_resource,
-	.num_resources = ARRAY_SIZE(laguna_net_resource),
-	.dev = {
-		.dma_mask = &laguna_net_dmamask,
-		.coherent_dma_mask = DMA_BIT_MASK(32),
-		.platform_data = &laguna_net_data,
-	}
-};
-
-/*
- * UART
- */
-static void __init laguna_early_serial_setup(void)
-{
-#ifdef CONFIG_SERIAL_8250_CONSOLE
-	static struct uart_port laguna_serial_port = {
-		.membase        = (void __iomem *)CNS3XXX_UART0_BASE_VIRT,
-		.mapbase        = CNS3XXX_UART0_BASE,
-		.irq            = IRQ_CNS3XXX_UART0,
-		.iotype         = UPIO_MEM,
-		.flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
-		.regshift       = 2,
-		.uartclk        = 24000000,
-		.line           = 0,
-		.type           = PORT_16550A,
-		.fifosize       = 16,
-	};
-
-	early_serial_setup(&laguna_serial_port);
-#endif
-}
-
-static struct resource laguna_uart_resources[] = {
-	{
-		.start = CNS3XXX_UART0_BASE,
-		.end   = CNS3XXX_UART0_BASE + SZ_4K - 1,
-		.flags    = IORESOURCE_MEM
-	},{
-		.start = CNS3XXX_UART1_BASE,
-		.end   = CNS3XXX_UART1_BASE + SZ_4K - 1,
-		.flags    = IORESOURCE_MEM
-	},{
-		.start = CNS3XXX_UART2_BASE,
-		.end   = CNS3XXX_UART2_BASE + SZ_4K - 1,
-		.flags    = IORESOURCE_MEM
-	},
-};
-
-static struct plat_serial8250_port laguna_uart_data[] = {
-	{
-		.mapbase        = (CNS3XXX_UART0_BASE),
-		.irq            = IRQ_CNS3XXX_UART0,
-		.iotype         = UPIO_MEM,
-		.flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE | UPF_IOREMAP,
-		.regshift       = 2,
-		.uartclk        = 24000000,
-		.type           = PORT_16550A,
-	},{
-		.mapbase        = (CNS3XXX_UART1_BASE),
-		.irq            = IRQ_CNS3XXX_UART1,
-		.iotype         = UPIO_MEM,
-		.flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE | UPF_IOREMAP,
-		.regshift       = 2,
-		.uartclk        = 24000000,
-		.type           = PORT_16550A,
-	},{
-		.mapbase        = (CNS3XXX_UART2_BASE),
-		.irq            = IRQ_CNS3XXX_UART2,
-		.iotype         = UPIO_MEM,
-		.flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE | UPF_IOREMAP,
-		.regshift       = 2,
-		.uartclk        = 24000000,
-		.type           = PORT_16550A,
-	},
-	{ },
-};
-
-static struct platform_device laguna_uart = {
-	.name     = "serial8250",
-	.id     = PLAT8250_DEV_PLATFORM,
-	.dev.platform_data  = laguna_uart_data,
-	.num_resources    = 3,
-	.resource   = laguna_uart_resources
-};
-
-/*
- * USB
- */
-static struct resource cns3xxx_usb_ehci_resources[] = {
-	[0] = {
-		.start = CNS3XXX_USB_BASE,
-		.end   = CNS3XXX_USB_BASE + SZ_16M - 1,
-		.flags = IORESOURCE_MEM,
-	},
-	[1] = {
-		.start = IRQ_CNS3XXX_USB_EHCI,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-static u64 cns3xxx_usb_ehci_dma_mask = DMA_BIT_MASK(32);
-
-static int csn3xxx_usb_power_on(struct platform_device *pdev)
-{
-	/*
-	 * EHCI and OHCI share the same clock and power,
-	 * resetting twice would cause the 1st controller been reset.
-	 * Therefore only do power up  at the first up device, and
-	 * power down at the last down device.
-	 *
-	 * Set USB AHB INCR length to 16
-	 */
-	if (atomic_inc_return(&usb_pwr_ref) == 1) {
-		cns3xxx_pwr_power_up(1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB);
-		cns3xxx_pwr_clk_en(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST);
-		cns3xxx_pwr_soft_rst(1 << PM_SOFT_RST_REG_OFFST_USB_HOST);
-		__raw_writel((__raw_readl(MISC_CHIP_CONFIG_REG) | (0X2 << 24)),
-			MISC_CHIP_CONFIG_REG);
-	}
-
-	return 0;
-}
-
-static void csn3xxx_usb_power_off(struct platform_device *pdev)
-{
-	/*
-	 * EHCI and OHCI share the same clock and power,
-	 * resetting twice would cause the 1st controller been reset.
-	 * Therefore only do power up  at the first up device, and
-	 * power down at the last down device.
-	 */
-	if (atomic_dec_return(&usb_pwr_ref) == 0)
-		cns3xxx_pwr_clk_dis(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST);
-}
-
-static struct usb_ehci_pdata cns3xxx_usb_ehci_pdata = {
-	.power_on	= csn3xxx_usb_power_on,
-	.power_off	= csn3xxx_usb_power_off,
-};
-
-static struct platform_device cns3xxx_usb_ehci_device = {
-	.name          = "ehci-platform",
-	.num_resources = ARRAY_SIZE(cns3xxx_usb_ehci_resources),
-	.resource      = cns3xxx_usb_ehci_resources,
-	.dev           = {
-		.dma_mask          = &cns3xxx_usb_ehci_dma_mask,
-		.coherent_dma_mask = DMA_BIT_MASK(32),
-		.platform_data     = &cns3xxx_usb_ehci_pdata,
-	},
-};
-
-static struct resource cns3xxx_usb_ohci_resources[] = {
-	[0] = {
-		.start = CNS3XXX_USB_OHCI_BASE,
-		.end   = CNS3XXX_USB_OHCI_BASE + SZ_16M - 1,
-		.flags = IORESOURCE_MEM,
-	},
-	[1] = {
-		.start = IRQ_CNS3XXX_USB_OHCI,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-static u64 cns3xxx_usb_ohci_dma_mask = DMA_BIT_MASK(32);
-
-static struct usb_ohci_pdata cns3xxx_usb_ohci_pdata = {
-	.num_ports	= 1,
-	.power_on	= csn3xxx_usb_power_on,
-	.power_off	= csn3xxx_usb_power_off,
-};
-
-static struct platform_device cns3xxx_usb_ohci_device = {
-	.name          = "ohci-platform",
-	.num_resources = ARRAY_SIZE(cns3xxx_usb_ohci_resources),
-	.resource      = cns3xxx_usb_ohci_resources,
-	.dev           = {
-		.dma_mask          = &cns3xxx_usb_ohci_dma_mask,
-		.coherent_dma_mask = DMA_BIT_MASK(32),
-		.platform_data	   = &cns3xxx_usb_ohci_pdata,
-	},
-};
-
-static struct resource cns3xxx_usb_otg_resources[] = {
-	[0] = {
-		.start = CNS3XXX_USBOTG_BASE,
-		.end   = CNS3XXX_USBOTG_BASE + SZ_16M - 1,
-		.flags = IORESOURCE_MEM,
-	},
-	[1] = {
-		.start = IRQ_CNS3XXX_USB_OTG,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-static u64 cns3xxx_usb_otg_dma_mask = DMA_BIT_MASK(32);
-
-static struct platform_device cns3xxx_usb_otg_device = {
-	.name          = "dwc2",
-	.num_resources = ARRAY_SIZE(cns3xxx_usb_otg_resources),
-	.resource      = cns3xxx_usb_otg_resources,
-	.dev           = {
-		.dma_mask          = &cns3xxx_usb_otg_dma_mask,
-		.coherent_dma_mask = DMA_BIT_MASK(32),
-	},
-};
-
-/*
- * I2C
- */
-static struct resource laguna_i2c_resource[] = {
-	{
-		.start    = CNS3XXX_SSP_BASE + 0x20,
-		.end      = CNS3XXX_SSP_BASE + 0x3f,
-		.flags    = IORESOURCE_MEM,
-	},{
-		.start    = IRQ_CNS3XXX_I2C,
-		.flags    = IORESOURCE_IRQ,
-	},
-};
-
-static struct platform_device laguna_i2c_controller = {
-	.name   = "cns3xxx-i2c",
-	.num_resources  = 2,
-	.resource = laguna_i2c_resource,
-};
-
-static struct nvmem_device *at24_nvmem;
-
-static void at24_setup(struct nvmem_device *mem_acc, void *context)
-{
-	char buf[16];
-
-	at24_nvmem = mem_acc;
-
-	/* Read MAC addresses */
-	if (nvmem_device_read(at24_nvmem, 0x100, 6, buf) == 6)
-		memcpy(&laguna_net_data.hwaddr[0], buf, ETH_ALEN);
-	if (nvmem_device_read(at24_nvmem, 0x106, 6, buf) == 6)
-		memcpy(&laguna_net_data.hwaddr[1], buf, ETH_ALEN);
-	if (nvmem_device_read(at24_nvmem, 0x10C, 6, buf) == 6)
-		memcpy(&laguna_net_data.hwaddr[2], buf, ETH_ALEN);
-	if (nvmem_device_read(at24_nvmem, 0x112, 6, buf) == 6)
-		memcpy(&laguna_net_data.hwaddr[3], buf, ETH_ALEN);
-
-	/* Read out Model Information */
-	if (nvmem_device_read(at24_nvmem, 0x130, 16, buf) == 16)
-		memcpy(&laguna_info.model, buf, 16);
-	if (nvmem_device_read(at24_nvmem, 0x140, 1, buf) == 1)
-		memcpy(&laguna_info.nor_flash_size, buf, 1);
-	if (nvmem_device_read(at24_nvmem, 0x141, 1, buf) == 1)
-		memcpy(&laguna_info.spi_flash_size, buf, 1);
-	if (nvmem_device_read(at24_nvmem, 0x142, 4, buf) == 4)
-		memcpy(&laguna_info.config_bitmap, buf, 4);
-	if (nvmem_device_read(at24_nvmem, 0x146, 4, buf) == 4)
-		memcpy(&laguna_info.config2_bitmap, buf, 4);
-};
-
-static struct at24_platform_data laguna_eeprom_info = {
-	.byte_len = 1024,
-	.page_size = 16,
-	.flags = AT24_FLAG_READONLY,
-	.setup = at24_setup,
-};
-
-static struct pca953x_platform_data laguna_pca_data = {
- 	.gpio_base = 100,
-	.irq_base = -1,
-};
-
-static struct pca953x_platform_data laguna_pca2_data = {
- 	.gpio_base = 116,
-	.irq_base = -1,
-};
-
-static struct i2c_board_info __initdata laguna_i2c_devices[] = {
-	{
-		I2C_BOARD_INFO("pca9555", 0x23),
-		.platform_data = &laguna_pca_data,
-	},{
-		I2C_BOARD_INFO("pca9555", 0x27),
-		.platform_data = &laguna_pca2_data,
-	},{
-		I2C_BOARD_INFO("gsp", 0x29),
-	},{
-		I2C_BOARD_INFO ("24c08",0x50),
-		.platform_data = &laguna_eeprom_info,
-	},{
-		I2C_BOARD_INFO("ds1672", 0x68),
-	},
-};
-
-/*
- * Watchdog
- */
-
-static struct resource laguna_watchdog_resources[] = {
-	[0] = {
-		.start	= CNS3XXX_TC11MP_TWD_BASE + 0x100, // CPU0 watchdog
-		.end	= CNS3XXX_TC11MP_TWD_BASE + SZ_4K - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-};
-
-static struct platform_device laguna_watchdog = {
-	.name		= "mpcore_wdt",
-	.id		= PLATFORM_DEVID_NONE,
-	.num_resources	= ARRAY_SIZE(laguna_watchdog_resources),
-	.resource	= laguna_watchdog_resources,
-};
-
-/*
- * GPS PPS
- */
-static struct pps_gpio_platform_data laguna_pps_data = {
-	.gpio_pin = 0,
-	.gpio_label = "GPS_PPS",
-	.assert_falling_edge = 0,
-	.capture_clear = 0,
-};
-
-static struct platform_device laguna_pps_device = {
-	.name = "pps-gpio",
-	.id = PLATFORM_DEVID_NONE,
-	.dev.platform_data = &laguna_pps_data,
-};
-
-/*
- * GPIO
- */
-
-static struct gpio laguna_gpio_gw2391[] = {
-	{   0, GPIOF_IN           , "*GPS_PPS" },
-	{   1, GPIOF_IN           , "*GSC_IRQ#" },
-	{   2, GPIOF_IN           , "*USB_FAULT#" },
-	{   5, GPIOF_OUT_INIT_LOW , "*USB0_PCI_SEL" },
-	{   6, GPIOF_OUT_INIT_HIGH, "*USB_VBUS_EN" },
-	{   7, GPIOF_OUT_INIT_LOW , "*USB1_PCI_SEL" },
-	{   8, GPIOF_OUT_INIT_HIGH, "*PERST#" },
-	{   9, GPIOF_OUT_INIT_LOW , "*FP_SER_EN#" },
-	{ 100, GPIOF_IN           , "*USER_PB#" },
-	{ 103, GPIOF_OUT_INIT_HIGH, "*V5_EN" },
-	{ 108, GPIOF_IN           , "DIO0" },
-	{ 109, GPIOF_IN           , "DIO1" },
-	{ 110, GPIOF_IN           , "DIO2" },
-	{ 111, GPIOF_IN           , "DIO3" },
-	{ 112, GPIOF_IN           , "DIO4" },
-};
-
-static struct gpio laguna_gpio_gw2388[] = {
-	{   0, GPIOF_IN           , "*GPS_PPS" },
-	{   1, GPIOF_IN           , "*GSC_IRQ#" },
-	{   3, GPIOF_IN           , "*USB_FAULT#" },
-	{   6, GPIOF_OUT_INIT_HIGH, "*USB_VBUS_EN" },
-	{   7, GPIOF_OUT_INIT_LOW , "*GSM_SEL0" },
-	{   8, GPIOF_OUT_INIT_LOW , "*GSM_SEL1" },
-	{   9, GPIOF_OUT_INIT_LOW , "*FP_SER_EN" },
-	{ 100, GPIOF_OUT_INIT_HIGH, "*USER_PB#" },
-	{ 108, GPIOF_IN           , "DIO0" },
-	{ 109, GPIOF_IN           , "DIO1" },
-	{ 110, GPIOF_IN           , "DIO2" },
-	{ 111, GPIOF_IN           , "DIO3" },
-	{ 112, GPIOF_IN           , "DIO4" },
-};
-
-static struct gpio laguna_gpio_gw2387[] = {
-	{   0, GPIOF_IN           , "*GPS_PPS" },
-	{   1, GPIOF_IN           , "*GSC_IRQ#" },
-	{   2, GPIOF_IN           , "*USB_FAULT#" },
-	{   5, GPIOF_OUT_INIT_LOW , "*USB_PCI_SEL" },
-	{   6, GPIOF_OUT_INIT_HIGH, "*USB_VBUS_EN" },
-	{   7, GPIOF_OUT_INIT_LOW , "*GSM_SEL0" },
-	{   8, GPIOF_OUT_INIT_LOW , "*GSM_SEL1" },
-	{   9, GPIOF_OUT_INIT_LOW , "*FP_SER_EN" },
-	{ 100, GPIOF_IN           , "*USER_PB#" },
-	{ 103, GPIOF_OUT_INIT_HIGH, "*V5_EN" },
-	{ 108, GPIOF_IN           , "DIO0" },
-	{ 109, GPIOF_IN           , "DIO1" },
-	{ 110, GPIOF_IN           , "DIO2" },
-	{ 111, GPIOF_IN           , "DIO3" },
-	{ 112, GPIOF_IN           , "DIO4" },
-	{ 113, GPIOF_IN           , "DIO5" },
-};
-
-static struct gpio laguna_gpio_gw2386[] = {
-	{   0, GPIOF_IN           , "*GPS_PPS" },
-	{   2, GPIOF_IN           , "*USB_FAULT#" },
-	{   6, GPIOF_OUT_INIT_LOW , "*USB_PCI_SEL" },
-	{   7, GPIOF_OUT_INIT_LOW , "*GSM_SEL0" },
-	{   8, GPIOF_OUT_INIT_LOW , "*GSM_SEL1" },
-	{   9, GPIOF_OUT_INIT_LOW , "*FP_SER_EN" },
-	{ 108, GPIOF_IN           , "DIO0" },
-	{ 109, GPIOF_IN           , "DIO1" },
-	{ 110, GPIOF_IN           , "DIO2" },
-	{ 111, GPIOF_IN           , "DIO3" },
-	{ 112, GPIOF_IN           , "DIO4" },
-	{ 113, GPIOF_IN           , "DIO5" },
-};
-
-static struct gpio laguna_gpio_gw2385[] = {
-	{   0, GPIOF_IN           , "*GSC_IRQ#" },
-	{   1, GPIOF_OUT_INIT_HIGH, "*USB_HST_VBUS_EN" },
-	{   2, GPIOF_IN           , "*USB_HST_FAULT#" },
-	{   5, GPIOF_IN           , "*USB_OTG_FAULT#" },
-	{   6, GPIOF_OUT_INIT_LOW , "*USB_HST_PCI_SEL" },
-	{   7, GPIOF_OUT_INIT_LOW , "*GSM_SEL0" },
-	{   8, GPIOF_OUT_INIT_LOW , "*GSM_SEL1" },
-	{   9, GPIOF_OUT_INIT_LOW , "*SER_EN" },
-	{  10, GPIOF_IN,            "*USER_PB#" },
-	{  11, GPIOF_OUT_INIT_HIGH, "*PERST#" },
-	{ 100, GPIOF_IN           , "*USER_PB#" },
-	{ 103, GPIOF_OUT_INIT_HIGH, "V5_EN" },
-};
-
-static struct gpio laguna_gpio_gw2384[] = {
-	{   0, GPIOF_IN           , "*GSC_IRQ#" },
-	{   1, GPIOF_OUT_INIT_HIGH, "*USB_HST_VBUS_EN" },
-	{   2, GPIOF_IN           , "*USB_HST_FAULT#" },
-	{   5, GPIOF_IN           , "*USB_OTG_FAULT#" },
-	{   6, GPIOF_OUT_INIT_LOW , "*USB_HST_PCI_SEL" },
-	{   7, GPIOF_OUT_INIT_LOW , "*GSM_SEL0" },
-	{   8, GPIOF_OUT_INIT_LOW , "*GSM_SEL1" },
-	{   9, GPIOF_OUT_INIT_LOW , "*FP_SER_EN" },
-	{  12, GPIOF_OUT_INIT_LOW , "J10_DIOLED0" },
-	{  13, GPIOF_OUT_INIT_HIGH, "*I2CMUX_RST#" },
-	{  14, GPIOF_OUT_INIT_LOW , "J10_DIOLED1" },
-	{  15, GPIOF_OUT_INIT_LOW , "J10_DIOLED2" },
-	{ 100, GPIOF_IN           , "*USER_PB#" },
-	{ 103, GPIOF_OUT_INIT_HIGH, "V5_EN" },
-	{ 108, GPIOF_IN           , "J9_DIOGSC0" },
-};
-
-static struct gpio laguna_gpio_gw2383[] = {
-	{   0, GPIOF_IN           , "*GPS_PPS" },
-	{   1, GPIOF_IN           , "*GSC_IRQ#" },
-	{   2, GPIOF_OUT_INIT_HIGH, "*PCIE_RST#" },
-	{   3, GPIOF_IN           , "GPIO0" },
-	{   8, GPIOF_IN           , "GPIO1" },
-	{ 100, GPIOF_IN           , "DIO0" },
-	{ 101, GPIOF_IN           , "DIO1" },
-	{ 108, GPIOF_IN           , "*USER_PB#" },
-};
-
-static struct gpio laguna_gpio_gw2382[] = {
-	{   0, GPIOF_IN           , "*GPS_PPS" },
-	{   1, GPIOF_IN           , "*GSC_IRQ#" },
-	{   2, GPIOF_OUT_INIT_HIGH, "*PCIE_RST#" },
-	{   3, GPIOF_IN           , "GPIO0" },
-	{   4, GPIOF_IN           , "GPIO1" },
-	{   9, GPIOF_OUT_INIT_HIGH, "*USB_VBUS_EN" },
-	{  10, GPIOF_OUT_INIT_HIGH, "*USB_PCI_SEL#" },
-	{ 100, GPIOF_IN           , "DIO0" },
-	{ 101, GPIOF_IN           , "DIO1" },
-	{ 108, GPIOF_IN           , "*USER_PB#" },
-};
-
-static struct gpio laguna_gpio_gw2380[] = {
-	{   0, GPIOF_IN           , "*GPS_PPS" },
-	{   1, GPIOF_IN           , "*GSC_IRQ#" },
-	{   3, GPIOF_IN           , "GPIO0" },
-	{   8, GPIOF_IN           , "GPIO1" },
-	{ 100, GPIOF_IN           , "DIO0" },
-	{ 101, GPIOF_IN           , "DIO1" },
-	{ 102, GPIOF_IN           , "DIO2" },
-	{ 103, GPIOF_IN           , "DIO3" },
-	{ 108, GPIOF_IN           , "*USER_PB#" },
-};
-
-/*
- * Initialization
- */
-static void __init laguna_init(void)
-{
-	struct clk *clk;
-	u32 __iomem *reg;
-
-	clk = clk_register_fixed_rate(NULL, "cpu", NULL,
-				      CLK_IGNORE_UNUSED,
-				      cns3xxx_cpu_clock() * (1000000 / 8));
-	clk_register_clkdev(clk, "cpu", NULL);
-
-	platform_device_register(&laguna_watchdog);
-
-	platform_device_register(&laguna_i2c_controller);
-
-	/* Set I2C 0-3 drive strength to 21 mA */
-	reg = MISC_IO_PAD_DRIVE_STRENGTH_CTRL_B;
-	*reg |= 0x300;
-
-	/* Enable SCL/SDA for I2C */
-	reg = MISC_GPIOB_PIN_ENABLE_REG;
-	*reg |= BIT(12) | BIT(13);
-
-	/* Enable MMC/SD pins */
-	*reg |= BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11);
-
-	cns3xxx_pwr_clk_en(1 << PM_CLK_GATE_REG_OFFSET_SPI_PCM_I2C);
-	cns3xxx_pwr_power_up(1 << PM_CLK_GATE_REG_OFFSET_SPI_PCM_I2C);
-	cns3xxx_pwr_soft_rst(1 << PM_CLK_GATE_REG_OFFSET_SPI_PCM_I2C);
-
-	cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(SPI_PCM_I2C));
-	cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SPI_PCM_I2C));
-
-	i2c_register_board_info(0, ARRAY_AND_SIZE(laguna_i2c_devices));
-
-	pm_power_off = cns3xxx_power_off;
-}
-
-static struct map_desc laguna_io_desc[] __initdata = {
-	{
-		.virtual	= CNS3XXX_UART0_BASE_VIRT,
-		.pfn		= __phys_to_pfn(CNS3XXX_UART0_BASE),
-		.length		= SZ_4K,
-		.type		= MT_DEVICE,
-	},
-};
-
-static void __init laguna_map_io(void)
-{
-	cns3xxx_map_io();
-	iotable_init(ARRAY_AND_SIZE(laguna_io_desc));
-	laguna_early_serial_setup();
-}
-
-static int laguna_register_gpio(struct gpio *array, size_t num)
-{
-	int i, err, ret;
-
-	ret = 0;
-	for (i = 0; i < num; i++, array++) {
-		const char *label = array->label;
-		if (label[0] == '*')
-			label++;
-		err = gpio_request_one(array->gpio, array->flags, label);
-		if (err)
-			ret = err;
-		else {
-			err = gpio_export(array->gpio, array->label[0] != '*');
-		}
-	}
-	return ret;
-}
-
-/* allow disabling of external isolated PCIe IRQs */
-static int cns3xxx_pciextirq = 1;
-static int __init cns3xxx_pciextirq_disable(char *s)
-{
-      cns3xxx_pciextirq = 0;
-      return 1;
-}
-__setup("noextirq", cns3xxx_pciextirq_disable);
-
-static int __init laguna_pcie_init_irq(void)
-{
-	u32 __iomem *mem = (void __iomem *)(CNS3XXX_GPIOB_BASE_VIRT + 0x0004);
-	u32 reg = (__raw_readl(mem) >> 26) & 0xf;
-	int irqs[] = {
-		IRQ_CNS3XXX_EXTERNAL_PIN0,
-		IRQ_CNS3XXX_EXTERNAL_PIN1,
-		IRQ_CNS3XXX_EXTERNAL_PIN2,
-		154,
-	};
-
-	if (!machine_is_gw2388())
-		return 0;
-
-	/* Verify GPIOB[26:29] == 0001b indicating support for ext irqs */
-	if (cns3xxx_pciextirq && reg != 1)
-		cns3xxx_pciextirq = 0;
-
-	if (cns3xxx_pciextirq) {
-		printk("laguna: using isolated PCI interrupts:"
-		       " irq%d/irq%d/irq%d/irq%d\n",
-		       irqs[0], irqs[1], irqs[2], irqs[3]);
-		cns3xxx_pcie_set_irqs(0, irqs);
-	} else {
-		printk("laguna: using shared PCI interrupts: irq%d\n",
-		       IRQ_CNS3XXX_PCIE0_DEVICE);
-	}
-
-	return 0;
-}
-subsys_initcall(laguna_pcie_init_irq);
-
-static int __init laguna_model_setup(void)
-{
-	u32 __iomem *mem;
-	u32 reg;
-
-	if (!machine_is_gw2388())
-		return 0;
-
-	printk("Running on Gateworks Laguna %s\n", laguna_info.model);
-	cns3xxx_gpio_init( 0, 32, CNS3XXX_GPIOA_BASE_VIRT, IRQ_CNS3XXX_GPIOA,
-		NR_IRQS_CNS3XXX);
-
-	/*
-	 * If pcie external interrupts are supported and desired
-	 * configure IRQ types and configure pin function.
-	 * Note that cns3xxx_pciextirq is enabled by default, but can be
-	 * unset via the 'noextirq' kernel param or by laguna_pcie_init() if
-	 * the baseboard model does not support this hardware feature.
-	 */
-	if (cns3xxx_pciextirq) {
-		mem = (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + 0x0018);
-		reg = __raw_readl(mem);
-		/* GPIO26 is gpio, EXT_INT[0:2] not gpio func */
-		reg &= ~0x3c000000;
-		reg |= 0x38000000;
-		__raw_writel(reg, mem);
-
-		cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT,
-				  IRQ_CNS3XXX_GPIOB, NR_IRQS_CNS3XXX + 32);
-
-		irq_set_irq_type(154, IRQ_TYPE_LEVEL_LOW);
-		irq_set_irq_type(93, IRQ_TYPE_LEVEL_HIGH);
-		irq_set_irq_type(94, IRQ_TYPE_LEVEL_HIGH);
-		irq_set_irq_type(95, IRQ_TYPE_LEVEL_HIGH);
-	} else {
-		cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT,
-				  IRQ_CNS3XXX_GPIOB, NR_IRQS_CNS3XXX + 32);
-	}
-
-	if (strncmp(laguna_info.model, "GW", 2) == 0) {
-		if (laguna_info.config_bitmap & ETH0_LOAD)
-			laguna_net_data.ports |= BIT(0);
-		if (laguna_info.config_bitmap & ETH1_LOAD)
-			laguna_net_data.ports |= BIT(1);
-		if (laguna_info.config_bitmap & ETH2_LOAD)
-			laguna_net_data.ports |= BIT(2);
-		if (laguna_net_data.ports)
-			platform_device_register(&laguna_net_device);
-
-		if ((laguna_info.config_bitmap & SATA0_LOAD) ||
-		    (laguna_info.config_bitmap & SATA1_LOAD))
-			cns3xxx_ahci_init();
-
-		if (laguna_info.config_bitmap & (USB0_LOAD)) {
-			cns3xxx_pwr_power_up(1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB);
-
-			/* DRVVBUS pins share with GPIOA */
-			mem = (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + 0x0014);
-			reg = __raw_readl(mem);
-			reg |= 0x8;
-			__raw_writel(reg, mem);
-
-			/* Enable OTG */
-			mem = (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + 0x0808);
-			reg = __raw_readl(mem);
-			reg &= ~(1 << 10);
-			__raw_writel(reg, mem);
-
-			platform_device_register(&cns3xxx_usb_otg_device);
-		}
-
-		if (laguna_info.config_bitmap & (USB1_LOAD)) {
-			platform_device_register(&cns3xxx_usb_ehci_device);
-			platform_device_register(&cns3xxx_usb_ohci_device);
-		}
-
-		if (laguna_info.config_bitmap & (SD_LOAD))
-			cns3xxx_sdhci_init();
-
-		if (laguna_info.config_bitmap & (UART0_LOAD))
-			laguna_uart.num_resources = 1;
-		if (laguna_info.config_bitmap & (UART1_LOAD))
-			laguna_uart.num_resources = 2;
-		if (laguna_info.config_bitmap & (UART2_LOAD))
-			laguna_uart.num_resources = 3;
-		platform_device_register(&laguna_uart);
-
-		if (laguna_info.config2_bitmap & (NOR_FLASH_LOAD)) {
-			laguna_nor_partitions[2].size =
-				(SZ_4M << laguna_info.nor_flash_size) -
-				laguna_nor_partitions[2].offset;
-			laguna_nor_res.end = CNS3XXX_FLASH_BASE +
-				laguna_nor_partitions[2].offset +
-				laguna_nor_partitions[2].size - 1;
-			platform_device_register(&laguna_nor_pdev);
-		}
-
-		if (laguna_info.config2_bitmap & (SPI_FLASH_LOAD)) {
-			laguna_spi_partitions[2].size =
-				(SZ_2M << laguna_info.spi_flash_size) -
-				laguna_spi_partitions[2].offset;
-			spi_register_board_info(ARRAY_AND_SIZE(laguna_spi_devices));
-		}
-
-		if ((laguna_info.config_bitmap & SPI0_LOAD) ||
-		    (laguna_info.config_bitmap & SPI1_LOAD))
-			platform_device_register(&laguna_spi_controller);
-
-		if (laguna_info.config2_bitmap & GPS_LOAD)
-			platform_device_register(&laguna_pps_device);
-
-		/*
-		 * Do any model specific setup not known by the bitmap by matching
-		 *  the first 6 characters of the model name
-		 */
-
-		if ( (strncmp(laguna_info.model, "GW2388", 6) == 0)
-		  || (strncmp(laguna_info.model, "GW2389", 6) == 0) )
-		{
-			// configure GPIO's
-			laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2388));
-			// configure LED's
-			laguna_gpio_leds_data.num_leds = 2;
-		} else if (strncmp(laguna_info.model, "GW2387", 6) == 0) {
-			// configure GPIO's
-			laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2387));
-			// configure LED's
-			laguna_gpio_leds_data.num_leds = 2;
-		} else if (strncmp(laguna_info.model, "GW2386", 6) == 0) {
-			// configure GPIO's
-			laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2386));
-			// configure LED's
-			laguna_gpio_leds_data.num_leds = 2;
-		} else if (strncmp(laguna_info.model, "GW2385", 6) == 0) {
-			// configure GPIO's
-			laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2385));
-			// configure LED's
-			laguna_gpio_leds[0].gpio = 115;
-			laguna_gpio_leds[1].gpio = 12;
-			laguna_gpio_leds[1].name = "red";
-			laguna_gpio_leds[1].active_low = 0,
-			laguna_gpio_leds[2].gpio = 14;
-			laguna_gpio_leds[2].name = "green";
-			laguna_gpio_leds[2].active_low = 0,
-			laguna_gpio_leds[3].gpio = 15;
-			laguna_gpio_leds[3].name = "blue";
-			laguna_gpio_leds[3].active_low = 0,
-			laguna_gpio_leds_data.num_leds = 4;
-		} else if ( (strncmp(laguna_info.model, "GW2384", 6) == 0)
-			 || (strncmp(laguna_info.model, "GW2394", 6) == 0) )
-		{
-			// configure GPIO's
-			laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2384));
-			// configure LED's
-			laguna_gpio_leds_data.num_leds = 1;
-		} else if (strncmp(laguna_info.model, "GW2383", 6) == 0) {
-			// configure GPIO's
-			laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2383));
-			// configure LED's
-			laguna_gpio_leds[0].gpio = 107;
-			laguna_gpio_leds_data.num_leds = 1;
-		} else if (strncmp(laguna_info.model, "GW2382", 6) == 0) {
-			// configure GPIO's
-			laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2382));
-			// configure LED's
-			laguna_gpio_leds[0].gpio = 107;
-			laguna_gpio_leds_data.num_leds = 1;
-		} else if (strncmp(laguna_info.model, "GW2380", 6) == 0) {
-			// configure GPIO's
-			laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2380));
-			// configure LED's
-			laguna_gpio_leds[0].gpio = 107;
-			laguna_gpio_leds[1].gpio = 106;
-			laguna_gpio_leds_data.num_leds = 2;
-		} else if ( (strncmp(laguna_info.model, "GW2391", 6) == 0)
-			 || (strncmp(laguna_info.model, "GW2393", 6) == 0) )
-		{
-			// configure GPIO's
-			laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2391));
-			// configure LED's
-			laguna_gpio_leds_data.num_leds = 2;
-		}
-		platform_device_register(&laguna_gpio_leds_device);
-	} else {
-		// Do some defaults here, not sure what yet
-	}
-	return 0;
-}
-late_initcall(laguna_model_setup);
-
-MACHINE_START(GW2388, "Gateworks Corporation Laguna Platform")
-	.smp		= smp_ops(cns3xxx_smp_ops),
-	.atag_offset	= 0x100,
-	.map_io		= laguna_map_io,
-	.init_irq	= cns3xxx_init_irq,
-	.init_time	= cns3xxx_timer_init,
-	.init_machine	= laguna_init,
-	.init_late      = cns3xxx_pcie_init_late,
-	.restart	= cns3xxx_restart,
-MACHINE_END
diff --git a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/platsmp.c b/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/platsmp.c
deleted file mode 100644
index cb81d1e752..0000000000
--- a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/platsmp.c
+++ /dev/null
@@ -1,327 +0,0 @@
-/*
- *  linux/arch/arm/mach-cns3xxx/platsmp.c
- *
- *  Copyright (C) 2002 ARM Ltd.
- *  Copyright 2012 Gateworks Corporation
- *		   Chris Lang <clang@gateworks.com>
- *         Tim Harvey <tharvey@gateworks.com>
- *
- *  All Rights Reserved
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/init.h>
-#include <linux/errno.h>
-#include <linux/delay.h>
-#include <linux/device.h>
-#include <linux/jiffies.h>
-#include <linux/smp.h>
-#include <linux/io.h>
-
-#include <asm/cacheflush.h>
-#include <asm/smp_scu.h>
-#include <asm/unified.h>
-#include <asm/fiq.h>
-#include <mach/smp.h>
-#include "cns3xxx.h"
-
-static struct fiq_handler fh = {
-	.name = "cns3xxx-fiq"
-};
-
-struct fiq_req {
-	union {
-		struct {
-			const void *addr;
-			size_t size;
-		} map;
-		struct {
-			const void *addr;
-			size_t size;
-		} unmap;
-		struct {
-			const void *start;
-			const void *end;
-		} flush;
-	};
-	volatile uint flags;
-	void __iomem *reg;
-} ____cacheline_aligned;
-
-extern unsigned int fiq_number[2];
-
-DEFINE_PER_CPU(struct fiq_req, fiq_data);
-
-#define FIQ_ENABLED         0x80000000
-#define FIQ_GENERATE        0x00010000
-#define CNS3XXX_MAP_AREA    0x01000000
-#define CNS3XXX_UNMAP_AREA  0x02000000
-#define CNS3XXX_FLUSH_RANGE 0x03000000
-
-extern void cns3xxx_secondary_startup(void);
-extern unsigned char cns3xxx_fiq_start, cns3xxx_fiq_end;
-
-#define SCU_CPU_STATUS 0x08
-static void __iomem *scu_base;
-
-static inline void cns3xxx_set_fiq_regs(unsigned int cpu)
-{
-	struct pt_regs FIQ_regs;
-	struct fiq_req *fiq_req = &per_cpu(fiq_data, !cpu);
-
-	FIQ_regs.ARM_r8 = 0;
-	FIQ_regs.ARM_ip = (unsigned int)fiq_req;
-	FIQ_regs.ARM_sp = (int) MISC_FIQ_CPU(!cpu);
-	fiq_req->reg = MISC_FIQ_CPU(!cpu);
-
-	set_fiq_regs(&FIQ_regs);
-}
-
-static void __init cns3xxx_init_fiq(void)
-{
-	void *fiqhandler_start;
-	unsigned int fiqhandler_length;
-	int ret;
-
-	fiqhandler_start = &cns3xxx_fiq_start;
-	fiqhandler_length = &cns3xxx_fiq_end - &cns3xxx_fiq_start;
-
-	ret = claim_fiq(&fh);
-	if (ret)
-		return;
-
-	set_fiq_handler(fiqhandler_start, fiqhandler_length);
-}
-
-
-/*
- * Write pen_release in a way that is guaranteed to be visible to all
- * observers, irrespective of whether they're taking part in coherency
- * or not.  This is necessary for the hotplug code to work reliably.
- */
-static void write_pen_release(int val)
-{
-	pen_release = val;
-	smp_wmb();
-	__cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
-	outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
-}
-
-static DEFINE_SPINLOCK(boot_lock);
-
-static void cns3xxx_secondary_init(unsigned int cpu)
-{
-	/*
-	 * Setup Secondary Core FIQ regs
-	 */
-	cns3xxx_set_fiq_regs(1);
-
-	/*
-	 * let the primary processor know we're out of the
-	 * pen, then head off into the C entry point
-	 */
-	write_pen_release(-1);
-
-	/*
-	 * Synchronise with the boot thread.
-	 */
-	spin_lock(&boot_lock);
-	spin_unlock(&boot_lock);
-}
-
-static int cns3xxx_boot_secondary(unsigned int cpu, struct task_struct *idle)
-{
-	unsigned long timeout;
-
-	/*
-	 * Set synchronisation state between this boot processor
-	 * and the secondary one
-	 */
-	spin_lock(&boot_lock);
-
-	/*
-	 * The secondary processor is waiting to be released from
-	 * the holding pen - release it, then wait for it to flag
-	 * that it has been released by resetting pen_release.
-	 *
-	 * Note that "pen_release" is the hardware CPU ID, whereas
-	 * "cpu" is Linux's internal ID.
-	 */
-	write_pen_release(cpu);
-
-	/*
-	 * Send the secondary CPU a soft interrupt, thereby causing
-	 * the boot monitor to read the system wide flags register,
-	 * and branch to the address found there.
-	 */
-	arch_send_wakeup_ipi_mask(cpumask_of(cpu));;
-
-	timeout = jiffies + (1 * HZ);
-	while (time_before(jiffies, timeout)) {
-		smp_rmb();
-		if (pen_release == -1)
-			break;
-
-		udelay(10);
-	}
-
-	/*
-	 * now the secondary core is starting up let it run its
-	 * calibrations, then wait for it to finish
-	 */
-	spin_unlock(&boot_lock);
-
-	return pen_release != -1 ? -ENOSYS : 0;
-}
-
-/*
- * Initialise the CPU possible map early - this describes the CPUs
- * which may be present or become present in the system.
- */
-static void __init cns3xxx_smp_init_cpus(void)
-{
-	unsigned int i, ncores;
-	unsigned int status;
-
-	scu_base = (void __iomem *) CNS3XXX_TC11MP_SCU_BASE_VIRT;
-
-	/* for CNS3xxx SCU_CPU_STATUS must be examined instead of SCU_CONFIGURATION
-	 * used in scu_get_core_count
-	 */
-	status = __raw_readl(scu_base + SCU_CPU_STATUS);
-	for (i = 0; i < NR_CPUS+1; i++) {
-		if (((status >> (i*2)) & 0x3) == 0)
-			set_cpu_possible(i, true);
-		else
-			break;
-	}
-	ncores = i;
-}
-
-static void __init cns3xxx_smp_prepare_cpus(unsigned int max_cpus)
-{
-	/*
-	 * enable SCU
-	 */
-	scu_enable(scu_base);
-
-	/*
-	 * Write the address of secondary startup into the
-	 * system-wide flags register. The boot monitor waits
-	 * until it receives a soft interrupt, and then the
-	 * secondary CPU branches to this address.
-	 */
-	__raw_writel(virt_to_phys(cns3xxx_secondary_startup),
-			(void __iomem *)(CNS3XXX_MISC_BASE_VIRT + 0x0600));
-
-	/*
-	 * Setup FIQ's for main cpu
-	 */
-	cns3xxx_init_fiq();
-	cns3xxx_set_fiq_regs(0);
-}
-
-extern void v6_dma_map_area(const void *, size_t, int);
-extern void v6_dma_unmap_area(const void *, size_t, int);
-extern void v6_dma_flush_range(const void *, const void *);
-extern void v6_flush_kern_dcache_area(void *, size_t);
-
-void fiq_dma_map_area(const void *addr, size_t size, int dir)
-{
-	unsigned long flags;
-	struct fiq_req *req;
-
-	raw_local_irq_save(flags);
-	/* currently, not possible to take cpu0 down, so only check cpu1 */
-	if (!cpu_online(1)) {
-		raw_local_irq_restore(flags);
-		v6_dma_map_area(addr, size, dir);
-		return;
-	}
-
-	req = this_cpu_ptr(&fiq_data);
-	req->map.addr = addr;
-	req->map.size = size;
-	req->flags = dir | CNS3XXX_MAP_AREA;
-	smp_mb();
-
-	writel_relaxed(FIQ_GENERATE, req->reg);
-
-	v6_dma_map_area(addr, size, dir);
-	while (req->flags)
-		barrier();
-
-	raw_local_irq_restore(flags);
-}
-
-void fiq_dma_unmap_area(const void *addr, size_t size, int dir)
-{
-	unsigned long flags;
-	struct fiq_req *req;
-
-	raw_local_irq_save(flags);
-	/* currently, not possible to take cpu0 down, so only check cpu1 */
-	if (!cpu_online(1)) {
-		raw_local_irq_restore(flags);
-		v6_dma_unmap_area(addr, size, dir);
-		return;
-	}
-
-	req = this_cpu_ptr(&fiq_data);
-	req->unmap.addr = addr;
-	req->unmap.size = size;
-	req->flags = dir | CNS3XXX_UNMAP_AREA;
-	smp_mb();
-
-	writel_relaxed(FIQ_GENERATE, req->reg);
-
-	v6_dma_unmap_area(addr, size, dir);
-	while (req->flags)
-		barrier();
-
-	raw_local_irq_restore(flags);
-}
-
-void fiq_dma_flush_range(const void *start, const void *end)
-{
-	unsigned long flags;
-	struct fiq_req *req;
-
-	raw_local_irq_save(flags);
-	/* currently, not possible to take cpu0 down, so only check cpu1 */
-	if (!cpu_online(1)) {
-		raw_local_irq_restore(flags);
-		v6_dma_flush_range(start, end);
-		return;
-	}
-
-	req = this_cpu_ptr(&fiq_data);
-
-	req->flush.start = start;
-	req->flush.end = end;
-	req->flags = CNS3XXX_FLUSH_RANGE;
-	smp_mb();
-
-	writel_relaxed(FIQ_GENERATE, req->reg);
-
-	v6_dma_flush_range(start, end);
-
-	while (req->flags)
-		barrier();
-
-	raw_local_irq_restore(flags);
-}
-
-void fiq_flush_kern_dcache_area(void *addr, size_t size)
-{
-	fiq_dma_flush_range(addr, addr + size);
-}
-
-struct smp_operations cns3xxx_smp_ops __initdata = {
-	.smp_init_cpus      = cns3xxx_smp_init_cpus,
-	.smp_prepare_cpus   = cns3xxx_smp_prepare_cpus,
-	.smp_secondary_init = cns3xxx_secondary_init,
-	.smp_boot_secondary = cns3xxx_boot_secondary,
-};