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| author | Gabor Juhos <juhosg@openwrt.org> | 2012-05-18 20:10:53 +0000 |
|---|---|---|
| committer | Gabor Juhos <juhosg@openwrt.org> | 2012-05-18 20:10:53 +0000 |
| commit | c2a2d59db5ef7b8b9c35d1756585d8b3c6f35543 (patch) | |
| tree | 66049fc1334ba92332e345b934956b48aca8cc4f /target/linux/cns3xxx/patches-3.3/054-cns3xxx_pcie_clock.patch | |
| parent | 1fd4bf270b2100ef13eb41677ff36a377d0d6dba (diff) | |
| download | upstream-c2a2d59db5ef7b8b9c35d1756585d8b3c6f35543.tar.gz upstream-c2a2d59db5ef7b8b9c35d1756585d8b3c6f35543.tar.bz2 upstream-c2a2d59db5ef7b8b9c35d1756585d8b3c6f35543.zip | |
cns3xxx: add support for 3.3
Compile tested only.
SVN-Revision: 31809
Diffstat (limited to 'target/linux/cns3xxx/patches-3.3/054-cns3xxx_pcie_clock.patch')
| -rw-r--r-- | target/linux/cns3xxx/patches-3.3/054-cns3xxx_pcie_clock.patch | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/target/linux/cns3xxx/patches-3.3/054-cns3xxx_pcie_clock.patch b/target/linux/cns3xxx/patches-3.3/054-cns3xxx_pcie_clock.patch new file mode 100644 index 0000000000..0c6c525039 --- /dev/null +++ b/target/linux/cns3xxx/patches-3.3/054-cns3xxx_pcie_clock.patch @@ -0,0 +1,11 @@ +--- a/arch/arm/mach-cns3xxx/pcie.c ++++ b/arch/arm/mach-cns3xxx/pcie.c +@@ -378,8 +378,6 @@ static int __init cns3xxx_pcie_init(void + for (i = 0; i < ARRAY_SIZE(cns3xxx_pcie); i++) { + iotable_init(cns3xxx_pcie[i].cfg_bases, + ARRAY_SIZE(cns3xxx_pcie[i].cfg_bases)); +- cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_PCIE(i)); +- cns3xxx_pwr_soft_rst(0x1 << PM_SOFT_RST_REG_OFFST_PCIE(i)); + cns3xxx_pcie_check_link(&cns3xxx_pcie[i]); + cns3xxx_pcie_hw_init(&cns3xxx_pcie[i]); + pci_common_init(&cns3xxx_pcie[i].hw_pci); |