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| author | Koen Vandeputte <koen.vandeputte@ncentric.com> | 2017-02-07 16:19:18 +0100 |
|---|---|---|
| committer | Felix Fietkau <nbd@nbd.name> | 2017-02-10 11:05:57 +0100 |
| commit | 1db4135e32e03c0131301ed46d906a2bf8f08c9b (patch) | |
| tree | f1da4a38a5ee6d7337843d9528f7e21fa61a006f /target/linux/cns3xxx/patches-4.9/093-add-virt-pci-io-mapping.patch | |
| parent | b96566aad4340c5b790bdaea0514885857ea84bf (diff) | |
| download | upstream-1db4135e32e03c0131301ed46d906a2bf8f08c9b.tar.gz upstream-1db4135e32e03c0131301ed46d906a2bf8f08c9b.tar.bz2 upstream-1db4135e32e03c0131301ed46d906a2bf8f08c9b.zip | |
cns3xxx: add preliminary 4.9 support
Adds preliminary kernel 4.9 support for this target.
- Refreshed/Updated all patches
Added 3 new patches:
- 093 --> Add virtual PCI MMIO mapping
- 230 --> Remove deprecated code
- 240 --> Rework AT24 eeprom code to use the new NVMEM API
Compiled & tested on cns3xxx (gw2388)
Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
Diffstat (limited to 'target/linux/cns3xxx/patches-4.9/093-add-virt-pci-io-mapping.patch')
| -rw-r--r-- | target/linux/cns3xxx/patches-4.9/093-add-virt-pci-io-mapping.patch | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/target/linux/cns3xxx/patches-4.9/093-add-virt-pci-io-mapping.patch b/target/linux/cns3xxx/patches-4.9/093-add-virt-pci-io-mapping.patch new file mode 100644 index 0000000000..0fa7ed483f --- /dev/null +++ b/target/linux/cns3xxx/patches-4.9/093-add-virt-pci-io-mapping.patch @@ -0,0 +1,41 @@ +--- a/arch/arm/mach-cns3xxx/cns3xxx.h ++++ b/arch/arm/mach-cns3xxx/cns3xxx.h +@@ -162,11 +162,13 @@ + #define CNS3XXX_L2C_BASE 0x92000000 /* L2 Cache Control */ + + #define CNS3XXX_PCIE0_MEM_BASE 0xA0000000 /* PCIe Port 0 IO/Memory Space */ ++#define CNS3XXX_PCIE0_MEM_BASE_VIRT 0xE0000000 + + #define CNS3XXX_PCIE0_HOST_BASE 0xAB000000 /* PCIe Port 0 RC Base */ + #define CNS3XXX_PCIE0_HOST_BASE_VIRT 0xE1000000 + + #define CNS3XXX_PCIE0_IO_BASE 0xAC000000 /* PCIe Port 0 */ ++#define CNS3XXX_PCIE0_IO_BASE_VIRT 0xE2000000 + + #define CNS3XXX_PCIE0_CFG0_BASE 0xAD000000 /* PCIe Port 0 CFG Type 0 */ + #define CNS3XXX_PCIE0_CFG0_BASE_VIRT 0xE3000000 +@@ -175,13 +177,16 @@ + #define CNS3XXX_PCIE0_CFG1_BASE_VIRT 0xE4000000 + + #define CNS3XXX_PCIE0_MSG_BASE 0xAF000000 /* PCIe Port 0 Message Space */ ++#define CNS3XXX_PCIE0_MSG_BASE_VIRT 0xE5000000 + + #define CNS3XXX_PCIE1_MEM_BASE 0xB0000000 /* PCIe Port 1 IO/Memory Space */ ++#define CNS3XXX_PCIE1_MEM_BASE_VIRT 0xE8000000 + + #define CNS3XXX_PCIE1_HOST_BASE 0xBB000000 /* PCIe Port 1 RC Base */ + #define CNS3XXX_PCIE1_HOST_BASE_VIRT 0xE9000000 + + #define CNS3XXX_PCIE1_IO_BASE 0xBC000000 /* PCIe Port 1 */ ++#define CNS3XXX_PCIE1_IO_BASE_VIRT 0xEA000000 + + #define CNS3XXX_PCIE1_CFG0_BASE 0xBD000000 /* PCIe Port 1 CFG Type 0 */ + #define CNS3XXX_PCIE1_CFG0_BASE_VIRT 0xEB000000 +@@ -190,6 +195,7 @@ + #define CNS3XXX_PCIE1_CFG1_BASE_VIRT 0xEC000000 + + #define CNS3XXX_PCIE1_MSG_BASE 0xBF000000 /* PCIe Port 1 Message Space */ ++#define CNS3XXX_PCIE1_MSG_BASE_VIRT 0xED000000 + + /* + * Testchip peripheral and fpga gic regions |