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| author | Felix Fietkau <nbd@nbd.name> | 2020-09-13 09:34:37 +0200 |
|---|---|---|
| committer | Felix Fietkau <nbd@nbd.name> | 2020-09-13 11:14:32 +0200 |
| commit | f0cc5f6c0a72b7da9ed5915cf561e2f81d514c68 (patch) | |
| tree | 87523c6da3cfdbd48968d21eacb3049508ea21a9 /target/linux/generic/backport-5.4/760-net-ethernet-mediatek-Integrate-GDM-PSE-setup-operat.patch | |
| parent | 17e64b9447959858c5c85f7f6c98264775585711 (diff) | |
| download | upstream-f0cc5f6c0a72b7da9ed5915cf561e2f81d514c68.tar.gz upstream-f0cc5f6c0a72b7da9ed5915cf561e2f81d514c68.tar.bz2 upstream-f0cc5f6c0a72b7da9ed5915cf561e2f81d514c68.zip | |
ramips/mediatek: improve GRO performance, fix PPE packet parsing
Backport upstream changes to initialize GDM settings and reset PPE
Allow GMAC to recognize the special tag to fix PPE packet parsing
Improve GRO performance by passing PPE L4 hash as skb hash
Signed-off-by: Felix Fietkau <nbd@nbd.name>
Diffstat (limited to 'target/linux/generic/backport-5.4/760-net-ethernet-mediatek-Integrate-GDM-PSE-setup-operat.patch')
| -rw-r--r-- | target/linux/generic/backport-5.4/760-net-ethernet-mediatek-Integrate-GDM-PSE-setup-operat.patch | 80 |
1 files changed, 80 insertions, 0 deletions
diff --git a/target/linux/generic/backport-5.4/760-net-ethernet-mediatek-Integrate-GDM-PSE-setup-operat.patch b/target/linux/generic/backport-5.4/760-net-ethernet-mediatek-Integrate-GDM-PSE-setup-operat.patch new file mode 100644 index 0000000000..4df1fd2677 --- /dev/null +++ b/target/linux/generic/backport-5.4/760-net-ethernet-mediatek-Integrate-GDM-PSE-setup-operat.patch @@ -0,0 +1,80 @@ +From: MarkLee <Mark-MC.Lee@mediatek.com> +Date: Wed, 13 Nov 2019 10:38:42 +0800 +Subject: [PATCH] net: ethernet: mediatek: Integrate GDM/PSE setup operations + +Integrate GDM/PSE setup operations into single function "mtk_gdm_config" + +Signed-off-by: MarkLee <Mark-MC.Lee@mediatek.com> +Signed-off-by: David S. Miller <davem@davemloft.net> +--- + +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c +@@ -2211,6 +2211,28 @@ static int mtk_start_dma(struct mtk_eth + return 0; + } + ++static void mtk_gdm_config(struct mtk_eth *eth, u32 config) ++{ ++ int i; ++ ++ for (i = 0; i < MTK_MAC_COUNT; i++) { ++ u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i)); ++ ++ /* default setup the forward port to send frame to PDMA */ ++ val &= ~0xffff; ++ ++ /* Enable RX checksum */ ++ val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN; ++ ++ val |= config; ++ ++ mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i)); ++ } ++ /* Reset and enable PSE */ ++ mtk_w32(eth, RST_GL_PSE, MTK_RST_GL); ++ mtk_w32(eth, 0, MTK_RST_GL); ++} ++ + static int mtk_open(struct net_device *dev) + { + struct mtk_mac *mac = netdev_priv(dev); +@@ -2406,8 +2428,6 @@ static int mtk_hw_init(struct mtk_eth *e + mtk_w32(eth, 0, MTK_QDMA_DELAY_INT); + mtk_tx_irq_disable(eth, ~0); + mtk_rx_irq_disable(eth, ~0); +- mtk_w32(eth, RST_GL_PSE, MTK_RST_GL); +- mtk_w32(eth, 0, MTK_RST_GL); + + /* FE int grouping */ + mtk_w32(eth, MTK_TX_DONE_INT, MTK_PDMA_INT_GRP1); +@@ -2416,18 +2436,7 @@ static int mtk_hw_init(struct mtk_eth *e + mtk_w32(eth, MTK_RX_DONE_INT, MTK_QDMA_INT_GRP2); + mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP); + +- for (i = 0; i < MTK_MAC_COUNT; i++) { +- u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i)); +- +- /* setup the forward port to send frame to PDMA */ +- val &= ~0xffff; +- +- /* Enable RX checksum */ +- val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN; +- +- /* setup the mac dma */ +- mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i)); +- } ++ mtk_gdm_config(eth, MTK_GDMA_TO_PDMA); + + return 0; + +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h +@@ -84,6 +84,7 @@ + #define MTK_GDMA_ICS_EN BIT(22) + #define MTK_GDMA_TCS_EN BIT(21) + #define MTK_GDMA_UCS_EN BIT(20) ++#define MTK_GDMA_TO_PDMA 0x0 + + /* Unicast Filter MAC Address Register - Low */ + #define MTK_GDMA_MAC_ADRL(x) (0x508 + (x * 0x1000)) |