kernel: split patches folder up into backport, pending and hack folders

* properly format/comment all patches
* merge debloat patches
* merge Kconfig patches
* merge swconfig patches
* merge hotplug patches
* drop 200-fix_localversion.patch - upstream
* drop 222-arm_zimage_none.patch - unused
* drop 252-mv_cesa_depends.patch - no longer required
* drop 410-mtd-move-forward-declaration-of-struct-mtd_info.patch - unused
* drop 661-fq_codel_keep_dropped_stats.patch - outdated
* drop 702-phy_add_aneg_done_function.patch - upstream
* drop 840-rtc7301.patch - unused
* drop 841-rtc_pt7c4338.patch - upstream
* drop 921-use_preinit_as_init.patch - unused
* drop spio-gpio-old and gpio-mmc - unused

Signed-off-by: John Crispin <john@phrozen.org>

1 files changed, 716 insertions, 0 deletions

diff --git a/target/linux/generic/pending-3.18/032-bcma-from-4.6.patch b/target/linux/generic/pending-3.18/032-bcma-from-4.6.patch
new file mode 100644
index 0000000000..85eeaad4d3
--- /dev/null
+++ b/target/linux/generic/pending-3.18/032-bcma-from-4.6.patch
@@ -0,0 +1,716 @@
+--- a/drivers/bcma/driver_chipcommon.c
++++ b/drivers/bcma/driver_chipcommon.c
+@@ -15,6 +15,8 @@
+ #include <linux/platform_device.h>
+ #include <linux/bcma/bcma.h>
+ 
++static void bcma_chipco_serial_init(struct bcma_drv_cc *cc);
++
+ static inline u32 bcma_cc_write32_masked(struct bcma_drv_cc *cc, u16 offset,
+ 					 u32 mask, u32 value)
+ {
+@@ -113,8 +115,37 @@ int bcma_chipco_watchdog_register(struct
+ 	return 0;
+ }
+ 
++static void bcma_core_chipcommon_flash_detect(struct bcma_drv_cc *cc)
++{
++	struct bcma_bus *bus = cc->core->bus;
++
++	switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
++	case BCMA_CC_FLASHT_STSER:
++	case BCMA_CC_FLASHT_ATSER:
++		bcma_debug(bus, "Found serial flash\n");
++		bcma_sflash_init(cc);
++		break;
++	case BCMA_CC_FLASHT_PARA:
++		bcma_debug(bus, "Found parallel flash\n");
++		bcma_pflash_init(cc);
++		break;
++	default:
++		bcma_err(bus, "Flash type not supported\n");
++	}
++
++	if (cc->core->id.rev == 38 ||
++	    bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) {
++		if (cc->capabilities & BCMA_CC_CAP_NFLASH) {
++			bcma_debug(bus, "Found NAND flash\n");
++			bcma_nflash_init(cc);
++		}
++	}
++}
++
+ void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc)
+ {
++	struct bcma_bus *bus = cc->core->bus;
++
+ 	if (cc->early_setup_done)
+ 		return;
+ 
+@@ -129,6 +160,12 @@ void bcma_core_chipcommon_early_init(str
+ 	if (cc->capabilities & BCMA_CC_CAP_PMU)
+ 		bcma_pmu_early_init(cc);
+ 
++	if (IS_BUILTIN(CONFIG_BCM47XX) && bus->hosttype == BCMA_HOSTTYPE_SOC)
++		bcma_chipco_serial_init(cc);
++
++	if (bus->hosttype == BCMA_HOSTTYPE_SOC)
++		bcma_core_chipcommon_flash_detect(cc);
++
+ 	cc->early_setup_done = true;
+ }
+ 
+@@ -185,11 +222,12 @@ u32 bcma_chipco_watchdog_timer_set(struc
+ 			ticks = 2;
+ 		else if (ticks > maxt)
+ 			ticks = maxt;
+-		bcma_cc_write32(cc, BCMA_CC_PMU_WATCHDOG, ticks);
++		bcma_pmu_write32(cc, BCMA_CC_PMU_WATCHDOG, ticks);
+ 	} else {
+ 		struct bcma_bus *bus = cc->core->bus;
+ 
+ 		if (bus->chipinfo.id != BCMA_CHIP_ID_BCM4707 &&
++		    bus->chipinfo.id != BCMA_CHIP_ID_BCM47094 &&
+ 		    bus->chipinfo.id != BCMA_CHIP_ID_BCM53018)
+ 			bcma_core_set_clockmode(cc->core,
+ 						ticks ? BCMA_CLKMODE_FAST : BCMA_CLKMODE_DYNAMIC);
+@@ -314,9 +352,9 @@ u32 bcma_chipco_gpio_pulldown(struct bcm
+ 	return res;
+ }
+ 
+-#ifdef CONFIG_BCMA_DRIVER_MIPS
+-void bcma_chipco_serial_init(struct bcma_drv_cc *cc)
++static void bcma_chipco_serial_init(struct bcma_drv_cc *cc)
+ {
++#if IS_BUILTIN(CONFIG_BCM47XX)
+ 	unsigned int irq;
+ 	u32 baud_base;
+ 	u32 i;
+@@ -358,5 +396,5 @@ void bcma_chipco_serial_init(struct bcma
+ 		ports[i].baud_base = baud_base;
+ 		ports[i].reg_shift = 0;
+ 	}
++#endif /* CONFIG_BCM47XX */
+ }
+-#endif /* CONFIG_BCMA_DRIVER_MIPS */
+--- a/drivers/bcma/driver_chipcommon_pmu.c
++++ b/drivers/bcma/driver_chipcommon_pmu.c
+@@ -15,44 +15,44 @@
+ 
+ u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset)
+ {
+-	bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
+-	bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
+-	return bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
++	bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_ADDR, offset);
++	bcma_pmu_read32(cc, BCMA_CC_PMU_PLLCTL_ADDR);
++	return bcma_pmu_read32(cc, BCMA_CC_PMU_PLLCTL_DATA);
+ }
+ EXPORT_SYMBOL_GPL(bcma_chipco_pll_read);
+ 
+ void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset, u32 value)
+ {
+-	bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
+-	bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
+-	bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, value);
++	bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_ADDR, offset);
++	bcma_pmu_read32(cc, BCMA_CC_PMU_PLLCTL_ADDR);
++	bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_DATA, value);
+ }
+ EXPORT_SYMBOL_GPL(bcma_chipco_pll_write);
+ 
+ void bcma_chipco_pll_maskset(struct bcma_drv_cc *cc, u32 offset, u32 mask,
+ 			     u32 set)
+ {
+-	bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
+-	bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
+-	bcma_cc_maskset32(cc, BCMA_CC_PLLCTL_DATA, mask, set);
++	bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_ADDR, offset);
++	bcma_pmu_read32(cc, BCMA_CC_PMU_PLLCTL_ADDR);
++	bcma_pmu_maskset32(cc, BCMA_CC_PMU_PLLCTL_DATA, mask, set);
+ }
+ EXPORT_SYMBOL_GPL(bcma_chipco_pll_maskset);
+ 
+ void bcma_chipco_chipctl_maskset(struct bcma_drv_cc *cc,
+ 				 u32 offset, u32 mask, u32 set)
+ {
+-	bcma_cc_write32(cc, BCMA_CC_CHIPCTL_ADDR, offset);
+-	bcma_cc_read32(cc, BCMA_CC_CHIPCTL_ADDR);
+-	bcma_cc_maskset32(cc, BCMA_CC_CHIPCTL_DATA, mask, set);
++	bcma_pmu_write32(cc, BCMA_CC_PMU_CHIPCTL_ADDR, offset);
++	bcma_pmu_read32(cc, BCMA_CC_PMU_CHIPCTL_ADDR);
++	bcma_pmu_maskset32(cc, BCMA_CC_PMU_CHIPCTL_DATA, mask, set);
+ }
+ EXPORT_SYMBOL_GPL(bcma_chipco_chipctl_maskset);
+ 
+ void bcma_chipco_regctl_maskset(struct bcma_drv_cc *cc, u32 offset, u32 mask,
+ 				u32 set)
+ {
+-	bcma_cc_write32(cc, BCMA_CC_REGCTL_ADDR, offset);
+-	bcma_cc_read32(cc, BCMA_CC_REGCTL_ADDR);
+-	bcma_cc_maskset32(cc, BCMA_CC_REGCTL_DATA, mask, set);
++	bcma_pmu_write32(cc, BCMA_CC_PMU_REGCTL_ADDR, offset);
++	bcma_pmu_read32(cc, BCMA_CC_PMU_REGCTL_ADDR);
++	bcma_pmu_maskset32(cc, BCMA_CC_PMU_REGCTL_DATA, mask, set);
+ }
+ EXPORT_SYMBOL_GPL(bcma_chipco_regctl_maskset);
+ 
+@@ -60,18 +60,18 @@ static u32 bcma_pmu_xtalfreq(struct bcma
+ {
+ 	u32 ilp_ctl, alp_hz;
+ 
+-	if (!(bcma_cc_read32(cc, BCMA_CC_PMU_STAT) &
++	if (!(bcma_pmu_read32(cc, BCMA_CC_PMU_STAT) &
+ 	      BCMA_CC_PMU_STAT_EXT_LPO_AVAIL))
+ 		return 0;
+ 
+-	bcma_cc_write32(cc, BCMA_CC_PMU_XTAL_FREQ,
+-			BIT(BCMA_CC_PMU_XTAL_FREQ_MEASURE_SHIFT));
++	bcma_pmu_write32(cc, BCMA_CC_PMU_XTAL_FREQ,
++			 BIT(BCMA_CC_PMU_XTAL_FREQ_MEASURE_SHIFT));
+ 	usleep_range(1000, 2000);
+ 
+-	ilp_ctl = bcma_cc_read32(cc, BCMA_CC_PMU_XTAL_FREQ);
++	ilp_ctl = bcma_pmu_read32(cc, BCMA_CC_PMU_XTAL_FREQ);
+ 	ilp_ctl &= BCMA_CC_PMU_XTAL_FREQ_ILPCTL_MASK;
+ 
+-	bcma_cc_write32(cc, BCMA_CC_PMU_XTAL_FREQ, 0);
++	bcma_pmu_write32(cc, BCMA_CC_PMU_XTAL_FREQ, 0);
+ 
+ 	alp_hz = ilp_ctl * 32768 / 4;
+ 	return (alp_hz + 50000) / 100000 * 100;
+@@ -127,8 +127,8 @@ static void bcma_pmu2_pll_init0(struct b
+ 		mask = (u32)~(BCMA_RES_4314_HT_AVAIL |
+ 			      BCMA_RES_4314_MACPHY_CLK_AVAIL);
+ 
+-		bcma_cc_mask32(cc, BCMA_CC_PMU_MINRES_MSK, mask);
+-		bcma_cc_mask32(cc, BCMA_CC_PMU_MAXRES_MSK, mask);
++		bcma_pmu_mask32(cc, BCMA_CC_PMU_MINRES_MSK, mask);
++		bcma_pmu_mask32(cc, BCMA_CC_PMU_MAXRES_MSK, mask);
+ 		bcma_wait_value(cc->core, BCMA_CLKCTLST,
+ 				BCMA_CLKCTLST_HAVEHT, 0, 20000);
+ 		break;
+@@ -140,7 +140,7 @@ static void bcma_pmu2_pll_init0(struct b
+ 
+ 	/* Flush */
+ 	if (cc->pmu.rev >= 2)
+-		bcma_cc_set32(cc, BCMA_CC_PMU_CTL, BCMA_CC_PMU_CTL_PLL_UPD);
++		bcma_pmu_set32(cc, BCMA_CC_PMU_CTL, BCMA_CC_PMU_CTL_PLL_UPD);
+ 
+ 	/* TODO: Do we need to update OTP? */
+ }
+@@ -195,9 +195,9 @@ static void bcma_pmu_resources_init(stru
+ 
+ 	/* Set the resource masks. */
+ 	if (min_msk)
+-		bcma_cc_write32(cc, BCMA_CC_PMU_MINRES_MSK, min_msk);
++		bcma_pmu_write32(cc, BCMA_CC_PMU_MINRES_MSK, min_msk);
+ 	if (max_msk)
+-		bcma_cc_write32(cc, BCMA_CC_PMU_MAXRES_MSK, max_msk);
++		bcma_pmu_write32(cc, BCMA_CC_PMU_MAXRES_MSK, max_msk);
+ 
+ 	/*
+ 	 * Add some delay; allow resources to come up and settle.
+@@ -269,23 +269,33 @@ static void bcma_pmu_workarounds(struct
+ 
+ void bcma_pmu_early_init(struct bcma_drv_cc *cc)
+ {
++	struct bcma_bus *bus = cc->core->bus;
+ 	u32 pmucap;
+ 
+-	pmucap = bcma_cc_read32(cc, BCMA_CC_PMU_CAP);
++	if (cc->core->id.rev >= 35 &&
++	    cc->capabilities_ext & BCMA_CC_CAP_EXT_AOB_PRESENT) {
++		cc->pmu.core = bcma_find_core(bus, BCMA_CORE_PMU);
++		if (!cc->pmu.core)
++			bcma_warn(bus, "Couldn't find expected PMU core");
++	}
++	if (!cc->pmu.core)
++		cc->pmu.core = cc->core;
++
++	pmucap = bcma_pmu_read32(cc, BCMA_CC_PMU_CAP);
+ 	cc->pmu.rev = (pmucap & BCMA_CC_PMU_CAP_REVISION);
+ 
+-	bcma_debug(cc->core->bus, "Found rev %u PMU (capabilities 0x%08X)\n",
+-		   cc->pmu.rev, pmucap);
++	bcma_debug(bus, "Found rev %u PMU (capabilities 0x%08X)\n", cc->pmu.rev,
++		   pmucap);
+ }
+ 
+ void bcma_pmu_init(struct bcma_drv_cc *cc)
+ {
+ 	if (cc->pmu.rev == 1)
+-		bcma_cc_mask32(cc, BCMA_CC_PMU_CTL,
+-			      ~BCMA_CC_PMU_CTL_NOILPONW);
++		bcma_pmu_mask32(cc, BCMA_CC_PMU_CTL,
++				~BCMA_CC_PMU_CTL_NOILPONW);
+ 	else
+-		bcma_cc_set32(cc, BCMA_CC_PMU_CTL,
+-			     BCMA_CC_PMU_CTL_NOILPONW);
++		bcma_pmu_set32(cc, BCMA_CC_PMU_CTL,
++			       BCMA_CC_PMU_CTL_NOILPONW);
+ 
+ 	bcma_pmu_pll_init(cc);
+ 	bcma_pmu_resources_init(cc);
+@@ -472,8 +482,8 @@ u32 bcma_pmu_get_cpu_clock(struct bcma_d
+ static void bcma_pmu_spuravoid_pll_write(struct bcma_drv_cc *cc, u32 offset,
+ 					 u32 value)
+ {
+-	bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
+-	bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, value);
++	bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_ADDR, offset);
++	bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_DATA, value);
+ }
+ 
+ void bcma_pmu_spuravoid_pllupdate(struct bcma_drv_cc *cc, int spuravoid)
+@@ -497,20 +507,20 @@ void bcma_pmu_spuravoid_pllupdate(struct
+ 		       bus->chipinfo.id == BCMA_CHIP_ID_BCM53572) ? 6 : 0;
+ 
+ 		/* RMW only the P1 divider */
+-		bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR,
++		bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_ADDR,
+ 				BCMA_CC_PMU_PLL_CTL0 + phypll_offset);
+-		tmp = bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
++		tmp = bcma_pmu_read32(cc, BCMA_CC_PMU_PLLCTL_DATA);
+ 		tmp &= (~(BCMA_CC_PMU1_PLL0_PC0_P1DIV_MASK));
+ 		tmp |= (bcm5357_bcm43236_p1div[spuravoid] << BCMA_CC_PMU1_PLL0_PC0_P1DIV_SHIFT);
+-		bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp);
++		bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_DATA, tmp);
+ 
+ 		/* RMW only the int feedback divider */
+-		bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR,
++		bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_ADDR,
+ 				BCMA_CC_PMU_PLL_CTL2 + phypll_offset);
+-		tmp = bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
++		tmp = bcma_pmu_read32(cc, BCMA_CC_PMU_PLLCTL_DATA);
+ 		tmp &= ~(BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_MASK);
+ 		tmp |= (bcm5357_bcm43236_ndiv[spuravoid]) << BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT;
+-		bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp);
++		bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_DATA, tmp);
+ 
+ 		tmp = BCMA_CC_PMU_CTL_PLL_UPD;
+ 		break;
+@@ -646,7 +656,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
+ 		break;
+ 	}
+ 
+-	tmp |= bcma_cc_read32(cc, BCMA_CC_PMU_CTL);
+-	bcma_cc_write32(cc, BCMA_CC_PMU_CTL, tmp);
++	tmp |= bcma_pmu_read32(cc, BCMA_CC_PMU_CTL);
++	bcma_pmu_write32(cc, BCMA_CC_PMU_CTL, tmp);
+ }
+ EXPORT_SYMBOL_GPL(bcma_pmu_spuravoid_pllupdate);
+--- a/drivers/bcma/driver_chipcommon_sflash.c
++++ b/drivers/bcma/driver_chipcommon_sflash.c
+@@ -38,6 +38,7 @@ static const struct bcma_sflash_tbl_e bc
+ 	{ "M25P32", 0x15, 0x10000, 64, },
+ 	{ "M25P64", 0x16, 0x10000, 128, },
+ 	{ "M25FL128", 0x17, 0x10000, 256, },
++	{ "MX25L25635F", 0x18, 0x10000, 512, },
+ 	{ NULL },
+ };
+ 
+--- a/drivers/bcma/scan.c
++++ b/drivers/bcma/scan.c
+@@ -98,6 +98,9 @@ static const struct bcma_device_id_name
+ 	{ BCMA_CORE_SHIM, "SHIM" },
+ 	{ BCMA_CORE_PCIE2, "PCIe Gen2" },
+ 	{ BCMA_CORE_ARM_CR4, "ARM CR4" },
++	{ BCMA_CORE_GCI, "GCI" },
++	{ BCMA_CORE_CMEM, "CNDS DDR2/3 memory controller" },
++	{ BCMA_CORE_ARM_CA7, "ARM CA7" },
+ 	{ BCMA_CORE_DEFAULT, "Default" },
+ };
+ 
+@@ -315,6 +318,8 @@ static int bcma_get_next_core(struct bcm
+ 		switch (core->id.id) {
+ 		case BCMA_CORE_4706_MAC_GBIT_COMMON:
+ 		case BCMA_CORE_NS_CHIPCOMMON_B:
++		case BCMA_CORE_PMU:
++		case BCMA_CORE_GCI:
+ 		/* Not used yet: case BCMA_CORE_OOB_ROUTER: */
+ 			break;
+ 		default:
+--- a/drivers/net/wireless/b43/main.c
++++ b/drivers/net/wireless/b43/main.c
+@@ -1215,10 +1215,10 @@ void b43_wireless_core_phy_pll_reset(str
+ 	case B43_BUS_BCMA:
+ 		bcma_cc = &dev->dev->bdev->bus->drv_cc;
+ 
+-		bcma_cc_write32(bcma_cc, BCMA_CC_CHIPCTL_ADDR, 0);
+-		bcma_cc_mask32(bcma_cc, BCMA_CC_CHIPCTL_DATA, ~0x4);
+-		bcma_cc_set32(bcma_cc, BCMA_CC_CHIPCTL_DATA, 0x4);
+-		bcma_cc_mask32(bcma_cc, BCMA_CC_CHIPCTL_DATA, ~0x4);
++		bcma_cc_write32(bcma_cc, BCMA_CC_PMU_CHIPCTL_ADDR, 0);
++		bcma_cc_mask32(bcma_cc, BCMA_CC_PMU_CHIPCTL_DATA, ~0x4);
++		bcma_cc_set32(bcma_cc, BCMA_CC_PMU_CHIPCTL_DATA, 0x4);
++		bcma_cc_mask32(bcma_cc, BCMA_CC_PMU_CHIPCTL_DATA, ~0x4);
+ 		break;
+ #endif
+ #ifdef CONFIG_B43_SSB
+--- a/include/linux/bcma/bcma.h
++++ b/include/linux/bcma/bcma.h
+@@ -151,6 +151,8 @@ struct bcma_host_ops {
+ #define BCMA_CORE_PCIE2			0x83C	/* PCI Express Gen2 */
+ #define BCMA_CORE_USB30_DEV		0x83D
+ #define BCMA_CORE_ARM_CR4		0x83E
++#define BCMA_CORE_GCI			0x840
++#define BCMA_CORE_CMEM			0x846	/* CNDS DDR2/3 memory controller */
+ #define BCMA_CORE_ARM_CA7		0x847
+ #define BCMA_CORE_SYS_MEM		0x849
+ #define BCMA_CORE_DEFAULT		0xFFF
+@@ -200,6 +202,7 @@ struct bcma_host_ops {
+ #define  BCMA_PKG_ID_BCM4707	1
+ #define  BCMA_PKG_ID_BCM4708	2
+ #define  BCMA_PKG_ID_BCM4709	0
++#define BCMA_CHIP_ID_BCM47094	53030
+ #define BCMA_CHIP_ID_BCM53018	53018
+ 
+ /* Board types (on PCI usually equals to the subsystem dev id) */
+--- a/include/linux/bcma/bcma_driver_chipcommon.h
++++ b/include/linux/bcma/bcma_driver_chipcommon.h
+@@ -217,6 +217,11 @@
+ #define	 BCMA_CC_CLKDIV_JTAG_SHIFT	8
+ #define	 BCMA_CC_CLKDIV_UART		0x000000FF
+ #define BCMA_CC_CAP_EXT			0x00AC		/* Capabilities */
++#define  BCMA_CC_CAP_EXT_SECI_PRESENT	0x00000001
++#define  BCMA_CC_CAP_EXT_GSIO_PRESENT	0x00000002
++#define  BCMA_CC_CAP_EXT_GCI_PRESENT	0x00000004
++#define  BCMA_CC_CAP_EXT_SECI_PUART_PRESENT		0x00000008    /* UART present */
++#define  BCMA_CC_CAP_EXT_AOB_PRESENT	0x00000040
+ #define BCMA_CC_PLLONDELAY		0x00B0		/* Rev >= 4 only */
+ #define BCMA_CC_FREFSELDELAY		0x00B4		/* Rev >= 4 only */
+ #define BCMA_CC_SLOWCLKCTL		0x00B8		/* 6 <= Rev <= 9 only */
+@@ -351,12 +356,12 @@
+ #define BCMA_CC_PMU_RES_REQTS		0x0640 /* PMU res req timer sel */
+ #define BCMA_CC_PMU_RES_REQT		0x0644 /* PMU res req timer */
+ #define BCMA_CC_PMU_RES_REQM		0x0648 /* PMU res req mask */
+-#define BCMA_CC_CHIPCTL_ADDR		0x0650
+-#define BCMA_CC_CHIPCTL_DATA		0x0654
+-#define BCMA_CC_REGCTL_ADDR		0x0658
+-#define BCMA_CC_REGCTL_DATA		0x065C
+-#define BCMA_CC_PLLCTL_ADDR		0x0660
+-#define BCMA_CC_PLLCTL_DATA		0x0664
++#define BCMA_CC_PMU_CHIPCTL_ADDR	0x0650
++#define BCMA_CC_PMU_CHIPCTL_DATA	0x0654
++#define BCMA_CC_PMU_REGCTL_ADDR		0x0658
++#define BCMA_CC_PMU_REGCTL_DATA		0x065C
++#define BCMA_CC_PMU_PLLCTL_ADDR		0x0660
++#define BCMA_CC_PMU_PLLCTL_DATA		0x0664
+ #define BCMA_CC_PMU_STRAPOPT		0x0668 /* (corerev >= 28) */
+ #define BCMA_CC_PMU_XTAL_FREQ		0x066C /* (pmurev >= 10) */
+ #define  BCMA_CC_PMU_XTAL_FREQ_ILPCTL_MASK	0x00001FFF
+@@ -566,17 +571,16 @@
+  * Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU)
+  */
+ struct bcma_chipcommon_pmu {
++	struct bcma_device *core;	/* Can be separated core or just ChipCommon one */
+ 	u8 rev;			/* PMU revision */
+ 	u32 crystalfreq;	/* The active crystal frequency (in kHz) */
+ };
+ 
+-#ifdef CONFIG_BCMA_DRIVER_MIPS
++#ifdef CONFIG_BCMA_PFLASH
+ struct bcma_pflash {
+ 	bool present;
+-	u8 buswidth;
+-	u32 window;
+-	u32 window_size;
+ };
++#endif
+ 
+ #ifdef CONFIG_BCMA_SFLASH
+ struct bcma_sflash {
+@@ -602,6 +606,7 @@ struct bcma_nflash {
+ };
+ #endif
+ 
++#ifdef CONFIG_BCMA_DRIVER_MIPS
+ struct bcma_serial_port {
+ 	void *regs;
+ 	unsigned long clockspeed;
+@@ -621,8 +626,9 @@ struct bcma_drv_cc {
+ 	/* Fast Powerup Delay constant */
+ 	u16 fast_pwrup_delay;
+ 	struct bcma_chipcommon_pmu pmu;
+-#ifdef CONFIG_BCMA_DRIVER_MIPS
++#ifdef CONFIG_BCMA_PFLASH
+ 	struct bcma_pflash pflash;
++#endif
+ #ifdef CONFIG_BCMA_SFLASH
+ 	struct bcma_sflash sflash;
+ #endif
+@@ -630,6 +636,7 @@ struct bcma_drv_cc {
+ 	struct bcma_nflash nflash;
+ #endif
+ 
++#ifdef CONFIG_BCMA_DRIVER_MIPS
+ 	int nr_serial_ports;
+ 	struct bcma_serial_port serial_ports[4];
+ #endif /* CONFIG_BCMA_DRIVER_MIPS */
+@@ -663,6 +670,19 @@ struct bcma_drv_cc_b {
+ #define bcma_cc_maskset32(cc, offset, mask, set) \
+ 	bcma_cc_write32(cc, offset, (bcma_cc_read32(cc, offset) & (mask)) | (set))
+ 
++/* PMU registers access */
++#define bcma_pmu_read32(cc, offset) \
++	bcma_read32((cc)->pmu.core, offset)
++#define bcma_pmu_write32(cc, offset, val) \
++	bcma_write32((cc)->pmu.core, offset, val)
++
++#define bcma_pmu_mask32(cc, offset, mask) \
++	bcma_pmu_write32(cc, offset, bcma_pmu_read32(cc, offset) & (mask))
++#define bcma_pmu_set32(cc, offset, set) \
++	bcma_pmu_write32(cc, offset, bcma_pmu_read32(cc, offset) | (set))
++#define bcma_pmu_maskset32(cc, offset, mask, set) \
++	bcma_pmu_write32(cc, offset, (bcma_pmu_read32(cc, offset) & (mask)) | (set))
++
+ extern u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks);
+ 
+ extern u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc);
+--- a/drivers/bcma/bcma_private.h
++++ b/drivers/bcma/bcma_private.h
+@@ -44,10 +44,6 @@ int bcma_sprom_get(struct bcma_bus *bus)
+ void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc);
+ void bcma_core_chipcommon_init(struct bcma_drv_cc *cc);
+ void bcma_chipco_bcm4331_ext_pa_lines_ctl(struct bcma_drv_cc *cc, bool enable);
+-#ifdef CONFIG_BCMA_DRIVER_MIPS
+-void bcma_chipco_serial_init(struct bcma_drv_cc *cc);
+-extern struct platform_device bcma_pflash_dev;
+-#endif /* CONFIG_BCMA_DRIVER_MIPS */
+ 
+ /* driver_chipcommon_b.c */
+ int bcma_core_chipcommon_b_init(struct bcma_drv_cc_b *ccb);
+@@ -59,6 +55,21 @@ void bcma_pmu_init(struct bcma_drv_cc *c
+ u32 bcma_pmu_get_alp_clock(struct bcma_drv_cc *cc);
+ u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc);
+ 
++/**************************************************
++ * driver_chipcommon_sflash.c
++ **************************************************/
++
++#ifdef CONFIG_BCMA_PFLASH
++extern struct platform_device bcma_pflash_dev;
++int bcma_pflash_init(struct bcma_drv_cc *cc);
++#else
++static inline int bcma_pflash_init(struct bcma_drv_cc *cc)
++{
++	bcma_err(cc->core->bus, "Parallel flash not supported\n");
++	return 0;
++}
++#endif /* CONFIG_BCMA_PFLASH */
++
+ #ifdef CONFIG_BCMA_SFLASH
+ /* driver_chipcommon_sflash.c */
+ int bcma_sflash_init(struct bcma_drv_cc *cc);
+--- a/drivers/bcma/driver_gpio.c
++++ b/drivers/bcma/driver_gpio.c
+@@ -229,6 +229,7 @@ int bcma_gpio_init(struct bcma_drv_cc *c
+ 	case BCMA_CHIP_ID_BCM4707:
+ 	case BCMA_CHIP_ID_BCM5357:
+ 	case BCMA_CHIP_ID_BCM53572:
++	case BCMA_CHIP_ID_BCM47094:
+ 		chip->ngpio	= 32;
+ 		break;
+ 	default:
+--- a/drivers/bcma/driver_mips.c
++++ b/drivers/bcma/driver_mips.c
+@@ -14,8 +14,6 @@
+ 
+ #include <linux/bcma/bcma.h>
+ 
+-#include <linux/mtd/physmap.h>
+-#include <linux/platform_device.h>
+ #include <linux/serial.h>
+ #include <linux/serial_core.h>
+ #include <linux/serial_reg.h>
+@@ -29,26 +27,6 @@ enum bcma_boot_dev {
+ 	BCMA_BOOT_DEV_NAND,
+ };
+ 
+-static const char * const part_probes[] = { "bcm47xxpart", NULL };
+-
+-static struct physmap_flash_data bcma_pflash_data = {
+-	.part_probe_types	= part_probes,
+-};
+-
+-static struct resource bcma_pflash_resource = {
+-	.name	= "bcma_pflash",
+-	.flags  = IORESOURCE_MEM,
+-};
+-
+-struct platform_device bcma_pflash_dev = {
+-	.name		= "physmap-flash",
+-	.dev		= {
+-		.platform_data  = &bcma_pflash_data,
+-	},
+-	.resource	= &bcma_pflash_resource,
+-	.num_resources	= 1,
+-};
+-
+ /* The 47162a0 hangs when reading MIPS DMP registers registers */
+ static inline bool bcma_core_mips_bcm47162a0_quirk(struct bcma_device *dev)
+ {
+@@ -269,48 +247,11 @@ static enum bcma_boot_dev bcma_boot_dev(
+ 	return BCMA_BOOT_DEV_SERIAL;
+ }
+ 
+-static void bcma_core_mips_flash_detect(struct bcma_drv_mips *mcore)
++static void bcma_core_mips_nvram_init(struct bcma_drv_mips *mcore)
+ {
+ 	struct bcma_bus *bus = mcore->core->bus;
+-	struct bcma_drv_cc *cc = &bus->drv_cc;
+-	struct bcma_pflash *pflash = &cc->pflash;
+ 	enum bcma_boot_dev boot_dev;
+ 
+-	switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
+-	case BCMA_CC_FLASHT_STSER:
+-	case BCMA_CC_FLASHT_ATSER:
+-		bcma_debug(bus, "Found serial flash\n");
+-		bcma_sflash_init(cc);
+-		break;
+-	case BCMA_CC_FLASHT_PARA:
+-		bcma_debug(bus, "Found parallel flash\n");
+-		pflash->present = true;
+-		pflash->window = BCMA_SOC_FLASH2;
+-		pflash->window_size = BCMA_SOC_FLASH2_SZ;
+-
+-		if ((bcma_read32(cc->core, BCMA_CC_FLASH_CFG) &
+-		     BCMA_CC_FLASH_CFG_DS) == 0)
+-			pflash->buswidth = 1;
+-		else
+-			pflash->buswidth = 2;
+-
+-		bcma_pflash_data.width = pflash->buswidth;
+-		bcma_pflash_resource.start = pflash->window;
+-		bcma_pflash_resource.end = pflash->window + pflash->window_size;
+-
+-		break;
+-	default:
+-		bcma_err(bus, "Flash type not supported\n");
+-	}
+-
+-	if (cc->core->id.rev == 38 ||
+-	    bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) {
+-		if (cc->capabilities & BCMA_CC_CAP_NFLASH) {
+-			bcma_debug(bus, "Found NAND flash\n");
+-			bcma_nflash_init(cc);
+-		}
+-	}
+-
+ 	/* Determine flash type this SoC boots from */
+ 	boot_dev = bcma_boot_dev(bus);
+ 	switch (boot_dev) {
+@@ -328,13 +269,10 @@ static void bcma_core_mips_flash_detect(
+ 
+ void bcma_core_mips_early_init(struct bcma_drv_mips *mcore)
+ {
+-	struct bcma_bus *bus = mcore->core->bus;
+-
+ 	if (mcore->early_setup_done)
+ 		return;
+ 
+-	bcma_chipco_serial_init(&bus->drv_cc);
+-	bcma_core_mips_flash_detect(mcore);
++	bcma_core_mips_nvram_init(mcore);
+ 
+ 	mcore->early_setup_done = true;
+ }
+--- a/drivers/bcma/host_pci.c
++++ b/drivers/bcma/host_pci.c
+@@ -294,7 +294,7 @@ static const struct pci_device_id bcma_p
+ 	{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4358) },
+ 	{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4359) },
+ 	{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4360) },
+-	{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4365) },
++	{ PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, 0x4365, PCI_VENDOR_ID_DELL, 0x0016) },
+ 	{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x43a0) },
+ 	{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x43a9) },
+ 	{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x43aa) },
+--- a/drivers/bcma/Kconfig
++++ b/drivers/bcma/Kconfig
+@@ -70,6 +70,11 @@ config BCMA_DRIVER_MIPS
+ 
+ 	  If unsure, say N
+ 
++config BCMA_PFLASH
++	bool
++	depends on BCMA_DRIVER_MIPS
++	default y
++
+ config BCMA_SFLASH
+ 	bool
+ 	depends on BCMA_DRIVER_MIPS
+--- a/drivers/bcma/Makefile
++++ b/drivers/bcma/Makefile
+@@ -1,6 +1,7 @@
+ bcma-y					+= main.o scan.o core.o sprom.o
+ bcma-y					+= driver_chipcommon.o driver_chipcommon_pmu.o
+ bcma-y					+= driver_chipcommon_b.o
++bcma-$(CONFIG_BCMA_PFLASH)		+= driver_chipcommon_pflash.o
+ bcma-$(CONFIG_BCMA_SFLASH)		+= driver_chipcommon_sflash.o
+ bcma-$(CONFIG_BCMA_NFLASH)		+= driver_chipcommon_nflash.o
+ bcma-$(CONFIG_BCMA_DRIVER_PCI)		+= driver_pci.o
+--- /dev/null
++++ b/drivers/bcma/driver_chipcommon_pflash.c
+@@ -0,0 +1,49 @@
++/*
++ * Broadcom specific AMBA
++ * ChipCommon parallel flash
++ *
++ * Licensed under the GNU/GPL. See COPYING for details.
++ */
++
++#include "bcma_private.h"
++
++#include <linux/bcma/bcma.h>
++#include <linux/mtd/physmap.h>
++#include <linux/platform_device.h>
++
++static const char * const part_probes[] = { "bcm47xxpart", NULL };
++
++static struct physmap_flash_data bcma_pflash_data = {
++	.part_probe_types	= part_probes,
++};
++
++static struct resource bcma_pflash_resource = {
++	.name	= "bcma_pflash",
++	.flags  = IORESOURCE_MEM,
++};
++
++struct platform_device bcma_pflash_dev = {
++	.name		= "physmap-flash",
++	.dev		= {
++		.platform_data  = &bcma_pflash_data,
++	},
++	.resource	= &bcma_pflash_resource,
++	.num_resources	= 1,
++};
++
++int bcma_pflash_init(struct bcma_drv_cc *cc)
++{
++	struct bcma_pflash *pflash = &cc->pflash;
++
++	pflash->present = true;
++
++	if (!(bcma_read32(cc->core, BCMA_CC_FLASH_CFG) & BCMA_CC_FLASH_CFG_DS))
++		bcma_pflash_data.width = 1;
++	else
++		bcma_pflash_data.width = 2;
++
++	bcma_pflash_resource.start = BCMA_SOC_FLASH2;
++	bcma_pflash_resource.end = BCMA_SOC_FLASH2 + BCMA_SOC_FLASH2_SZ;
++
++	return 0;
++}
+--- a/drivers/bcma/main.c
++++ b/drivers/bcma/main.c
+@@ -325,7 +325,7 @@ static int bcma_register_devices(struct
+ 		bcma_register_core(bus, core);
+ 	}
+ 
+-#ifdef CONFIG_BCMA_DRIVER_MIPS
++#ifdef CONFIG_BCMA_PFLASH
+ 	if (bus->drv_cc.pflash.present) {
+ 		err = platform_device_register(&bcma_pflash_dev);
+ 		if (err)