diff options
author | John Crispin <john@openwrt.org> | 2010-04-10 20:11:28 +0000 |
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committer | John Crispin <john@openwrt.org> | 2010-04-10 20:11:28 +0000 |
commit | b4d0b6cbb34d1cd5c71c122c2137e32476ec342a (patch) | |
tree | 39d1d9278deef057a8d2ccfe5e9d55325f28a991 /target/linux/ifxmips/patches-2.6.33/010-mips_clocksource_init_war.patch | |
parent | be4d9660e8cb66fde329d829a53b1bd75382351e (diff) | |
download | upstream-b4d0b6cbb34d1cd5c71c122c2137e32476ec342a.tar.gz upstream-b4d0b6cbb34d1cd5c71c122c2137e32476ec342a.tar.bz2 upstream-b4d0b6cbb34d1cd5c71c122c2137e32476ec342a.zip |
adss 2.6.33 kernel patches, not defult yet as linux-atm breaks on 2.6.33
SVN-Revision: 20789
Diffstat (limited to 'target/linux/ifxmips/patches-2.6.33/010-mips_clocksource_init_war.patch')
-rw-r--r-- | target/linux/ifxmips/patches-2.6.33/010-mips_clocksource_init_war.patch | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/target/linux/ifxmips/patches-2.6.33/010-mips_clocksource_init_war.patch b/target/linux/ifxmips/patches-2.6.33/010-mips_clocksource_init_war.patch new file mode 100644 index 0000000000..15fd78f4e6 --- /dev/null +++ b/target/linux/ifxmips/patches-2.6.33/010-mips_clocksource_init_war.patch @@ -0,0 +1,35 @@ +Index: linux-2.6.32.10/arch/mips/kernel/cevt-r4k.c +=================================================================== +--- linux-2.6.32.10.orig/arch/mips/kernel/cevt-r4k.c 2010-04-02 21:11:39.000000000 +0200 ++++ linux-2.6.32.10/arch/mips/kernel/cevt-r4k.c 2010-04-02 21:11:52.000000000 +0200 +@@ -22,6 +22,22 @@ + + #ifndef CONFIG_MIPS_MT_SMTC + ++/* ++ * Compare interrupt can be routed and latched outside the core, ++ * so a single execution hazard barrier may not be enough to give ++ * it time to clear as seen in the Cause register. 4 time the ++ * pipeline depth seems reasonably conservative, and empirically ++ * works better in configurations with high CPU/bus clock ratios. ++ */ ++ ++#define compare_change_hazard() \ ++ do { \ ++ irq_disable_hazard(); \ ++ irq_disable_hazard(); \ ++ irq_disable_hazard(); \ ++ irq_disable_hazard(); \ ++ } while (0) ++ + static int mips_next_event(unsigned long delta, + struct clock_event_device *evt) + { +@@ -31,6 +47,7 @@ + cnt = read_c0_count(); + cnt += delta; + write_c0_compare(cnt); ++ compare_change_hazard(); + res = ((int)(read_c0_count() - cnt) > 0) ? -ETIME : 0; + return res; + } |