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| author | Pavel Kubelun <be.dissent@gmail.com> | 2017-07-06 17:20:18 +0300 |
|---|---|---|
| committer | Felix Fietkau <nbd@nbd.name> | 2018-01-17 11:02:05 +0100 |
| commit | 83499bef73cc67b9290360cf76c345a7b3c29f08 (patch) | |
| tree | 62a2fd8e3903847e90087e030a4ba37482415c3b /target/linux/ipq806x/patches-4.9/0039-clk-qcom-Add-HFPLL-driver.patch | |
| parent | 36a96a449303560395e9566faee58afbfdab745d (diff) | |
| download | upstream-83499bef73cc67b9290360cf76c345a7b3c29f08.tar.gz upstream-83499bef73cc67b9290360cf76c345a7b3c29f08.tar.bz2 upstream-83499bef73cc67b9290360cf76c345a7b3c29f08.zip | |
ipq806x: force 2nd pci slot into gen1 mode
According to QSDK and OEM tarballs (checked c2600, r7500v2, r7800) 2nd pci slot (pci1, 2,4 GHz card)) on ap148 based boards should operate in gen1 mode.
EA8500 is an exception and according to GPL pcie0 should operate in gen1 mode.
In previous commit we've added the support for this option, so enable it in DT for affected devices.
QSDK ref:
https://source.codeaurora.org/quic/qsdk/oss/kernel/linux-msm/commit/?h=release/endive_preview_cc&id=f3b07fe309027c52fc163149500cedddd707c506
While at it move the phy transmit termination offset value into dtsi file as it's platform specific.
Signed-off-by: Pavel Kubelun <be.dissent@gmail.com>
Diffstat (limited to 'target/linux/ipq806x/patches-4.9/0039-clk-qcom-Add-HFPLL-driver.patch')
0 files changed, 0 insertions, 0 deletions